Erasable and programmable single-poly non-volatile memory cell

Abstract

To provide an erasable programmable single-poly non-volatile memory cell.SOLUTION: A memory cell includes multiple doped regions formed by different manufacturing procedures. The memory cell includes a select transistor and a floating gate transistor. The channel length of the floating gate transistor is shorter than the channel length of the select transistor. A doping process in a manufacturing method is changed, such that the multiple doped regions have different parameters and characteristics, and the channel resistance of the floating gate transistor is larger than the channel resistance of the select transistor.SELECTED DRAWING: Figure 2H

Description

Technical Field

[0001] The present invention relates to non-volatile memories, and more particularly to erasable programmable single-poly non-volatile memory cells.

Background Art

[0002] As is well known, a memory cell of a non-volatile memory includes a storage unit. For example, the storage unit is a floating gate transistor. The storage state of the memory cell is determined according to the number of charges accumulated in the floating gate of the floating gate transistor.

[0003] In order to be compatible with a standard CMOS manufacturing process, a memory cell of a conventional non-volatile memory includes a single-poly floating gate transistor. The floating gate transistor and related electronic components are collaboratively formed as a single-poly non-volatile memory cell.

[0004] For example, an erasable programmable single-poly non-volatile memory is disclosed in Patent Document 1. FIG. 1A is a schematic top view showing a conventional single-poly non-volatile memory cell. FIG. 1B is a schematic cross-sectional view showing a conventional single-poly non-volatile memory cell, which is a view cut along line a1-a1. FIG. 1C is a schematic cross-sectional view showing a conventional single-poly non-volatile memory cell, which is a view cut along line b1-b1. FIG. 1D is a schematic equivalent circuit diagram of a conventional single-poly non-volatile memory cell.

[0005] As shown in FIGS. 1A to 1D, three p-type doped regions 131, 132, and 133 are formed in the N-well region NW. Further, a select gate 134 and a floating gate 136 formed of a polysilicon layer are disposed on the regions between the p-type doped regions 131, 132, and 133. An n-type doped region 138 is formed in the P-well region PW. The floating gate 136 extends externally from the isolation structure 139 and is disposed beside the n-type doped region 138. For example, the isolation structure 139 is a shallow trench isolation (STI) structure.

[0006] A conventional single-layer poly non-volatile memory cell is composed of a select transistor MS, a floating gate transistor MF, and an n-type transistor Mn. The select transistor MS and the floating gate transistor MF are p-type transistors and are formed in the N-well region NW. The n-type transistor Mn is formed in the P-well region PW.

[0007] The p-type doped region 131, the p-type doped region 132, the select gate 134, and the N-well region NW are formed together as the select transistor MS. The p-type doped region 132, the p-type doped region 133, the floating gate 136, and the N-well region NW are formed together as the floating gate transistor MF. The floating gate 136 and the assist gate region 135 are formed together as the n-type transistor Mn. Further, the erase gate region 135 includes the P-well region PW and the n-type doped region 138.

[0008] Refer to FIG. 1D. A selection gate voltage VSG is applied to the selection gate 134 of the selection transistor MS. A source line voltage VSL is applied to the first drain / source terminal of the selection transistor MS. An N-well voltage VNW is applied to the body terminal of the selection transistor MS. The first drain / source terminal of the floating gate transistor MF is connected to the second drain / source terminal of the selection transistor MS. A bit line voltage VBL is applied to the second drain / source terminal of the floating gate transistor MF. An N-well voltage VNW is applied to the body terminal of the floating gate transistor MF.

[0009] Furthermore, the two drain / source terminals of the n-type transistor Mn can be regarded as being connected to the n-type doped region 138. A P-well voltage VPW is applied to the body terminal of the n-type transistor Mn. The gate terminal of the n-type transistor Mn is connected to the floating gate 136. An erase line voltage VEL is applied to the two drain / source terminals of the n-type transistor Mn. In other words, the n-type transistor Mn is equivalent to a metal-oxide semiconductor capacitor and is also referred to as a MOS capacitor hereinafter.

[0010] Since a conventional memory cell is composed of two transistors MS and MF and one capacitor, this memory cell is sometimes called a 2T1C cell.

[0011] By providing appropriate bias voltages as the selection gate voltage VSG, the source line voltage VSL, the bit line voltage VBL, the erase line voltage VEL, the N-well voltage VNW, and the P-well voltage VPW, a program operation, an erase operation, or a read operation can be selectively executed on the memory cell.

[0012] Generally, in the doping process of the manufacturing process of the above-mentioned memory cell, since all the p-type doped regions 131, 132, and 133 are formed by the same manufacturing procedure, the p-type doped regions 131, 132, and 133 have the same parameters and characteristics.

[0013] Similarly, all of the p-type doped regions of other memory cells disclosed in Patent Document 1 are also formed by the same manufacturing procedure.

Prior Art Documents

Patent Documents

[0014]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0015] Numerous objects, features, and advantages of the present invention will become apparent upon reading the following detailed description of embodiments of the present invention in conjunction with the accompanying drawings. However, the drawings used herein are for illustrative purposes only and should not be considered limiting.

Means for Solving the Problems

[0016] One embodiment of the present invention provides an erasable programmable single-layer poly non-volatile memory cell. The erasable programmable single-layer poly non-volatile memory cell includes an isolation structure, a first well region, a second well region, a first gate structure, and a second gate structure. The isolation structure is formed on a semiconductor substrate. The surface of the semiconductor substrate is divided into a first region and a second region by the isolation structure. The first well region is formed on the surface of the semiconductor substrate corresponding to the first region. The second well region is formed on the surface of the semiconductor substrate corresponding to the second region. The first gate structure and the second gate structure are formed on the surface of the semiconductor substrate corresponding to the first region. The region of the surface of the semiconductor substrate corresponding to the first region is divided into a first merged doped region, a second merged doped region, and a third merged doped region by the first gate structure and the second gate structure. The memory cell further includes a fourth merged doped region. The fourth merged doped region is formed on the surface of the semiconductor substrate corresponding to the second region and is disposed laterally beside the second gate structure. The first merged doped region is disposed laterally beside the first side of the first gate structure. The second merged doped region is disposed between the second side of the first gate structure and the first side of the second gate structure. The third merged doped region is disposed laterally beside the second side of the second gate structure. The second gate structure extends outwardly into the second region through the surface of the isolation structure. A part of the second region is covered by the second gate structure. The first merged doped region, the first gate structure, and the second merged doped region are formed as a selection transistor in cooperation. The second merged doped region, the second gate structure, and the third merged doped region are formed as a floating gate transistor in cooperation. The channel resistance value of the floating gate transistor is larger than the channel resistance value of the selection transistor.

Brief Description of the Drawings

[0017]

Figure 1A

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Figure 2H

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Figure 2M

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Figure 7H

Embodiments for Carrying Out the Invention

[0018] The present invention provides a single-layer poly non-volatile memory cell. In the memory cell, a plurality of doped regions are formed by different manufacturing procedures. That is, the doping process in the method for manufacturing the memory cell is changed. As a result, the plurality of doped regions have different parameters and characteristics, and the channel resistance value of the floating gate transistor becomes larger than the channel resistance value of the selection transistor. The inventive concept of the present invention will be described in more detail below.

[0019] Figures 2A to 2H schematically show the steps of a method for manufacturing a single-layer poly non-volatile memory cell according to a first embodiment of the present invention. Figure 2I is a schematic equivalent circuit diagram of a single-layer poly non-volatile memory cell according to a first embodiment of the present invention. Hereinafter, the single-layer poly non-volatile memory cell is referred to as a memory cell.

[0020] As shown in FIG. 2A, a separation structure forming step is performed. A separation structure 202 is formed on a semiconductor substrate Sub. The separation structure 202 defines regions A and B. The semiconductor substrate Sub is covered with the separation structure 202. The surfaces of the semiconductor substrate Sub corresponding to regions A and B are exposed. Next, a well region forming step is performed. A first well region (for example, a P well region) is formed on the surface of the semiconductor substrate Sub corresponding to region A. Further, a second well region is formed on the surface of the semiconductor substrate Sub corresponding to region B. For example, the second well region is a low-concentration doped P well region LPW, a P well region PW, or an N well region NW.

[0021] Next, a gate structure forming step is performed. As shown in FIG. 2B, four gate oxide layers 223, 225, 227, and 229 are formed on the surface of the semiconductor substrate Sub. The gate structure 223 includes a gate dielectric layer 203 and a polysilicon gate layer 213. The gate structure 225 includes a gate dielectric layer 205 and a polysilicon gate layer 215. The gate structure 227 includes a gate dielectric layer 207 and a polysilicon gate layer 217. The gate structure 229 includes a gate dielectric layer 209 and a polysilicon gate layer 219. The gate dielectric layer 203 is disposed between the polysilicon gate layer 213 and the semiconductor substrate Sub. The gate dielectric layer 205 is disposed between the polysilicon gate layer 215 and the semiconductor substrate Sub. The gate dielectric layer 207 is disposed between the polysilicon gate layer 217 and the semiconductor substrate Sub, and the gate dielectric layer 209 is disposed between the polysilicon gate layer 219 and the semiconductor substrate Sub.

[0022] Two gate structures 223 and 225 are formed on the surface of region A. Further, region A is divided into three sub-regions by the two gate structures 223 and 225. The gate structure 225 is L-shaped. The extended portion of the gate structure 225 passes through the surface of the isolation structure 202 and extends outwardly to a region on the surface of region B. Two gate structures 227 and 229 cover only the isolation structure 202. Further, the two gate structures 227 and 229 are respectively disposed laterally on two opposite sides of the gate structure 225. The polysilicon gate layer 215 of the gate structure 225 functions as a floating gate of a floating gate transistor. The polysilicon gate layer 213 of the gate structure 223 functions as a selection gate of a selection transistor. In one embodiment, the channel length LF of the floating gate transistor is shorter than the channel length LS of the selection transistor. That is, LF < LS.

[0023] As is well known, the channel resistance value of a transistor is related to the channel length and channel width of the transistor. The wider the channel width, the smaller the channel resistance value. The narrower the channel width, the larger the channel resistance value. The shorter the channel length, the smaller the channel resistance value. The longer the channel length, the larger the channel resistance value. That is, when the n-doped regions in the structure of FIG. 2B are formed by the same manufacturing process, the channel resistance value of the floating gate transistor is smaller than the channel resistance value of the selection transistor.

[0024] In one embodiment, the doping process for doping the n-type doped region is specially designed to change the concentration distribution of the n-type doped region. In particular, the channel resistance value of the floating gate transistor is changed, and thus, the channel resistance value of the floating gate transistor is larger than the channel resistance value of the selection transistor. Hereinafter, such a doping process will be described in more detail with reference to a cross-sectional view taken along the c-d line of the structure shown in FIG. 2B.

[0025] Please refer to FIG. 2C. First, the gate structure 225 in region A and the regions on both sides thereof are covered with a mask 240 indicated by a dotted line. The gate structure 223 and the regions on both sides thereof are exposed. Further, region B is exposed. That is, only a part of the surface between the gate structure 223 and the gate structure 225 is covered with the mask 240, and the other part of the surface between the gate structure 223 and the gate structure 225 is not covered with the mask 240. Next, a first low-concentration doped drain process (LDD process) is performed. As a result, n-type low-concentration doped drain regions (n-LDD regions) 241, 242, and 243 are formed on the surface of the semiconductor substrate Sub not covered by the mask 240. The n-LDD regions 241 and 242 are formed under the surface of region A and are respectively disposed on both sides of the gate structure 223. The n-LDD region 243 is formed under the surface of region B and is disposed beside the gate structure 225.

[0026] Please refer to FIG. 2D. After the mask 240 is removed, the gate structures 223 (and the side regions thereof) in regions A and B are covered with a mask 250 indicated by a dotted line. In other words, the regions previously covered by the mask 240 are exposed. Next, a second LDD process is performed. As a result, n-type low-concentration doped drain regions (n-LDD regions) 251 and 252 are formed on the surface of the semiconductor substrate Sub not covered by the mask 250. The n-LDD regions 251 and 252 are formed under the surface of region A and are respectively disposed on both sides of the gate structure 225.

[0027] For example, the masks 240 and 250 are photoresists. In one embodiment, the dopant concentrations of the n-LDD regions 251 and 252 are smaller than the dopant concentrations of the n-LDD regions 241, 242, and 243.

[0028] Please refer to FIG. 2E. After the mask 250 is removed, spacers 248 are formed on the sidewalls of the gate structure 223, and spacers 258 are formed on the sidewalls of the gate structure 225. Further, spacers (not shown) are formed on the sidewalls of the gate structures 227 and 229.

[0029] Refer to FIG. 2F. Next, an n-type ion implantation process is performed on the surface of the semiconductor substrate Sub using two gate structures 223 and 225 and two spacers 248 and 258 as masks. As a result, three n-type ion implantation regions 261, 262, and 263 indicated by hatching are formed in three sub-regions of region A not covered by the two gate structures 223 and 225 and the two spacers 248 and 258, and an n-type ion implantation region 264 indicated by hatching is formed in region B not covered by the gate structure 225 and the spacer 258. In particular, the n-type ion implantation regions 261, 262, 263, and 264 have the highest doping concentration, and their dopant concentrations are higher than those of the n-LDD regions 241, 242, 243, and 251.

[0030] Refer to FIG. 2F. Next, the n-LDD region 241 and the n-type ion implantation region 261 are formed as a merged n-doped region 271 in cooperation. The merged n-doped region 271 is formed on the surface of the semiconductor substrate Sub and is disposed adjacent to the first side of the gate structure 223. The n-LDD region 242, the n-LDD region 251, and the n-type ion implantation region 262 are formed as a merged n-doped region 272 in cooperation. The merged n-doped region 272 is formed on the surface of the semiconductor substrate Sub and is disposed between the second side of the gate structure 223 and the first side of the gate structure 225. The n-LDD region 252 and the n-type ion implantation region 263 are formed as a merged n-doped region 273 in cooperation. The merged n-doped region 273 is formed on the surface of the semiconductor substrate Sub, and the n-LDD region 243 and the n-type ion implantation region 264 are formed on the surface of the semiconductor substrate Sub and are disposed beside the second side of the gate structure 225. The n-type LDD region 243 and the n-type ion implantation region 264 are formed as a merged n-doped region 274 in cooperation. The merged n-doped region 274 is formed on the surface of the semiconductor substrate Sub and is disposed beside the extended portion of the gate structure 225. A bird's-eye view of the structure of FIG. 2F is shown in FIG. 2G.

[0031] In region A, the gate structure 223 and the merged n-doped regions 271 and 272 on both sides thereof cooperate to form a selection transistor. Also, the gate structure 225 and the two merged n-doped regions 272 and 273 on both sides thereof cooperate to form a floating gate transistor. In the present embodiment, the floating gate transistor and the selection transistor are n-type transistors and are formed within the P-well region PW. That is, the body terminals of the floating gate transistor and the selection transistor are connected to the P-well region PW.

[0032] In region B, the n-doped region 274 is an erase gate region. The gate structure 225 extends outward and is disposed beside the erase gate region. As a result, the erase gate region and the gate structure 225 cooperate to form an n-type transistor. Further, the n-type transistor is connected as a MOS capacitor.

[0033] Refer to FIG. 2H. Next, a metal layer 280 is formed on the polysilicon gate layer 215. The metal layer 280 is electrically connected to the two polysilicon gate layers 217 and 219. When the process of forming the metal conductor line is completed, the memory cell of the first embodiment is manufactured. That is, the n-doped region 271 is connected to the source line SL, the n-doped region 273 is connected to the bit line BL, the n-doped region 274 is connected to the erase line EL, the polysilicon gate layer 213 is connected to the selection gate line SG, and the metal layer 280 is connected to the assist gate line AG.

[0034] In the memory cell according to this embodiment, gate structures 227 and 229 are disposed on the surface of isolation structure 202. Further, metal layer 280 is disposed on polysilicon gate structure 225. As a result, polysilicon gate layer 215 and polysilicon gate layer 217 are formed as a first poly / poly plate capacitor in cooperation, and polysilicon gate layer 215 and polysilicon gate layer 219 are formed as a second poly / poly plate capacitor in cooperation. Further, polysilicon gate layer 215 and metal layer 280 are formed as a metal / poly plate capacitor in cooperation.

[0035] As shown in FIG. 2I, the memory cell according to the first embodiment includes a selection transistor MS, a floating gate transistor MF, a MOS capacitor CMOS, a first poly / poly plate capacitor CP1, a metal / poly plate capacitor CP2, and a second poly / poly plate capacitor CP3. The first poly / poly plate capacitor CP1, the metal / poly plate capacitor CP2, and the second poly / poly plate capacitor CP3 are connected in parallel to each other. The three capacitors CP1, CP2, and CP3 connected in parallel are equivalent to the plate capacitor CP. Note that the capacitor CP of the memory cell is not limited to the three capacitors CP1, CP2, and CP3 connected in parallel. For example, at least one capacitor is feasible.

[0036] The gate terminal of selection transistor MS is connected to selection gate line SG. The first drain / source terminal of selection transistor MS is connected to source line SL. The first drain / source terminal of floating gate transistor MF is connected to the second drain / source terminal of selection transistor MS. The second drain / source terminal of floating gate transistor MF is connected to bit line BL.

[0037] The first terminal of the MOS capacitor CMOS is connected to the floating gate 215. The second terminal of the MOS capacitor CMOS is connected to the erase line EL. The first terminal of the first poly / poly plate capacitor CP1 is connected to the floating gate 215. The second terminal of the first poly / poly plate capacitor CP1 is connected to the assist gate line AG. The first terminal of the metal / poly plate capacitor CP2 is connected to the floating gate 215. The second terminal of the metal / poly plate capacitor CP2 is connected to the assist gate line AG. The first terminal of the second poly / poly plate capacitor CP3 is connected to the floating gate 215. The second terminal of the second poly / poly plate capacitor CP3 is connected to the assist gate line AG. That is, the first terminal of the plate capacitor CP is connected to the floating gate 215, and the second terminal of the plate capacitor CP is connected to the assist gate line AG.

[0038] Since the memory cell according to the first embodiment includes two transistors MS and MF and two capacitors CP and CMOS, this memory cell may be called a 2T2C cell.

[0039] FIG. 2J is a bias voltage table showing bias voltages for performing program operation, erase operation, and read operation on the memory cell according to the first embodiment of the present invention. FIG. 2K is a diagram showing the program operation in the memory cell according to the first embodiment of the present invention. FIG. 2L is a diagram showing the erase operation in the memory cell according to the first embodiment of the present invention. FIG. 2M is a diagram showing the read operation in the memory cell according to the first embodiment of the present invention.

[0040] When the program operation (PGM), erase operation (ERS), and read operation (Read) are executed, a ground voltage (0V) is applied to the P-well region PW and the source line SL. Also, the assist gate line voltage VAG is higher than the erase voltage VEE, the erase voltage VEE is higher than the program voltage VPP, the program voltage VPP is higher than the read voltage VR, and the read voltage VR is higher than the ground voltage (0V). For example, the assist gate line voltage VAG is 15V, the erase voltage VEE is 12V, the program voltage VPP is 9V, and the read voltage VR is 5V.

[0041] Please refer to FIG. 2K. When the program operation is executed, the program voltage VPP is applied to the bit line BL, the program voltage VPP is applied to the select gate line SG, a voltage between the ground voltage (0V) and the erase voltage VEE is applied to the erase line EL, and a voltage between the ground voltage (0V) and the assist gate line voltage VAG is applied to the assist gate line AG.

[0042] While the program operation is being executed, the select transistor MS is turned on, and a program current IP is generated between the bit line BL and the source line SL. When the hot carriers (e.g., electrons) of the program current IP flow through the channel region corresponding to the floating gate 215, the channel hot electron (CHE) effect occurs. Due to the CHE effect, electrons are injected into the floating gate 215.

[0043] As described above, the channel resistance value of the floating gate transistor MF is larger than the channel resistance value of the select transistor MS. After the program voltage VPP is supplied to the bit line BL, the voltage between the first drain / source terminal and the second drain / source terminal of the floating gate transistor MF becomes larger than the voltage between the first drain / source terminal and the second drain / source terminal of the select transistor MS. As a result, when the program operation is executed, electrons are more efficiently injected into the floating gate 215.

[0044] Please refer to FIG. 2L. When the erase operation (ERS) is executed, a ground voltage (0V) is applied to the bit line BL, a ground voltage (0V) is applied to the source line SL, a ground voltage (0V) is applied to the select gate line SG, an erase voltage VEE is applied to the erase line EL, and a voltage between a negative assist gate line voltage -VAG and a ground voltage (0V) is applied to the assist gate line AG.

[0045] When the erase operation is executed, the select transistor MS turns off. Under this situation, the Fowler-Nordheim tunneling effect (FN) occurs between the two terminals of the MOS transistor CMOS. As a result, electrons are discharged from the floating gate 215 to the erase line EL. The voltage applied to the assist gate line AG helps to increase the speed at which electrons are discharged from the floating gate 215. As a result, the erase efficiency is improved.

[0046] Please refer to FIG. 2M. When the read operation is executed, a read voltage VR is applied to the bit line BL, a ground voltage (0V) is applied to the source line SL, a read voltage VR is applied to the select gate line SG, a ground voltage (0V) is applied to the erase line EL, and a voltage between a negative assist gate line voltage -VAG and a positive assist gate line voltage VAG is applied to the assist gate line AG. The magnitude of the read current IR is adjusted according to the voltage applied to the assist gate line AG.

[0047] When a read operation is executed, the selection transistor MS is turned on, and a read current IR is generated between the bit line BL and the source line SL. The storage state of the memory cell can be determined according to the magnitude of the read current IR. For example, when electrons are accumulated in the floating gate 215, the magnitude of the read current IR is very small (e.g., almost zero). Therefore, the memory cell is determined to be in the first storage state. On the other hand, when no electrons are accumulated in the floating gate 215, the magnitude of the read current IR is very large. In this situation, the memory cell is determined to be in the second storage state.

[0048] As described above, the present invention provides two LDD processes to generate LDD regions with different dopant concentrations. As a result, the floating gate transistor MF with a short channel length has a high channel resistance value. Please refer to FIG. 2F again. In the merged n-doped region 272, the n-LDD region 251 closer to the first side of the gate structure 225 of the floating gate transistor MF has a lower dopant concentration. In the merged n-doped region 273, the n-LDD region 252 closer to the second side of the gate structure 225 of the floating gate transistor MF has a lower dopant concentration. In the merged n-doped region 271, the n-LDD region 241 closer to the first side of the gate structure 223 of the selection transistor MS has a higher dopant concentration. In the merged n-doped region 272, the n-LDD region 242 closer to the first side of the gate structure 223 of the selection transistor MS has a higher dopant concentration. The dopant concentration difference near the channel can affect the channel resistance value of the floating gate transistor MF and the channel resistance value of the selection transistor MS. Therefore, the channel resistance value of the floating gate transistor MF is larger than the channel resistance value of the selection transistor MS.

[0049] Note that the doping process of the first embodiment is deformable. Hereinafter, some deformation examples of the doping process will be described. By using these deformation examples, the channel resistance value of the floating gate transistor MF with a short channel length becomes high.

[0050] FIG. 3A, FIG. 3B, and FIG. 3C are diagrams schematically showing a first modification of the doping process in the manufacturing method of the first embodiment. The procedure of the doping process of this modification follows the structure of FIG. 2B.

[0051] Refer to FIG. 3A. First, the gate structures 225 in region A, the gate structure 223, and the regions on both sides of the gate structure 225 are covered with a mask 340 shown by a dotted line. Further, only the side region (for example, the right region) of the gate structure 223 is exposed. Next, a first low-concentration doped drain process (LDD process) is executed. As a result, n-type low-concentration doped drain regions (n-LDD regions) 341 and 343 are formed on the surface of the semiconductor substrate Sub not covered by the mask 340. The n-LDD region 341 is formed under the surface of region A and is located beside the side (for example, the right side) of the gate structure 223. The n-LDD region 343 is formed under the surface of region B and is located beside the gate structure 225.

[0052] Refer to FIG. 3B. After the mask 340 is removed, the sides (for example, the right side) of the gate structure 223 in regions A and B are covered with a mask 350 shown by a dotted line. In other words, the regions previously covered by the mask 340 are exposed. Next, a second LDD process is executed. As a result, n-type low-concentration doped drain regions (n-LDD regions) 351 and 352 are formed on the surface of the semiconductor substrate Sub not covered by the mask 350. The n-LDD regions 351 and 352 are formed under the surface of region A and are respectively arranged on both sides of the gate structure 225.

[0053] For example, the masks 340 and 350 are photoresists. In one embodiment, the dopant concentrations of the n-LDD regions 351 and 352 are smaller than the dopant concentrations of the n-LDD regions 341 and 243.

[0054] Please refer to FIG. 3C. After forming the spacers 248 and 258, a p-type ion implantation process is performed on the surface of the semiconductor substrate Sub using the two gate structures 223 and 225 and the two spacers 248 and 258 as masks. As a result, three p-type ion implantation regions 261, 262, and 263 indicated by hatching are formed in three sub-regions of the region A not covered by the two gate structures 223 and 225 and the two spacers 248 and 258, and a p-type ion implantation region 264 indicated by hatching is formed in the region B not covered by the gate structure 225 and the spacer 258.

[0055] Please refer to FIG. 3C again. Next, the n-LDD region 341 and the p-type ion implantation region 261 are formed as a merged p-doped region 271 in cooperation. The merged p-doped region 271 is formed on the surface of the semiconductor substrate Sub and is disposed adjacent to the first side of the gate structure 223. The n-LDD region 351 and the p-type ion implantation region 262 are formed as a merged p-doped region 272 in cooperation. The merged p-doped region 272 is formed on the surface of the semiconductor substrate Sub and is disposed between the second side of the gate structure 223 and the first side of the gate structure 225. The n-LDD region 352 and the p-type ion implantation region 263 are formed as a merged p-doped region 273 in cooperation. The merged p-doped region 273 is formed on the surface of the semiconductor substrate Sub and is disposed adjacent to the second side of the gate structure 225. The n-LDD region 343 and the p-type ion implantation region 264 are formed as a merged p-doped region 274 in cooperation. The merged p-doped region 274 is formed on the surface of the semiconductor substrate Sub and is disposed beside the extension of the gate structure 225.

[0056] Please compare and refer to the structure of FIG. 2F and the structure of FIG. 3C. The dopant concentration of the n-LDD region 242 on the left side of the gate structure 223 of the memory cell in FIG. 2F is higher than the dopant concentration of the n-LDD region 351 on the left side of the gate structure 223 of the memory cell in FIG. 3C. The dopant concentrations of the other n-LDD regions are the same.

[0057] Please refer to FIG. 3C again. In the merged n-doped region 272, the n-LDD region 351 closer to the first side of the gate structure 225 of the floating gate transistor MF has a lower dopant concentration. In the merged n-doped region 273, the n-LDD region 352 closer to the second side of the gate structure 225 of the floating gate transistor MF has a lower dopant concentration. In the merged n-doped region 271, the n-LDD region 341 closer to the first side of the gate structure 223 of the selection transistor MS has a higher dopant concentration. In the merged n-doped region 272, the n-LDD region 351 closer to the first side of the gate structure 223 of the selection transistor MS has a lower dopant concentration. Since the dopant concentration difference near the channel can affect the channel resistance value of the floating gate transistor MF and the channel resistance value of the selection transistor MS, the channel resistance value of the floating gate transistor MF becomes larger than the channel resistance value of the selection transistor MS.

[0058] Subsequent procedures for manufacturing the memory cell can be referred to FIGS. 2G and 2H, and the equivalent circuit is the same as that in FIG. 2I.

[0059] FIGS. 4A, 4B, and 4C are diagrams schematically showing a second modification of the doping process in the manufacturing method of the first embodiment. The procedure of the doping process in this modification follows the structure of FIG. 2B.

[0060] Please refer to FIG. 4A. First, the gate structure 225 and the side (e.g., the left side) of the gate structure 225 in region A are covered with a mask 440 indicated by a dotted line. The gate structure 223 and the regions on both sides thereof are exposed. Further, region B is exposed. Next, a first low-concentration doped drain process (LDD process) is executed. As a result, n-type low-concentration doped drain regions (n-LDD regions) 441, 442, and 443 are formed on the surface of the semiconductor substrate Sub not covered by the mask 440. The n-LDD region 441 is formed under the surface of region A and is located beside one side (e.g., the right side) of the gate structure 223. The n-LDD region 442 is formed under the surface of region A and is located beside the other side (e.g., the left side) of the gate structure 223. The n-LDD region 443 is formed under the surface of region B and is located beside the gate structure 225.

[0061] Please refer to FIG. 4B. After the mask 440 is removed, the gate structure 223 (and its side regions) in regions A and B are covered with a mask 450 indicated by a dotted line. In other words, the regions previously covered by the mask 440 are exposed. Next, a second LDD process is executed. As a result, an n-type low-concentration doped drain region (n-LDD region) 452 is formed on the surface of the semiconductor substrate Sub not covered by the mask 450. The n-LDD region 452 is formed under the surface of region A and is located beside the side (e.g., the left side) of the gate structure 225. For example, the masks 440 and 450 are photoresists. In one embodiment, the dopant concentration of the n-LDD region 452 is smaller than the dopant concentrations of the n-LDD regions 441, 442, and 443.

[0062] Please refer to FIG. 4C. After forming the spacers 248 and 258, an n-type ion implantation process is performed on the surface of the semiconductor substrate Sub using the two gate structures 223 and 225 and the two spacers 248 and 258 as masks. As a result, three n-type ion implantation regions 261, 262, and 263 indicated by hatching are formed in three sub-regions of region A not covered by the two gate structures 223 and 225 and the two spacers 248 and 258, and an n-type ion implantation region 264 indicated by hatching is formed in region B not covered by the gate structure 225 and the spacer 258.

[0063] Please refer to FIG. 4C again. Next, the n-LDD region 441 and the n-type ion implantation region 261 are formed as a merged n-doped region 271 in cooperation. The merged n-doped region 271 is formed on the surface of the semiconductor substrate Sub and is disposed adjacent to the first side of the gate structure 223. The n-LDD region 442 and the n-type ion implantation region 262 are formed as a merged n-doped region 272 in cooperation. The integrated n-doped region 272 is formed on the surface of the semiconductor substrate Sub and is disposed between the second side of the gate structure 223 and the first side of the gate structure 225. The n-LDD region 452 and the n-type ion implantation region 263 are formed as a merged n-doped region 273 in cooperation. The merged n-doped region 273 is formed on the surface of the semiconductor substrate Sub and is disposed adjacent to the second side of the gate structure 225. The n-LDD region 443 and the n-type ion implantation region 264 are formed as a merged n-doped region 274 in cooperation. The merged n-doped region 274 is formed on the surface of the semiconductor substrate Sub and is located beside the extension of the gate structure 225.

[0064] Please compare and refer to the structure of FIG. 2F and the structure of FIG. 4C. The dopant concentration of the n-LDD region 251 on the right side of the gate structure 225 in the memory cell of FIG. 2F is lower than the dopant concentration of the n-LDD region 442 on the right side of the gate structure 225 in the memory cell of FIG. 4C. The dopant concentrations of the other n-LDD regions are the same.

[0065] Please refer to FIG. 4C again. In the merged n-doped region 272, the n-LDD region 442 closer to the first side of the gate structure 225 of the floating gate transistor MF has a higher dopant concentration. In the merged n-doped region 273, the n-LDD region 452 closer to the second side of the gate structure 225 of the floating gate transistor MF has a lower dopant concentration. In the merged n-doped region 271, the n-LDD region 441 closer to the first side of the gate structure 223 of the select transistor MS has a higher dopant concentration. In the merged n-doped region 272, the n-LDD region 442 closer to the first side of the gate structure 223 of the select transistor MS has a higher dopant concentration. The dopant concentration difference near the channel can affect the channel resistance value of the floating gate transistor MF and the channel resistance value of the select transistor MS. Therefore, the channel resistance value of the floating gate transistor MF is larger than the channel resistance value of the select transistor MS.

[0066] Subsequent procedures for manufacturing the memory cell can be referred to FIGS. 2G and 2H, and the equivalent circuit is the same as that in FIG. 2I.

[0067] From the above description, by adjusting the dopant concentration of the n-LDD regions in the merged n-doped regions 271, 272, and 273, the channel resistance value of the floating gate transistor MF becomes larger than the channel resistance value of the select transistor MS. The merged n-doped region 271 includes a first n-LDD region located beside the first side of the gate structure 223. The merged n-doped region 272 includes a second n-LDD region and a third n-LDD region. The second n-LDD region is located beside the second side of the gate structure 223. The third n-LDD region is located beside the first side of the gate structure 225. The merged n-doped region 273 includes a fourth n-LDD region located beside the second side of the gate structure 225.

[0068] In the example of FIG. 2F, the dopant concentration of the 4n-LDD region 252 is the same as that of the 3n-LDD region 251, the dopant concentration of the 2n-LDD region 242 is the same as that of the 1n-LDD region 241, and the dopant concentration of the 4n-LDD region 252 is lower than that of the 1n-LDD region 241.

[0069] In the example of FIG. 3C, the dopant concentration of the 4n-LDD region 352 is the same as that of the 3n-LDD region 351, the dopant concentration of the 3n-LDD region 351 is the same as that of the 2n-LDD region 351, and the dopant concentration of the 4n-LDD region 352 is lower than that of the 1n-LDD region 341.

[0070] In the example of FIG. 4C, the dopant concentration of the 3n-LDD region 442 is the same as that of the 2n-LDD region 442, the dopant concentration of the 2n-LDD region 442 is the same as that of the 1n-LDD region 441, and the dopant concentration of the 4n-LDD region 452 is lower than that of the 1n-LDD region 441.

[0071] In the foregoing embodiments, the n-LDD regions 243, 343, 443, and 543 in region B are all formed by the first LDD process, and their dopant concentrations are relatively high. It should be noted that various modifications and changes can be made while maintaining the teachings of the present invention. For example, in another embodiment, the n-LDD regions in region B are created using two LDD processes, and the dopant concentration is reduced. In some other embodiments, the order of the two LDD processes is changed. For example, the dopant concentration of the first LDD process is low, and the dopant concentration of the second LDD process is high.

[0072] Of course, the doping process can be further modified to achieve the concentration distribution of FIG. 2F, FIG. 3C, or FIG. 4C. FIGS. 5A, 5B, and 5C schematically show a third modification of the doping process in the manufacturing method of the first embodiment. The procedure of the doping process in this modification follows the structure of FIG. 2B.

[0073] Refer to FIG. 5A. First, using the gate structures 223 and 225 as masks, a first low-concentration doped drain process (LDD process) is performed. As a result, n-type low-concentration doped drain regions (n-LDD regions) 541, 542, and 543 are formed on the surface of the semiconductor substrate Sub that is not covered by the masks. The n-LDD region 541 is formed under the surface of the semiconductor substrate Sub and is disposed beside the first side of the gate structure 223. The n-LDD region 542 is formed under the surface of the semiconductor substrate Sub and is disposed between the second side of the gate structure 223 and the first side of the gate structure 225. The n-LDD region 544 is formed under the surface of the semiconductor substrate Sub and is disposed beside the second side of the gate structure 225. The n-LDD region 543 is formed under the surface of region B and is disposed beside the gate structure 225.

[0074] Refer to FIG. 5B. After forming the spacers 248 and 258, an n-type ion implantation process is performed on the surface of the semiconductor substrate Sub using the two gate structures 223 and 225 and the two spacers 248 and 258 as masks. As a result, three n-type ion implantation regions 261, 262, and 263 shown by hatches are formed in three sub-regions of region A that are not covered by the two gate structures 223 and 225 and the two spacers 248 and 258, and an n-type ion implantation region 264 shown by hatches is formed in region B that is not covered by the gate structure 225 and the spacer 258.

[0075] In this embodiment, the dopant concentrations of the n-LDD regions 541, 542, and 544 are the same. As described above, it is preferable that the channel resistance value of the floating gate transistor MF is larger than the channel resistance value of the select transistor MS. Refer to FIG. 5C. To achieve this purpose, the surface of the semiconductor substrate Sub is covered with a mask 560, and only the gate structure 225 in region A and the regions on both sides thereof are exposed. Next, an anti-punch through (APT) process is executed. As a result, two anti-punch through (APT) regions 561 and 562 are formed. The APT region 561 is in contact with the n-LDD region 542. The APT region 562 is in contact with the n-LDD region 544. For example, the APT process is a halo injection process or a pocket injection process. Since the APT regions 561 and 562 are in contact with the n-LDD regions 542 and 544, respectively, a high resistance and a high electric field are generated in the n-LDD regions 542 and 544. As a result, the channel resistance value of the floating gate transistor MF becomes larger than the channel resistance value of the select transistor MS.

[0076] After removing the mask 560, the subsequent procedures for manufacturing the memory cell can be referred to FIGS. 2G and 2H, and the equivalent circuit is the same as that in FIG. 2I.

[0077] In the doping processes of FIGS. 5A, 5B, and 5C, APT regions 561 and 562 are respectively disposed beside n-LDD regions 542 and 544. It should be noted that various modifications and changes can be made while maintaining the teachings of the present invention. For example, in one variation, a single APT region is in contact with the n-LDD region 544 adjacent to the second side of the gate structure 225. In another variation, a single APT region is in contact with the n-LDD region 542 adjacent to the first side of the gate structure 225. In another variation, three APT regions are formed. Two of the three APT regions are respectively in contact with the n-LDD regions 542 and 544 beside the two sides of the gate structure 225, and one of the three APT regions is in contact with the n-LDD region 541 beside the first side of the gate structure 223. However, there is no APT region in contact with the n-LDD region 542 beside the second side of the gate structure 223. As a result, the channel resistance value of the floating gate transistor MF becomes larger than that of the select transistor MS.

[0078] Furthermore, it should be noted that the conductivity of the aforementioned APT region may be n-type or p-type, but p-type is preferred because of its excellent performance.

[0079] In other embodiments, a p-type channel implantation process is performed in the region under the gate structure 225. As a result, the channel resistance value of the floating gate transistor MF increases. FIG. 6 schematically shows a fourth variation of the doping process in the manufacturing method of the first embodiment. The procedure of the doping process in this variation follows the structure of FIG. 2F.

[0080] By subjecting the structure of FIG. 2F to a p-type channel implantation process, a p-type channel doped region 602 is formed. The p-type channel doped region 602 is formed on the surface of the semiconductor substrate Sub and is located under the gate structure 225. Since the p-type channel doped region 602 and the merged n-doped regions 272 and 273 have different dopant types, the channel resistance value of the floating gate transistor MF can be increased. Similarly, the p-type channel implantation process can be applied to the structures of FIGS. 3C, 4C, 5B, or 5C. As a result, a p-type channel doped region 602 is formed on the surface of the semiconductor substrate Sub and is located under the gate structure 225.

[0081] FIGS. 7A to 7G schematically show the steps of a method for manufacturing a single-layer poly non-volatile memory cell according to a second embodiment of the present invention. FIG. 7H is a schematic equivalent circuit diagram of the single-layer poly non-volatile memory cell according to the second embodiment of the present invention.

[0082] As shown in FIG. 7A, an isolation structure forming step is performed. First, an isolation structure 702 is formed on the p-type substrate Sub. The isolation structure 702 defines a region A and a region B. Region B is a rectangular region. Region A is composed of two rectangular sub-regions A1 and A2. Next, a well region forming step is performed. A first well region (for example, a P well region) is formed on the surface of the semiconductor substrate Sub corresponding to region A. Further, a second well region is formed on the surface of the semiconductor substrate Sub corresponding to region B. For example, the second well region is a low-concentration doped P well region LPW, a P well region PW, or an N well region NW. In subsequent steps, a floating gate transistor, a selection transistor, and an assist gate region are formed in region A, and an erase gate region is formed in region B.

[0083] Next, a gate structure formation process is performed. As shown in FIG. 7B, two gate oxide films 703 and 705 are formed. Next, two polysilicon gate layers 713 and 715 are formed on the two gate oxide films 703 and 705, respectively. As a result, two gate structures 723 and 725 are formed. The two gate structures 723 and 725 are formed on the surface of region A. Further, region A is divided into three sub-regions by the two gate structures 723 and 725. The gate structures 723 and 725 are formed on the surface corresponding to region A1. The first sub-region is disposed laterally to the left of the gate structure 723. The second sub-region 723 is disposed between the right side of the gate structure 723 and the left side of the gate structure 725. The third sub-region is disposed laterally to the right of the gate structure 725 (including region A2). In other words, the third sub-region is an L-shaped sub-region.

[0084] Furthermore, two extension segments extend outwardly through the surface of the isolation structure 702 from the gate structure 725. The first extension segment of the gate structure 725 extends outwardly toward region B. Further, a part of region B is covered by the first extension segment of the gate structure 725. The second extension segment of the gate structure 725 extends outwardly toward sub-region A2. Further, a part of sub-region A2 is covered by the second extension segment of the gate structure 725. In this embodiment, the polysilicon gate layer 715 of the gate structure 725 functions as a floating gate. The polysilicon gate layer 713 of the gate structure 723 functions as a select gate. In one embodiment, the channel length LF of the floating gate transistor is shorter than the channel length LS of the select transistor. That is, LF < LS.

[0085] Hereinafter, the doping process will be described in more detail with reference to a cross-sectional view taken along the e-f line of the structure shown in FIG. 7B.

[0086] Please refer to FIG. 7C. First, the gate structure 725 in region A and the regions on both sides thereof are covered with a mask 740 indicated by a dotted line. The gate structure 723 and the regions on both sides thereof are exposed. Further, region B is exposed. That is, only a part of the surface between the gate structure 723 and the gate structure 725 is covered with the mask 740, and the other part of the surface between the gate structure 723 and the gate structure 725 is not covered with the mask 740. Next, a first low-concentration doped drain process (LDD process) is executed. As a result, n-type low-concentration doped drain regions (n-LDD regions) 741, 742, and 743 are formed on the surface of the semiconductor substrate Sub not covered by the mask 740. The n-LDD regions 741 and 742 are formed under the surface of region A and are respectively disposed laterally on both sides of the gate structure 723. The n-LDD region 743 is formed under the surface of region B and is disposed laterally of the gate structure 725.

[0087] Please refer to FIG. 7D. After the mask 740 is removed, the gate structure 723 (and its side regions) in regions A and B are covered with a mask 750 indicated by a dotted line. In other words, the regions previously covered by the mask 740 are exposed. Next, a second LDD process is executed. As a result, n-type low-concentration doped drain regions (n-LDD regions) 751 and 752 are formed on the surface of the semiconductor substrate Sub not covered by the mask 750. The n-LDD regions 751 and 752 are formed under the surface of region A and are respectively disposed laterally on both sides of the gate structure 725.

[0088] For example, the masks 740 and 750 are photoresists. In one embodiment, the dopant concentrations of the n-LDD regions 751 and 752 are smaller than the dopant concentrations of the n-LDD regions 741, 742, and 743.

[0089] Refer to FIG. 7E. After removing the mask 750, spacers 748 are formed on the sidewalls of the gate structure 723, and spacers 758 are formed on the sidewalls of the gate structure 725. After forming the spacers 748 and 758, a p-type ion implantation process is performed on the surface of the semiconductor substrate Sub using the two gate structures 723 and 725 and the two spacers 748 and 758 as masks. As a result, three p-type ion implantation regions 761, 762, and 763 indicated by hatching are formed in three sub-regions of the region A not covered by the two gate structures 723 and 725 and the two spacers 748 and 758, and a p-type ion implantation region 764 indicated by hatching is formed in the region B not covered by the gate structure 725 and the spacer 758. In particular, the p-type ion implantation regions 761, 762, 763, and 764 have the highest doping concentration, and their dopant concentration is higher than the dopant concentration of the p-LDD regions 741, 742, 743, 751, and 752.

[0090] Refer to FIG. 7E. Next, the p-LDD region 741 and the p-type ion implantation region 761 are formed as a merged p-doped region 771 in cooperation. The merged p-doped region 771 is formed on the surface of the semiconductor substrate Sub and is disposed adjacent to the first side of the gate structure 723. The p-LDD region 742, the p-LDD region 751, and the p-type ion implantation region 762 are formed as a merged p-doped region 772 in cooperation. The merged p-doped region 772 is formed on the surface of the semiconductor substrate Sub and is disposed between the second side of the gate structure 723 and the first side of the gate structure 775. The p-LDD region 752 and the p-type ion implantation region 763 are formed as a merged p-doped region 773 in cooperation. The merged p-doped region 773 is formed on the surface of the semiconductor substrate Sub and is disposed adjacent to the second side of the gate structure 775. The p-LDD region 743 and the p-type ion implantation region 764 are formed as a merged p-type doped region 774 in cooperation. The merged p-type doped region 774 is formed on the surface of the semiconductor substrate Sub and is disposed beside the extension of the gate structure 725. A bird's-eye view of the structure of FIG. 7E is shown in FIG. 7F.

[0091] In region A, the gate structure 723 and the merged n-doped regions 771 and 772 on both sides thereof cooperate to form a selection transistor. Also, the gate structure 725 and the two merged n-doped regions 772 and 773 on both sides thereof cooperate to form a floating gate transistor. In this embodiment, the floating gate transistor and the selection transistor are n-type transistors and are formed within the P-well region PW. That is, the body terminals of the floating gate transistor and the selection transistor are connected to the P-well region PW.

[0092] The n-doped region 773 is the drain / source terminal of the floating transistor. Further, the n-doped region 773 can function as an assist gate region. That is, the second extension segment of the gate structure 725 extends outward to the region beside the assist gate region. As a result, the assist gate region and the gate structure 725 cooperate to form an n-type transistor. Further, the n-type transistor is connected as a MOS capacitor.

[0093] In region B, the n-type doped region 774 is an erase gate region. The first extension segment of the gate structure 725 extends outward to the region beside the erase gate region. As a result, the erase gate region and the gate structure 725 cooperate to form an n-type transistor. Further, the n-type transistor is connected as another MOS capacitor.

[0094] Refer to FIG. 7G. When the process of forming the metal conductor line is completed, the memory cell according to this embodiment is manufactured. That is, the n-type doped region 771 is connected to the source line SL, the n-type doped region 773 is connected to the bit line BL, the n-type doped region 775 is connected to the erase line EL, and the polysilicon gate layer 713 is connected to the selection gate line SG.

[0095] As shown in FIG. 7H, the equivalent circuit of the memory cell according to this embodiment includes a selection transistor MS, a floating gate transistor MF, a first MOS capacitor CEG, and a second MOS capacitor CAG.

[0096] The gate terminal of the selection transistor MS is connected to the selection gate line SG. The first drain / source terminal of the selection transistor MS is connected to the source line SL. The first drain / source terminal of the floating gate transistor MF is connected to the second drain / source terminal of the selection transistor MS. The second drain / source terminal of the floating gate transistor MF is connected to the bit line BL. The first terminal of the first MOS capacitor CEG is connected to the floating gate 715 of the floating gate transistor MF. The second terminal of the first MOS capacitor CEG is connected to the erase line EL. The first terminal of the second MOS capacitor CAG is connected to the floating gate 715 of the floating gate transistor MF. The second terminal of the second MOS capacitor CAG is connected to the bit line BL.

[0097] Since the memory cell according to the second embodiment is composed of two transistors MS and MF and two capacitors CEG and CAG, this memory cell may be called a 2T2C cell.

[0098] By applying an appropriate bias voltage to the memory cell according to the second embodiment, a program operation (PGM), an erase operation (ERS), or a read operation (Read) can be executed. In this embodiment, an assist gate line AG is not implemented in the memory cell. Therefore, in the bias voltage table shown in FIG. 2J, the bias voltage corresponding to the assist gate line AG is ignored. Since the operation of the memory cell according to the second embodiment is the same as that of the first embodiment, it will not be described repeatedly here.

[0099] Please refer to FIG. 7E again. In the merged n-doped region 772, the n-LDD region 751 closer to the first side of the gate structure 725 of the floating gate transistor MF has a lower dopant concentration. In the merged n-doped region 773, the n-LDD region 752 closer to the second side of the gate structure 725 of the floating gate transistor MF has a lower dopant concentration. In the merged n-doped region 771, the n-LDD region 741 closer to the first side of the gate structure 723 of the selection transistor MS has a higher dopant concentration. In the merged n-doped region 772, the n-LDD region 742 closer to the first side of the gate structure 723 of the selection transistor MS has a higher dopant concentration. The dopant concentration difference near the channel affects the channel resistance value of the floating gate transistor MF and the channel resistance value of the selection transistor MS. Therefore, the channel resistance value of the floating gate transistor MF is larger than the channel resistance value of the selection transistor MS.

[0100] Note that the doping process of the second embodiment can be changed with reference to the modification of the first embodiment. That is, the first modification of FIGS. 3A, 3B, and 3C, the second modification of FIGS. 4A, 4B, and 4C, the third modification of FIGS. 5A, 5B, and 5C, or the fourth modification of FIG. 6 can be applied to the memory cell according to the second embodiment. By using these modifications, the channel resistance value of the floating gate transistor MF becomes larger than the channel resistance value of the selection transistor MS.

[0101] In the foregoing embodiments, the floating gate transistor MF and the selection transistor MS of the memory cell are n-type transistors. That is, the LDD region is an n-type LDD region, and the ion implantation region is an n-type ion implantation region. It should be noted that various modifications and changes are possible while maintaining the teachings of the present invention. For example, in another embodiment, the floating gate transistor MF and the selection transistor MS of the memory cell are p-type transistors. That is, the LDD region is a p-type LDD region, and the ion implantation region is a p-type ion implantation region. Further, the p-type LDD region and the p-type ion implantation region are formed within the N-well region. Similarly, the MOS transistors CMOS, CEG, and CAG are p-type transistors.

[0102] From the above description, the present invention provides an erasable programmable single-layer poly non-volatile memory cell. In the foregoing embodiments, the memory cell is a 2T2C cell. Of course, the inventive concept of the present invention can also be applied to 2T1C cells. For example, in the example of FIG. 2I, a memory cell without the plate capacitors CP1, CP2, and CP3 can be regarded as a 2T1C cell. Similarly, in the example of FIG. 7H, a memory cell without the MOS capacitor CAG can be regarded as a 2T1C cell.

[0103] Although the present invention has been described with respect to the presently most practical and preferred embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, it is intended to contain various changes and similar configurations included within the spirit and scope of the appended claims, and the claims should be construed as broadly as possible so as to encompass all such changes and similar structures.

Claims

1. an isolation structure formed on a semiconductor substrate, the isolation structure dividing a surface of the semiconductor substrate into a first region and a second region; a first well region formed on a surface of the semiconductor substrate corresponding to the first region; a second well region formed on a surface of the semiconductor substrate corresponding to the second region; a first gate structure and a second gate structure formed on a surface of the semiconductor substrate corresponding to the first region, the first gate structure and the second gate structure dividing a region of the surface of the semiconductor substrate corresponding to the first region into a first merged doped region, a second merged doped region and a third merged doped region; a fourth merged doped region formed in a surface of the semiconductor substrate corresponding to the second region and located to the side of the second gate structure; having the first merged doped region is disposed laterally to a first side of the first gate structure, the second merged doped region is disposed between a second side of the first gate structure and a first side of the second gate structure, and the third merged doped region is disposed laterally to a second side of the second gate structure; the second gate structure extends outwardly through a surface of the isolation structure toward the second region, a portion of the second region being covered by the second gate structure; the first merged doped region, the first gate structure, and the second merged doped region are formed together as a select transistor, the second merged doped region, the second gate structure, and the third merged doped region are formed together as a floating gate transistor, and the second gate structure and the fourth merged doped region are formed together as a first MOS capacitor, and a channel resistance value of the floating gate transistor is greater than a channel resistance value of the select transistor; Erasable and programmable single-poly non-volatile memory cell.

2. the first merged doped region includes a first ion implantation region and a first lightly doped drain region, the second merged doped region includes a second ion implantation region, a second lightly doped drain region and a third lightly doped drain region, the third merged doped region includes a third ion implantation region and a fourth lightly doped drain region, the first lightly doped drain region is disposed laterally to the first side of the first gate structure, the second lightly doped drain region is disposed laterally to the second side of the first gate structure, the third lightly doped drain region is disposed laterally to the first side of the second gate structure, and the fourth lightly doped drain region is disposed laterally to the second side of the first gate structure.

10. The erasable programmable single-poly non-volatile memory cell of claim 1.

3. a dopant concentration of the first lightly doped drain region is equal to a dopant concentration of the second lightly doped drain region, a dopant concentration of the third lightly doped drain region is equal to a dopant concentration of the fourth lightly doped drain region, and a dopant concentration of the fourth lightly doped drain region is lower than a dopant concentration of the first lightly doped drain region; 3. The erasable programmable single-poly nonvolatile memory cell of claim 2.

4. a dopant concentration of the fourth lightly doped drain region, a dopant concentration of the third lightly doped drain region, and a dopant concentration of the second lightly doped drain region are the same, and a dopant concentration of the fourth lightly doped drain region is lower than a dopant concentration of the first lightly doped drain region; 3. The erasable programmable single-poly nonvolatile memory cell of claim 2.

5. a dopant concentration of the first lightly doped drain region, a dopant concentration of the second lightly doped drain region, and a dopant concentration of the third lightly doped drain region are equal to each other, and a dopant concentration of the fourth lightly doped drain region is lower than a dopant concentration of the first lightly doped drain region; 3. The erasable programmable single-poly nonvolatile memory cell of claim 2.

6. a first anti-punchthrough implant region, the first anti-punchthrough implant region in contact with the fourth lightly doped drain region.

3. The erasable programmable single-poly nonvolatile memory cell of claim 2.

7. a first anti-punchthrough implant region, the first anti-punchthrough implant region contacting the third lightly doped drain region.

3. The erasable programmable single-poly nonvolatile memory cell of claim 2.

8. a first anti-punchthrough implant region and a second anti-punchthrough implant region, the first anti-punchthrough implant region contacting the fourth lightly doped drain region and the second anti-punchthrough implant region contacting the third lightly doped drain region.

3. The erasable programmable single-poly nonvolatile memory cell of claim 2.

9. a first anti-punchthrough prevention region, a second anti-punchthrough implant region, and a third anti-punchthrough implant region, the first anti-punchthrough implant region contacting the fourth lightly doped drain region, the second anti-punchthrough implant region contacting the third lightly doped drain region, and the third anti-punchthrough implant region contacting the second lightly doped drain region.

3. The erasable programmable single-poly nonvolatile memory cell of claim 2.

10. a first anti-punchthrough implant region, a second anti-punchthrough implant region and a third anti-punchthrough implant region, the first anti-punchthrough implant region contacting the fourth lightly doped drain region, the second anti-punchthrough implant region contacting the third lightly doped drain region, and the third anti-punchthrough implant region contacting the first lightly doped drain region.

3. The erasable programmable single-poly nonvolatile memory cell of claim 2.

11. a channel doped region formed in a surface of the semiconductor substrate and disposed below the second gate structure, the channel doped region and the second merged doped region having different dopant types; 3. The erasable programmable single-poly nonvolatile memory cell of claim 2.

12. a third gate structure formed on the isolation structure and disposed laterally of the first side of the second gate structure, the third gate structure and the second gate structure cooperatively forming a first poly / poly plate capacitor.

10. The erasable programmable single-poly non-volatile memory cell of claim 1.

13. a fourth gate structure, the fourth gate structure being formed on the isolation structure and disposed laterally on the second side of the second gate structure, the fourth gate structure and the second gate structure cooperatively forming a second poly / poly plate capacitor, the second poly / poly plate capacitor and the first poly / poly plate capacitor being connected in parallel with each other; 13. The erasable programmable single-poly non-volatile memory cell of claim 12.

14. a metal layer formed on the second gate structure, the metal layer and the second gate structure cooperatively formed as a metal / poly plate capacitor, the metal / poly plate capacitor and the first poly / poly plate capacitor being connected in parallel with each other; 13. The erasable programmable single-poly non-volatile memory cell of claim 12.

15. the third gate structure is connected to an assist gate line, the first gate structure is connected to a select gate line, the first merged doped region is connected to a source line, the third merged doped region is connected to a bit line, and the fourth merged doped region is connected to an erase line; 13. The erasable programmable single-poly non-volatile memory cell of claim 12.

16. When a program operation is performed, a ground voltage is applied to the source line, a program voltage is applied to the select gate line, the program voltage is applied to the bit line, a first voltage in a range between the ground voltage and an erase voltage is applied to the erase line, and a second voltage in a range between the ground voltage and an assist gate voltage is applied to the assist gate line, the assist gate voltage being higher than the erase voltage, the erase voltage being higher than the program voltage, and the program voltage being higher than the ground voltage.

16. The erasable programmable single-poly nonvolatile memory cell of claim 15.

17. When an erase operation is performed, a ground voltage is applied to the source line, the ground voltage is applied to the select gate line, the ground voltage is applied to the bit line, an erase voltage is applied to the erase line, and a voltage in a range between a negative assist gate voltage and the ground voltage is applied to the assist gate line, the assist gate voltage being higher than the erase voltage, and the erase voltage being higher than the ground voltage.

16. The erasable programmable single-poly nonvolatile memory cell of claim 15.

18. When a read operation is performed, a ground voltage is applied to the source line, a read voltage is applied to the select gate line, the read voltage is applied to the bit line, the ground voltage is applied to the erase line, and a voltage in a range between a negative assist gate voltage and a positive assist gate voltage is applied to the assist gate line, the assist gate voltage being higher than the read voltage, and the read voltage being higher than the ground voltage.

16. The erasable programmable single-poly nonvolatile memory cell of claim 15.

19. the second gate structure has an extension portion extending through a surface of the isolation structure toward the third merged doped region, the extension portion of the second gate structure and the third merged doped region cooperate to form a second MOS capacitor, the first gate structure is connected to a select gate line, the first merged doped region is connected to a source line, the third merged doped region is connected to a bit line, and the fourth merged doped region is connected to an erase line; 10. The erasable programmable single-poly non-volatile memory cell of claim 1.

20. the channel length of the floating gate transistor is shorter than the channel length of the select transistor; 10. The erasable programmable single-poly non-volatile memory cell of claim 1.

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