Semiconductor device

Abstract

To provide a high-reliability semiconductor device capable of obtaining excellent characteristics for each of transistors of different characteristics.SOLUTION: A semiconductor device comprises: a first semiconductor layer; a first gate electrode opposed to the first semiconductor layer; a second gate electrode which is opposed to the first semiconductor layer and to which the same voltage as the first gate electrode is supplied; a first gate insulation layer between the first semiconductor layer and the first gate electrode and between the first semiconductor layer and the second gate electrode; a second semiconductor layer holding the first gate electrode together with the first semiconductor layer; a third gate electrode which is opposed to the second semiconductor layer and overlapping with the first gate electrode in a planar view at an opposite side of the first gate electrode with the second semiconductor layer defined as a reference; and a second gate insulation layer between the second semiconductor layer and the third gate electrode.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device.

Background Art

[0002] In recent years, the development of semiconductor devices in which transistors having different semiconductor materials as semiconductor layers are formed on the same substrate has been advanced. For example, for transistors that require high-speed operation, transistors using polysilicon are used, and for transistors that require a switching operation with low leakage current in the off state, transistors using an oxide semiconductor are used, so that transistors having different characteristics according to the required functions can be formed on the same substrate.

[0003] Patent Document 1 discloses a display device in which transistors using silicon are formed in a drive circuit in a peripheral region and transistors using an oxide semiconductor are formed in a pixel circuit in a display region on the same substrate.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] One object of one embodiment of the present invention is to provide a semiconductor device that exhibits good electrical characteristics for each of transistors having different characteristics and has high reliability.

Means for Solving the Problems

[0006] A semiconductor device according to an embodiment of the present invention includes a first semiconductor layer, a first gate electrode facing the first semiconductor layer, a second gate electrode facing the first semiconductor layer and supplied with the same voltage as the first gate electrode, a first gate insulating layer between the first semiconductor layer and the first gate electrode and between the first semiconductor layer and the second gate electrode, a second semiconductor layer sandwiching the first gate electrode together with the first semiconductor layer, a third gate electrode facing the second semiconductor layer on the side opposite to the first gate electrode with respect to the second semiconductor layer and overlapping the first gate electrode in plan view, and a second gate insulating layer between the second semiconductor layer and the third gate electrode.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Embodiments for Carrying Out the Invention

[0008] Embodiments of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that can be easily conceived by those skilled in the art by appropriately changing the configuration of the embodiments while maintaining the gist of the invention are naturally included in the scope of the present invention. For the sake of clarity in the description, the drawings may be schematically represented in terms of the width, thickness, shape, etc. of each part as compared with the actual aspect. However, the illustrated shape is merely an example and does not limit the interpretation of the present invention. In this specification and each drawing, components having the same configuration as those described above with respect to the previously shown drawings may be denoted by the same reference numerals, and detailed description thereof may be omitted as appropriate.

[0009] In each embodiment of the present invention, the direction from the substrate toward the semiconductor layer is referred to as up or upward. Conversely, the direction from the semiconductor layer toward the substrate is referred to as down or downward. Thus, for the sake of convenience in the description, the terms up or downward are used for explanation. However, for example, the vertical relationship between the substrate and the semiconductor layer may be arranged in a direction different from the illustration. In the following description, for example, the expression a semiconductor layer on a substrate merely explains the vertical relationship between the substrate and the semiconductor layer as described above, and other members may be arranged between the substrate and the semiconductor layer. Up or downward means the stacking order in a structure in which a plurality of layers are stacked. When expressing the second member above the first member, in a plan view, the positional relationship may be such that the first member and the second member do not overlap. On the other hand, when expressing the second member directly above the first member, in a plan view, it means the positional relationship in which the first member and the second member overlap.

[0010] In this specification, expressions such as "α includes A, B, or C", "α includes any one of A, B, and C", "α includes one selected from the group consisting of A, B, and C" do not exclude the case where α includes a plurality of combinations of A to C unless otherwise specified. Furthermore, these expressions do not exclude the case where α includes other elements.

[0011] Note that the following-described configurations can be combined with each other as long as no technical contradiction occurs.

[0012] [1. Cross-sectional Structure of Semiconductor Device] An example of the structure of the semiconductor device 10 according to an embodiment of the present invention will be described with reference to FIGS. 1 to 3. FIG. 1 is a cross-sectional view of the semiconductor device 10 according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor device 10 according to an embodiment of the present invention includes a transistor 100 provided on a substrate 101 and a transistor 200 provided above the transistor 100.

[0013] As the transistor 100, either an N-type transistor or a P-type transistor may be used. In this embodiment, an example in which a top-gate type P-type transistor using polysilicon in a semiconductor layer is used as the transistor 100 will be described.

[0014] As the transistor 200, either an N-type transistor or a P-type transistor may be used. In this embodiment, an example in which a dual-gate type N-type transistor using an oxide semiconductor in a semiconductor layer is used as the transistor 200 will be described.

[0015] In this embodiment, the transistor 100 is a P-type transistor and the transistor 200 is an N-type transistor. Therefore, the semiconductor device 10 constitutes a CMOS (Complementary Metal-Oxide-Semiconductor) circuit. However, an embodiment of the present invention is not limited to the above CMOS circuit. For example, the transistor 100 may be an N-type transistor and the transistor 200 may be a P-type transistor. Or, an embodiment of the present invention may not be a CMOS circuit. That is, both of the transistors 100 and 200 may be N-type transistors or P-type transistors.

[0016] [1-1. Structure of Transistor 100] The transistor 100 has a semiconductor layer 110, a gate insulating layer 120, gate electrodes 130, 140, and electrodes 150, 160. An insulating layer 102 is provided on a substrate 101. The insulating layer 102 suppresses the diffusion of impurities contained in the substrate 101 into the semiconductor layer 110. That is, the insulating layer 102 has barrier properties.

[0017] The semiconductor layer 110 is provided on the insulating layer 102. The semiconductor layer 110 is divided into channel regions 111, 112 and low-resistance regions 113 to 115. Impurities (dopants) are mixed into the semiconductor layer 110 in the low-resistance regions 113 to 115, and carriers are generated in the semiconductor layer 110 by the dopants. The dopants are not mixed or are slightly mixed into the semiconductor layer 110 in the channel regions 111, 112. That is, the dopant concentration in the low-resistance regions 113 to 115 is higher than the dopant concentration in the channel regions 111, 112. When the material used as the semiconductor layer 110 is silicon and the transistor 100 is a P-type transistor, boron is used as the dopant. On the other hand, when the transistor 100 is an N-type transistor, phosphorus is used as the dopant.

[0018] The gate electrodes 130, 140 face the semiconductor layer 110. Specifically, the gate electrode 130 faces the semiconductor layer 110 in the channel region 111. The gate electrode 140 faces the semiconductor layer 110 in the channel region 112. The gate insulating layer 120 is provided between the gate electrode 130 and the semiconductor layer 110 and between the gate electrode 140 and the semiconductor layer 110. The gate electrode 130 and the gate electrode 140 are provided in the same layer. That is, the gate electrode 130 and the gate electrode 140 are in contact with the gate insulating layer 120. In the D1 direction from the electrode 150 to the electrode 160, the length of the gate electrode 140 is smaller than the length of the gate electrode 130. Although details will be described later, the gate electrode 130 is connected to the gate electrode 140, and the same voltage as that of the gate electrode 130 is supplied to the gate electrode 140.

[0019] The channel regions 111, 112 and the low-resistance regions 113 to 115 are arranged in the order of the low-resistance region 113, the channel region 111, the low-resistance region 114, the channel region 112, and the low-resistance region 115 between the electrode 150 and the electrode 160. The electrode 150 is connected to the low-resistance region 113, and the electrode 160 is connected to the low-resistance region 115, but no electrode is connected to the low-resistance region 114. Therefore, when both of the channel regions 111 and 112 are in the off state, the low-resistance region 114 is in a floating state. As described above, the transistor 100 has a so-called double-gate structure in which the on state and the off state are controlled by the two gate electrodes 130 and 140.

[0020] In the above configuration, the semiconductor layer 110 may be referred to as the "first semiconductor layer", the gate electrode 130 may be referred to as the "first gate electrode", the gate electrode 140 may be referred to as the "second gate electrode", and the gate insulating layer 120 may be referred to as the "first gate insulating layer". In this case, it can be said that the first gate electrode (gate electrode 130) and the second gate electrode (gate electrode 140) face the first semiconductor layer (semiconductor layer 110). It can be said that the same voltage as that of the first gate electrode (gate electrode 130) is supplied to the second gate electrode (gate electrode 140). It can be said that the first gate insulating layer (gate insulating layer 120) is provided between the first semiconductor layer (semiconductor layer 110) and the first gate electrode (gate electrode 130) and between the first semiconductor layer (semiconductor layer 110) and the second gate electrode (gate electrode 140).

[0021] Although details will be described later, in a plan view, the channel region 111 overlaps with the gate electrode 130, and the channel region 112 overlaps with the gate electrode 140. However, the transistor 100 is not limited to the above configuration. For example, in a plan view, a part of the low-resistance regions 113 to 115 may overlap with the gate electrodes 130 and 140.

[0022] An LDD (Lightly Doped Drain) region may be provided between the channel regions 111 and 112 and the low-resistance regions 113 to 115. The dopant concentration of the LDD region is higher than that of the channel regions 111 and 112 and lower than that of the low-resistance regions 113 to 115. The LDD regions are provided between the low-resistance region 113 and the channel region 111, between the low-resistance region 114 and the channel region 111, between the low-resistance region 114 and the channel region 112, and between the low-resistance region 115 and the channel region 112.

[0023] An insulating layer 170 is provided over the gate insulating layer 120 and the gate electrodes 130 and 140. Openings 171 and 172 are provided in the insulating layer 170. The opening 171 is an opening reaching the semiconductor layer 110 of the low-resistance region 113. The opening 172 is an opening reaching the semiconductor layer 110 of the low-resistance region 115.

[0024] The electrode 150 is provided inside the opening 171 and is in contact with the semiconductor layer 110 of the low-resistance region 113. The electrode 160 is provided inside the opening 172 and is in contact with the semiconductor layer 110 of the low-resistance region 115.

[0025] [1-2. Structure of Transistor 200] The transistor 200 includes a semiconductor layer 210, a gate insulating layer 220, a gate electrode 230, and electrodes 250 and 260.

[0026] The semiconductor layer 210 is provided over the insulating layer 170. The semiconductor layer 210 is divided into a channel region 211 and low-resistance regions 213 and 214. Dopants are mixed into the semiconductor layer 210 of the low-resistance regions 213 and 214, and carriers are generated in the semiconductor layer 210 by the dopants. No dopants or a small amount of dopants are mixed into the semiconductor layer 210 of the channel region 211. That is, the dopant concentration of the low-resistance regions 213 and 214 is higher than that of the channel region 211. When the material used as the semiconductor layer 210 is an oxide semiconductor, phosphorus, boron, argon, etc. are used as dopants.

[0027] When an oxide semiconductor having a polycrystalline structure described later is used as the semiconductor layer 210, the sheet resistance of the low-resistance region can be made lower than that of an oxide semiconductor having a conventional amorphous structure. For example, the sheet resistance of the oxide semiconductor layer in the low-resistance regions 213 and 214 is 1000 Ω / sq. or less, preferably 500 Ω / sq. or less, and more preferably 250 Ω / sq. or less.

[0028] The gate electrode 230 faces the semiconductor layer 210. Specifically, the gate electrode 230 faces the semiconductor layer 210 in the channel region 211. A gate insulating layer 220 is provided between the gate electrode 230 and the semiconductor layer 210. The gate electrode 230 is formed in the same layer as the electrodes 150 and 160. That is, the gate electrode 230 and the electrodes 150 and 160 are in contact with the upper surface of the gate insulating layer 220. Openings 221 and 222 are provided in the gate insulating layer 220 at positions corresponding to the openings 171 and 172. The electrode 150 is provided inside the opening 221. The electrode 160 is provided inside the opening 222.

[0029] Although details will be described later, the gate electrode 230 is electrically connected to the gate electrode 130. That is, the same voltage as that of the gate electrode 130 is supplied to the gate electrode 230. In the D1 direction, the length of the gate electrode 230 is smaller than the length of the gate electrode 130.

[0030] In the above configuration, the semiconductor layer 210 may be referred to as the "second semiconductor layer", the gate electrode 230 may be referred to as the "third gate electrode", and the gate insulating layer 220 may be referred to as the "second gate insulating layer". In this case, it can be said that the second semiconductor layer (semiconductor layer 210) sandwiches the first gate electrode (gate electrode 130) together with the first semiconductor layer (semiconductor layer 110). The third gate electrode (gate electrode 230) can be said to face the second semiconductor layer (semiconductor layer 210) on the side opposite to the first gate electrode (gate electrode 130) with respect to the second semiconductor layer (semiconductor layer 210). The second gate insulating layer (gate insulating layer 220) can be said to be provided between the second semiconductor layer (semiconductor layer 210) and the third gate electrode (gate electrode 230).

[0031] In the above configuration, the electrode 150 may be referred to as the "first electrode", and the electrode 160 may be referred to as the "second electrode". The low-resistance region 113 may be referred to as the "first region", and the low-resistance region 115 may be referred to as the "second region". In this case, it can be said that the first electrode (electrode 150) is connected to the first region (low-resistance region 113) of the first semiconductor layer (semiconductor layer 110). The second electrode (electrode 160) can be said to be connected to the second region (low-resistance region 115) of the first semiconductor layer (semiconductor layer 110) on the side opposite to the first electrode (electrode 150) with respect to the first gate electrode (gate electrode 130) and the second gate electrode (gate electrode 140). Furthermore, in a cross-sectional view (the cross-sectional view shown in FIG. 1) along the line connecting the first region (low-resistance region 113) and the second region (low-resistance region 115) (the A-B line in FIG. 3), it can be said that the first gate electrode (gate electrode 130) and the second gate electrode (gate electrode 140) are separated from each other.

[0032] In the above configuration, the electrode 250 may be referred to as the "third electrode", and the electrode 260 may be referred to as the "fourth electrode". The low-resistance region 213 may be referred to as the "third region", and the low-resistance region 214 may be referred to as the "fourth region". In this case, it can be said that the third electrode (electrode 250) is connected to the third region (low-resistance region 213) of the second semiconductor layer (semiconductor layer 210). The fourth electrode (electrode 260) can be said to be connected to the fourth region (low-resistance region 214) of the second semiconductor layer (semiconductor layer 210) on the side opposite to the third electrode (electrode 250) with reference to the third gate electrode (gate electrode 230). Different voltages can be supplied to the second electrode (electrode 160) and the fourth electrode (electrode 260) respectively. The first electrode (electrode 150) and the third electrode (electrode 250) can be said to be electrically connected. The first electrode (electrode 150) and the third gate electrode (gate electrode 230) can be said to be in the same layer.

[0033] Details will be described later. In a plan view, the channel region 211 overlaps with the gate electrode 230. However, the transistor 200 is not limited to the above configuration. For example, in a plan view, a part of the low-resistance regions 213 and 214 may overlap with the gate electrode 230.

[0034] An insulating layer 270 is provided on the gate insulating layer 220 and the gate electrode 230. Openings 271 and 272 are provided in the insulating layer 270. The opening 271 is an opening that reaches the upper surface of the electrode 150 and the semiconductor layer 210 of the low-resistance region 213. Details will be described later. In a plan view, the opening 271 overlaps with the pattern end of the electrode 150. The opening 272 is an opening that reaches the semiconductor layer 210 of the low-resistance region 214.

[0035] The electrode 250 is provided on the upper surface of the insulating layer 270 and inside the opening 271, and is in contact with the upper surface of the electrode 150 and the semiconductor layer 210 of the low-resistance region 213. Since the pattern end of the electrode 150 is exposed by the opening 271, the electrode 250 is in contact with the pattern end. The electrode 260 is provided on the upper surface of the insulating layer 270 and inside the opening 272, and is in contact with the semiconductor layer 210 of the low-resistance region 214.

[0036] Above the transistor 200, a light-shielding layer 290 is provided. The light-shielding layer 290 is provided in at least a region that covers the channel region 211 in plan view. The light-shielding layer 290 suppresses external light incident on the semiconductor device 10 from above from reaching the semiconductor layer 210 of the channel region 211. Although external light incident on the semiconductor device 10 from below is blocked by the gate electrode 130, a light-shielding layer similar to the light-shielding layer 290 may be provided under the transistor 100.

[0037] In the present embodiment, the semiconductor device 10 constitutes a CMOS circuit including a P-type transistor 100 and an N-type transistor 200. A voltage Vdd is supplied to the electrode 160 of the transistor 100. A voltage Vss is supplied to the electrode 260 of the transistor 200. An input signal IN is supplied to the gate electrodes 130, 140 of the transistor 100 and the gate electrode 230 of the transistor 200, and an output signal OUT with respect to the input signal IN is output from the electrode 250 of the transistor 200 and / or the electrode 150 of the transistor 100.

[0038] [2. Circuit Configuration of Semiconductor Device] FIG. 2 shows a circuit configuration of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 2, the transistor 100 and the transistor 200 are connected in series between the voltage Vdd and the voltage Vss. The gate electrodes 130, 140 of the transistor 100 and the gate electrode 230 of the transistor 200 are connected, and a common input signal IN is supplied to these gate electrodes. An output signal OUT is output from a node (electrodes 150, 250) between the transistor 100 and the transistor 200.

[0039] [3. Planar Layout of Semiconductor Device] FIG. 3 is a plan view for explaining a semiconductor device according to an embodiment of the present invention. The cross-sectional view shown in FIG. 1 is a cross-sectional view taken along line A-B of FIG. 3. Using the plan view shown in FIG. 3, the layouts of the transistors 100 and 200 will be described.

[0040] The semiconductor layer 110 has a longitudinal direction in the D1 direction in which the line A-B extends. The gate electrode 130 and the gate electrode 140 cross the semiconductor layer 110 in the D2 direction. The gate electrode 130 is connected to the gate electrode 140 in a region that does not overlap the semiconductor layer 110 in plan view. The D2 direction is a direction that intersects the D1 direction. In the example of FIG. 1, the D2 direction is orthogonal to the D1 direction. However, the D2 direction may not be orthogonal to the D1 direction.

[0041] Among the semiconductor layer 110, the region that overlaps the gate electrode 130 in plan view is the channel region 111, and the region that overlaps the gate electrode 140 is the channel region 112. On the other hand, among the semiconductor layer 110, the regions that do not overlap either of the gate electrodes 130 and 140 in plan view are the low-resistance regions 113 to 115. The region closer to B than the gate electrode 130 is the low-resistance region 113. The region closer to A than the gate electrode 140 is the low-resistance region 115. The region between the gate electrode 130 and the gate electrode 140 is the low-resistance region 114.

[0042] The opening 171 is a region that overlaps the semiconductor layer 110 in plan view and is provided near the end closer to B. The electrode 150 is provided in a region that overlaps the opening 171 in plan view. The opening 172 is a region that overlaps the semiconductor layer 110 in plan view and is provided near the end closer to A. The electrode 160 is provided in a region that overlaps the opening 172 in plan view.

[0043] The semiconductor layer 210 has a longitudinal direction in the D1 direction, similar to the semiconductor layer 110. The semiconductor layer 210 overlaps the semiconductor layer 110 in plan view. Specifically, the pattern of the semiconductor layer 210 is located inside the pattern of the semiconductor layer 110 in plan view. That is, all of the outer edges of the pattern of the semiconductor layer 210 are surrounded by the outer edge of the pattern of the semiconductor layer 110. The gate electrode 230 crosses the semiconductor layer 210 in the D2 direction.

[0044] Of the semiconductor layer 210, the region overlapping with the gate electrode 230 in plan view is the channel region 211. On the other hand, in the semiconductor layer 210, the regions not overlapping with the gate electrode 230 in plan view are the low-resistance regions 213 and 214. The region closer to B than the gate electrode 230 is the low-resistance region 213. The region closer to A than the gate electrode 230 is the low-resistance region 214.

[0045] The gate electrode 230 overlaps with the gate electrode 130 in plan view. Specifically, the pattern of the gate electrode 230 is located inside the pattern of the gate electrode 130 in plan view. At least in the region overlapping with the semiconductor layer 110 in plan view, the pattern of the gate electrode 230 is located inside the pattern of the gate electrode 130. On the other hand, the gate electrode 230 does not overlap with the gate electrode 140 in plan view. The gate electrode 140 may be provided in any region other than the channel region 211 in the region between the opening 171 and the opening 172.

[0046] Although not shown in FIG. 1, an opening 231 is provided in the insulating layer 170 and the gate insulating layer 220 as shown in FIG. 3. The gate electrode 230 is connected to the gate electrode 130 through the opening 231. Since the same voltage is supplied to the gate electrodes 130 and 230, the transistor 200 operates as a dual-gate transistor controlled by a top gate (gate electrode 230) and a bottom gate (gate electrode 130).

[0047] The opening 272 is provided in a region overlapping with the semiconductor layer 210 in plan view. The opening 271 is provided in a region overlapping with the electrode 150 and the semiconductor layer 210 in plan view and overlapping with the pattern end of the electrode 150. By the opening 271 overlapping with the pattern end of the electrode 150, as shown in FIG. 1, the electrode 250 contacts both the electrode 150 and the semiconductor layer 210.

[0048] [4. Function of the semiconductor device] As shown in FIGS. 1 to 3, the transistor 100 is a double-gate transistor controlled by gate electrodes 130 and 140. Due to the double-gate structure, the source-drain voltage adjacent to the gate electrode 130 and the source-drain voltage adjacent to the gate electrode 140 can be reduced, so that the reduction in reliability due to hot carriers or the like can be suppressed. Furthermore, due to the double-gate structure, the electric field strength at each gate end can be lowered, so that the leakage current of the transistor 100 can be suppressed.

[0049] In the D1 direction, by making the length of the gate electrode 130 larger than the length of the gate electrode 230, the electric field generated in the channel region 211 of the transistor 200 by the gate electrode 130 can be made uniform, and furthermore, the light incident from the substrate 101 side reaching the semiconductor layer 210 can be suppressed.

[0050] In order to obtain the effect of suppressing the reduction in reliability as described above, it is only necessary to provide a low-resistance region 114 between the gate electrode 130 and the gate electrode 140, so that in the D1 direction, the length of the gate electrode 140 can be made smaller than the length of the gate electrode 130. Furthermore, according to the semiconductor device 10, the P-type transistor 100 and the N-type transistor 200 constituting the CMOS circuit can be stacked. In other words, in plan view, the channel region 111 of the transistor 100 and the channel region 211 of the transistor 200 overlap. By having such a feature, the circuit size of the semiconductor device 10 can be reduced. That is, the semiconductor device 10 has the effect of being able to suppress the reduction in reliability while reducing the circuit size.

[0051] [5. Materials of Each Member of the Semiconductor Device 10] As the substrate 101, a rigid substrate having translucency such as a glass substrate, a quartz substrate, and a sapphire substrate is used. When the substrate 101 needs to have flexibility, as the substrate 101, a substrate containing resin such as a polyimide substrate, an acrylic substrate, a siloxane substrate, and a fluororesin substrate is used. When a substrate containing resin is used as the substrate 101, impurities may be introduced into the above resin in order to improve the heat resistance of the substrate 101. In particular, when the semiconductor device 10 is a top emission type display device, since the substrate 101 does not need to be transparent, impurities that deteriorate the transparency of the substrate 101 may be used. When the semiconductor device 10 is used in an integrated circuit that is not a display device, as the substrate 101, a substrate that does not have translucency such as a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, and a compound semiconductor substrate, or a conductive substrate such as a stainless steel substrate is used.

[0052] As the semiconductor layer 110, for example, low-temperature polysilicon, amorphous silicon, and single-crystalline silicon are used.

[0053] As the conductive layer including the gate electrodes 130, 140, 230, and the electrodes 150, 160, 250, 260, a general metal material is used. For example, as these members, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof are used. As the above conductive layer, the above materials may be used in a single layer or in a laminated form.

[0054] As the insulating layer including the gate insulating layers 120, 220, and the insulating layers 102, 170, 270, a general insulating material is used. For example, as the insulating layer, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ), silicon nitride (SiNx ) Silicon oxynitride (SiN x O y ), aluminum nitride (AlN x ), aluminum oxynitride (AlN x O y ) and other inorganic insulating layers are used. As the above insulating layer, the above materials may be used singly or in a stacked manner.

[0055] As the insulating layers 170 and 270, an insulating layer having a function of releasing oxygen by heat treatment may be used. That is, as the insulating layers 170 and 270, an oxide insulating layer containing an excessive amount of oxygen may be used. The temperature of the heat treatment for the insulating layers 170 and 270 to release oxygen is, for example, 600 °C or lower, 500 °C or lower, 450 °C or lower, or 400 °C or lower. That is, the insulating layers 170 and 270 release oxygen at the heat treatment temperature performed in the manufacturing process of the semiconductor device 10 when a glass substrate is used as the substrate 101, for example.

[0056] As the gate insulating layers 120 and 220, an insulating layer with few defects is used. For example, when comparing the oxygen composition ratio in the gate insulating layers 120 and 220 with the oxygen composition ratio in an insulating layer having the same composition as the gate insulating layers 120 and 220 (hereinafter referred to as "other insulating layer"), the oxygen composition ratio in the gate insulating layers 120 and 220 is closer to the stoichiometric ratio of the insulating layer than the oxygen composition ratio in the other insulating layer. Specifically, when silicon oxide (SiO x ) is used for each of the gate insulating layers 120 and 220 and the insulating layers 170 and 270, the oxygen composition ratio in the silicon oxide used as the gate insulating layers 120 and 220 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio in the silicon oxide used as the insulating layers 170 and 270. For example, as the gate insulating layers 120 and 220, a layer in which no defects are observed when evaluated by the electron spin resonance method (ESR) may be used.

[0057] The above SiO x N y and AlO x N yIt is a silicon compound and an aluminum compound containing nitrogen (N) in a ratio less than that of oxygen (O) (x > y). SiN x O y and AlN x O y It is a silicon compound and an aluminum compound containing oxygen in a ratio less than that of nitrogen (x > y).

[0058] When an oxide semiconductor layer is used as the semiconductor layer 210, a metal oxide having semiconductor characteristics is used as the oxide semiconductor layer. For example, as the semiconductor layer 210, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) may be used. For example, as the semiconductor layer 210, an oxide semiconductor having a composition ratio of In:Ga:Zn:O = 1:1:1:4 may be used. However, the oxide semiconductor containing In, Ga, Zn, and O used in this embodiment is not limited to the above composition. As the oxide semiconductor, an oxide semiconductor having a composition different from the above may be used. For example, an oxide semiconductor layer in which the ratio of In is larger than the above may be used to improve mobility. On the other hand, an oxide semiconductor layer in which the ratio of Ga is larger than the above may be used to increase the bandgap and reduce the influence of light irradiation.

[0059] As the semiconductor layer 210, an oxide semiconductor containing two or more metals including indium (In) may be used. In this case, in the semiconductor layer 210, the ratio of indium element to all metal elements may be 50% or more in atomic ratio. As the semiconductor layer 210, in addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), and lanthanoids may be used. As the semiconductor layer 210, elements other than the above may be used.

[0060] As the semiconductor layer 210, other elements may be added to an oxide semiconductor containing In, Ga, Zn, and O. For example, metal elements such as Al and Sn may be added. In addition to the above oxide semiconductor, an oxide semiconductor containing In and Ga (IGO), an oxide semiconductor containing In and Zn (IZO), an oxide semiconductor containing In, Sn, and Zn (ITZO), and an oxide semiconductor containing In and W may be used as the semiconductor layer 210.

[0061] When the ratio of the indium element is large, the oxide semiconductor layer used as the semiconductor layer 210 is likely to crystallize. As described above, in the oxide semiconductor layer, by using a material in which the ratio of the indium element to all metal elements is 50% or more, an oxide semiconductor layer having a polycrystalline structure can be obtained. As a metal element other than indium, it is preferable that the oxide semiconductor layer contains gallium. Gallium belongs to the same Group 13 element as indium. Therefore, the crystallinity of the oxide semiconductor layer is not inhibited by gallium, and the oxide semiconductor layer has a polycrystalline structure.

[0062] The oxide semiconductor layer can be formed by a sputtering method. The composition of the oxide semiconductor layer formed by the sputtering method depends on the composition of the sputtering target. Even when the oxide semiconductor layer has a polycrystalline structure, the composition of the sputtering target and the composition of the oxide semiconductor layer are substantially the same. In this case, the composition of the metal elements in the oxide semiconductor layer can be specified based on the composition of the metal elements in the sputtering target.

[0063] When the oxide semiconductor layer has a polycrystalline structure, the composition of the oxide semiconductor layer may be specified using the X-ray Diffraction (XRD) method. Specifically, based on the crystal structure and lattice constant of the oxide semiconductor layer obtained by the XRD method, the composition of the metal elements in the oxide semiconductor layer can be specified. Furthermore, the composition of the metal elements in the oxide semiconductor layer can also be specified using fluorescent X-ray analysis or an Electron Probe Micro Analyzer (EPMA) analysis, etc. However, since the oxygen element contained in the oxide semiconductor layer changes depending on the process conditions of sputtering, etc., there are cases where it cannot be specified by these methods.

[0064] As described above, the oxide semiconductor layer may contain an amorphous structure or a polycrystalline structure. An oxide semiconductor having a polycrystalline structure can be manufactured using the Poly-OS (Poly-crystalline Oxide Semiconductor) technology described later. In the following description, when distinguishing from an oxide semiconductor having an amorphous structure, the oxide semiconductor having a polycrystalline structure may be described as Poly-OS for explanation.

[0065] Note that a semiconductor other than an oxide semiconductor may be used as the semiconductor layer 210. In that case, the semiconductor used as the semiconductor layer 210 is composed of a different material or a different composition from the semiconductor used for the semiconductor layer 110. That is, the transistor 100 has characteristics different from those of the transistor 200.

[0066] A metal oxide layer 300 may be provided between the insulating layer 170 and the semiconductor layer 210 (see FIG. 4). In this case, the metal oxide layer may be in contact with the semiconductor layer 210. As the metal oxide layer, a metal oxide mainly composed of aluminum is used. For example, as the metal oxide layer, aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ), aluminum nitride oxide (AlN x Oy ) An inorganic insulating layer such as this is used. The "metal oxide layer mainly composed of aluminum" means that the ratio of aluminum contained in the metal oxide layer is 1% or more of the entire metal oxide layer. The ratio of aluminum contained in the metal oxide layer may be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide layer. The above ratio may be a mass ratio or a weight ratio.

[0067] [6.Poly-OS Technology] As described above, the Poly-OS contained in the oxide semiconductor layer used as the semiconductor layer 210 can be formed using sputtering and heat treatment. Here, the method for forming the oxide semiconductor layer will be described.

[0068] First, an oxide semiconductor layer is formed by sputtering. The formed oxide semiconductor layer has an amorphous structure. Here, the amorphous structure refers to a structure in which there is no long-range order structure and no periodic crystal lattice arrangement can be seen. For example, when observing an oxide semiconductor layer having an amorphous structure using the XRD method, no specific peak based on the crystal structure can be obtained in the diffraction pattern. Note that an oxide semiconductor layer having an amorphous structure may have a short-range order structure in a minute region. However, since such an oxide semiconductor layer does not exhibit the characteristics of Poly-OS, it can be classified as an oxide semiconductor layer having an amorphous structure.

[0069] In the Poly-OS technology, the oxide semiconductor layer is formed at a low temperature. For example, the temperature of the substrate on which the oxide semiconductor layer is formed is 150°C or lower, preferably 100°C or lower, and more preferably 50°C or lower. When the temperature of the substrate is high while the oxide semiconductor layer is being formed, microcrystals are likely to be generated in the formed oxide semiconductor. The oxygen partial pressure in the chamber during film formation is 1% or more and 10% or less, preferably 1% or more and 5% or less, and more preferably 2% or more and 4% or less. When the oxygen partial pressure is high, microcrystals are generated in the oxide semiconductor layer due to the excessive oxygen contained in the oxide semiconductor. On the other hand, under the condition that the oxygen partial pressure is less than 1%, the oxygen composition in the oxide semiconductor layer becomes non-uniform, and an oxide semiconductor layer containing many microcrystals or an oxide semiconductor layer that does not crystallize even after heat treatment is formed.

[0070] Next, heat treatment is performed on the oxide semiconductor layer formed by sputtering. The heat treatment is performed in the atmosphere, but the atmosphere of the heat treatment is not limited to this. The temperature of the heat treatment is 300°C or higher and 500°C or lower, preferably 350°C or higher and 450°C or lower. The time of the heat treatment is 15 minutes or longer and 120 minutes or shorter, preferably 30 minutes or longer and 60 minutes or shorter. By performing the heat treatment, the oxide semiconductor layer having an amorphous structure is crystallized, and an oxide semiconductor layer containing Poly-OS is formed.

[0071] [7. Characteristics of Poly-OS] Subsequently, the characteristics of the oxide semiconductor layer used as the semiconductor layer 210 and containing Poly-OS will be described below.

[0072] The oxide semiconductor layer has excellent etching resistance. Specifically, when the oxide semiconductor layer is etched using an etching solution for wet etching, the etching rate is extremely low. This means that the oxide semiconductor layer is hardly etched by the etching solution. When the oxide semiconductor layer is etched using an etching solution containing phosphoric acid as the main component at a temperature of about 40°C, the etching rate is less than 3 nm / min, less than 2 nm / min, or less than 1 nm / min. The proportion of phosphoric acid in the etching solution is 50% or more, 60% or more, or 70% or more. The etching solution may contain nitric acid and acetic acid in addition to phosphoric acid. Note that the temperature of about 40°C mentioned above is the set temperature of the device holding the etching solution, and the actual temperature of the etching solution is 35°C or more and 45°C or less.

[0073] On the other hand, for an oxide semiconductor layer that does not contain Poly-OS, for example, an oxide semiconductor layer having an amorphous structure before heat treatment, when the oxide semiconductor layer is etched using an etching solution containing phosphoric acid as the main component at a temperature of about 40°C, the etching rate is 100 nm / min or more.

[0074] When the oxide semiconductor layer containing Poly-OS is etched using a 0.5% hydrofluoric acid solution at room temperature (for example, about 22°C), the etching rate is less than 5 nm / min, less than 4 nm / min, or less than 3 nm / min. Here, room temperature is 25°C ± 5°C. The actual temperature of the etching solution at this time is 20°C or more and 30°C or less.

[0075] On the other hand, when the oxide semiconductor layer that does not contain Poly-OS is etched using a 0.5% hydrofluoric acid solution at room temperature, the etching rate is 15 nm / min or more.

[0076] Here, Table 1 shows an example of the etching rate evaluation for the oxide semiconductor layer. Table 1 shows the etching rates for the mixed acid etching solution and the 0.5% hydrofluoric acid solution in each of the fabricated samples. As the mixed acid etching solution, "Mixed Acid AT-2F (product name)" of Rasa Industries Co., Ltd. was used. The proportion of phosphoric acid in the mixed acid etching solution is about 65%. When etching each sample, the temperature of the mixed acid etching solution was about 40°C, and the temperature of the 0.5% hydrofluoric acid solution was at room temperature. In Table 1, Sample 1 is an oxide semiconductor layer containing Poly-OS, Sample 2 is an oxide semiconductor layer having an amorphous structure before heat treatment, and Sample 3 is an oxide semiconductor layer containing indium gallium zinc oxide (IGZO) with an indium ratio of less than 50%.

[0077]

Table 1

[0078] As shown in Table 1, Sample 1 (oxide semiconductor layer containing Poly-OS) is hardly etched using the mixed acid etching solution, and is etched only at 2 nm / min even when using the 0.5% hydrofluoric acid solution. Compared with Sample 2 (oxide semiconductor layer having an amorphous structure before heat treatment), Sample 1 has an etching rate of 1 / 100 or less with the mixed acid etching solution and about 1 / 10 or less with the 0.5% hydrofluoric acid solution. Also, compared with Sample 3 (oxide semiconductor layer containing IGZO with an indium ratio of less than 50%), Sample 1 has an etching rate of 1 / 100 or less with the mixed acid etching solution. That is, Sample 1 is significantly more excellent in etching resistance than Sample 2 and Sample 3.

[0079] Such excellent etching resistance of the oxide semiconductor layer containing Poly-OS is a property that cannot be obtained with conventional oxide semiconductors having a polycrystalline structure fabricated by a process at 500°C or lower. Regarding the excellent etching resistance of the oxide semiconductor layer containing Poly-OS, although the detailed mechanism is unknown, it is considered that Poly-OS has a polycrystalline structure different from the conventional one.

[0080] As described above, the oxide semiconductor layer containing Poly-OS has a very small etching rate with respect to the etching solution. Therefore, patterning of the oxide semiconductor layer is very difficult. Therefore, when forming an island-shaped oxide semiconductor layer, the oxide semiconductor layer having an amorphous structure before heat treatment is patterned into an island shape, and then heat treatment is performed to crystallize it. Thereby, an island-shaped oxide semiconductor layer containing Poly-OS can be formed.

[0081] [8. Manufacturing method of semiconductor device 10] A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 5 to 8. FIGS. 5 to 8 are cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. In the method for manufacturing the semiconductor device 10 shown below, a configuration in which polysilicon is used as the semiconductor layer 110 and an oxide semiconductor (Poly-OS) is used as the semiconductor layer 210 will be described.

[0082] As shown in FIG. 5, first, a semiconductor layer composed of an insulating layer 102 and polysilicon is formed on a substrate 101, and the semiconductor layer is processed by a photolithography process to form a semiconductor layer 110. Next, a gate insulating layer 120 is formed on the insulating layer 102 and the semiconductor layer 110. Next, a conductive layer is formed on the gate insulating layer 120, and the conductive layer is processed by a photolithography process to form gate electrodes 130 and 140 that overlap the semiconductor layer 110.

[0083] Next, using the gate electrodes 130 and 140 as masks, impurities are implanted into the semiconductor layer 110 through the gate insulating layer 120. By implanting the impurities, channel regions 111 and 112 and other low-resistance regions 113 to 115 are formed. When the transistor 100 is a P-type transistor, boron is used as the impurity. On the other hand, when the transistor 100 is an N-type transistor, phosphorus is used as the impurity.

[0084] Next, an insulating layer 170 is formed over the gate insulating layer 120 and the gate electrodes 130 and 140. Next, an oxide semiconductor layer is formed over the insulating layer 170, and the oxide semiconductor layer is processed by a photolithography process to form a semiconductor layer 210. Next, a gate insulating layer 220 is formed over the insulating layer 170 and over the semiconductor layer 210.

[0085] As shown in FIG. 6, by processing the gate insulating layer 220 and the insulating layer 170 by a photolithography process, openings 171 and 221 that reach the drain region (low-resistance region 113) of the semiconductor layer 110, and openings 172 and 222 that reach the source region (low-resistance region 115) of the semiconductor layer 110 are formed. Next, a conductive layer is formed over the gate insulating layer 220 and inside the openings 171, 172, 221, and 222. By processing the formed conductive layer by a photolithography process, electrodes 150 and 160 and a gate electrode 230 are formed.

[0086] Next, using the gate electrode 230 as a mask, impurities are implanted into the semiconductor layer 210 through the gate insulating layer 220. By the implantation of the impurities, a channel region 211 and low-resistance regions 213 and 214 are formed. Details of the method for forming the low-resistance regions 213 and 214 will be described later.

[0087] As shown in FIG. 7, an insulating layer 270 that covers the electrodes 150 and 160 and the gate electrode 230 is formed over the gate insulating layer 220. By processing the gate insulating layer 220 and the insulating layer 270 by a photolithography process, openings 271 and 272 that reach the drain region (low-resistance region 213) and the source region (low-resistance region 214) of the semiconductor layer 210 are formed.

[0088] As shown in FIG. 8, a conductive layer 259 is formed over the insulating layer 270 and inside the openings 271 and 272. By processing the formed conductive layer 259 by a photolithography process, electrodes 250 and 260 shown in FIG. 1 are formed.

[0089] [9. Method for Forming Low-Resistance Regions 213 and 214] With reference to FIG. 6, a method for forming the drain region (low-resistance region 213) and the source region (low-resistance region 214) of the semiconductor layer 210 will be described. As shown in FIG. 6, ion implantation is performed on the semiconductor layer 210 with the gate insulating layer 220 and the gate electrode 230 formed thereon. For example, boron (B) is implanted into the semiconductor layer 210 as an impurity element by ion implantation. However, other impurity elements such as phosphorus (P) may be implanted into the semiconductor layer 210 instead of boron.

[0090] In the region where the gate electrode 230 is not provided, the impurity element passes through the gate insulating layer 220 and reaches the semiconductor layer 210. However, in the region where the gate electrode 230 is provided (channel region 211), the impurity element is blocked by the gate electrode 230 and thus does not reach the semiconductor layer 210.

[0091] By the above ion implantation, low-resistance regions 213 and 214 into which impurity elements are implanted are formed in the semiconductor layer 210. In the semiconductor layer 210 in the low-resistance regions 213 and 214, oxygen deficiency is formed by the implantation of the impurity element, so that the semiconductor layer 210 in the region has a lower resistance. Note that in the oxide semiconductor layer including Poly-OS, the oxide semiconductor layers in the low-resistance regions 213 and 214 into which impurity elements are implanted may have crystallinity. This is also one of the characteristics of Poly-OS. In this case, the crystal structure of each of the oxide semiconductor layers in the low-resistance regions 213 and 214 is the same as the crystal structure of the oxide semiconductor layer in the channel region 211.

[0092] In the above manufacturing method, the manufacturing method in the case where Poly-OS is used as the semiconductor layer 210 is exemplified, but the manufacturing method of the semiconductor device 10 is not limited to the above method. For example, a manufacturing method in which an amorphous oxide semiconductor is formed as the semiconductor layer 210 may be used.

[0093] As long as the embodiments described above as embodiments of the present invention do not conflict with each other, they can be implemented in appropriate combinations. Further, based on each embodiment, those in which those skilled in the art have appropriately added, deleted, or changed the design of components, or added, omitted, or changed the conditions of the process, as long as they have the gist of the present invention, they are included in the scope of the present invention.

[0094] Even if there are other effects different from the effects brought about by the aspects of the above-described embodiments, those that are obvious from the description of this specification or can be easily predicted by those skilled in the art are naturally understood to be brought about by the present invention.

Description of Reference Numerals

[0095] 10: Semiconductor device, 100: Transistor, 101: Substrate, 102: Insulating layer, 110: Semiconductor layer, 111, 112: Channel region, 113, 114, 115: Low-resistance region, 120: Gate insulating layer, 130, 140: Gate electrode, 150, 160: Electrode, 170: Insulating layer, 171, 172: Opening, 200: Transistor, 210: Semiconductor layer, 211: Channel region, 213, 214: Low-resistance region, 220: Gate insulating layer, 221, 222, 231: Opening, 230: Gate electrode, 250, 260: Electrode, 259: Conductive layer, 270: Insulating layer, 271, 272: Opening, 290: Light-shielding layer, 300: Metal oxide layer, IN: Input signal, OUT: Output signal

Claims

1. a first semiconductor layer; a first gate electrode facing the first semiconductor layer; a second gate electrode facing the first semiconductor layer and supplied with the same voltage as the first gate electrode; a first gate insulating layer between the first semiconductor layer and the first gate electrode and between the first semiconductor layer and the second gate electrode; a second semiconductor layer sandwiching the first gate electrode together with the first semiconductor layer; a third gate electrode facing the second semiconductor layer on the side opposite to the first gate electrode with respect to the second semiconductor layer and overlapping the first gate electrode in plan view; a second gate insulating layer between the second semiconductor layer and the third gate electrode, a semiconductor device having the same.

2. The semiconductor device according to claim 1, wherein the second semiconductor layer includes an oxide semiconductor.

3. The semiconductor device according to claim 1, wherein the second gate electrode does not overlap the third gate electrode in plan view.

4. a first electrode connected to a first region of the first semiconductor layer; a second electrode connected to a second region of the first semiconductor layer on the side opposite to the first electrode with respect to the first gate electrode and the second gate electrode, further comprising: The semiconductor device according to claim 3, wherein the first gate electrode and the second gate electrode are separated from each other in a cross-sectional view along a line connecting the first region and the second region.

5. The semiconductor device according to claim 4, wherein the first gate electrode is connected to the second gate electrode in a region that does not overlap the first semiconductor layer in plan view.

6. a first electrode connected to a first region of the first semiconductor layer; a second electrode connected to a second region of the first semiconductor layer on the side opposite to the first electrode with respect to the first gate electrode and the second gate electrode, further comprising: The semiconductor device according to claim 5, wherein in a first direction connecting the first region and the second region, the length of the second gate electrode is smaller than the length of the first gate electrode.

7. The semiconductor device according to claim 6, wherein the first gate electrode and the second gate electrode are in the same layer.

8. a first electrode connected to a first region of the first semiconductor layer; a second electrode connected to a second region of the first semiconductor layer on the side opposite to the first electrode with respect to the first gate electrode and the second gate electrode, further comprising: The semiconductor device according to claim 1, wherein, in a first direction connecting the first region and the second region, in a cross-sectional view along a line connecting the first region and the second region, a length of the first gate electrode is greater than a length of the third gate electrode.

9. a third electrode connected to a third region of the second semiconductor layer; further comprising: a fourth electrode connected to a fourth region of the second semiconductor layer on a side opposite to the third electrode with respect to the third gate electrode; different voltages are supplied to the second electrode and the fourth electrode, respectively; the semiconductor device according to claim 8, wherein the first electrode and the third electrode are electrically connected.

10. The semiconductor device according to claim 8, wherein the first electrode and the third gate electrode are in the same layer.

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