Semiconductor device

Abstract

To provide a semiconductor device capable of reducing a chip area while suppressing disturb between adjacent recording cells.SOLUTION: A semiconductor device comprises a semiconductor substrate, a plurality of first gates, a plurality of second gates, a plurality of first gate insulator films, a plurality of second gate insulator films, a plurality of first charge storage films, and a plurality of second charge storage films. The semiconductor substrate includes a principal surface. A first well region, a plurality of first impurity diffusion regions, a second well region, and a plurality of second impurity diffusion regions are formed on the principal surface. The first well region and the second well region extend in a first direction in a planar view and are disposed in parallel while being spaced apart from each other in a second direction which is vertical to the first direction.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] For example, Japanese Patent Laid-Open Publication No. 2021-190464 (Patent Document 1) describes a semiconductor device. The semiconductor device described in Patent Document 1 has a semiconductor layer, a gate insulating film, a gate, and a charge storage film.

[0003] The semiconductor layer has a main surface. The semiconductor layer has a well region, a source region, and a drain region. The well region is formed in the main surface. The source region and the drain region are formed in the main surface, in the well region. The source region and the drain region are arranged to be spaced apart from each other.

[0004] The gate is disposed on the main surface between the source region and the drain region with the gate insulating film interposed therebetween. The charge storage film is disposed on the main surface between the source region and the gate and between the drain region and the gate. The charge storage film is also disposed on the gate insulating film and on the side surfaces of the gate.

[0005] In the semiconductor device described in Patent Document 1, a current flows in the semiconductor layer from the source to the drain by applying a voltage higher than that of the drain to the gate and source. As this current flows, hot electrons are injected into the charge storage film. The injection of these hot electrons changes the threshold voltage of the gate, and data is written. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2021-190464 A [Summary] When attempting to form a plurality of memory structures as described above in the semiconductor device described in Patent Document 1, the gates of adjacent memory structures are connected to each other. In this case, when writing data to one memory structure, the current flowing through the one memory structure may flow to another memory structure adjacent to the one memory structure, and data may be written shallowly in the other memory structure (disturbance may occur).

[0007] The semiconductor device of the present disclosure includes a conductor substrate, a plurality of first gates, a plurality of second gates, a plurality of first gate insulating films, a plurality of second gate insulating films, a plurality of first charge storage films, and a plurality of second charge storage films. The semiconductor substrate has a main surface. A first well region, a plurality of first impurity diffusion regions, a second well region, and a plurality of second impurity diffusion regions are formed on the main surface. The first well region and the second well region extend along a first direction in a plan view, and are arranged at intervals along a second direction perpendicular to the first direction. The plurality of first impurity diffusion regions are formed on the main surface in the first well region so as to be arranged at intervals along the first direction. The plurality of second impurity diffusion regions are formed on the main surface in the second well region so as to be arranged at intervals along the first direction. Each of the plurality of first gates extends along the second direction while facing the main surface with each of the first gate insulating films interposed between two adjacent ones of the plurality of first impurity diffusion regions. Each of the second gates extends along the second direction facing the main surface with the second gate insulating film interposed between two adjacent ones of the second impurity diffusion regions. Each of the first charge storage films is disposed on the main surface between each of the first impurity diffusion regions and each of the first gates. Each of the second charge storage films is disposed on the main surface between each of the second impurity diffusion regions and each of the second gates. One of the first gates is connected to one of the second gates and is shifted from one of the second gates in the first direction. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view of a semiconductor device 100. [Diagram 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Diagram 3] FIG. 2 is a cross-sectional view taken along line III-III in FIG. [Figure 4] 2A to 2C are manufacturing process diagrams showing a manufacturing method of the semiconductor device 100. [Diagram 5] 11 is a cross-sectional view illustrating an element isolation film forming step S2. FIG. [Figure 6] FIG. 11 is a cross-sectional view illustrating a gate insulating film forming step S3. [Figure 7] FIG. 11 is a cross-sectional view illustrating a first ion implantation step S4. [Figure 8] FIG. 11 is a cross-sectional view illustrating a gate formation step S5. [Figure 9] 11 is a cross-sectional view illustrating a charge storage film forming step S6. [Figure 10] FIG. 11 is a cross-sectional view illustrating a second ion implantation step S7. [Figure 11] FIG. 11 is a cross-sectional view illustrating an insulating film forming step S8. [Figure 12] FIG. 11 is a cross-sectional view illustrating a silicide step S9. [Figure 13] 10 is a cross-sectional view illustrating an interlayer insulating film forming step S10. FIG. [Figure 14] 11 is a cross-sectional view illustrating a contact plug forming step S11. [Figure 15] FIG. 2 is a plan view of the semiconductor device 200. [Figure 16] 16 is a cross-sectional view taken along line XVI-XVI in FIG. 15. [Figure 17] FIG. 2 is a plan view of the semiconductor device 100A.

[0009] [Detailed Description] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant description will not be repeated.

[0010] (First embodiment) The semiconductor device according to the first embodiment will be described below. The semiconductor device according to the first embodiment is designated as semiconductor device 100.

[0011] <Configuration of Semiconductor Device 100A> The configuration of the semiconductor device 100A will be described below.

[0012] FIG. 1 is a plan view of a semiconductor device 100. In FIG. 1, the charge storage film 50, the charge storage film 51, the insulating spacer 52, the insulating spacer 53, the insulating film 54, the insulating film 55, the interlayer insulating film 60, the wiring 70, and the contact plug 80 are omitted. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 1. As shown in FIGS. 1 to 3, the semiconductor device 100 includes a semiconductor substrate 10, an element isolation film 20, a plurality of gate insulating films 30, a plurality of gate insulating films 31, a plurality of gates 40, a plurality of gates 41, a plurality of charge storage films 50, a plurality of charge storage films 51, a plurality of insulating spacers 52, a plurality of insulating spacers 53, a plurality of insulating films 54, a plurality of insulating films 55, the interlayer insulating film 60, the wiring 70, and the contact plug 80.

[0013] The semiconductor substrate 10 has a main surface 10a and a main surface 10b. The main surface 10b is the surface opposite to the main surface 10a. The main surface 10a and the main surface 10b constitute both end surfaces of the semiconductor substrate 10 in the thickness direction. The constituent material of the semiconductor substrate 10 is, for example, single crystal silicon. The conductivity type of the semiconductor substrate 10 is a first conductivity type. The first conductivity type is, for example, a p-type.

[0014] The semiconductor substrate 10 has a plurality of well regions 11 and a plurality of well regions 12. The well regions 11 and 12 are formed on the main surface 10a. A plan view refers to a view from the main surface 10a side along the normal direction of the main surface 10a. The well regions 11 and 12 extend along a first direction DR1 in a plan view. The well regions 11 and 12 are alternately arranged at intervals along a second direction DR2 perpendicular to the first direction DR1 in a plan view. The well regions 11 and 12 are positioned at offset positions in the first direction DR1. The conductivity type of the well regions 11 and 12 is a first conductivity type.

[0015] The distance between adjacent well regions 11 and 12 is defined as distance SP1. Distance SP1 corresponds to the width in the second direction DR2 of the isolation film 20 between adjacent well regions 11 and 12. The width in the second direction DR2 of the well region 11 is defined as width W1. The width in the second direction DR2 of the well region 12 is defined as width W2. It is preferable that distance SP1 is 0.9 times or less of widths W1 and W2. Distance SP1 may be 0.8 times or less of widths W1 and W2, or 0.7 times or less of widths W1 and W2.

[0016] The semiconductor substrate 10 further includes a plurality of impurity diffusion regions 13 and a plurality of impurity diffusion regions 14. The plurality of impurity diffusion regions 13 are formed on the main surface 10a in the well region 11. The plurality of impurity diffusion regions 13 are arranged at intervals along the first direction DR1. In a cross-sectional view perpendicular to the second direction DR2, the impurity diffusion region 13 is surrounded by the well region 11. The plurality of impurity diffusion regions 14 are formed on the main surface 10a in the well region 12. The plurality of impurity diffusion regions 14 are arranged at intervals along the first direction DR1. In a cross-sectional view perpendicular to the second direction DR2, the impurity diffusion region 14 is surrounded by the well region 12. The conductivity type of the impurity diffusion region 13 and the conductivity type of the impurity diffusion region 14 are the second conductivity type. The second conductivity type is, for example, n-type.

[0017] The element isolation film 20 is formed on the main surface 10a so as to surround each of the well regions 11 and 12. More specifically, a trench 10c is formed in the main surface 10a, and the element isolation film 20 is embedded in the trench 10c. That is, the element isolation film 20 has an STI (Shallow Trench Isolation) structure. The element isolation film 20 may have a LOCOS (Local Oxidation Of Silicon) structure. The constituent material of the element isolation film 20 is, for example, silicon oxide.

[0018] The gate 40 extends along the second direction DR2 facing the main surface 10a (well region 11) between two adjacent impurity diffusion regions 13 with the gate insulating film 30 interposed therebetween, and crosses the well region 11. That is, both ends of the gate 40 in the second direction DR2 are on the element isolation film 20. The gate 41 extends along the second direction DR2 facing the main surface 10a (well region 12) between two adjacent impurity diffusion regions 14 with the gate insulating film 31 interposed therebetween, and crosses the well region 12. That is, both ends of the gate 41 in the second direction DR2 are on the element isolation film 20.

[0019] Each gate 40 is connected to a gate 41 that is closest to the gate 40 in the first direction DR1 by a connection portion 42. The connection portion 42 is disposed on the element isolation film 20 and extends, for example, along the first direction DR1. The gate 40 connected to the connection portion 42 is shifted in the first direction DR1 from the gate 41 connected to the connection portion 42. The materials of the gate 40, the gate 41, and the connection portion 42 are, for example, polycrystalline silicon containing a dopant. The materials of the gate insulating film 30 and the gate insulating film 31 are, for example, silicon oxide.

[0020] The distance between adjacent gates 40 is defined as distance SP2. The distance between adjacent gates 41 is defined as distance SP3. The distance in the first direction DR1 between a gate 40 connected to one connection portion 42 and a gate 41 connected to that one connection portion 42 is defined as distance DIS. Distance DIS is, for example, 0.5 times or less of distance SP2 and distance SP3. Note that {(distance DIS) 2 +(interval SP1) 2} 0.5 The value of is greater than width W1 and width W2.

[0021] The charge storage film 50 is disposed on the main surface 10a (well region 11) between the impurity diffusion region 13 and the gate 40. The charge storage film 50 is also disposed on the side of the gate insulating film 30 and the side of the gate 40. The charge storage film 51 is disposed on the main surface 10a (well region 12) between the impurity diffusion region 14 and the gate 41. The charge storage film 50 is also disposed on the side of the gate insulating film 31 and the side of the gate 41. Each of the charge storage film 50 and the charge storage film 51 is composed of, for example, a first film 56 and a second film 57 disposed on the first film 56. The constituent material of the first film 56 and the constituent material of the second film 57 are different from each other. The constituent material of the first film 56 and the constituent material of the second film 57 are, for example, silicon oxide and silicon nitride, respectively.

[0022] The portion of the charge storage film 50 on the main surface 10a is the first portion of the charge storage film 50, and the portion of the charge storage film 50 on the side of the gate insulating film 30 and the side of the gate 40 is the second portion of the charge storage film 50. The portion of the charge storage film 51 on the main surface 10a is the first portion of the charge storage film 51, and the portion of the charge storage film 51 on the side of the gate insulating film 31 and the side of the gate 41 is the second portion of the charge storage film 51. An insulating spacer 52 is disposed on the first portion of the charge storage film 50 so as to contact the second portion of the charge storage film 50. An insulating spacer 53 is disposed on the first portion of the charge storage film 51 so as to contact the second portion of the charge storage film 51. The constituent material of the insulating spacer 52 and the constituent material of the insulating spacer 53 are, for example, silicon oxide.

[0023] Two adjacent impurity diffusion regions 13, a well region 11 between the two adjacent impurity diffusion regions 13, one gate 40 between the two adjacent impurity diffusion regions 13, and a charge storage film 50 between each of the two adjacent impurity diffusion regions 13 and the one gate 40 constitute one recording cell. Similarly, two adjacent impurity diffusion regions 14, a well region 12 between the two adjacent impurity diffusion regions 14, one gate 41 between the two adjacent impurity diffusion regions 14, and a charge storage film 51 between each of the two adjacent impurity diffusion regions 14 and the one gate 41 constitute one recording cell.

[0024] The insulating film 54 covers the gate 40, the charge storage film 50, the insulating spacer 53, and a portion of the impurity diffusion region 13 adjacent to the charge storage film 50. In the impurity diffusion region 13 exposed from the insulating film 54, the main surface 10a may be silicided (i.e., may be a silicide layer 13a). The insulating film 55 covers the gate 41, the charge storage film 51, the insulating spacer 53, and a portion of the impurity diffusion region 14 adjacent to the charge storage film 51. In the impurity diffusion region 14 exposed from the insulating film 55, the main surface 10a may be silicided (i.e., may be a silicide layer 14a). The constituent material of the insulating film 54 and the constituent material of the insulating film 55 are, for example, silicon oxide. The constituent material of the silicide layer 13a and the constituent material of the silicide layer 14a are a compound of silicon and a metal material.

[0025] The interlayer insulating film 60 is disposed on the main surface 10a so as to cover the element isolation film 20, the insulating film 54, and the insulating film 55. The interlayer insulating film 60 is made of silicon oxide. The wiring 70 is disposed on the interlayer insulating film 60. The wiring 70 is made of, for example, aluminum or an aluminum alloy. The contact plug 80 is embedded in a contact hole formed in the interlayer insulating film 60. The contact plug 80 connects the wiring 70 to the impurity diffusion region 13, the impurity diffusion region 14, the gate 40, or the gate 41. The contact plug 80 is made of, for example, tungsten.

[0026] <Operation of the semiconductor device 100> The operation of the semiconductor device 100 will now be described.

[0027] When data is written in the semiconductor device 100, a voltage (e.g., 5V) is applied to one of the two adjacent impurity diffusion regions 13 (impurity diffusion regions 14) and to the gate 40 (gate 41) between the two adjacent impurity diffusion regions 13 (impurity diffusion regions 14). At this time, a reference voltage (e.g., 0V) is applied to the other of the two adjacent impurity diffusion regions 13 (impurity diffusion regions 14). Therefore, a current flows in the semiconductor substrate 10 from one of the two adjacent impurity diffusion regions 13 (impurity diffusion regions 14) to the other. The current generates hot electrons, which are injected into the charge storage film 50 (charge storage film 51). The threshold voltage of the gate 40 (gate 41) changes due to the effect of the hot electrons, and data is written.

[0028] <Method of Manufacturing Semiconductor Device 100> A method for manufacturing the semiconductor device 100 will now be described.

[0029] Fig. 4 is a manufacturing process diagram showing a manufacturing method of the semiconductor device 100. As shown in Fig. 4, the manufacturing method of the semiconductor device 100 includes a preparation step S1, an element isolation film forming step S2, a gate insulating film forming step S3, a first ion implantation step S4, a gate forming step S5, a charge storage film forming step S6, a second ion implantation step S7, an insulating film forming step S8, a silicide step S9, an interlayer insulating film forming step S10, a contact plug forming step S11, and a wiring forming step S12.

[0030] In the preparation step S1, a semiconductor substrate 10 is prepared. After the preparation step S1, an element isolation film forming step S2 is performed. FIG. 5 is a cross-sectional view for explaining the element isolation film forming step S2. As shown in FIG. 5, an element isolation film 20 is formed in the element isolation film forming step S2. In the element isolation film forming step S2, first, a resist pattern is formed on the main surface 10a. Second, a trench 10c is formed in the main surface 10a by performing etching (e.g., anisotropic dry etching) using the resist pattern as a mask. Third, a constituent material of the element isolation film 20 is filled in the trench 10c by, for example, a CVD (Chemical Vapor Deposition) method. Fourth, the constituent material of the element isolation film 20 protruding from the trench 10c is removed by, for example, a CMP (Chemical Mechanical Polishing) method.

[0031] The gate insulating film forming step S3 is performed after the element isolation film forming step S2. FIG. 6 is a cross-sectional view illustrating the gate insulating film forming step S3. As shown in FIG. 6, in the gate insulating film forming step S3, for example, a gate insulating film 30 and a gate insulating film 31 are formed by a thermal oxidation method on the main surface 10a. The first ion implantation step S4 is performed after the gate insulating film forming step S3. FIG. 7 is a cross-sectional view illustrating the first ion implantation step S4. As shown in FIG. 7, in the first ion implantation step S4, ions are implanted to form the well region 11 and the well region 12.

[0032] The gate formation step S5 is performed after the first ion implantation step S4. FIG. 8 is a cross-sectional view for explaining the gate formation step S5. As shown in FIG. 8, in the gate formation step S5, the gate 40, the gate 41, and the connection part 42 are formed. In the gate formation step S5, first, a constituent material of the gate 40 (gate 41, connection part 42) is formed on the gate insulating film 30, the gate insulating film 31, and the element isolation film 20 by, for example, a CVD method. Second, a resist pattern is formed on the constituent material of the gate 40 (gate 41, connection part 42) thus formed. Third, the constituent material of the gate 40 (gate 41, connection part 42) thus formed is patterned by etching (for example, anisotropic dry etching) using the resist pattern as a mask. During the above patterning, the gate insulating film 30 other than under the gate 40 and the gate insulating film 31 other than under the gate 41 are removed.

[0033] The charge storage film forming step S6 is performed after the gate forming step S5. FIG. 9 is a cross-sectional view for explaining the charge storage film forming step S6. As shown in FIG. 9, in the charge storage film forming step S6, the charge storage film 50, the charge storage film 51, the insulating spacer 52, and the insulating spacer 53 are formed. In the charge storage film forming step S6, first, the main surface 10a, the gate 40, the gate 41, and the connection portion 42 are thermally oxidized to form the constituent material of the first film 56. Second, the constituent material of the second film 57 is formed on the constituent material of the formed first film 56 by, for example, a CVD method. Third, the constituent material of the insulating spacer 52 (insulating spacer 53) is formed on the constituent material of the formed second film 57 by, for example, a CVD method. Fourth, the constituent material of the formed first film 56, the constituent material of the formed second film 57, and the constituent material of the formed insulating spacer 52 (insulating spacer 53) are etched (for example, anisotropic try etching) on ​​the constituent material of the formed first film 56, the constituent material of the formed second film 57, and the constituent material of the formed insulating spacer 52 (insulating spacer 53).

[0034] The second ion implantation step S7 is performed after the charge storage film formation step S6. Fig. 10 is a cross-sectional view illustrating the second ion implantation step S7. As shown in Fig. 10, in the second ion implantation step S7, ion implantation is performed to form the impurity diffusion region 13 and the impurity diffusion region.

[0035] The insulating film forming step S8 is performed after the second ion implantation step S7. FIG. 11 is a cross-sectional view for explaining the insulating film forming step S8. As shown in FIG. 11, in the insulating film forming step S8, an insulating film 54 and an insulating film 55 are formed. In the insulating film forming step S8, first, a constituent material of the insulating film 54 (insulating film 55) is formed so as to cover the element isolation film 20, the gate 40, the gate 41, the charge storage film 50, the charge storage film 51, the insulating spacer 52, and the insulating spacer 53. Second, a resist pattern is formed on the constituent material of the formed insulating film 54 (insulating film 55). Third, etching (for example, anisotropic dry etching) is performed using the resist pattern as a mask.

[0036] The silicide step S9 is performed after the insulating film forming step S8. FIG. 12 is a cross-sectional view for explaining the silicide step S9. As shown in FIG. 12, in the silicide step S9, the silicide layer 13a and the silicide layer 14a are formed. In the silicide step S9, a metal film is formed on the main surface 10a by, for example, a sputtering method so as to cover the element isolation film 20, the insulating film 54, and the insulating film 55. Secondly, annealing is performed, whereby the metal film reacts with silicon on the main surface 10a, and the silicide layer 13a and the silicide layer 14a are formed. Thirdly, the metal film that has not reacted with silicon is removed by etching.

[0037] The interlayer insulating film forming step S10 is performed after the silicide step S9. FIG. 13 is a cross-sectional view illustrating the interlayer insulating film forming step S10. As shown in FIG. 13, in the interlayer insulating film forming step S10, an interlayer insulating film 60 is formed. In the interlayer insulating film forming step S10, first, a material for the interlayer insulating film 60 is deposited on the main surface 10a by, for example, a CVD method so as to cover the element isolation film 20, the insulating film 54, and the insulating film 55. Second, the deposited material for the interlayer insulating film 60 is planarized by, for example, a CMP method.

[0038] The contact plug forming step S11 is performed after the interlayer insulating film forming step S10. FIG. 14 is a cross-sectional view illustrating the contact plug forming step S11. In the contact plug forming step S11, a contact plug 80 is formed. In the contact plug forming step S11, first, a resist pattern is formed on the interlayer insulating film 60. Second, a contact hole is formed in the interlayer insulating film 60 by etching (e.g., anisotropic dry etching) using the resist pattern as a mask. Third, a constituent material of the contact plug 80 is embedded in the contact hole by, for example, a CVD method. Fourth, the constituent material of the contact plug 80 protruding from the contact hole is removed by, for example, a CMP method.

[0039] The wiring formation process S12 is performed after the contact plug formation process S11. In the wiring formation process S12, the wiring 70 is formed. In the wiring formation process S12, first, the constituent material of the wiring 70 is formed on the interlayer insulating film 60 by, for example, a sputtering method. Second, a resist pattern is formed on the formed constituent material of the wiring 70. Third, the formed constituent material of the wiring 70 is patterned by etching (for example, anisotropic dry etching) using the resist pattern as a mask. In this manner, the structure of the semiconductor device 100 shown in FIGS. 1 to 3 is formed.

[0040] <Effects of the semiconductor device 100> The effects of the semiconductor device 100 will be described below in comparison with a comparative example.

[0041] 15 is a plan view of the semiconductor device 200. In FIG. 15, the charge storage film 50, the charge storage film 51, the insulating spacer 52, the insulating spacer 53, the insulating film 54, the insulating film 55, the interlayer insulating film 60, the wiring 70, and the contact plug 80 are omitted. As shown in FIG. 15, in the semiconductor device 200, the position of the gate 40 connected to one connection portion 42 in the first direction DR1 is aligned with the position of the gate 41 connected to the one connection portion 42 in the first direction DR1. In other respects, the configuration of the semiconductor device 200 is common to the configuration of the semiconductor device 100.

[0042] Fig. 16 is a cross-sectional view taken along line XVI-XVI in Fig. 15. When data is written in the semiconductor device 200, a current flows in the semiconductor substrate 10 from one of two adjacent impurity diffusion regions 13 to the other of the two adjacent impurity diffusion regions 13 in one recording cell. As shown in Fig. 16 (see arrows), the current passes under the element isolation film 20 and may sneak into another recording cell adjacent to the one recording cell in the second direction DR2.

[0043] Since the gate 40 of the one recording cell is connected to the gate 41 of the other recording cell by the connection part 42, when a voltage is applied to the gate 40 of the one recording cell for writing data, the voltage is also applied to the gate 41 of the other recording cell. As a result, hot electrons are injected into the charge storage film 51 of the other recording cell due to the current that has sneaked in as described above, which may cause a disturbance.

[0044] In order to suppress the above-mentioned disturbance in the semiconductor device 200, it is necessary to increase the interval SP1 or form the element isolation film 20 so as to reach a deeper position. The former method increases the chip area of ​​the semiconductor device 200. The latter method may introduce defects into the semiconductor substrate 10 or increase the stress associated with the formation of the element isolation film 20 if an attempt is made to form the element isolation film 20 at a deeper position.

[0045] In this regard, in the semiconductor device 100, the position of the gate 40 connected to one connection part 42 in the first direction DR1 is shifted from the position of the gate 41 connected to the one connection part 42 in the first direction DR1. Therefore, the shortest distance between the gate 40 connected to one connection part 42 and the gate 41 connected to the one connection part 42 is larger than when the position of the gate 40 connected to one connection part 42 in the first direction DR1 is aligned with the position of the gate 41 connected to the one connection part 42 in the first direction DR1. Therefore, in the semiconductor device 100, it is possible to suppress the leakage of the current flowing when writing data without increasing the interval SP1, and thus to suppress the occurrence of disturbance. From another perspective, since disturbance is unlikely to occur even if the interval SP1 is reduced, the semiconductor device 100 can reduce the chip area.

[0046] Second embodiment A semiconductor device according to the second embodiment will be described. The semiconductor device according to the second embodiment is designated as semiconductor device 100A. Here, differences from semiconductor device 100A will be mainly described, and overlapping descriptions will not be repeated.

[0047] <Configuration of Semiconductor Device 100A> The configuration of the semiconductor device 100A will be described below.

[0048] Fig. 17 is a plan view of the semiconductor device 100A. As shown in Fig. 17, in the semiconductor device 100A, the position of the well region 11 in the first direction DR1 is aligned (not misaligned) with the position of the well region 12 in the first direction DR1. In the semiconductor device 100A, the connection portion 42 may extend in a direction inclined with respect to the first direction DR1 in a plan view. In the semiconductor device 100A, the distance DIS may be greater than 0.5 times the interval SP2 and the interval SP3.

[0049] In the semiconductor device 100A, the gate 40 at the end in the first direction DR1 (gate 40a) of the multiple gates 40 is not connected to the gate 41, and the gate 41 at the end in the first direction DR1 (gate 41a) of the multiple gates 41 is not connected to the gate 40. The recording cell including the gate 40a and the recording cell including the gate 41a may be dummy cells. Except for these points, the configuration of the semiconductor device 100A is common to the configuration of the semiconductor device 100.

[0050] <Effects of the semiconductor device 100A> The effects of the semiconductor device 100A will be described below.

[0051] In the semiconductor device 100A, the position of the well region 11 in the first direction DR1 is aligned with the position of the well region 12 in the first direction DR1. Therefore, in the semiconductor device 100A, the dimension in the first direction DR1 of the region required to form the well region 11 and the well region 12 can be made smaller than in the semiconductor device 100A, and the chip area can be further reduced.

[0052] Furthermore, while it is difficult to make the distance DIS larger than 0.5 times the intervals SP2 and SP3 in the semiconductor device 100, it is possible to make the distance DIS larger than 0.5 times the intervals SP2 and SP3 in the semiconductor device 100A. As a result, in the semiconductor device 100A, it is possible to further increase the shortest distance between the gate 40 connected to one connection portion 42 and the gate 41 connected to the same connection portion 42 without increasing the interval SP1. Therefore, the semiconductor device 100A can further suppress disturbance or further reduce the chip area.

[0053] (Additional Note) The embodiments of the present disclosure include the following features.

[0054] <Appendix 1> A semiconductor substrate; A plurality of first gates; A plurality of second gates; A plurality of first gate insulating films; A plurality of second gate insulating films; A plurality of first charge storage films; a plurality of second charge storage films; the semiconductor substrate has a main surface; a first well region, a plurality of first impurity diffusion regions, a second well region, and a plurality of second impurity diffusion regions are formed on the main surface; the first well region and the second well region extend along a first direction in a plan view and are arranged at intervals along a second direction perpendicular to the first direction; the first impurity diffusion regions are formed in the main surface so as to be spaced apart from one another along the first direction in the first well region; the second impurity diffusion regions are formed in the main surface so as to be spaced apart from one another along the first direction in the second well region; each of the first gates extends along the second direction while facing the main surface with each of the first gate insulating films interposed between two adjacent ones of the first impurity diffusion regions; each of the second gates extends along the second direction while facing the main surface with the second gate insulating films interposed between two adjacent ones of the second impurity diffusion regions; each of the first charge storage films is disposed on the main surface between each of the first impurity diffusion regions and each of the first gates; each of the second charge storage films is disposed on the main surface between each of the second impurity diffusion regions and each of the second gates; A semiconductor device, wherein one of the plurality of first gates is connected to one of the plurality of second gates and is shifted from the one of the plurality of second gates in the first direction.

[0055] <Appendix 2> 2. The semiconductor device according to claim 1, wherein the first well region and the second well region are offset from each other in the first direction.

[0056] <Appendix 3> 2. The semiconductor device according to claim 1, wherein the first well region and the second well region are aligned in the first direction.

[0057] <Appendix 4> the one of the plurality of first gates is connected to the one of the plurality of second gates by a connection portion; 4. The semiconductor device according to claim 1, wherein the connection portion extends along the first direction.

[0058] <Appendix 5> the one of the plurality of first gates is connected to the one of the plurality of second gates by a connection portion; 4. The semiconductor device according to claim 1, wherein the connection portion extends along a direction that is inclined with respect to the first direction in a plan view.

[0059] <Appendix 6> 6. The semiconductor device according to claim 1, wherein a distance in the second direction between the first well region and the second well region is 0.9 times or less a width of the first well region in the second direction and a width of the second well region in the second direction.

[0060] <Appendix 7> 5. The semiconductor device of claim 4, wherein a shortest distance between the one of the plurality of first gates and the one of the plurality of second gates is greater than a width of the first well region in the second direction and a width of the second well region in the second direction.

[0061] <Appendix 8> 8. The semiconductor device according to claim 1, wherein a distance in the first direction between the one of the plurality of first gates and the one of the plurality of second gates is greater than 0.5 times a spacing in the first direction between two adjacent ones of the plurality of first gates and a spacing in the first direction between two adjacent ones of the plurality of second gates.

[0062] <Appendix 9> Each of the plurality of first charge storage films and each of the plurality of second charge storage films includes a first film and a second film disposed on the first film, the first film is made of a silicon oxide material; 9. The semiconductor device according to claim 1, wherein a material of the second film is silicon nitride.

[0063] Although the embodiment of the present disclosure has been described above, the above-mentioned embodiment can be modified in various ways. The scope of the present invention is not limited to the above-mentioned embodiment. The scope of the present invention is defined by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0064] 100, 100A semiconductor device, 10 semiconductor substrate, 10a, 10b main surface, 10c trench, 11, 12 well region, 13 impurity diffusion region, 13a silicide layer, 14 impurity diffusion region, 14a silicide layer, 20 element isolation film, 30, 31 gate insulating film, 40, 40a, 41, 41a gate, 42 connection portion, 50, 51 charge storage film, 52, 53 insulating spacer, 54, 55 insulating film, 56 first film, 57 second film, 60 interlayer insulating film, 70 wiring, 80 contact plug, 200 semiconductor device, DR1 first direction, DR2 second direction, DIS distance, S1 preparation step, S2 element isolation film formation step, S3 gate insulating film formation step, S4 first ion implantation step, S5 gate formation step, S6 charge storage film formation step, S7 A second ion implantation step, S8 an insulating film forming step, S9 a silicide step, S10 an interlayer insulating film forming step, S11 a contact plug forming step, S12 a wiring forming step, SP1, SP2, SP3 intervals, W1, W2 widths.

Claims

1. A semiconductor substrate, a plurality of first gates, a plurality of second gates, a plurality of first gate insulating films, a plurality of second gate insulating films, a plurality of first charge storage films, and a plurality of second charge storage films, wherein the semiconductor substrate has a main surface, and a first well region, a plurality of first impurity diffusion regions, a second well region, and a plurality of second impurity diffusion regions are formed on the main surface, the first well region and the second well region extend along a first direction in a plan view and are arranged at intervals along a second direction perpendicular to the first direction, the plurality of first impurity diffusion regions are formed on the main surface in the first well region so as to be arranged at intervals along the first direction, the plurality of second impurity diffusion regions are formed on the main surface in the second well region so as to be arranged at intervals along the first direction, each of the plurality of first gates extends along the second direction while facing the main surface with each of the plurality of first gate insulating films interposed therebetween between two adjacent ones of the plurality of first impurity diffusion regions, each of the plurality of second gates extends along the second direction while facing the main surface with each of the plurality of second gate insulating films interposed therebetween between two adjacent ones of the plurality of second impurity diffusion regions, each of the plurality of first charge storage films is disposed on the main surface between each of the plurality of first impurity diffusion regions and each of the plurality of first gates, each of the plurality of second charge storage films is disposed on the main surface between each of the plurality of second impurity diffusion regions and each of the plurality of second gates, one of the plurality of first gates is connected to one of the plurality of second gates, and the semiconductor device is in a position shifted in the first direction from the one of the plurality of second gates.

2. The semiconductor device according to claim 1, wherein the first well region and the second well region are in positions shifted from each other in the first direction.

3. The semiconductor device according to claim 1, wherein the first well region and the second well region are aligned in the first direction.

4. The one of the plurality of first gates is connected to the one of the plurality of second gates by a connection portion, The semiconductor device according to claim 1, wherein the connection portion extends along the first direction.

5. One of the plurality of first gates is connected by a connection portion to one of the plurality of second gates, The semiconductor device according to claim 1, wherein the connection portion extends along a direction inclined with respect to the first direction in a plan view.

6. The distance in the second direction between the first well region and the second well region is 0.9 times or less the width in the second direction of the first well region and the width in the second direction of the second well region. The semiconductor device according to claim 1.

7. The shortest distance between one of the plurality of first gates and one of the plurality of second gates is greater than the width in the second direction of the first well region and the width in the second direction of the second well region. The semiconductor device according to claim 4.

8. The distance in the first direction between one of the plurality of first gates and one of the plurality of second gates is greater than 0.5 times the interval in the first direction between two adjacent ones of the plurality of first gates and the interval in the first direction between two adjacent ones of the plurality of second gates. The semiconductor device according to claim 1.

9. Each of the plurality of first charge storage films and each of the plurality of second charge storage films have a first film and a second film disposed on the first film, The constituent material of the first film is silicon oxide, The constituent material of the second film is silicon nitride. The semiconductor device according to any one of claims 1 to 8.

Images