Thin film transistor and manufacturing method, memory and manufacturing method, and electronic device

Abstract

To provide a thin film transistor and a manufacturing method, a memory and a manufacturing method, and an electronic device, and relate to the field of memory technologies, to reduce a size of the thin film transistor, improve area utilization, and reduce routing difficulty.SOLUTION: A thin film transistor includes a gate, a first electrode, a second electrode, a first dielectric layer, a second dielectric layer, and a semiconductor layer. The gate includes a gate base located at a top portion and a gate body extending from the gate base to a bottom portion. The first electrode is located at the bottom portion. The second electrode is located between the first electrode and the gate base. The first dielectric layer is disposed between the second electrode and the first electrode, and the first dielectric layer is configured to separate the first electrode from the second electrode. The second dielectric layer covers a surface of the gate base and a surface of the gate body. The semiconductor layer is disposed along a side surface of the gate body, and the second dielectric layer separates the semiconductor layer from the gate. The first electrode and the second electrode are electrically connected to the semiconductor layer respectively.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] Technical Field

[0002] This application relates to the field of memory technologies, and more particularly, to thin film transistors and manufacturing methods, memories and manufacturing methods, and electronic devices.

Background Art

[0003] Thin film transistors (TFTs) have the advantages of low leakage current, low growth temperature, and high mobility, so they have been widely used in various devices such as memories.

[0004] The structure of an existing thin film transistor is shown in FIG. 1. The thin film transistor 10 includes a semiconductor layer (sometimes referred to as an active layer) 102 disposed on a substrate 101, a source 103 and a drain 104 disposed on the semiconductor layer 102 and in contact with the semiconductor layer 102, a gate insulating layer 105 disposed on the semiconductor layer 102, and a gate 106 disposed on the gate insulating layer 105.

[0005] The semiconductor layer 102 of the existing thin film transistor 10 extends along a plane parallel to the gate 106, and the source 103 and the drain 104 are located in the same layer. Therefore, the size of the thin film transistor 10 is relatively large and the area utilization rate is low. In addition, since the source electrode 103 and the drain electrode 104 are located in the same layer, a short circuit is likely to occur during the routing of the signal line electrically connected to the source electrode 103 and the signal line electrically connected to the drain electrode 104, which does not contribute to the routing and increases the difficulty of the process.

Summary of the Invention

Problems to be Solved by the Invention

[0006] Embodiments of the present application provide a thin film transistor, a manufacturing method thereof, a memory and a manufacturing method thereof, and an electronic device for reducing the size of the thin film transistor, improving the area utilization rate, and reducing the difficulty of routing.

Means for Solving the Problems

[0007] To achieve the above object, the present application uses the following technical solutions.

[0008] According to a first aspect, a thin film transistor is provided. The thin film transistor includes a gate, a first electrode, a second electrode, a first dielectric layer, a second dielectric layer, and a semiconductor layer. The gate includes a gate base located at the top and a gate body extending from the gate base to the bottom. The first electrode is located at the bottom. The second electrode is located between the first electrode and the gate base. The first dielectric layer is disposed between the second electrode and the first electrode, and the first dielectric layer is configured to separate the first electrode from the second electrode. The semiconductor layer is disposed along the side surface of the gate body, and the second dielectric layer separates the semiconductor layer from the gate. The first electrode and the second electrode are each electrically connected to the semiconductor layer.

[0009] Compared with the prior art, the semiconductor layer is arranged along a plane parallel to the gate (the gate in the prior art is equivalent to the gate base in this embodiment of the present application), and the second electrode and the first electrode are arranged in the same layer. In this embodiment of the present application, the semiconductor layer is arranged along the side surface of the gate body, the first electrode is located at the bottom, the second electrode is located between the first electrode and the gate base, and the first electrode and the second electrode are electrically connected to the semiconductor layer respectively. Therefore, the thin-film transistor provided in this embodiment of the present application has a relatively small size on a plane parallel to the gate base. Therefore, in this embodiment of the present application, the size of the thin-film transistor is reduced and the area utilization rate is improved. In addition, since the second electrode and the first electrode of the thin-film transistor in this embodiment of the present application are located in different layers, it is possible to avoid a short circuit occurring during the routing of the signal line electrically connected to the second electrode and the signal line electrically connected to the first electrode, thereby reducing the difficulty of the process.

[0010] In a possible implementation, the second electrode is arranged near the gate base. Thereby, when the first electrode and the second electrode are manufactured, it is possible to avoid the first electrode and the second electrode being directly electrically connected.

[0011] In a possible implementation, the boundary of the projection of the gate body on the gate base is located within the boundary of the gate base. In this case, the gate body is arranged in the central region of the gate base.

[0012] In a possible implementation, the boundary of the projection of the gate body on the gate base partially overlaps the boundary of the gate base. In this case, the gate body is arranged in the edge region of the gate base.

[0013] In a possible implementation, the gate body has a hollow structure, and the outer boundary of the projection of the gate body on the gate base overlaps the boundary of the gate base. Since the gate body has a hollow structure, the second dielectric layer, the semiconductor layer, the second electrode, and the first dielectric layer can be arranged within the hollow structure.

[0014] In one possible implementation, the semiconductor layer further includes an extension portion that extends along the surface of the gate base. In this way, the area of the semiconductor layer can be increased, thereby increasing the electrical connection area between the semiconductor layer and the second electrode, and improving the switching speed of the thin-film transistor.

[0015] In one possible implementation, the semiconductor layer further includes an extension portion located between the gate body and the first electrode. In this way, the area of the semiconductor layer can be increased, thereby increasing the electrical connection area between the semiconductor layer and the first electrode, and improving the switching speed of the thin-film transistor.

[0016] In one possible implementation, the semiconductor layer is disposed around the entire side surface of the gate body. In this way, the area of the semiconductor layer can be increased, and the switching speed of the thin-film transistor is improved.

[0017] In one possible implementation, the semiconductor layer surrounds the entire side surface of the gate body.

[0018] In one possible implementation, the second electrode is disposed on the side of the semiconductor layer away from the second dielectric layer.

[0019] In one possible implementation, the second electrode is disposed between the semiconductor layer and the second dielectric layer.

[0020] In one possible implementation, the material of the second dielectric layer is a ferroelectric material, and the thin-film transistor further includes a third dielectric layer disposed between the semiconductor layer and the second dielectric layer. The gate, the second dielectric layer, and the third dielectric layer can form a composite gate structure. By using the composite gate structure, the thin-film transistor can achieve the performance of a negative capacitance transistor, and the gate control ability of the thin-film transistor can be improved by using negative capacitance. When the thin-film transistor is used in a memory, the performance of the memory can be improved.

[0021] In one possible implementation, the thin film transistor further includes a first conductive layer disposed between a second dielectric layer and a third dielectric layer. A composite gate structure including a gate, a second dielectric layer, a first conductive layer, and a third dielectric layer can enable the thin film transistor to achieve the performance of a negative capacitance transistor, and the gate control ability of the thin film transistor can be improved by using negative capacitance. When the thin film transistor is used in a memory, the performance of the memory can be improved.

[0022] In one possible implementation, the thin film transistor further includes a fourth dielectric layer disposed between a second electrode and a semiconductor layer and / or a fifth dielectric layer disposed between a first electrode and the semiconductor layer. The fourth dielectric layer is disposed between the second electrode and the semiconductor layer so as to avoid the problem of diffusion of the second electrode in the contact region with the semiconductor layer and reduce the problem of Fermi level pinning of the contact between the second electrode and the semiconductor layer. The fifth dielectric layer is disposed between the first electrode and the semiconductor layer so as to avoid the problem of diffusion of the first electrode in the contact region with the semiconductor layer and reduce the Fermi level pinning problem of the contact between the first electrode and the semiconductor layer.

[0023] In one possible implementation, the thicknesses of both the fourth dielectric layer and the fifth dielectric layer are in the range of 0.1 nm to 2 nm. Thereby, when a voltage is applied to the gate, the second electrode and the first electrode can be electrically connected through the semiconductor layer, ensuring that the performance of the thin film transistor is not affected.

[0024] In one possible implementation, the thin film transistor further includes a modulation gate electrode disposed between the first electrode and the second electrode. The modulation gate electrode is disposed on the side of the semiconductor layer away from the gate body, and the modulation gate electrode is surrounded by the first dielectric layer so that the modulation gate electrode is separated from the first electrode, the second electrode, and the semiconductor layer. The threshold voltage of the thin film transistor can be adjusted by using the modulation gate electrode.

[0025] In one possible implementation, the first electrode is the drain and the second electrode is the source; or the first electrode is the source and the second electrode is the drain.

[0026] According to a second aspect, a memory is provided. The memory includes at least one layer of a memory array disposed on a substrate, and each layer of the memory array includes a plurality of memory cells, write word lines, write bit lines, read word lines, and read bit lines distributed within the array; the memory cells include a stacked second thin film transistor and a first thin film transistor, the gate of the second thin film transistor is electrically connected to the write word line, and the second electrode is electrically connected to the write bit line; the second electrode and the first electrode of the first thin film transistor are electrically connected to the read word line and the read bit line, respectively. The second thin film transistor and the first thin film transistor are the thin film transistors described above. The first electrode of the second thin film transistor is close to the gate of the first thin film transistor, and the first electrode of the second thin film transistor is electrically connected to the gate of the first thin film transistor. The second thin film transistor and the first thin film transistor in the memory are the aforementioned thin film transistors, and since the second thin film transistor and the first thin film transistor have the same technical effects as those in the aforementioned embodiments, the details will not be described again here.

[0027] In one possible implementation, the memory cell further includes a connection electrode disposed between the first thin film transistor and the second thin film transistor, and the gate of the first thin film transistor is electrically connected to the first electrode of the second thin film transistor by using the connection electrode.

[0028] In one possible implementation, the gates of the second thin film transistors in a plurality of memory cells sequentially arranged within each layer of the memory array along a first direction are electrically connected to the same write word line, and the second electrodes of the second thin film transistors in a plurality of memory cells sequentially arranged within each layer of the memory array along a second direction are electrically connected to the same write bit line, and the first direction intersects the second direction. In each layer of the memory array, the gates of the second thin film transistors in a plurality of memory cells sequentially arranged along the first direction are electrically connected to the same write word line, and the second electrodes of the second thin film transistors in a plurality of memory cells sequentially arranged along the second direction are electrically connected to the same write bit line. Thus, in the write operation process, a first switch signal can be provided to the plurality of write word lines row by row. Thereby, a plurality of rows of the second thin film transistors are turned on row by row. When the first switch signal is provided to the write word line of the current row, logical information is simultaneously written to a plurality of memory cells electrically connected to the write word line of the current row by using a plurality of write bit lines, whereby the logical information is written to the memory cells row by row, and thereby, rapid writing of a plurality of memory cells within the memory array can be implemented.

[0029] In a possible implementation, the second electrodes of the first thin film transistors in a plurality of memory cells sequentially arranged in each layer of the memory array along a first direction are electrically connected to the same read bit line, and the first electrodes of the first thin film transistors in a plurality of memory cells sequentially arranged in each layer of the memory array along a second direction are electrically connected to the same read word line; the second electrodes of the first thin film transistors in a plurality of memory cells sequentially arranged in each layer of the memory array along a first direction are electrically connected to the same read word line, and the first electrodes of the first thin film transistors in a plurality of memory cells sequentially arranged in each layer of the memory array along a second direction are electrically connected to the same read bit line; the second electrodes of the first thin film transistors in a plurality of memory cells sequentially arranged in each layer of the memory array along a second direction are electrically connected to the same read bit line, and the first electrodes of the first thin film transistors in a plurality of memory cells sequentially arranged in each layer of the memory array along a first direction are electrically connected to the same read word line; or the second electrodes of the first thin film transistors in a plurality of memory cells sequentially arranged in each layer of the memory array along a second direction are electrically connected to the same read word line, and the first electrodes of the first thin film transistors in a plurality of memory cells sequentially arranged in each layer of the memory array along a first direction are electrically connected to the same read bit line. Here, the first direction intersects the second direction. In the read operation process, a third level signal can be provided to each row of the plurality of read word lines. When the third level signal is provided to the read word line of the current row, the current on each read bit line is detected. In this way, the logical information stored in the plurality of memory cells electrically connected to the read word line of the current row can be read out simultaneously. Thereby, the logical information stored in the memory cells can be read out row by row, thereby implementing a rapid readout of the plurality of memory cells in the memory array.

[0030] In a possible implementation, the first direction and the second direction are orthogonal.

[0031] In a possible implementation, the first thin film transistor further includes a first modulation gate electrode disposed between the first electrode and the second electrode. The first modulation gate electrode is disposed on the side of the semiconductor layer away from the gate body. The first modulation gate electrode is surrounded by the first dielectric layer of the first thin film transistor so as to be spaced apart from the second electrode, the first electrode, and the semiconductor layer. The first modulation gate electrodes of a plurality of first thin film transistors located in the same layer are electrically connected together. And / or, the second thin film transistor further includes a second modulation gate electrode disposed between the first electrode and the second electrode. The second modulation gate electrode is disposed on the side of the semiconductor layer away from the gate body. The second modulation gate electrode is surrounded by the first dielectric layer of the second thin film transistor so as to be spaced apart from the second electrode, the first electrode, and the semiconductor layer. The second modulation gate electrodes of a plurality of second thin film transistors located in the same layer are electrically connected together. Since the first thin film transistor includes the first modulation gate electrode, the threshold voltage of the first thin film transistor can be adjusted using the first modulation gate electrode. Also, since the first modulation gate electrodes of a plurality of first thin film transistors are electrically connected together, batch modulation of the plurality of first thin film transistors can be realized. Since the second thin film transistor includes the second modulation gate electrode, the threshold voltage of the second thin film transistor can be adjusted using the second modulation gate electrode. Also, since the second modulation gate electrodes of a plurality of second thin film transistors are electrically connected together, batch modulation of the plurality of second thin film transistors can be realized. Based on this, the storage performance of the memory can be adjusted more flexibly.

[0032] In a possible implementation, the memory further includes an integrated circuit, and the memory array is disposed on the integrated circuit. In this case, the memory is an on-chip memory.

[0033] In a possible implementation, the memory cell is electrically connected to the integrated circuit. In this way, the memory cell can be controlled using the integrated circuit.

[0034] According to a third aspect, an electronic device is provided. The electronic device includes a circuit board and a memory electrically connected to the circuit board, and the memory is the aforementioned memory. The electronic device has the same technical effects as those in the foregoing embodiments, and details are not described herein again.

[0035] According to a fourth aspect, a method for manufacturing a thin-film transistor is provided. The method for manufacturing a thin-film transistor includes: first, a step of forming a first electrode, a first dielectric layer, a second electrode, and a semiconductor layer on a substrate, wherein the first electrode, the first dielectric layer, and the second electrode are sequentially stacked, the first dielectric layer separates the first electrode from the second electrode, the semiconductor layer is formed on a side surface of the first dielectric layer, and both the second electrode and the first electrode are electrically connected to the semiconductor layer; and then, a step of sequentially forming a second dielectric layer and a gate, wherein the gate includes a gate base portion located at an upper portion and a gate body extending from the gate base portion to a bottom portion, and the second dielectric layer separates the gate from the semiconductor layer, the first electrode, and the second electrode. The method for manufacturing a thin-film transistor has the same technical effects as those in the foregoing embodiments, and details are not described herein again.

[0036] In a possible implementation, the first electrode is formed as a drain, and the second electrode is formed as a source; or the first electrode is formed as a source, and the second electrode is formed as a drain.

[0037] In a possible implementation, the step of forming a first electrode, a first dielectric layer, a second electrode, and a semiconductor layer on a substrate includes: first, a step of sequentially forming a first conductive thin film, a first dielectric thin film, and a second conductive thin film stacked on the substrate; then, a step of patterning the first conductive thin film, the first dielectric thin film, and the second conductive thin film to form the first electrode, the first dielectric layer, and the second electrode sequentially stacked; and then, a step of forming a semiconductor layer on a side surface of the first dielectric layer and a side surface of the second electrode.

[0038] In a possible implementation, the steps of forming a first electrode, a first dielectric layer, a second electrode, and a semiconductor layer on a substrate are: first, forming a first conductive thin film and a third dielectric thin film sequentially laminated on the substrate; then, forming a modulation gate electrode on the third dielectric thin film; then, forming a fourth dielectric thin film surrounding the modulation gate electrode; then, forming a second conductive thin film on the fourth dielectric thin film; next, patterning the first conductive thin film to form the first electrode, patterning the fourth dielectric thin film and the third dielectric thin film to form the first dielectric layer, and patterning the second conductive thin film to form the second electrode; and forming a semiconductor layer on the side surfaces of the first dielectric layer and the second electrode. The threshold voltage of the thin film transistor can be adjusted by using the modulation gate electrode.

[0039] In a possible implementation, the steps of forming a first electrode, a first dielectric layer, a second electrode, and a semiconductor layer on a substrate are: first, forming a first conductive thin film and a first dielectric thin film sequentially laminated on the substrate; then, patterning the first conductive thin film and the first dielectric thin film to form the first electrode and the first dielectric layer laminated sequentially; then, forming a semiconductor layer on the side surface of the first dielectric layer; and then, forming a second electrode on the first dielectric layer.

[0040] In a possible implementation, the material of the second dielectric layer is a ferroelectric material; after the semiconductor layer is formed and before the second dielectric layer is formed, the manufacturing method further includes a step of forming a third dielectric layer, where the third dielectric layer is formed on the side surface of the first dielectric layer. The third dielectric layer has the same technical effect as that in the foregoing embodiments, and the details are not described again here.

[0041] In a possible implementation, after the third dielectric layer is formed and before the second dielectric layer is formed, the manufacturing method further includes the step of forming a first conductive layer, where the first conductive layer is formed on the side surface of the first dielectric layer. The first conductive layer has the same technical effect as that in the foregoing embodiment, and details are not described again here.

[0042] In a possible implementation, after the first electrode is formed and before the semiconductor layer is formed, the manufacturing method further includes the step of forming a fifth dielectric layer, where the fifth dielectric layer is in contact with the first electrode and the semiconductor layer respectively. In this way, the problem of diffusion of the first electrode in the contact region with the semiconductor layer can be avoided, and the Fermi level pinning problem of the contact between the first electrode and the semiconductor layer can be reduced.

[0043] In a possible implementation, after the second electrode is formed and before the semiconductor layer is formed; or after the semiconductor layer is formed and before the second electrode is formed, the manufacturing method further includes the step of forming a fourth dielectric layer, where the fourth dielectric layer is in contact with the second electrode and the semiconductor layer respectively. In this way, the problem of diffusion of the second electrode in the contact region with the semiconductor layer can be avoided, and the Fermi level pinning problem of the contact between the second electrode and the semiconductor layer can be reduced.

[0044] According to a fifth aspect, a memory manufacturing method is provided. The memory manufacturing method includes forming at least one layer of a memory array on a substrate. The method of manufacturing any layer of the memory array includes: first, forming a plurality of first signal lines arranged in parallel on the substrate; then, forming a plurality of first thin film transistors distributed in an array and a plurality of second signal lines arranged in parallel on the plurality of first signal lines, wherein the first thin film transistors are manufactured using the above-described thin film transistor manufacturing method, the first electrode of the first thin film transistor is electrically connected to the first signal line, and the second electrode of the first thin film transistor is electrically connected to the second signal line; the first signal line is one of a read bit line and a read word line, and the second signal line is the other of the read bit line and the read word line; next, forming a plurality of second thin film transistors distributed in an array and a plurality of write bit lines arranged in parallel on the first thin film transistors, wherein the second electrode of the second thin film transistor is electrically connected to the write bit line, the second thin film transistors are manufactured using the above-described thin film transistor manufacturing method, one second thin film transistor corresponds to one first thin film transistor, and the first electrode of the second thin film transistor is electrically connected to the gate of the corresponding first thin film transistor; and forming a plurality of write word lines arranged in parallel on the second thin film transistors, wherein the gate of the second thin film transistor is electrically connected to the write word line. Both the first thin film transistors and the second thin film transistors in the memory are manufactured using the above-described thin film transistor manufacturing method. As a result, the sizes of the first thin film transistors and the second thin film transistors in the manufactured memory are relatively small, thereby improving the area utilization rate.

[0045] In a possible implementation, after forming a plurality of first thin film transistors distributed in an array and a plurality of second signal lines arranged in parallel on a plurality of first signal lines, before forming a plurality of second thin film transistors distributed in an array and a plurality of write bit lines arranged in parallel on the first thin film transistors, a manufacturing method for any layer of the memory array further includes a step of forming a plurality of connection electrodes distributed in an array, and the gate of the first thin film transistor is electrically connected to the first electrode of the corresponding second thin film transistor by using the connection electrode.

Brief Description of the Drawings

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[0088] Reference numerals:

[0089] 1 - Antenna, 2 - Antenna, 10 - Thin - film transistor, 100 - Electronic device, 101 - Substrate, 102 - Semiconductor layer, 103 - Source, 104 - Drain, 105 - Gate insulating layer, 106 - Gate, 107 - Inter - layer dielectric layer, 108 - Second electrode, 109 - First electrode, 110 - Processor, 111 - Connection electrode, 112 - Second dielectric layer, 113 - First dielectric layer, 114 - Fourth dielectric layer, 115 - Fifth dielectric layer, 116 - Third dielectric layer, 117 - First conductive layer, 118 - Modulation gate electrode, 118a - First modulation gate electrode, 118b - Second modulation gate electrode, 120 - External memory interface, 121 - Internal memory, 130 - USB interface, 140 - Charge management module, 141 - Power management module, 142 - Battery, 150 - Mobile communication module, 160 - Wireless communication module, 170 - Audio module, 180 - Sensor module, 190 - Button, 191 - Motor, 192 - Indicator, 193 - Camera, 194 - Display screen, 195 - SIM card interface, 200 - Memory, 201 - Memory array, 201A - Memory cell, 202 - Sixth dielectric layer, 203 - Integrated circuit, 1080 - Second conductive thin film, 1090 - First conductive thin film, 1121 - First dielectric part, 1122 - Second dielectric part, 1130 - First dielectric thin film, 1131 - Third dielectric thin film, and 1132 - Fourth dielectric thin film.

Embodiments for Carrying Out the Invention

[0090] Hereinafter, with reference to the accompanying drawings in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described. It is obvious that the described embodiments are only some, not all, of the embodiments of the present application.

[0091] The following terms, such as "first" and "second", are merely intended to facilitate the description and should not be understood as indicating or implying relative importance or implicitly indicating the amount of the indicated technical features. Therefore, the features limited by "first", "second", etc. may explicitly or implicitly include one or more of those features. In the description of the present application, unless otherwise specified, "a plurality" means two or more.

[0092] In the embodiments of the present application, unless there are separate clear specifications and limitations, the term "connection" should be understood in a broad sense. For example, "connection" may be a fixed connection, a detachable connection, or an integral connection; or it may be a direct connection; or it may be an indirect connection through an intermediate medium. Also, the term "electrically connected" may be a direct electrical connection or an indirect electrical connection through an intermediate medium. In addition, the term "coupled" may indicate that two or more components are in direct physical contact or electrical contact, or it may indicate that two or more components are not in direct contact with each other but are electrically connected or interact with each other through an intermediate medium.

[0093] In the embodiments of the present application, words such as "example" or "for example" are used to represent giving an example, illustration, or explanation. Any embodiment or design solution described as an "example" or "for example" in the embodiments of the present application should not be described as being more preferable or having more advantages than another embodiment or design solution. Exactly, words such as "example", "for example" are intended to specifically present relative concepts.

[0094] In the embodiments of the present application, the term "and / or" describes the association relationship between associated objects and may indicate that three relationships exist. For example, A and / or B may indicate the following cases: only A exists, both A and B exist, and only B exists. Here, A and B can be singular or plural. The symbol " / " generally indicates the "or" relationship between associated objects.

[0095] In the embodiments of the present application, the description regarding the accompanying drawings is based on the directions shown in the accompanying drawings. When the directions shown in the accompanying drawings change, the corresponding descriptions also change accordingly.

[0096] With the continuous development of integrated circuit technology, the number of transistors placed on a chip per unit area in electronic products such as computers or mobile phones has been continuously increasing. As a result, the performance of electronic products has been continuously optimized. On the one hand, the amount of data that can be operated by the processor on the chip within a unit time has been constantly increasing. On the other hand, the storage density of the memory on the chip has also been constantly increasing, thereby meeting people's requirements for data processing in the information age. However, since the logical units in the processor and the storage cells in the memory have different structures and technologies, the degree of performance improvement of the processor and the memory is different. Specifically, the storage density and read / write speed of the memory cannot catch up with the operating speed of the processor, and the "storage wall" appears, which ultimately limits the overall performance improvement of electronic products.

[0097] To solve the above problems, various types of memories have emerged. Among various types of memories, gain cell memory is widely used, and the main target application scenarios of gain cell memory are high-speed and high-density memories. The gain cell memory with a 2T0C structure can achieve a read / write speed at the nanosecond level and a storage time at the millisecond level. The storage time refers to the time for which the information stored in the memory is retained, that is, the time from the point when the information is written to the point when the information is correctly read. However, the storage time of the gain cell memory with a 2T0C structure is relatively short, and the gain cell memory with a 2T0C structure needs to be continuously refreshed in actual applications. This causes relatively large dynamic power consumption.

[0098] Based on the above description, in order to improve the retention duration of the memory with a 2T0C structure and solve the problem that the power consumption of the gain cell memory with a 2T0C structure is relatively large, currently, the gain cell memory with a 2T0C structure can be prepared based on TFTs. On the one hand, the advantage of the ultra-low leakage current of TFTs can be used, thereby significantly increasing the retention time of the memory with a 2T0C structure and reducing the dynamic power consumption; on the other hand, the advantage of the low temperature of the TFT manufacturing process can be used. Thereby, three-dimensional (3D) memory integration can be implemented to improve the storage density.

[0099] Referring to FIG. 2a, FIG. 2a is a schematic diagram of the structure of a memory cell in a 2T0C structure memory. The memory cell includes a first thin film transistor Tr0 and a second thin film transistor Tr1. The gate of the second thin film transistor Tr1 is electrically connected to a write word line WWL, the source of the second thin film transistor Tr1 is electrically connected to a write bit line WBL, the drain of the second thin film transistor Tr1 is electrically connected to the gate of the first thin film transistor Tr0, and the source of the first thin film transistor Tr0 is electrically connected to a read word line RWL. The drain of the first thin film transistor Tr0 is electrically connected to a read bit line RBL.

[0100] FIGS. 2b and 2c are schematic diagrams of the structures of the first thin film transistor Tr0 and the second thin film transistor Tr1, respectively, within a memory cell of a TFT-based memory having a 2T0C structure. Referring to FIGS. 2b and 2c, both the first thin film transistor Tr0 and the second thin film transistor Tr1 include a semiconductor layer 102 disposed on a substrate 101, a source 103 and a drain 104 disposed on the semiconductor layer 102 and in contact with the semiconductor layer 102, a gate insulating layer 105 disposed on the semiconductor layer 102, and a gate 106 disposed on the gate insulating layer 105. In addition, the interlayer dielectric layer 107 in FIGS. 2b and 2c is configured to separate different conductive film layers, and the signal lines are electrically connected to the corresponding electrodes by using vias. For example, the read word line RWL is electrically connected to the source 103 of the first thin film transistor Tr0 by using a via.

[0101] However, in the first thin-film transistor Tr0 and the second thin-film transistor Tr1 shown in FIGS. 2b and 2c, the semiconductor layers 102 both extend along a plane parallel to the gate 106, and the source 103 and the drain 104 are arranged in the same layer. Thus, the sizes of the first thin-film transistor Tr0 and the second thin-film transistor Tr1 are relatively large, and the area utilization rates of the first thin-film transistor Tr0 and the second thin-film transistor Tr1 are low. In addition, since the source 103 and the drain 104 are located in the same layer, short circuits easily occur in the signal line electrically connected to the source electrode 103 and the signal line electrically connected to the drain electrode 104, which does not contribute to the routing and increases the difficulty of the process.

[0102] To solve the above problems, some embodiments of the present application provide a memory. The memory can be used in an electronic device. The electronic device may be a mobile phone, a tablet computer, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a mobile phone, a personal digital assistant (PDA), an augmented reality (AR) device, a virtual reality (VR) device, an artificial intelligence (AI) device, a wearable device, an in-vehicle device, a smart home device, and / or a smart city device, and the specific type of the electronic device is not particularly limited in the embodiments of the present application.

[0103] FIG. 3 is a schematic diagram of the structure of an electronic device. The electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identity module (SIM) card interface 195.

[0104] It can be understood that the structure shown in this embodiment of the present application does not constitute a specific limitation on the electronic device 100. In some other embodiments of the present application, the electronic device 100 may include more or fewer components than those shown in the figure, or some components may be combined, or some components may be divided, or different component deployments may be used. The components shown in the figure may be implemented by hardware, software, or a combination of software and hardware.

[0105] Processor 110 may include one or more processing units. For example, processor 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU). Different processing units may be independent components or may be integrated into one or more processors.

[0106] The controller may generate an operation control signal based on the instruction operation code and the time series signal to complete the control of instruction reading and instruction execution.

[0107] Memory may be further disposed within processor 110 and is configured to store instructions and data. In some embodiments, the memory within processor 110 is cache memory. The memory may store instructions or data that have just been used or are periodically used by processor 110. When processor 110 needs to reuse an instruction or data, the processor can directly call the instruction or data from the memory. This avoids repeated accesses, reduces the latency of processor 110, and thus improves system efficiency.

[0108] In some embodiments, processor 110 may include one or more interfaces. The interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface.

[0109] The I2C interface is a bidirectional synchronous serial bus and includes a serial data line (SDA) and a serial clock line (SCL). The I2S interface may be configured to perform audio communication.

[0110] The PCM interface also performs audio communication and is configured to sample, quantize, and encode analog signals.

[0111] The UART interface is a universal serial data bus and is configured to perform asynchronous communication. The bus may be a bidirectional communication bus. The UART interface converts data to be transmitted between serial communication and parallel communication.

[0112] The MIPI interface can be configured to connect the processor 110 to peripheral components such as the display screen 194 or the camera 193. The MIPI interface includes a camera serial interface (CSI), a display serial interface (DSI), and the like.

[0113] The GPIO interface may be configured by software. The GPIO interface can be configured as a control signal or a data signal. Alternatively, the GPIO interface can be configured as an I2C interface, an I2S interface, a UART interface, or a MIPI interface.

[0114] The USB interface 130 is an interface compliant with the USB standard specification. Specifically, it may be a Mini USB interface, a Micro USB interface, or a USB Type-C interface. The USB interface 130 may be configured to connect to a charger to charge the electronic device 100, or may be configured to transmit data between the electronic device 100 and a peripheral device, or may be configured to connect to a headset to play audio by using the headset.

[0115] It can be understood that the interface connection relationship between the modules shown in this embodiment of the present invention is only an example for explanation and does not constitute a limitation on the structure of the electronic device 100. In some other embodiments of the present application, the electronic device 100 may alternatively use an interface connection method different from that in the foregoing embodiments, or may use a combination of multiple interface connection methods.

[0116] The charging management module 140 is configured to receive a charging input from a charger. The charger can be a wireless charger or a wired charger.

[0117] The power management module 141 is configured to connect to the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives inputs from the battery 142 and / or the charging management module 140 and supplies power to the processor 110, the internal memory 121, the display screen 194, the camera 193, and the wireless communication module 160. The power management module 141 may be further configured to monitor parameters such as battery capacity, battery cycle count, and battery health (leakage or impedance). In some other embodiments, the power management module 141 may alternatively be disposed within the processor 110. In some other embodiments, the power management module 141 and the charging management module 140 may alternatively be disposed within the same component.

[0118] The wireless communication function of the electronic device 100 may be implemented by using the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, the modem processor, and the baseband processor.

[0119] The antenna 1 and the antenna 2 are configured to transmit and receive electromagnetic wave signals. Each antenna within the electronic device 100 may be configured to cover one or more communication frequency bands. Different antennas may be further multiplexed to improve antenna utilization. For example, the antenna 1 may be multiplexed as a diversity antenna for a wireless local area network. In some other embodiments, the antenna may be used in combination with a tuning switch.

[0120] The mobile communication module 150 can provide wireless communication solutions including 2G / 3G / 4G / 5G applicable to the electronic device 100. The mobile communication module 150 may include at least one filter, switch, power amplifier, and low noise amplifier (LNA). The mobile communication module 150 can receive electromagnetic waves through the antenna 1, perform processing such as filtering or amplification on the received electromagnetic waves, and transmit the electromagnetic waves to the modem processor for demodulation. The mobile communication module 150 further amplifies the signal modulated by the modem processor and converts the signal into electromagnetic waves for radiation through the antenna 1.

[0121] The modem processor may include a modulator and a demodulator. The modulator is configured to modulate a low-frequency baseband signal to be transmitted into a medium-high frequency signal. The demodulator is configured to demodulate the received electromagnetic wave signal into a low-frequency baseband signal. Next, the demodulator transmits the low-frequency baseband signal obtained through demodulation to the baseband processor for processing. The low-frequency baseband signal is processed by the baseband processor and then transmitted to the application processor. The application processor outputs an audio signal using an audio device (not limited to a speaker or a telephone receiver), or displays an image or video using the display screen 194.

[0122] The wireless communication module 160 is applied to the electronic device 100 and can provide wireless communication solutions including wireless local area network (WLAN) (e.g., wireless fidelity (Wi-Fi) network), Bluetooth (registered trademark) (Bluetooth, BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC) technology, or infrared (IR) technology. The wireless communication module 160 can be one or more components integrating at least one communication processor module. The wireless communication module 160 receives electromagnetic waves through the antenna 2, performs frequency modulation and filtering processing on the electromagnetic wave signals, and sends the processed signals to the processor 110. The wireless communication module 160 further receives the signals to be transmitted from the processor 110, performs frequency modulation and amplification on the signals, and converts the signals into electromagnetic waves for radiation through the antenna 2.

[0123] In some embodiments, the antenna 1 of the electronic device 100 is electrically connected to the mobile communication module 150, and the antenna 2 is electrically connected to the wireless communication module 160, whereby the electronic device 100 can communicate with networks and other devices by using wireless communication technologies. The wireless communication technologies include global system for mobile communications (GSM (registered trademark)), general packet radio service (GPRS), and code division multiple access (CDMA).

[0124] The electronic device 100 can implement a display function through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing and is connected to the display screen 194 and the application processor. The GPU is configured to execute mathematical and geometric calculations and render images. The processor 110 can include one or more GPUs that execute program instructions for generating or changing display information.

[0125] The display screen 194 is configured to display images or videos. In some embodiments, the electronic device 100 can include one or N display screens 194, where N is a positive integer greater than 1.

[0126] The electronic device 100 can implement a photography function through an ISP, a camera 193, a video codec, a GPU, a display screen 194, and an application processor.

[0127] The ISP is configured to process data fed back by the camera 193.

[0128] The camera 193 is configured to capture still images or videos. In some embodiments, the electronic device 100 may include one or N cameras 193, where N is a positive integer greater than 1.

[0129] The external memory interface 120 may be configured to connect to an external memory card, such as a micro SD card, to expand the storage capacity of the electronic device 100. The external memory card communicates with the processor 110 through the external memory interface 120 to implement a data storage function. For example, files such as music and videos are stored in the external memory card.

[0130] The internal memory 121 may be configured to store computer-executable program code. The executable program code includes instructions. The internal memory 121 may include a program storage area and a data storage area. The program storage area may store an operating system and an application program required by at least one function (for example, an audio playback function or an image display function). The data storage area can store data (such as audio data and an address book) created during the use of the electronic device 100. In addition, the internal memory 121 may include a high-speed random access memory, or may include a non-volatile memory, for example, at least one magnetic disk storage device, a flash memory device, or a universal flash storage (UFS). The processor 110 executes the instructions stored in the internal memory 121 and / or the instructions stored in the memory disposed within the processor to perform various functional applications and data processing of the electronic device 100.

[0131] The electronic device 100 can implement audio functions, such as music playback and recording functions, by using the audio module 170 and the application processor.

[0132] The audio module 170 is configured to convert digital audio information into an analog audio signal for output, and is also configured to convert an analog audio input into a digital audio signal. The audio module 170 may be further configured to encode and decode audio signals.

[0133] The button 190 includes a power button, a volume button, etc. The button 190 may be a mechanical button or a touch button. The electronic device 100 can receive a button input and generate a button signal input related to user settings and function control of the electronic device 100.

[0134] The motor 191 may generate a vibration prompt. The motor 191 may be configured to provide an incoming call vibration prompt and a touch vibration feedback.

[0135] The indicator 192 may be an indicator light and may be configured to indicate a charging status and a power change, or may be configured to indicate a message, a missed call, and a notification.

[0136] The SIM card interface 195 is configured to connect to a SIM card. The SIM card may be inserted into or removed from the SIM card interface 195 to achieve contact with or separation from the electronic device 100. The electronic device 100 may support one or N SIM card interfaces, where N is a positive integer greater than 1.

[0137] Based on this, the electronic device 100 may further include a circuit board, such as a printed circuit board (PCB). The processor 110 and the internal memory 121 may be disposed on the circuit board, and the processor 110 and the internal memory 121 are electrically connected to the circuit board.

[0138] The memory provided in this embodiment of the present application may be used as the internal memory 121 within the electronic device 100, or may be used as the memory within the processor 110 of the electronic device 100.

[0139] The memory provided in this embodiment of the present application may be an off-chip memory or may be an on-chip memory (which may also be referred to as an embedded memory).

[0140] In addition, the memory provided in this embodiment of the present application may be a memory prepared based on a back end of line (BEOL) process.

[0141] Referring to FIG. 4, the memory 200 includes at least one layer of a memory array 201 disposed on a substrate 101. FIG. 4 is a schematic diagram by using an example in which the memory 200 includes a two-layer memory array 201. When the memory 200 includes a multi-layer memory array 201, as shown in FIG. 4, the memory arrays 201 may be sequentially stacked along the vertical direction.

[0142] Also, when the memory 200 includes a multi-layer memory array 201, the memory 200 may also be referred to as a three-dimensional integrated memory.

[0143] In addition, the number of layers of the memory array 201 may be stacked as needed. The larger the number of layers of the stacked memory array 201, the higher the memory density of the memory 200.

[0144] When the memory 200 includes a multi-layer memory array 201, in some embodiments, referring to FIG. 4, the memory 200 further includes a sixth dielectric layer 202 disposed between two adjacent layers of the memory array 201, and two adjacent layers of the memory array 201 are separated by using the sixth dielectric layer 202.

[0145] The material of the sixth dielectric layer 202 is SiO 2 (silicon dioxide), Al 2 O 3 (aluminum oxide), HfO 2 (hafnium dioxide), ZrO 2 (zirconium oxide), TiO 2 (titanium dioxide), Y 2 O 3 (yttrium trioxide), and Si 3 N 4 (silicon nitride), or one or more of insulating materials such as these may be used.

[0146] The sixth dielectric layer 202 may have a single-layer structure or a multilayer stacked structure. Also, the material of the single-layer structure and the materials of the respective layers in the multilayer stacked structure may be one or more of SiO 2 、Al 2 O 3 、HfO 2 、ZrO 2 、TiO 2 、Y 2 O 3 and Si 3 N 4 among others.

[0147] Referring to FIGS. 5 and 6a, each layer of the memory array 201 includes a plurality of memory cells 201A, write word lines WWL (write word line), write bit lines WBL (write bit line), read word lines RWL (read word line), and read bit lines RBL (read bit line) arranged in an array.

[0148] Referring to FIGS. 6a, 6b, 6c, 6d, and 6e, the memory cell 201A includes a stacked first thin film transistor Tr0 and second thin film transistor Tr1.

[0149] The first thin film transistor Tr0 includes a gate 106a, and the gate 106a includes a gate base 1061a located at the upper part and a gate body 1062a extending from the gate base 1061a to the bottom. The first thin film transistor Tr0 further includes a first electrode 109a, a second electrode 108a, a first dielectric layer 113a, a second dielectric layer 112a, and a semiconductor layer 102a. The first electrode 109a is located at the bottom, and the second electrode 108a is located between the first electrode 109a and the gate base 1061a. The first dielectric layer 113a is disposed between the second electrode 108a and the first electrode 109a, and the first dielectric layer 113a is configured to separate the first electrode 109a from the second electrode 108a. The semiconductor layer 102a is disposed along the side surface of the gate body 1062a, and the second dielectric layer 112a separates the semiconductor layer 102a from the gate 106a. The first electrode 109a and the second electrode 108a are each electrically connected to the semiconductor layer 102a.

[0150] As shown in FIGS. 6a, 6b, 6c, and 6d, the second dielectric layer 112a covers the surface of the gate base 1061a and the surface of the gate body 1062a. Also, the second dielectric layer 112a surrounds the outside of the gate body 1062a on the first electrode 109a, the semiconductor layer 102a surrounds the outside of the second dielectric layer 112a, the second electrode 108a is disposed outside the semiconductor layer 102a and is electrically connected to the semiconductor layer 102a. The second electrode 108a is on the first electrode 109a and is separated by the first dielectric layer 113a, and the first electrode 109a is electrically connected to the semiconductor layer 102a.

[0151] The second thin film transistor Tr1 includes a gate 106b, and the gate 106b includes a gate base 1061b located at the upper part and a gate body 1062b extending from the gate base 1061b to the bottom. The second thin film transistor Tr1 further includes a first electrode 109b, a second electrode 108b, a first dielectric layer 113b, a second dielectric layer 112b, and a semiconductor layer 102b. The first electrode 109b is located at the bottom, and the second electrode 108b is located between the first electrode 109a and the gate base 1061a. The first dielectric layer 113b is disposed between the second electrode 108b and the first electrode 109b, and the first dielectric layer 113b is configured to separate the first electrode 109b from the second electrode 108b. The second dielectric layer 112b covers the surface of the gate base 1061b and the surface of the gate body 1062b. The semiconductor layer 102b is disposed along the side surface of the gate body 1062b, and the second dielectric layer 112b separates the semiconductor layer 102b from the gate 106b. The first electrode 109b and the second electrode 108b are each electrically connected to the semiconductor layer 102b.

[0152] As shown in FIGS. 6a, 6b, 6c, and 6d, the second dielectric layer 112b surrounds the outside of the gate body 1062b on the first electrode 109b, the semiconductor layer 102b surrounds the outside of the second dielectric layer 112b, the second electrode 108b is disposed outside the semiconductor layer 102b and is electrically connected to the semiconductor layer 102b. The second electrode 108b is on the first electrode 109b and is separated by the first dielectric layer 113b, and the first electrode 109b is electrically connected to the semiconductor layer 102b.

[0153] The gate 106b (gate, G) of the second thin-film transistor Tr1 is electrically connected to the write word line WWL, and the second electrode 108b is electrically connected to the write bit line WBL. The first electrode 109a and the second electrode 108a of the first thin-film transistor Tr0 are electrically connected to the read word line RWL and the read bit line RBL, respectively. The first electrode 109b of the second thin-film transistor Tr1 is close to the gate 106a of the first thin-film transistor Tr0, and the first electrode 109b of the second thin-film transistor Tr1 is electrically connected to the gate 106a of the first thin-film transistor Tr0.

[0154] FIG. 6b is a schematic cross-sectional view along the first direction X in FIG. 6a, and FIG. 6c is a schematic cross-sectional view along the second direction Y in FIG. 6a. FIG. 6d is a schematic cross-sectional view along the direction AA in FIG. 6b or FIG. 6c, and FIG. 6e is another schematic cross-sectional view along the direction AA in FIG. 6b or FIG. 6c.

[0155] It can be understood that the memory 200 provided in this embodiment of the present application is a memory with a gain cell structure based on a 2T0C structure.

[0156] In some embodiments, the first electrode 109b of the second thin-film transistor Tr1 is in direct contact with the gate 106a of the first thin-film transistor Tr0. In some other embodiments, referring to FIGS. 6a, 6b, and 6c, both the first electrode 109b of the second thin-film transistor Tr1 and the gate 106a of the first thin-film transistor Tr0 are in contact with the connection electrode 111, and the first electrode 109b of the second thin-film transistor Tr1 is electrically connected to the gate 106a of the first thin-film transistor Tr0 by using the connection electrode 111.

[0157] Note that the second thin-film transistor Tr1 is a write transistor, and the first thin-film transistor Tr0 is a read transistor.

[0158] The structures of the second thin film transistor Tr1 and the first thin film transistor Tr0 may be the same or different. It should be understood that in some embodiments, the projection of the second thin film transistor Tr1 onto the substrate overlaps the projection of the first thin film transistor Tr0 onto the substrate.

[0159] The write word line WWL may be manufactured in synchronization with the gate 106b of the second thin film transistor Tr1, and the write bit line WBL may be manufactured in synchronization with the second electrode 108b of the second thin film transistor Tr1.

[0160] The second electrode 108a of the first thin film transistor Tr0 may be electrically connected to the read word line RWL, and the first electrode 109a may be electrically connected to the read bit line RBL. In this case, the second electrode 108a of the first thin film transistor Tr0 and the read word line RWL may be manufactured in synchronization, and the first electrode 109a of the first thin film transistor Tr0 and the read bit line RBL may be manufactured in synchronization. Alternatively, the second electrode 108a of the first thin film transistor Tr0 may be electrically connected to the read bit line RBL, and the first electrode 109a may be electrically connected to the read word line RWL. In this case, the second electrode 108a of the first thin film transistor Tr0 and the read bit line RBL may be manufactured in synchronization, and the first electrode 109a of the first thin film transistor Tr0 and the read word line RWL may be manufactured in synchronization.

[0161] In this embodiment of the present application, for the first thin film transistor Tr0, the second electrode 108a may be the source (S) 103, and the first electrode 109a may be the drain (D) 104; or the second electrode 108a may be the drain 104, and the first electrode 109a may be the source 103. For the second thin film transistor Tr1, the second electrode 108b may be the source 103, and the first electrode 109b may be the drain 104; or the second electrode 108b may be the drain 104, and the first electrode 109b may be the source 103.

[0162] Note that both the first thin film transistor Tr0 and the second thin film transistor Tr1 may be N-type transistors, or P-type transistors. Of course, one of the first thin film transistor Tr0 and the second thin film transistor Tr1 may be an N-type transistor and the other may be a P-type transistor.

[0163] In some embodiments, the plurality of first thin film transistors Tr0 included in each layer of the memory array 201 may be manufactured synchronously, and / or the plurality of second thin film transistors Tr1 included in each layer of the memory array 201 may be manufactured synchronously.

[0164] Referring to FIG. 5, the following describes the write operation process and read operation process of the memory 200 by using one memory cell 201A as an example.

[0165] Writing operation process: In the writing operation process, the voltages on the read word line RWL and the read bit line RBL are 0, and the first thin film transistor Tr0 does not operate. The write word line WWL provides a first switch signal, and the first switch signal controls the second thin film transistor Tr1 to be turned on. When the first logical information is written and the first logical information is, for example, "0", the write bit line WBL provides a first level signal, and the first level signal is written to the node N by using the second thin film transistor Tr1, and the first level signal can control the first thin film transistor Tr0 to be turned on. When the second logical information is written and the second logical information is, for example, "1", the write bit line WBL provides a second level signal, and the second level signal is written to the node N by using the second thin film transistor Tr1. Here, the second level signal can control the first thin film transistor Tr0 to be turned off.

[0166] After the writing operation is completed, it should be understood that the voltages on the read word line RWL and the read bit line RBL are 0, and the first thin film transistor Tr0 does not operate. The write word line WWL provides a second switch signal, and the second switch signal controls the second thin film transistor Tr1 to be turned off. In this case, the potential stored by the node N is not affected by the external environment.

[0167] Read operation process: The write word line WWL provides a second switch signal, and the second switch signal controls the second thin film transistor Tr1 to be turned off. The read word line RWL provides a third level signal, and the logical information stored in the memory cell 201A is determined based on the current on the read bit line RBL. When the node N stores the first level signal, since the first level signal can control the first thin film transistor Tr0 to be turned on, when the read word line RWL provides the third level signal, the read word line RWL charges the read bit line RBL by using the first thin film transistor Tr0, and the voltage of the read bit line RBL rises. In this way, when it is detected that the current on the read bit line RBL is relatively large, the logical information "0" stored in the memory cell 201A can be read. When the node N stores the second level signal, since the second level signal can control the first thin film transistor Tr0 to be turned off, when the read word line RWL provides the third level signal, the read word line RWL does not charge the read bit line RBL by using the first thin film transistor Tr0, and the read bit line RBL maintains a 0V voltage. In this way, when it is detected that the current on the read bit line RBL is relatively small, the logical information "1" stored in the memory cell 201A can be read.

[0168] Regarding a plurality of second thin film transistors Tr1, in some embodiments, referring to FIGS. 5, 6a, and 6b, the gates 106b of the second thin film transistors Tr1 in a plurality of memory cells 201A sequentially arranged in each layer of the memory array 201 along the first direction X are electrically connected to the same write word line WWL. Referring to FIGS. 5, 6a, and 6c, the second electrodes 108b of the second thin film transistors Tr1 in a plurality of memory cells 201A sequentially arranged in each layer of the memory array 201A along the second direction Y are electrically connected to the same write bit line WBL. Here, the first direction X intersects the second direction Y.

[0169] In some examples, the first direction X and the second direction Y are orthogonal. For simplicity of description, hereinafter, an example will be used in which the first direction X is the row direction and the second direction Y is the column direction.

[0170] In each layer of the memory array 201, the gates 106b of the second thin film transistors Tr1 in the plurality of memory cells 201A sequentially arranged along the first direction X are electrically connected to the same write word line WWL, and the second electrodes 108b of the second thin film transistors Tr1 in the plurality of memory cells 201A sequentially arranged along the second direction Y are electrically connected to the same write bit line WBL. Therefore, in the write operation process, a first switch signal may be provided for each row with respect to the plurality of write word lines WWL, whereby a plurality of rows of the second thin film transistors Tr1 are turned on one by one. When the first switch signal is provided to the write word line WWL of the current row, logical information is simultaneously written to the plurality of memory cells 201A electrically connected to the write word line WWL of the current row by using the plurality of write bit lines WBL. Thereby, logical information is written to the memory cells 201A row by row, thereby realizing a rapid write of the plurality of memory cells 201A in the memory array 201.

[0171] For example, the plurality of first thin film transistors Tr0 can be connected in the following four modes.

[0172] When the first electrode 109a of the first thin film transistor Tr0 is electrically connected to the read bit line RBL and the second electrode 108a is electrically connected to the read word line RWL, the following first mode or second mode may be used.

[0173] First aspect: Referring to FIGS. 5, 6a, and 6b, the second electrode 108a of the first thin-film transistor Tr0 in a plurality of memory cells 201A sequentially arranged in each layer of the memory array 201 along the first direction X is electrically connected to the same read word line RWL; Referring to FIGS. 5, 6a, and 6c, the first electrode 109a of the first thin-film transistor Tr in a plurality of memory cells 201A sequentially arranged in each layer of the memory array 201 along the second direction Y is electrically connected to the same read bit line RBL. Here, the first direction X intersects the second direction Y.

[0174] In each layer of the memory array 201, the second electrode 108a of the first thin-film transistor Tr0 in a plurality of memory cells 201A arranged sequentially along the first direction X is electrically connected to the same read word line RWL, and the first electrode 109a of the first thin-film transistor Tr0 in a plurality of memory cells 201A arranged sequentially along the second direction Y is electrically connected to the same read bit line RBL. Thus, in the read operation process, a third-level signal may be provided to the plurality of read word lines RWL row by row. When the third-level signal is provided to the read word line RWL of the current row, the current on each read bit line RBL is detected. In this way, the logical information stored in the plurality of memory cells 201A electrically connected to the read word line RWL of the current row can be read simultaneously. Thereby, the logical information stored in the memory cell 201A can be read row by row, thereby enabling rapid reading of the plurality of memory cells 201A in the memory array 201.

[0175] Second aspect: The second electrodes 108a of the first thin-film transistors Tr0 of the plurality of memory cells 201A sequentially arranged in each layer of the memory array 201 along the second direction Y are electrically connected to the same read word line RWL, and the first electrodes 109a of the first thin-film transistors Tr0 in the plurality of memory cells 201A sequentially arranged in each layer of the memory array 201 along the first direction X are electrically connected to the same read bit line RBL. Here, the first direction X intersects the second direction Y.

[0176] When the first electrode 109a of the first thin-film transistor Tr0 is electrically connected to the read word line RWL and the second electrode 108a is electrically connected to the read bit line RBL, the following third aspect or fourth aspect may be used.

[0177] Third aspect: The second electrodes 108a of the first thin-film transistors Tr0 in the plurality of memory cells 201A sequentially arranged in each layer of the memory array 201 along the first direction X are electrically connected to the same read bit line RWL; the first electrodes 109a of the first thin-film transistors Tr0 in the plurality of memory cells 201A sequentially arranged in each layer of the memory array 201 along the second direction Y are electrically connected to the same read word line RWL. Here, the first direction X intersects the second direction Y.

[0178] Fourth aspect: The second electrodes 108a of the first thin-film transistors Tr0 in the plurality of memory cells 201A sequentially arranged in each layer of the memory array 201 along the second direction Y are electrically connected to the same read bit line RWL; the first electrodes 109a of the first thin-film transistors Tr0 in the plurality of memory cells 201A sequentially arranged in each layer of the memory array 201 along the first direction X are electrically connected to the same read word line RWL. Here, the first direction X intersects the second direction Y.

[0179] It should be noted that the second, third, and fourth aspects have the same technical effects as the first aspect. For details, refer to the above description of the technical effects of the first aspect. Details will not be described again here.

[0180] Based on the above description, for each layer of the memory array 201, the amount of memory cells 201A along the first direction X and / or the second direction Y may be increased to implement a larger-scale memory array.

[0181] Referring to FIG. 7, in some embodiments, the memory 200 further includes an integrated circuit 203, and the memory array 201 is disposed on the integrated circuit 203. In this case, the memory 200 is an on-chip memory. In this case, the substrate in the memory 200 is the integrated circuit 203.

[0182] The substrate of the integrated circuit 203 may be a silicon substrate, that is, the integrated circuit 203 may be an integrated circuit on a silicon substrate.

[0183] Also, the integrated circuit 203 may be a control circuit of the memory array 201, or may be other functional circuits.

[0184] It should be noted that since the process temperature for manufacturing thin film transistors is relatively low, the memory array 201 can be integrated into the backend of the integrated circuit 203. In addition, for implementing 3D system integration, stacking of multiple layers of the memory array 201 may be performed on the integrated circuit 203.

[0185] In some examples, the memory cells 201A in the memory array 201 may be electrically connected to the integrated circuit 203. For example, the memory cells 201A in the memory array 201 may be connected to a lower integrated circuit 203 by using interconnecting lines.

[0186] Embodiments of the present application further provide a thin film transistor 10. This thin film transistor may be used as the first thin film transistor Tr0 described above, or may be used as the second thin film transistor Tr1 described above.

[0187] Hereinafter, the structure of the thin film transistor 10 will be described in detail.

[0188] Referring to FIGS. 8a, 8b, and 8c, the thin film transistor 10 includes a gate 106, a first electrode 109, a second electrode 108, a first dielectric layer 113, a second dielectric layer 112, and a semiconductor layer 102.

[0189] The gate 106 includes a gate base 1061 located at the upper part and a gate body 1062 extending from the gate base 1061 to the bottom. The first electrode 109 is located at the bottom. The second electrode 108 is located between the first electrode 109 and the gate base 1061. The first dielectric layer 113 is disposed between the second electrode 108 and the first electrode 109, and the first dielectric layer 113 is configured to separate the first electrode 109 from the second electrode 108. The second dielectric layer 112 covers the surface of the gate base 1061 and the surface of the gate body 1062. The semiconductor layer 102 is disposed along the side surface of the gate body 1062, and the second dielectric layer 112 separates the semiconductor layer 102 from the gate 106. The first electrode 109 and the second electrode 108 are each electrically connected to the semiconductor layer 102.

[0190] FIG. 8b is a schematic cross-sectional view along the BB direction of FIG. 8a, and FIG. 8c is another schematic cross-sectional view along the BB direction of FIG. 8a.

[0191] As shown in FIGS. 8a and 8b, the second dielectric layer 112 surrounds the outside of the gate body 1062 on the first electrode 109, the semiconductor layer 102 surrounds the outside of the second dielectric layer 112, the second electrode 108 is disposed outside the semiconductor layer 102 and is electrically connected to the semiconductor layer 102. The second electrode 108 is on the first electrode 109 and is separated by the first dielectric layer 113, and the first electrode 109 is electrically connected to the semiconductor layer 102.

[0192] Note that the gate body 1062 has a surface in contact with the gate base 1061, a surface away from the gate base 1061, and side surfaces. The surface in contact with the gate base 1061 and the surface away from the gate base 1061 are disposed opposite to each other.

[0193] In some embodiments, the gate body 1062 and the gate base 1061 are integrally formed. In some other embodiments, the gate body 1062 and the gate base 1061 are manufactured separately.

[0194] In some examples, the gate body 1062 is disposed perpendicular to the gate base 1061.

[0195] The first electrode 109 forms a resistive contact with the semiconductor layer 102, and the second electrode 108 forms a resistive contact with the semiconductor layer 102. Also, the fact that the first electrode 109 is electrically connected to the semiconductor layer 102 may mean that the first electrode 109 is in direct contact with the semiconductor layer 102, or the first electrode 109 is not in direct contact with the semiconductor layer 102 and is electrically connected to the semiconductor layer 102 using another medium. Similarly, the fact that the second electrode 108 is electrically connected to the semiconductor layer 102 may mean that the second electrode 108 is in direct contact with the semiconductor layer 102, or the second electrode 108 is not in direct contact with the semiconductor layer 102 and is electrically connected to the semiconductor layer 102 using another medium.

[0196] Note that, the first electrode 109 of the thin film transistor 10 may be a drain, and the second electrode 108 may be a source; alternatively, the first electrode 109 of the thin film transistor 10 may be a source, and the second electrode 108 may be a drain.

[0197] Also, the thin film transistor 10 may be an N-type transistor, or may be a P-type transistor.

[0198] In addition, since the second dielectric layer 112 covers the surfaces of the gate base 1061 and the gate body 1062, as shown in FIG. 8a, the second dielectric layer 112 includes a first dielectric portion 1121 and a second dielectric portion 1122. The first dielectric portion 1121 covers the surface of the gate base 1061, and the second dielectric portion 1122 covers the surface of the gate body 1062.

[0199] Based on this, in some embodiments, the first dielectric portion 1121 and the second dielectric portion 1122 are manufactured synchronously. In some other embodiments, the first dielectric portion 1121 and the second dielectric portion 1122 may be manufactured separately.

[0200] If the distance between the first electrode 109 and the second electrode 108 is too short, there may be a risk that the first electrode 109 and the second electrode 108 are directly conductive when manufacturing the first electrode 109 and the second electrode 108. To avoid direct conduction between the first electrode 109 and the second electrode 108, in some embodiments, the second electrode 108 is disposed close to the gate base 1061.

[0201] It should be understood that the materials of the gate 106, the first electrode 109, and the second electrode 108 are all conductive materials, such as metal materials. Specifically, the materials of the gate 106, the first electrode 109, and the second electrode 108 may be one or more of conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), etc.

[0202] For the materials of the first dielectric layer 113 and the second dielectric layer 112, refer to the materials of the sixth dielectric layer 202. Details will not be described again here. Also, the first dielectric layer 113 and the second dielectric layer 112 may each have a single-layer structure or a multi-layer stacked structure.

[0203] The material of the semiconductor layer 102 may be one or more of semiconductor materials such as Si (silicon), poly-Si (p-Si, polysilicon), amorphous-Si (a-Si, amorphous silicon), In-Ga-Zn-O (IGZO, indium gallium zinc oxide) polycompound, ZnO (zinc oxide), ITO, TiO 2 (titanium dioxide), and MoS 2 (molybdenum disulfide), etc.

[0204] One embodiment of the present invention provides a thin-film transistor 10. The gate 106 of the thin-film transistor 10 includes a gate base 1061 located at the upper part and a gate body 1062 extending from the gate base 1061 to the bottom. The semiconductor layer 102 is arranged along the side of the gate body 1062. The first electrode 109 is located at the bottom, the second electrode 108 is located between the first electrode 109 and the gate base 1061, and the first electrode 109 and the second electrode 108 are each electrically connected to the semiconductor layer 102. In the prior art, the semiconductor layer 102 is arranged along a plane parallel to the gate 106 (the gate 106 in the prior art is equivalent to the gate base 1061 in this embodiment of the present application). The second electrode 108 and the first electrode 109 are arranged in the same layer. As a result, the size of the thin-film transistor 10 provided in this embodiment of the present application is relatively small in a plane parallel to the gate base 1061. Therefore, in this embodiment of the present application, the size of the thin-film transistor 10 is reduced and the area utilization rate is improved. In addition, since the second electrode 108 and the first electrode 109 of the thin-film transistor 10 in this embodiment of the present application are located in different layers, a short circuit that occurs during the routing of the signal line electrically connected to the second electrode 108 and the signal line electrically connected to the first electrode 109 can be avoided, thereby reducing the difficulty of the process.

[0205] When the structures of the first thin-film transistor Tr0 and the second thin-film transistor Tr1 in the memory 200 are the thin-film transistor 10 described above, the sizes of the first thin-film transistor Tr0 and the second thin-film transistor Tr1 in the memory 200 can be reduced, and the area utilization rate can be improved.

[0206] Regarding the structure of the gate 106, the following three implementations can be used as examples.

[0207] First implementation: As shown in FIGS. 8a, 9, 10, and 11, the boundary of the projection of the gate body 1062 onto the gate base 1061 is located within the boundary of the gate base 1061, that is, the gate body 1062 is disposed in the intermediate region of the gate base 1061.

[0208] Second implementation: As shown in FIGS. 12a and 12c, the boundary of the projection of the gate body 1062 onto the gate base 1061 partially overlaps the boundary of the gate base 1061, that is, the gate body 1062 is disposed in the edge region of the gate base 1061.

[0209] Third implementation: As shown in FIG. 12b, the gate body 1062 has a hollow structure, and the outer boundary of the projection of the gate body 1062 on the gate base 11061 overlaps the boundary of the gate base 1061.

[0210] It should be understood that since the gate body 1062 has a hollow structure, the projection of the gate body 1062 on the gate base 1061 includes two boundaries, namely an outer boundary and an inner boundary. The boundary closer to the center of the gate base 1061 is called the inner boundary, and the boundary farther from the center of the gate base 10161 is called the outer boundary.

[0211] In addition, since the gate body 1062 has a hollow structure and the outer boundary of the projection of the gate body 1062 on the gate base 1061 overlaps the boundary of the gate base 11061, at least a part of the region of the second dielectric layer 112 is located within the hollow structure, at least a part of the region of the semiconductor layer 102 is located within the hollow structure, the second electrode 108 is located within the hollow structure, and at least a part of the region of the first dielectric layer 113 is located within the hollow structure.

[0212] When the gate body 1062 has a hollow structure, the gate 106 adjusts and controls the current in the semiconductor layer 102 from the outside of the semiconductor layer 102.

[0213] Regarding the structure of the semiconductor layer 102, the following four implementations can be used as examples.

[0214] The first implementation: As shown in FIG. 8a, the semiconductor layer 102 is disposed only along the side surface of the gate body 1062.

[0215] As shown in FIG. 8a, the semiconductor layer 102 surrounds only the side surface of the gate body 1062 and is disposed on the first electrode 109.

[0216] The second electrode 108 and the first electrode 109 are electrically connected to or in end contact with the semiconductor layer 102.

[0217] The second implementation: As shown in FIG. 12c, the semiconductor layer 102 is disposed along the side surface of the gate body 1062, and the semiconductor layer 102 further includes an extension portion that extends along the surface of the gate base 1061. The second dielectric layer 112 separates the semiconductor layer 102 from the gate 106. Also, as shown in FIG. 12c, the semiconductor layer 102 is disposed on the side surface of the first dielectric layer 113 and the side surface of the second electrode 108 and covers the upper surface of the second electrode 108.

[0218] In some examples, as shown in FIG. 12c, the semiconductor layer 102 is further disposed on the side surface of the first electrode 109.

[0219] The third implementation: As shown in FIG. 9, the semiconductor layer 102 is disposed along the side surface of the gate body 1062, and the semiconductor layer 102 extends from the side surface of the gate body 1062 to the side portion of the gate body 1062 away from the gate base 1061, that is, is located between the gate body 1062 and the first electrode 109. That is, the semiconductor layer 102 further includes an extension portion located between the gate body 1062 and the first electrode 109. Also, as shown in FIG. 9, the semiconductor layer 102 covers the side surface and the bottom surface of the second dielectric layer 112.

[0220] In some examples, as shown in FIG. 9, the semiconductor layer 102 is disposed on the first electrode 109.

[0221] Fourth implementation: As shown in FIGS. 10, 11, 12a, and 12b, the semiconductor layer 102 is disposed along the side surface of the gate body 1062, and the semiconductor layer 102 further includes an extending portion extending along the surface of the gate base 1061 and an extending portion located between the gate body 1062 and the first electrode 109. In this case, the semiconductor layer 102 is in a "Z" shape. In other words, as shown in FIGS. 10, 12a, and 12b, the semiconductor layer 102 covers the side surface, bottom surface, and top surface of the second dielectric layer 112. Alternatively, as shown in FIG. 11, the semiconductor layer 102 covers the side surface and the bottom surface of the second dielectric layer 112 and further covers the bottom surface of the second electrode 108.

[0222] In some examples, as shown in FIGS. 10, 11, 12a, and 12b, the semiconductor layer 102 is disposed on the first electrode 109.

[0223] In some embodiments, as shown in FIG. 8b, the semiconductor layer 102 is disposed around the entire side surface of the gate body 1062. In this case, the semiconductor layer 102 may surround the entire side surface of the gate body 1062, or alternatively, the semiconductor layer 102 may surround a part of the side surface of the gate body 1062.

[0224] Since the semiconductor layer 102 is disposed on the entire side surface of the gate body 1062, the area of the semiconductor layer 102 can be increased, and the carrier mobility can be improved.

[0225] Regarding the second electrode 108, in some embodiments, as shown in FIGS. 8a, 9, 10, 12a, and 12b, the second electrode 108 is disposed on the side of the semiconductor layer 102 away from the second dielectric layer 112.

[0226] When the semiconductor layer 102 further includes an extending portion that extends along the surface of the gate base 1061, as shown in FIGS. 10, 12a, and 12b, when the second electrode 108 is disposed on the side of the semiconductor layer 102 away from the second dielectric layer 112, the second electrode 108 does not contact the second dielectric layer 112, and it should be understood that the second electrode 108 and the second dielectric layer 112 are separated by the semiconductor layer 102. When the semiconductor layer 102 is disposed along the side surface of the gate body 1062 and does not include an extending portion that extends along the surface of the gate base 1061, as shown in FIGS. 8a and 9, when the second electrode 108 is disposed on the side of the semiconductor layer 102 away from the second dielectric layer 112, the second electrode 108 contacts the second dielectric layer 112.

[0227] In some other embodiments, as shown in FIG. 11, the second electrode 108 may be disposed on the side of the semiconductor layer 102 close to the second dielectric layer 112. In this case, the second electrode 108 is located between the second dielectric layer 112 and the semiconductor layer 102.

[0228] Also, the second electrode 108 may be disposed around the entire side surface of the gate body 1062, or the second electrode 108 may be disposed around the side surface of the gate body 1062 but not around the entire side surface.

[0229] Regarding the first electrode 109, the first electrode 109 is located at the bottom, that is, the first electrode 109 is disposed on the side of the second electrode 108 away from the gate base 1061. In some embodiments, as shown in FIGS. 8a, 9, 10, 11, 12a, and 12b, the first electrode 109 is disposed on the side of the gate body 1062 away from the gate base 1061. In this case, the semiconductor layer 102 is disposed on the first electrode 109. In some other embodiments, as shown in FIG. 12c, the first electrode 109 is disposed on the side surface of the gate body 1062. In this case, the semiconductor layer 102 also extends along the side surface of the first electrode 109.

[0230] In some embodiments, as shown in FIG. 13, the thin film transistor 10 further includes a fourth dielectric layer 114 disposed between the second electrode 108 and the semiconductor layer 102, and / or a fifth dielectric layer 115 disposed between the first electrode 109 and the semiconductor layer 102.

[0231] For the materials of the fourth dielectric layer 114 and the fifth dielectric layer 115, refer to the material of the sixth dielectric layer 202. Details are not described again here. Also, the fourth dielectric layer 114 and the fifth dielectric layer 115 may have a single-layer structure or a multi-layer stacked structure.

[0232] It should be noted that the fourth dielectric layer 114 is disposed between the second electrode 108 and the semiconductor layer 102, and the second electrode 108 may or may not be in contact with the semiconductor layer 102. The fifth dielectric layer 115 is disposed between the first electrode 109 and the semiconductor layer 102, and the first electrode 109 may or may not be in contact with the semiconductor layer 102.

[0233] In some embodiments, to ensure reliable conduction between the first electrode 109 and the second electrode 108 using the semiconductor layer 102 when a voltage is applied to the gate 106, the thicknesses of both the fourth dielectric layer 114 and the fifth dielectric layer 115 are in the range of 0.1 nm to 2 nm.

[0234] For example, the thicknesses of the fourth dielectric layer 114 and the fifth dielectric layer 115 may be 0.1 nm, 0.5 nm, 1 nm, 1.5 nm, and 2 nm.

[0235] Since the thicknesses of the fourth dielectric layer 114 and the fifth dielectric layer 115 are relatively small and are in the range of 0.1 nm to 2 nm, even if the fourth dielectric layer 114 is disposed between the second electrode 108 and the semiconductor layer 102 and / or the fifth dielectric layer 115 is disposed between the first electrode 109 and the semiconductor layer 102, when a voltage is applied to the gate 106, the first electrode 109 and the second electrode 108 can still conduct by using the semiconductor layer 102, and the performance of the thin film transistor 10 is not affected. In addition, the fourth dielectric layer 114 is disposed between the second electrode 108 and the semiconductor layer 102 so as to avoid the diffusion problem of the second electrode 108 in the contact region with the semiconductor layer 102 and reduce the Fermi level pinning problem of the contact between the second electrode 108 and the semiconductor layer 102. The fifth dielectric layer 115 is disposed between the first electrode 109 and the semiconductor layer 102 so as to avoid the diffusion problem of the first electrode 109 in the contact region with the semiconductor layer 102 and reduce the Fermi level pinning problem of the contact between the first electrode 109 and the semiconductor layer 102.

[0236] In some embodiments, the material of the second dielectric layer 112 is a ferroelectric material. In this case, as shown in FIG. 14, the thin film transistor 10 further includes a third dielectric layer 116 disposed between the semiconductor layer 102 and the second dielectric layer 112.

[0237] For the material of the third dielectric layer 116, refer to the material of the sixth dielectric layer 202. Details will not be described again here. Also, the third dielectric layer 116 may have a single-layer structure or a multi-layer stacked structure.

[0238] When the material of the second dielectric layer 112 is a ferroelectric material, it can be understood that the gate 106, the second dielectric layer 112, and the third dielectric layer 116 form a composite gate structure. By using the composite gate structure, the thin film transistor 10 can achieve the performance of a negative capacitance transistor, and the gate control ability of the thin film transistor 10 can be improved by using negative capacitance. When the thin film transistor 10 is used in the memory 200, the performance of the memory 200 can be improved.

[0239] Note that in this embodiment of the present application, the materials of the first dielectric layer 113, the second dielectric layer 112, the third dielectric layer 116, the fourth dielectric layer 114, and the fifth dielectric layer 115 may be the same or different.

[0240] Based on this, when the material of the second dielectric layer 112 is a ferroelectric material and the thin film transistor 10 includes the third dielectric layer 116, as shown in FIG. 15, the thin film transistor 10 further includes a first conductive layer 117 disposed between the second dielectric layer 112 and the third dielectric layer 116.

[0241] For the material of the first conductive layer 117, refer to the materials of the gate 106, the first electrode 109, and the second electrode 108. Details will not be described again here.

[0242] The composite gate structure including the gate 106, the second dielectric layer 112, the first conductive layer 117, and the third dielectric layer 116 can enable the thin film transistor 10 to achieve the performance of a negative capacitance transistor, and the gate control ability of the thin film transistor 10 can be improved by using negative capacitance. When the thin film transistor 10 is used in the memory 200, the performance of the memory 200 can be improved.

[0243] In some embodiments, as shown in FIG. 16, the thin film transistor 10 further includes a modulation gate electrode 118 disposed between the first electrode 109 and the second electrode 108, and the modulation gate electrode 118 is surrounded by a first dielectric layer 113.

[0244] For the material of the modulation gate electrode 118, refer to the materials of the gate 106, the first electrode 109, and the second electrode 108. Details will not be described again here.

[0245] Note that the modulation gate electrode 118 is surrounded by the first dielectric layer 113 such that the modulation gate electrode 118 is spaced apart from the first electrode 109, the second electrode 108, and the semiconductor layer 102. That is, the modulation gate electrode 118 is electrically insulated from the first electrode 109, the second electrode 108, and the semiconductor layer 102 by using the first dielectric layer 113.

[0246] In this embodiment of the present application, since the thin film transistor 10 includes the modulation gate electrode 118, the threshold voltage of the thin film transistor 10 can be adjusted by using the modulation gate electrode 118.

[0247] When the thin film transistor 10 is used as the first thin film transistor Tr0 and the second thin film transistor Tr1 of the memory 200, as shown in FIGS. 17a, 17b, and 17c, in the memory 200, the first thin film transistor Tr0 further includes a first modulation gate electrode 118a disposed between the first electrode 109a and the second electrode 108a. The first modulation gate electrode 118a is disposed on the side of the semiconductor layer 102a away from the gate body 1062a. The first modulation gate electrode 118a is surrounded by the first dielectric layer 113a, whereby the first modulation gate electrode 118a is spaced apart from the first electrode 109a, the second electrode 108a, and the semiconductor layer 102a; the first modulation gate electrodes 118a of a plurality of first thin film transistors Tr0 located in the same layer are electrically connected together; and / or the second thin film transistor Tr1 further includes a second modulation gate electrode 118b disposed between the first electrode 109b and the second electrode 108b. The second modulation gate electrode 118b is disposed on the side of the semiconductor layer 102b away from the gate body 1062b. The second modulation gate electrode 118b is surrounded by the first dielectric layer 113b, whereby the second modulation gate electrode 118b is spaced apart from the first electrode 109b, the second electrode 108b, and the semiconductor layer 102b; the second modulation gate electrodes 118b of a plurality of second thin film transistors Tr1 located in the same layer are electrically connected together.

[0248] Note that FIGS. 17b and 17c are both schematic cross-sectional views along the CC direction of FIG. 17a.

[0249] The first modulation gate electrodes 118a of a plurality of first thin film transistors Tr located in the same layer may be electrically connected to each other. That is, all of the first modulation gate electrodes 118a of the plurality of first thin film transistors Tr0 located in the same layer may be electrically connected together, or alternatively, some of the first modulation gate electrodes 118a of the plurality of first thin film transistors Tr0 located in the same layer may be electrically connected together. Similarly, the second modulation gate electrodes 118b of a plurality of second thin film transistors Tr1 located in the same layer may be electrically connected together. That is, the second modulation gate electrodes 118b of the plurality of second thin film transistors Tr1 located in the same layer may be electrically connected together, or alternatively, some of the second modulation gate electrodes 118b of the plurality of second thin film transistors Tr1 located in the same layer may be electrically connected together.

[0250] For example, as shown in FIG. 17b, the first modulation gate electrodes 118a of four first thin film transistors Tr0 located in the same layer are electrically connected together. In this way, the common modulation of four memory cells 201A can be implemented.

[0251] It should be noted that in actual applications, the number of memory cells 201A to be modulated in common can be selected as needed.

[0252] For the materials of the first modulation gate electrode 118a and the second modulation gate electrode 118b, refer to the materials of the gate 106, the first electrode 109, and the second electrode 108. Details will not be described again here.

[0253] Since the first thin film transistor Tr0 includes the first modulation gate electrode 118a, the threshold voltage of the first thin film transistor Tr0 can be adjusted by using the first modulation gate electrode 118a. Since the second thin film transistor Tr1 includes the second modulation gate electrode 118b, the threshold voltage of the second thin film transistor Tr1 can be adjusted by using the second modulation gate electrode 118b. Based on this, the storage performance of the memory 200 can be adjusted more flexibly. For example, for the first thin film transistor Tr0, a relatively low potential may be set for the first modulation gate electrode 118a, whereby the leakage currents of the first electrode 109a and the second electrode 108a of the first thin film transistor Tr0 are reduced, thereby realizing a longer storage and retention time. Also, a relatively high potential may be set for the second modulation gate electrode 118b of the second thin film transistor Tr1, whereby the overall current of the second thin film transistor Tr1 is increased, thereby improving the data readout speed.

[0254] Certain embodiments of the present application further provide a method for manufacturing the thin film transistor 10, and this method can be used to manufacture the aforementioned thin film transistor 10. Referring to FIG. 18, the method for manufacturing the thin film transistor 10 includes the following.

[0255] S10. Form a first electrode 109, a first dielectric layer 113, a second electrode 108, and a semiconductor layer 102 on a substrate. The first electrode 109, the first dielectric layer 113, and the second electrode 108 are sequentially stacked, the first dielectric layer 113 separates the first electrode 109 from the second electrode 108, the semiconductor layer 102 is formed on the side surface of the first dielectric layer 113, and both the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102.

[0256] It should be noted that the order of forming the first electrode 109, the first dielectric layer 113, the second electrode 108, and the semiconductor layer 102 is not limited.

[0257] Both the first electrode 109 and the second electrode 108 may be in direct contact with the semiconductor layer 102, or the first electrode 109 and the second electrode 108 may be in contact with the semiconductor layer 102 through separate dielectric layers, respectively.

[0258] For the materials of the first electrode 109, the first dielectric layer 113, the second electrode 108, and the semiconductor layer 102, refer to the foregoing embodiments. Details are not described again here.

[0259] In addition, the first dielectric layer 113 has a surface close to the second electrode 108, a surface close to the first electrode 109, and side surfaces. The surface close to the second electrode 108 and the surface close to the first electrode 109 are arranged to face each other.

[0260] Based on this, the first electrode 109 may be formed as a drain and the second electrode 108 may be formed as a source; alternatively, the first electrode 109 may be formed as a source and the second electrode 108 may be formed as a drain.

[0261] S11. Sequentially form the second dielectric layer 112 and the gate 106. Here, the gate 106 includes a gate base 1061 located at the upper part and a gate body 1062 extending from the gate base 1061 to the bottom, and the second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0262] For the material of the second dielectric layer 112, refer to the foregoing embodiments. Details are not described again here.

[0263] In addition, for the material of the gate 106, refer to the foregoing embodiments. Details are not described again here.

[0264] Note that the gate base 1061 and the gate body 1062 may be formed simultaneously, or the gate base 1061 and the gate body 1062 may be formed separately.

[0265] Based on the foregoing description, in this embodiment of the present application, when the thin film transistor 10 is manufactured, steps S10 and S11 may be sequentially executed, or steps S11 and S10 may be sequentially executed.

[0266] An embodiment of the present invention provides a method for manufacturing a thin film transistor 10. The method for manufacturing the thin film transistor 10 provided in this embodiment of the present application has the same technical effects as the foregoing thin film transistor 10. For details, please refer to the foregoing description. Details will not be described again here.

[0267] The following uses examples to describe the specific implementation of the method for manufacturing the thin film transistor 10.

Example

[0268] Embodiment 1 For example, the manufacture of the thin film transistor 10 shown in FIG. 8a specifically includes the following steps.

[0269] S100. As shown in FIG. 19, the first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 laminated on the substrate 101 are sequentially formed.

[0270] The first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 can be sequentially formed by methods such as chemical vapor deposition, physical vapor deposition, sputtering, and electroplating.

[0271] S101. As shown in FIG. 19, the first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 are patterned to form the first electrode 109, the first dielectric layer 113, and the second electrode 108 that are sequentially laminated. Here, the first electrode 109, the first dielectric layer 113, and the second electrode 108 form a groove structure.

[0272] The first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 can be patterned using dry etching or wet etching.

[0273] Also, the first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 may be etched separately, or the first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 may be etched simultaneously.

[0274] S102. As shown in FIG. 19, a semiconductor layer 102 is formed. Here, the semiconductor layer 102 is formed on the sidewalls of the groove structure, that is, the semiconductor layer 102 is formed on the side surfaces of the first dielectric layer 113 and the second electrode 108, and both the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102.

[0275] First, the semiconductor thin film may be formed by using an epitaxial growth method. Here, the semiconductor thin film is the entire layer and covers the exposed surfaces of the first electrode 109, the first dielectric layer 113, and the second electrode 108; thereafter, the semiconductor thin film is etched. In addition to the semiconductor thin film formed on the sidewalls of the groove, the semiconductor thin film formed on other portions such as the bottom of the groove, the upper surface of the second electrode 108, and the outside of the groove is etched, thereby forming the semiconductor layer 102.

[0276] The epitaxial growth method includes, for example, chemical vapor deposition, physical vapor deposition, sputtering, electroplating, and other processes.

[0277] S103. As shown in FIG. 19, a second dielectric layer 112 is formed. Here, the second dielectric layer 112 covers the semiconductor layer 102, the second electrode 108, and the first electrode 109.

[0278] Note that step S103 can be implemented in two modes. In the first mode, the second dielectric layer 112 can be directly formed by using methods such as chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. In this case, the second dielectric layer 112 is the entire layer and covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. In the second mode, first, a seventh dielectric thin film may be formed by using chemical vapor deposition, physical vapor deposition, sputtering, or electroplating, where the seventh dielectric thin film covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113; then, the seventh dielectric thin film is etched. In addition to the portions formed on the side and bottom of the groove, the upper surface of the second electrode 108, and the upper surface of the semiconductor layer 102, all other seventh dielectric thin films are etched, thereby forming the second dielectric layer 112. The first mode is not shown in the accompanying drawings.

[0279] S104. As shown in FIG. 19, a gate 106 is formed. Here, the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061. The gate body 1062 extends into the groove structure, that is, the gate body 1062 extends along the side surfaces of the first dielectric layer 113 and the second electrode 108. The gate base 1061 is formed on the side of the gate body 1062 away from the first electrode 109. The second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0280] Specifically, the process of forming the gate 106 may be to first form a conductive thin film and then etch the conductive thin film to form the gate 106.

Embodiment

[0281] Embodiment 2 For example, the manufacturing method of the thin film transistor 10 shown in FIG. 9 specifically includes the following.

[0282] S110. As shown in FIG. 20, the first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 laminated on the substrate 101 are sequentially formed.

[0283] For the specific implementation process of step S110, please refer to step S100 described above. Details will not be described again here.

[0284] S111. As shown in FIG. 20, the first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 are patterned to form the first electrode 109, the first dielectric layer 113, and the second electrode 108 laminated sequentially, and the first electrode 109, the first dielectric layer 113, and the second electrode 108 form a groove structure.

[0285] For the specific implementation process of step S111, please refer to step S101 described above. Details will not be described again here.

[0286] S112. As shown in FIG. 20, a semiconductor layer 102 is formed. Here, the semiconductor layer 102 is formed on the sidewalls and bottom of the groove structure, that is, the semiconductor layer 102 is formed on the side surfaces of the first dielectric layer 113 and the second electrode 108, and the semiconductor layer 102 extends further from the side surfaces of the first dielectric layer 113 and the second electrode 108 to the surface of the first electrode 109 closer to the second electrode 108, that is, the upper surface of the first electrode 109, and both the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102.

[0287] First, the semiconductor thin film may be formed by using an epitaxial growth method. Here, the semiconductor thin film is the entire layer and covers the exposed surfaces of the first electrode 109, the first dielectric layer 113, and the second electrode 108; then, the semiconductor thin film is etched. In addition to the semiconductor thin film formed on the sidewalls and bottom of the groove, the semiconductor thin film formed on other parts such as the upper surface of the second electrode 108 and the outside of the groove is etched, thereby forming the semiconductor layer 102.

[0288] S113. As shown in FIG. 20, a second dielectric layer 112 is formed. Here, the second dielectric layer 112 covers the semiconductor layer 102 and the second electrode 108.

[0289] For the specific implementation process of step S113, please refer to step S103 described above. Details are not described again here.

[0290] S114. As shown in FIG. 20, a gate 106 is formed. Here, the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061. The gate body 1062 extends into the groove structure, that is, the gate body 1062 extends along the side surfaces of the first dielectric layer 113 and the second electrode 108. The gate base 1061 is formed on the side of the gate body 1062 away from the first electrode 109. The second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0291] For the specific implementation process of step S114, please refer to step S104 described above. Details are not described again here.

Embodiment

[0292] Embodiment 3 For example, the manufacturing of the thin film transistor 10 shown in FIG. 10 specifically includes the following.

[0293] S120. As shown in FIG. 21, a first conductive thin film 1090, a first dielectric thin film 1130, and a second conductive thin film 1080 laminated on the substrate 101 are sequentially formed.

[0294] For the specific implementation process of step S120, please refer to step S100 described above. Details are not described again here.

[0295] S121. As shown in FIG. 21, the first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 are patterned to form the sequentially stacked first electrode 109, the first dielectric layer 113, and the second electrode 108, and the first electrode 109, the first dielectric layer 113, and the second electrode 108 form a groove structure.

[0296] For the specific implementation process of step S121, please refer to the aforementioned step S101. Details will not be described again here.

[0297] S122. As shown in FIG. 21, a semiconductor layer 102 is formed. Here, the semiconductor layer 102 is formed on the sidewalls and bottom of the groove structure, and on the surface of the second electrode 108 on the side away from the first electrode 109, that is, the semiconductor layer 102 is formed on the side surfaces of the first dielectric layer 113 and the second electrode 108. The semiconductor layer 102 extends further from the side surfaces of the first dielectric layer 113 and the second electrode 108 to the surface of the second electrode 108 on the side away from the first electrode 109 (i.e., the upper surface of the second electrode 108) and the surface of the first electrode 109 on the side close to the second electrode 108 (i.e., the upper surface of the first electrode 109). Both the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102.

[0298] First, the semiconductor thin film may be formed by using the epitaxial growth method. Here, the semiconductor thin film is the entire layer and covers the exposed surfaces of the first electrode 109, the first dielectric layer 113, and the second electrode 108; then, the semiconductor thin film is etched. In addition to the semiconductor thin film formed on the sidewalls and bottom of the groove and on the upper surface of the second electrode 108, the semiconductor thin film formed outside the groove is etched, thereby forming the semiconductor layer 102.

[0299] S123. As shown in FIG. 21, a second dielectric layer 112 is formed, and the second dielectric layer 112 covers the semiconductor layer 102.

[0300] For the specific implementation process of step S123, please refer to step S103 described above. Details will not be described again here.

[0301] S124. As shown in FIG. 21, a gate 106 is formed. Here, the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061. The gate body 1062 extends into the groove structure, that is, the gate body 1062 extends along the side surfaces of the first dielectric layer 113 and the second electrode 108. The gate base 1061 is formed on the side of the gate body 1062 away from the first electrode 109. The second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0302] For the specific implementation process of step S124, please refer to step S104 described above. Details will not be described again here.

[0303] Note that the differences among Embodiment 1, Embodiment 2, and Embodiment 3 lie in the structure of the formed semiconductor layer 102.

Example

[0304] Embodiment 4 For example, the manufacturing method of the thin film transistor 10 shown in FIG. 13 specifically includes the following.

[0305] S130. As shown in FIG. 22, a first conductive thin film 1090, a first dielectric thin film 1130, and a second conductive thin film 1080 laminated on the substrate 101 are sequentially formed.

[0306] For the specific implementation process of step S130, please refer to step S100 described above. Details will not be described again here.

[0307] S131. As shown in FIG. 22, the first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 are patterned to form a first electrode 109, a first dielectric layer 113, and a second electrode 108 that are sequentially stacked. Here, the first electrode 109, the first dielectric layer 113, and the second electrode 108 form a groove structure.

[0308] For the specific implementation process of step S131, please refer to step S101 described above. Details will not be described again here.

[0309] S132. As shown in FIG. 22, a fifth dielectric layer 115 is formed at the bottom of the groove structure. That is, the fifth dielectric layer 115 is formed on the upper surface of the first electrode 109. Here, the fifth dielectric layer 115 is in contact with the first electrode 109.

[0310] The process of forming the fifth dielectric layer 115 may specifically be: first, forming a fifth dielectric thin film, and then etching the fifth dielectric thin film to form the fifth dielectric layer 115.

[0311] S133. As shown in FIG. 22, a fourth dielectric layer 114 is formed on the side of the second electrode 108 away from the first electrode 109. That is, the fourth dielectric layer 114 is formed on the upper surface of the second electrode 108. Here, the fourth dielectric layer 114 is in contact with the second electrode 108.

[0312] The process of forming the fourth dielectric layer 114 may specifically be: first, forming a sixth dielectric thin film, and then etching the sixth dielectric thin film to form the fourth dielectric layer 114.

[0313] Note that steps S132 and S133 may be executed for each step. In this case, step S132 may be executed first and then step S133, or step S133 may be executed first and then step S132. Steps S132 and S133 may alternatively be executed synchronously. That is, the fourth dielectric layer 114 and the fifth dielectric layer 115 are formed simultaneously.

[0314] S134. As shown in FIG. 22, a semiconductor layer 102 is formed. Here, the semiconductor layer 102 is formed on the sidewalls and bottom of the groove structure and on the surface of the fourth dielectric layer 114 on the side away from the second electrode 108. That is, the semiconductor layer 102 is formed on the side surfaces of the first dielectric layer 113, the second electrode 108, and the fourth dielectric layer 114. The semiconductor layer 102 extends further from the side surfaces of the first dielectric layer 113, the second electrode 108, and the fourth dielectric layer 114 to the surface of the fourth dielectric layer 114 on the side away from the second electrode 108 (i.e., the upper surface of the fourth dielectric layer 114) and the surface of the fifth dielectric layer 115 on the side away from the first electrode 109 (i.e., the upper surface of the fifth dielectric layer 115). The semiconductor layer 102 contacts both the fourth dielectric layer 114 and the fifth dielectric layer 115, and both the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102.

[0315] First, a semiconductor thin film may be formed by using an epitaxial growth method. The semiconductor thin film is the entire layer and covers the exposed surfaces of the fourth dielectric layer 114, the fifth dielectric layer 115, the first electrode 109, the first dielectric layer 113, and the second electrode 108. Then, the semiconductor thin film is etched. In addition to the semiconductor thin film formed on the sidewalls and bottom of the groove and on the upper surface of the fourth dielectric layer 114, the semiconductor thin film formed outside the groove is etched to form the semiconductor layer 102.

[0316] S135. As shown in FIG. 22, a second dielectric layer 112 is formed. Here, the second dielectric layer 112 covers the semiconductor layer 102.

[0317] For the specific implementation process of step S135, please refer to step S103 described above. Details will not be described again here.

[0318] S136. As shown in FIG. 22, form gate 106. Here, gate 106 includes gate base 1061 and gate body 1062 extending from gate base 1061. Gate body 1062 extends within the groove structure, that is, gate body 1062 extends along the side surfaces of the first dielectric layer 113, the second electrode 108, and the fourth dielectric layer 114. Gate base 1061 is formed on the side of gate body 1062 away from the first electrode 109. The second dielectric layer 112 separates gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0319] For the specific implementation process of step S136, please refer to step S104 described above. Details will not be described again here.

[0320] Note that compared with Embodiment 3, in Embodiment 4, steps S132 and S133 are added.

[0321] In Embodiment 4, both step S132 and step S133 are executed. In some embodiments, one of step S132 and step S133 may be alternatively executed.

[0322] Also, in Embodiment 4, the structure of the semiconductor layer 102 formed in step S134 is the same as the structure of the semiconductor layer 102 formed in Embodiment 3. In some embodiments, the structure of the semiconductor layer 102 formed in step S134 may also be the same as the configuration of the semiconductor layer 102 formed in Embodiment 1 or Embodiment 2.

Example

[0323] Embodiment 5 For example, the manufacturing method of the thin film transistor 10 shown in FIG. 14 specifically includes the following.

[0324] S140. As shown in FIG. 23, the first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 laminated on the substrate 101 are sequentially formed.

[0325] For the specific implementation process of step S140, please refer to step S100 described above. Details will not be described again here.

[0326] S141. As shown in FIG. 23, the first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 are patterned to form the first electrode 109, the first dielectric layer 113, and the second electrode 108 laminated sequentially, and the first electrode 109, the first dielectric layer 113, and the second electrode 108 form a groove structure.

[0327] For the specific implementation process of step S141, please refer to step S101 described above. Details will not be described again here.

[0328] S142. As shown in FIG. 23, the semiconductor layer 102 is formed, and the semiconductor layer 102 is formed on the sidewalls and bottom of the groove structure, that is, the semiconductor layer 102 is formed on the side surfaces of the first dielectric layer 113 and the second electrode 108, and the semiconductor layer 102 extends further from the side surfaces of the first dielectric layer 113 and the second electrode 108 to the surface of the first electrode 109 close to the second electrode 108, that is, the upper surface of the first electrode 109, and both the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102.

[0329] For the specific implementation process of step S142, please refer to step S112 described above. Details will not be described again here.

[0330] S143. As shown in FIG. 23, a third dielectric layer 116 is formed. Here, the third dielectric layer 116 is formed on the sidewalls and bottom of the groove structure.

[0331] Note that step S143 can be implemented in two modes. In the first mode, the third dielectric layer 116 can be directly formed by using methods such as chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. In this case, the third dielectric layer 116 is the entire layer and covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. In the second mode, first, an eighth dielectric thin film may be formed by using chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. The eighth dielectric thin film covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. Then, the eighth dielectric thin film is etched. In addition to the portions formed on the side and bottom of the groove, all other eighth dielectric thin films are etched to form the third dielectric layer 116.

[0332] S144. As shown in FIG. 23, a second dielectric layer 112 is formed. Here, the second dielectric layer 112 covers the third dielectric layer 116, the semiconductor layer 102, and the second electrode 108, and the material of the second dielectric layer 112 is a ferroelectric material.

[0333] For the specific implementation process of step S144, please refer to step S103 described above. Details will not be described again here.

[0334] S145. As shown in FIG. 23, form a gate 106. Here, the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061. The gate body 1062 extends into the groove structure, that is, the gate body 1062 extends along the side surfaces of the first dielectric layer 113 and the second electrode 108. The gate base 1061 is formed on the side of the gate body 1062 away from the first electrode 109. The second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0335] For the specific implementation process of step S145, please refer to step S104 described above. Details will not be described again here.

[0336] Note that in Embodiment 5, compared with Embodiment 2, step S143 is added.

[0337] Also, in Embodiment 5, the structure of the semiconductor layer 102 formed in step S142 is the same as the structure of the semiconductor layer 102 formed in Embodiment 2. In some embodiments, the structure of the semiconductor layer 102 formed in step S142 is also the same as the configuration of the semiconductor layer 102 formed in Embodiment 1 or Embodiment 3.

Example

[0338] Embodiment 6 For example, the manufacturing method of the thin film transistor 10 shown in FIG. 15 specifically includes the following.

[0339] S150. As shown in FIG. 24, sequentially form a first conductive thin film 1090, a first dielectric thin film 1130, and a second conductive thin film 1080 laminated on the substrate 101.

[0340] For the specific implementation process of step S150, please refer to step S100 described above. Details will not be described again here.

[0341] As shown in FIG. 24, the first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 are patterned to form the first electrode 109, the first dielectric layer 113, and the second electrode 108 that are sequentially stacked. Here, the first electrode 109, the first dielectric layer 113, and the second electrode 108 form a groove structure.

[0342] For the specific implementation process of step S151, please refer to step S101 described above. Details are not described again here.

[0343] S152. As shown in FIG. 24, a semiconductor layer 102 is formed. Here, the semiconductor layer 102 is formed on the sidewalls and bottom of the groove structure, that is, the semiconductor layer 102 is formed on the side surfaces of the first dielectric layer 113 and the second electrode 108, and the semiconductor layer 102 extends further from the side surfaces of the first dielectric layer 113 and the second electrode 108 to the surface of the first electrode 109 closer to the second electrode 108, that is, the upper surface of the first electrode 1109, and both the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102.

[0344] For the specific implementation process of step S152, please refer to step S112 described above. Details are not described again here.

[0345] S153. As shown in FIG. 24, a third dielectric layer 116 is formed, and the third dielectric layer 116 is formed on the sidewalls and bottom of the groove structure.

[0346] For the specific implementation process of step S153, please refer to step S143 described above. Details are not described again here.

[0347] S154. As shown in FIG. 24, a first conductive layer 117 is formed, and the first conductive layer 117 is formed on the sidewalls and bottom of the groove structure.

[0348] First, a fourth conductive thin film may be formed. Here, the fourth conductive thin film covers the exposed surfaces of the third dielectric layer 116, the semiconductor layer 102, the second electrode 108, the first dielectric layer 113, and the first electrode 109; then, the fourth conductive thin film is etched. In addition to the portions formed on the side and bottom of the groove, other fourth conductive thin films are etched to form the first conductive layer 117.

[0349] S155. As shown in FIG. 24, a second dielectric layer 112 is formed. Here, the second dielectric layer 112 covers the first conductive layer 117, the second dielectric layer 116, the semiconductor layer 102, and the second electrode 108, and the material of the second dielectric layer 112 is a ferroelectric material.

[0350] For the specific implementation process of step S155, please refer to step S103 described above. Details will not be described again here.

[0351] S156. As shown in FIG. 24, a gate 106 is formed. Here, the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061. The gate body 1062 extends into the groove structure, that is, the gate body 1062 extends along the side surfaces of the first dielectric layer 113 and the second electrode 108. The gate base 1061 is formed on the side of the gate body 1062 away from the first electrode 109, and the second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0352] For the specific implementation process of step S156, please refer to step S104 described above. Details will not be described again here.

[0353] Note that in Embodiment 6, compared with Embodiment 5, step S154 is added.

Example

[0354] Embodiment 7 For example, the manufacture of the thin film transistor 10 shown in FIG. 12b specifically includes the following.

[0355] S160. As shown in FIG. 25, the first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 laminated on the substrate 101 are sequentially formed.

[0356] For the specific implementation process of step S160, refer to step S100 described above. Details are not described again here.

[0357] S161. As shown in FIG. 25, the first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 are patterned to form the first electrode 109, the first dielectric layer 113, and the second electrode 108 laminated sequentially. Here, the boundary of the projection of the first dielectric layer 113 and the second electrode 108 on the first electrode 109 is located within the boundary of the first electrode 109, that is, the first dielectric layer 113 and the second electrode 108 are located in the central region of the first electrode 109.

[0358] For the specific implementation process of step S161, refer to step S101 described above. Details are not described again here.

[0359] S162. As shown in FIG. 25, the semiconductor layer 102 is formed. Here, the semiconductor layer 102 covers the exposed surfaces of the second electrode 108 and the first dielectric layer 113 and the upper surface of the first electrode 109, that is, the semiconductor layer 102 covers the upper surface and side surfaces of the second electrode 108, the side surface of the first dielectric layer 113, and the upper surface of the first electrode 109.

[0360] First, the semiconductor thin film may be formed by using an epitaxial growth method. Here, the semiconductor thin film is the entire layer, covering the exposed surfaces of the first electrode 109, the first dielectric layer 113, and the second electrode 108, and then the semiconductor thin film is etched. In addition to the upper and side surfaces of the second electrode 108, the side surface of the first dielectric layer 113, and the semiconductor thin film formed on the upper surface of the first electrode 109, the semiconductor thin film formed on other portions is etched, thereby forming the semiconductor layer 102.

[0361] S163. As shown in FIG. 25, form the second dielectric layer 112. Here, the second dielectric layer 112 covers the semiconductor layer 102.

[0362] For the specific implementation process of step S163, please refer to step S103 described above. Details will not be described again here.

[0363] S164. As shown in FIG. 25, form the gate 106. Here, the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061. The gate body 1062 is disposed around the entire side surfaces of the first dielectric layer 113 and the second electrode 108. That is, the gate body 1062 has a hollow structure. The gate base 1061 is formed on the side of the gate body 1062 away from the first electrode 109. The second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0364] For the specific implementation process of step S164, please refer to step S104 described above. Details will not be described again here.

Embodiment

[0365] Embodiment 8 For example, the manufacture of the thin film transistor shown in FIG. 12a specifically includes the following steps.

[0366] S170. As shown in FIG. 26, a first conductive thin film 1090, a first dielectric thin film 1130, and a second conductive thin film 1080 laminated on the substrate 101 are sequentially formed.

[0367] For the specific implementation process of step S170, please refer to step S100 described above. Details will not be described again here.

[0368] S171. As shown in FIG. 26, the first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 are patterned to form a first electrode 109, a first dielectric layer 113, and a second electrode 108 laminated sequentially. Here, the boundary of the projection of the first dielectric layer 113 and the second electrode 108 on the first electrode 109 partially overlaps the boundary of the first electrode 109, that is, the first dielectric layer 113 and the second electrode 108 are located in the edge region of the first electrode 109.

[0369] For the specific implementation process of step S171, please refer to step S101 described above. Details will not be described again here.

[0370] S172. As shown in FIG. 26, a semiconductor layer 102 is formed. Here, the semiconductor layer 102 is formed on the side surfaces of the second electrode 108 and the first dielectric layer 113, and the semiconductor layer 102 further extends from the side surfaces of the second electrode 108 and the first dielectric layer 113 to the upper surfaces of the second electrode 108 and the first electrode 109.

[0371] First, the semiconductor thin film may be formed by using an epitaxial growth method. The semiconductor thin film is the entire layer and covers the exposed surfaces of the first electrode 109, the first dielectric layer 113, and the second electrode 108. Then, the semiconductor thin film is etched. In addition to the semiconductor thin film formed on the side surfaces of the second electrode 108 and the first dielectric layer 113, the upper surface of the second electrode 108, and the upper surface of the first electrode 109, the semiconductor thin film formed on other parts is etched, thereby forming the semiconductor layer 102.

[0372] S173. As shown in FIG. 26, a second dielectric layer 112 is formed. Here, the second dielectric layer 112 covers the semiconductor layer 102.

[0373] Note that step S173 can be implemented in two modes. In the first mode, the second dielectric layer 112 can be directly formed by using methods such as chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. In this case, the second dielectric layer 112 is the entire layer and covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. In the second mode, first, a seventh dielectric thin film is formed by using chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. The seventh dielectric thin film covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. Then, the seventh dielectric thin film is etched. In addition to the seventh dielectric thin film formed on the surface of the semiconductor layer 102 on the side away from the first electrode 109, the seventh dielectric thin film formed at another location is etched to form the second dielectric layer 112. The first mode is not shown in the accompanying drawings.

[0374] S174. As shown in FIG. 26, a gate 106 is formed. Here, the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061. The gate body 1062 extends along the side surfaces of the first dielectric layer 113 and the second electrode 108. The gate base 1061 is formed on the side of the gate body 1062 away from the first electrode 109. The second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0375] For the specific implementation process of step S174, please refer to step S104 described above. Details will not be described again here.

Embodiment

[0376] Embodiment 9 For example, the manufacture of the thin film transistor shown in FIG. 12c specifically includes the following.

[0377] S180. As shown in FIG. 27, a first conductive thin film 1090, a first dielectric thin film 1130, and a second conductive thin film 1080 laminated on a substrate 101 are sequentially formed.

[0378] For the specific implementation process of step S180, please refer to step S100 described above. Details are not described again here.

[0379] S181. As shown in FIG. 27, the first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 are patterned to form a first electrode 109, a first dielectric layer 113, and a second electrode 108 laminated sequentially, and the boundary of the projection of the first dielectric layer 113 and the second electrode 108 on the first electrode 109 overlaps the boundary of the first electrode 109.

[0380] For the specific implementation process of step S181, please refer to step S101 described above. Details are not described again here.

[0381] S182. As shown in FIG. 27, a semiconductor layer 102 is formed. The semiconductor layer 102 is formed on the side surfaces of the first electrode 109, the first dielectric layer 113, and the second electrode 108, and the semiconductor layer 102 further extends from the side surfaces of the first electrode 109, the first dielectric layer 113, and the second electrode 108 to the surface on the side of the second electrode 108 away from the first electrode 109, that is, to the upper surface of the second electrode 108. First, a semiconductor thin film may be formed by using an epitaxial growth method. The semiconductor thin film is the entire layer and covers the exposed surfaces of the first electrode 109, the first dielectric layer 113, and the second electrode 108; thereafter, the semiconductor thin film is etched. In addition to the semiconductor thin film formed on the left side surface of the first electrode 109, the left side surface of the first dielectric layer 113, the left side surface of the second electrode 108, and the upper surface of the second electrode 108, the semiconductor thin film formed in other portions is etched, thereby forming the semiconductor layer 102.

[0382] S183. As shown in FIG. 27, a second dielectric layer 112 is formed. Here, the second dielectric layer 112 covers the semiconductor layer 102.

[0383] Note that step S183 can be implemented in two modes. In the first mode, the second dielectric layer 112 can be directly formed by using methods such as chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. In this case, the second dielectric layer 112 is the entire layer and covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. In the second mode, first, a seventh dielectric thin film may be formed by using chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. The seventh dielectric thin film covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. Thereafter, the seventh dielectric thin film is etched. In addition to the seventh dielectric thin film formed on the side surface and the upper surface of the semiconductor layer 102, the seventh dielectric thin film formed in other places is etched, thereby forming the second dielectric layer 112. The first mode is not shown in the accompanying drawings.

[0384] S184. As shown in FIG. 27, form a gate 106. Here, the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061. The gate body 1062 extends along the side surfaces of the first dielectric layer 113 and the second electrode 108, and the gate base 1061 is formed on the side of the gate body 1062 away from the first electrode 109. The second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0385] For the specific implementation process of step S184, please refer to the aforementioned step S104. Details will not be described again here.

[0386] Note that the differences between Embodiment 7, Embodiment 8, and Embodiment 9 and the other aforementioned embodiments lie in the different structures of the formed first electrode 109, the first dielectric layer 113, and the second electrode 108 that are stacked.

Example

[0387] Embodiment 10 For example, the manufacturing method of the thin film transistor 10 shown in FIG. 16 specifically includes the following.

[0388] S190. As shown in FIG. 28, form a first conductive thin film 1090 and a third dielectric thin film 1131 sequentially stacked on a substrate 101.

[0389] For the specific implementation process of step S190, please refer to the aforementioned step S100. Details will not be described again here.

[0390] S191. As shown in FIG. 28, form a modulation gate electrode 118 on the third dielectric thin film 1131.

[0391] A specific process for forming the modulation gate electrode 118 may be to first form a fifth conductive thin film and then pattern the fifth conductive thin film to form the modulation gate electrode 118.

[0392] S192. As shown in FIG. 28, a fourth dielectric thin film 1132 is formed on the modulation gate electrode 118. Here, the fourth dielectric thin film 1132 covers the modulation gate electrode 118.

[0393] The fourth dielectric thin film 1132 can be formed by using methods such as chemical vapor deposition, physical vapor deposition, sputtering, electroplating, etc.

[0394] S193. As shown in FIG. 28, the fourth dielectric thin film 1132 is subjected to grinding.

[0395] The grinding may be performed on the fourth dielectric thin film 1132 by using chemical mechanical polishing technology.

[0396] Note that step S193 is an optional step. For example, in some embodiments, step S193 may be omitted.

[0397] S194. As shown in FIG. 28, a second conductive thin film 1080 is formed on the fourth dielectric thin film 1132.

[0398] The second conductive thin film 1080 can be formed by using methods such as chemical vapor deposition, physical vapor deposition, sputtering, electroplating, etc.

[0399] As shown in FIG. 28, the second conductive thin film 1080 is patterned to form the second electrode 108, the fourth dielectric thin film 1132 and the third dielectric thin film 1131 are patterned to form the first dielectric layer 113, and the first conductive thin film 1090 is patterned to form the first electrode 109. Here, the second electrode 108, the first dielectric layer 113, and the first electrode 109 form a groove structure, and the first dielectric layer 113 surrounds the modulation gate electrode 118, whereby the modulation gate electrode 118 is separated from the second electrode 108 and the first electrode 109.

[0400] For the specific implementation process of step S195, please refer to step S101 described above. Details will not be described again here.

[0401] S196. As shown in FIG. 28, a semiconductor layer 102 is formed. Here, the semiconductor layer 102 is formed on the sidewalls and bottom of the groove structure, and on the surface of the second electrode 108 on the side away from the first electrode 109, that is, the semiconductor layer 102 is formed on the side surfaces of the first dielectric layer 113 and the second electrode 108. The semiconductor layer 102 extends further from the side surfaces of the first dielectric layer 113 and the second electrode 108 to the surface of the second electrode 108 on the side away from the first electrode 109 (i.e., the upper surface of the second electrode 108) and the surface of the first electrode 109 on the side close to the second electrode 108 (i.e., the upper surface of the first electrode 109). Both the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102.

[0402] For the specific implementation process of step S196, please refer to step S122 described above. Details will not be described again here.

[0403] S197. As shown in FIG. 28, a second dielectric layer 112 is formed. Here, the second dielectric layer 112 covers the semiconductor layer 102.

[0404] For the specific implementation process of step S197, please refer to step S103 described above. Details will not be elaborated here again.

[0405] S198. As shown in FIG. 28, gate 106 is formed. Here, gate 106 includes a gate base 1061 and a gate body 1062 extending from gate base 1061. Gate body 1062 extends within the groove structure, that is, gate body 1062 extends along the side surfaces of the first dielectric layer 113 and the second electrode 108. Gate base 1061 is formed on the side of gate body 1062 away from the first electrode 109. The second dielectric layer 112 separates gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0406] For the specific implementation process of step S198, please refer to step S104 described above. Details will not be elaborated here again.

[0407] Note that the difference between Embodiment 10 and the other embodiments described above mainly lies in that step S191 is added in Embodiment 10.

Example

[0408] Embodiment 11 For example, the manufacturing of the thin film transistor 10 shown in FIG. 11 specifically includes the following.

[0409] S200. As shown in FIG. 29, a first conductive thin film 1090 and a first dielectric thin film 1130 sequentially stacked on the substrate 101 are formed.

[0410] For the specific implementation process of step S200, please refer to step S100 described above. Details will not be elaborated here again.

[0411] S201. As shown in FIG. 29, the first conductive thin film 1090 and the first dielectric thin film 1130 are patterned to form the first electrode 109 and the first dielectric layer 113 that are sequentially stacked. Here, the first dielectric layer 113 and the first electrode 109 form a groove structure.

[0412] For the specific implementation process of step S201, please refer to the aforementioned step S101. Details will not be described again here.

[0413] S202. As shown in FIG. 29, a semiconductor layer 102 is formed. Here, the semiconductor layer 102 is formed on the sidewalls and bottom of the groove structure, as well as on the surface of the first dielectric layer 113 on the side away from the first electrode 109. That is, the semiconductor layer 102 is formed on the side surface of the first dielectric layer 113, and the semiconductor layer 102 extends further from the side surface of the first dielectric layer 113 to the surface of the first dielectric layer 113 close to the first electrode 109 (i.e., the upper surface of the first electrode 109) and the surface of the first dielectric layer 113 on the side away from the first electrode 109 (i.e., the upper surface of the first dielectric layer 113), and the first electrode 109 is electrically connected to the semiconductor layer 102.

[0414] First, the semiconductor thin film may be formed by using an epitaxial growth method. Here, the semiconductor thin film is the entire layer, covering the exposed surfaces of the first electrode 109 and the first dielectric layer 113, and then the semiconductor thin film is etched. In addition to the semiconductor thin film formed on the sidewalls and bottom of the groove and the upper surface of the first dielectric layer 113, the semiconductor thin film formed outside the groove is etched to form the semiconductor layer 102.

[0415] S203. As shown in FIG. 29, a second electrode 108 is formed. Here, the second electrode 108 is located on the side of the first dielectric layer 113 away from the first electrode 109. That is, the second electrode 108 is located on the upper surface of the first dielectric layer 113.

[0416] The process of forming the second electrode 108 may specifically be, first, forming a second conductive thin film and then etching the second conductive thin film to form the second electrode 108.

[0417] S204. As shown in FIG. 29, a second dielectric layer 112 is formed. Here, the second dielectric layer 112 covers the semiconductor layer 102 and the second electrode 108.

[0418] Note that step S204 can be implemented in two modes. In the first mode, the second dielectric layer 112 can be directly formed by using methods such as chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. In this case, the second dielectric layer 112 is the entire layer and covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. In the second mode, first, a seventh dielectric thin film may be formed by using chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. The seventh dielectric thin film covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. Then, the seventh dielectric thin film is etched. In addition to the side and bottom of the trench and the portions formed on the upper and side surfaces of the second electrode 108, all other seventh dielectric thin films are etched, thereby forming the second dielectric layer 112. The first mode is not shown in the accompanying drawings.

[0419] S205. As shown in FIG. 29, a gate 106 is formed. The gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061. The gate body 1062 extends into the trench structure, that is, the gate body 1062 extends along the side surfaces of the first dielectric layer 113 and the second electrode 108. The gate base 1061 is formed on the side of the gate body 1062 away from the first electrode 109. The second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0420] For the specific implementation process of step S205, please refer to the aforementioned step S104. Details will not be described again here.

[0421] It should be noted that the difference between Embodiment 11 and the other aforementioned embodiments mainly lies in that the sequence of forming the semiconductor layer 102 and the second electrode 108 in Embodiment 11 is different from that of the other aforementioned embodiments.

[0422] It should be understood that the thin film transistor 10 provided in the embodiments of the present application may be manufactured by using the aforementioned manufacturing method of the thin film transistor 10, or may be manufactured by using another manufacturing method. This is not limited here.

[0423] Certain embodiments of the present application further provide a memory manufacturing method including forming at least one layer of the memory array 201 on the substrate 101.

[0424] For example, as shown in FIG. 30, manufacturing any layer of the memory array 201 shown in FIG. 4 specifically includes the following steps.

[0425] S300. Form a plurality of first signal lines arranged in parallel on the substrate 101.

[0426] S301. On the plurality of first signal lines, form a plurality of first thin film transistors Tr0 distributed in an array and a plurality of second signal lines arranged in parallel. The first electrode 109a of the first thin film transistor Tr0 is electrically connected to the first signal line, the second electrode 108a of the first thin film transistor Tr0 is electrically connected to the second signal line, the first signal line is one of the read bit line RBL or the read word line RWL, and the second signal line is the other of the read bit line RBL and the read word line RWL. The first thin film transistor Tr0 may be manufactured by using the manufacturing method of the thin film transistor 10 provided in any of the foregoing embodiments. Here, it can be understood that the plurality of first thin film transistors Tr0 distributed in an array may be formed synchronously.

[0427] Note that the first signal line may be the read bit line RBL, and the second signal line may be the read word line RWL. In this case, the first electrode 109a of the first thin film transistor Tr0 is electrically connected to the read bit line RBL, and the second electrode 108a is electrically connected to the read word line RWL. Alternatively, the first signal line may be the read word line RWL, and the second signal line may be the read bit line RBL. In this case, the first electrode 109a of the first thin film transistor Tr0 is electrically connected to the read word line RWL, and the second electrode 108a is electrically connected to the read bit line RBL.

[0428] In some embodiments, it can be understood that the first electrode 109a may be formed synchronously with the first signal line, and the second electrode 108a may be formed synchronously with the second signal line.

[0429] S302. Form a plurality of connection electrodes 111 distributed in an array. Here, the gate 106a of one first thin film transistor Tr0 is electrically connected to one connection electrode 111.

[0430] Note that step S302 is an optional step. For example, in some embodiments, step S302 may be omitted.

[0431] First, a sixth conductive thin film may be formed, and then the sixth conductive thin film may be etched to form a plurality of connection electrodes 111.

[0432] S303. On the first thin film transistor Tr0, a plurality of second thin film transistors Tr1 distributed in an array and a plurality of write bit lines WBL arranged in parallel are formed. Here, the second electrode 108b of the second thin film transistor Tr1 is electrically connected to the write bit line WBL. One second thin film transistor Tr1 corresponds to one first thin film transistor Tr0, and the first electrode 109b of the second thin film transistor Tr1 is electrically connected to the gate 106a of the corresponding first thin film transistor Tr0. The second thin film transistor Tr1 can be manufactured by using the manufacturing method of the thin film transistor 10 provided in any of the foregoing embodiments. Here, it is understood that the plurality of second thin film transistors Tr1 distributed in an array may be formed synchronously.

[0433] Note that when the manufacturing method of any layer of the memory array 201 includes step S302, the first electrode 109b of the second thin film transistor Tr1 is electrically connected to the gate 106a of the corresponding first thin film transistor Tr0 by using the connection electrode 111.

[0434] In some embodiments, the second electrode 108b of the second thin film transistor Tr1 may be formed synchronously with the write bit line WBL.

[0435] S304. A plurality of write word lines WWL arranged in parallel are formed on the second thin film transistor Tr1. Here, the gate 106b of the second thin film transistor Tr1 is electrically connected to the write word line WWL.

[0436] In some embodiments, the write word line WWL may be formed in synchronization with the gate 106b of the second thin film transistor Tr1.

[0437] Based on the foregoing description, when the memory 200 includes the multi-layer memory array 201 disposed on the substrate 101, steps S300 to S304 may be repeated to form the multi-layer memory array 201 when the memory 200 is manufactured.

[0438] Furthermore, after the first layer of the memory array 201 is manufactured and before the second layer of the memory array 201 is formed, the sixth dielectric layer 202 may first be formed. In this case, the sixth dielectric layer 202 is used as the substrate of the second layer of the memory array 201. Similarly, the sixth dielectric layer 202 may also be first formed before the third layer of the memory array 201, the fourth layer of the memory array 201, etc. are manufactured. The foregoing description is merely a specific implementation of the present application and is not intended to limit the protection scope of the present application. Any deformation or substitution that can be easily conceived by those skilled in the art within the technical scope disclosed in the present application shall fall within the protection scope of the present application. Therefore, the protection scope of the present application shall comply with the protection scope of the claims.

Claims

1. 1. A thin film transistor comprising: a gate including a gate base located at an upper portion and a gate body extending from the gate base to a bottom portion; a first electrode located at the bottom; a second electrode located between the first electrode and the gate base; a first dielectric layer disposed between the second electrode and the first electrode, the first dielectric layer configured to separate the second electrode from the first electrode; a semiconductor layer disposed along a side of the gate body; a second dielectric layer separating the semiconductor layer from the gate and separating the second electrode from the gate base; the second electrode is located between the first dielectric layer and the second dielectric layer; the first electrode and the second electrode are each electrically connected to the semiconductor layer; Thin film transistor.

2. The thin film transistor of claim 1 , wherein the semiconductor layer further comprises an extension portion located between the gate body and the first electrode.

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