Overcurrent suppression circuit, DC / DC converter, power supply device and overcurrent suppression method

Abstract

To provide an overcurrent suppression circuit, a DC / DC converter, a power supply device, and an overcurrent suppression method, for suppressing an overcurrent resulting from sudden change of a load or the like.SOLUTION: In a DC / DC converter of a power supply device, an overcurrent suppression circuit 5 includes an output part 6 to which a DC current is inputted and from which a DC current is output, and a control part 7. The output part includes a plurality of semiconductor switches Q1 to Qn connected in parallel, and output capacitors C1 to Cn respectively connected to each semiconductor switch in series. The control part performs control to switch the plurality of semiconductor switches to a non-conduction state, then sequentially switch them to a conduction state when sudden change occurs in a load current from the output part.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to an overcurrent suppression circuit, a DC / DC converter, a power supply device, and an overcurrent suppression method.

Background Art

[0002] In a DC / DC converter, for example, a step-down DC / DC converter, generally, feedback control is performed. In this feedback control, the output voltage of the DC / DC converter is controlled such that the voltage on the load side of the DC / DC converter is monitored and becomes a constant voltage value. In such a DC / DC converter, when a rapid load fluctuation occurs, the feedback operation cannot follow the load fluctuation and the output voltage fluctuates greatly. Therefore, an output capacitor for preventing this is mounted. During the period when the DC / DC converter cannot follow, the charge stored in the output capacitor is supplied to the load side, thereby suppressing the fluctuation of the output voltage. When the operation of the DC / DC converter catches up, the DC / DC converter charges the output capacitor and supplies current to the load, and returns to the set voltage value (for this circuit configuration, see, for example, Patent Document 1). Note that "DC" is an abbreviation for "Direct Current".

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The above prior art documents are incorporated herein by reference.

[0005] The following analysis was made by the inventor of the present invention.

[0006] For example, in order to cope with larger load fluctuations or output voltage fluctuations, a DC / DC converter may include a plurality of output capacitors connected in parallel. However, in this case, since all the capacitors are charged simultaneously during the charging process, a large inrush current flows. As a result, overcurrent protection may operate, and the operation of the DC / DC converter may stop.

[0007] An object of the present disclosure is to provide an overcurrent suppression circuit, a DC / DC converter, a power supply device, and an overcurrent suppression method that contribute to suppressing overcurrent generated during sudden load changes or the like.

Means for Solving the Problems

[0008] (1) According to a first aspect of the present disclosure, there is provided an overcurrent suppression circuit including an output section that inputs a direct current and outputs a direct current, and a control section. The output section includes a plurality of semiconductor switches connected in parallel, and an output capacitor connected in series to each semiconductor switch. The control section is configured to perform control to sequentially switch the plurality of semiconductor switches to a conducting state after switching the plurality of semiconductor switches to a non-conducting state when a sudden change in the load current from the output section occurs. (2) According to a second aspect of the present disclosure, there is provided a DC / DC converter including the overcurrent suppression circuit of the present disclosure and a DC / DC converter circuit provided in front of the overcurrent suppression circuit. (3) According to a third aspect of the present disclosure, there is provided a power supply device including the DC / DC converter of the present disclosure and a direct current power supply section provided in front of the DC / DC converter. (4) According to a fourth aspect of the present disclosure, a DC / DC converter circuit, and a plurality of semiconductor switches connected in parallel, an output capacitor connected in series to each semiconductor switch, and a control section, and an overcurrent suppression circuit that outputs the direct current input from the DC / DC converter circuit to a load as a direct current load current is provided with an overcurrent suppression method in a DC / DC converter including the same. When a sudden change occurs in the load current, the control unit switches the plurality of semiconductor switches to a non-conducting state and then sequentially switches them to a conducting state.

Advantages of the Invention

[0009] The present disclosure or each aspect thereof can contribute to suppressing overcurrent generated during a sudden change in load or the like.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Modes for Carrying Out the Invention

[0011] Preferred embodiments of the present disclosure are shown below, but the present disclosure is not limited thereto. (Embodiment 1) Refer to the first aspect of the present disclosure described above. (Embodiment 2) In the overcurrent suppression circuit described in Embodiment 1 above, the control unit includes a plurality of timer circuits having different setting times, and preferably each of the plurality of timer circuits is assigned to one semiconductor switch. (Embodiment 3) In the overcurrent suppression circuit described in Embodiment 2 above, when a sudden change in the load current occurs, the timer circuit is activated to turn off the semiconductor switch assigned to the timer circuit, and after the elapse of the setting time of the timer circuit, the semiconductor switch is turned on again. It is preferably configured as follows. (Embodiment 4) In the overcurrent suppression circuit described in Embodiment 1 above, when the differential value of the voltage obtained from the load current is greater than a predetermined reference voltage value, it is preferably configured to execute control when a sudden change in the load current occurs. (Embodiment 5) In the overcurrent suppression circuit described in Embodiment 1 above, the semiconductor switch has a conduction direction in the same direction as the charging direction of the output capacitor, the sudden change in the load current is preferably a sudden increase in the load current. (Embodiment 6) In the overcurrent suppression circuit described in Embodiment 1 above, the semiconductor switch has a conduction direction in the opposite direction to the charging direction of the output capacitor, the sudden change in the load current is preferably a sudden decrease in the load current. (Embodiment 7) In the overcurrent suppression circuit described in Embodiment 1 above, the output section preferably includes a rectifier connected in parallel to each semiconductor switch and having a forward direction opposite to the conduction direction of the semiconductor switch. (Embodiment 8) Refer to the second perspective of the present disclosure above. (Embodiment 9) Refer to the third perspective of the present disclosure above. (Embodiment 10) Refer to the fourth perspective of the present disclosure above.

[0012] Note that the present disclosure can also be embodied as a computer-executable program, and the program can be recorded on a computer-readable non-transitory (non-transitory) storage medium. That is, the present disclosure can also be embodied as a computer program product. The program is input into a computer device through an input device or externally via a communication interface, stored in a storage device, drives a processor according to predetermined steps or processes, and can display the processing results including intermediate states step by step via a display device as needed, or communicate with the outside via a communication interface. A computer device for that purpose typically includes, as an example, a processor, a storage device, an input device, a communication interface, and a display device as needed, which are connectable to each other by a bus.

[0013] The following describes an overview of the present disclosure. Note that the reference numerals in the drawings appended to this overview are for assisting in understanding the present disclosure only and are not intended to limit the present disclosure to the illustrated embodiments. Also, the connection lines between blocks in each figure include both bidirectional and unidirectional ones. One-way arrows schematically show the flow of signals, information, data, etc. and do not exclude bidirectionality. Further, the connection between blocks in each figure can be either wired or wireless. Further, the program is executed via a computer device, and the computer device includes, for example, a processor, a storage device, an input device, a communication interface, and a display device as needed. The computer device is configured to be communicable with devices inside or outside the device (including computers) via a communication interface, whether wired or wireless.

[0014] Further, in the following description and drawings, the same reference numerals are assigned to elements having the same or common functions.

[0015] FIG. 1 shows a conceptual diagram of an example of a power supply device including an example of an overcurrent suppression circuit of the present disclosure.

[0016] The power supply device 1 includes a DC / DC converter 2 and a DC power supply unit 3 connected to the input side of the DC / DC converter 2. A load R is connected to the output side of the power supply device 1.

[0017] The DC / DC converter 2 includes a DC / DC converter circuit 4 supplied with a DC current from the DC power supply unit 3 and an overcurrent suppression circuit 5 connected to the output side of the DC / DC converter circuit 4.

[0018] The overcurrent suppression circuit 5 includes an output unit 6 that receives a DC current from the DC / DC converter circuit 4 and outputs the DC current, particularly after smoothing, to the load R, and a control unit 7 that controls the output unit 6.

[0019] FIG. 2 shows a conceptual diagram of an example of the output unit.

[0020] The output unit 6 includes a plurality of semiconductor switches Q 1 , Q 2 , … Q n (n is an integer of 2 or more) and output capacitors C 1 , Q 2 , … Q n connected in series to each semiconductor switch Q 1 , C 2 , … C n (n is an integer of 2 or more). And each semiconductor switch Q 1 , Q 2 , … Q n has its conduction state controlled by the control unit 7 (or an external computer (not shown), etc.).

[0021] FIG. 3 shows a flowchart of an example of a mode for suppressing an overcurrent generated when the load R changes suddenly by the overcurrent suppression circuit 5 including the output unit 6 shown in FIG. 2. Here, each semiconductor switch Q 1 , Q 2 , … Q n is normally always ON, that is, in a conducting state.

[0022] First, it is determined whether or not a sudden change in the load current has occurred (step 1). In the following, step 1 and the like are abbreviated as S1 and the like.

[0023] If a sudden change in the load current has occurred (YES), the control unit 7 turns off all the semiconductor switches Q 1 , Q 2 , … Q n simultaneously, that is, switches them to the non-conducting state (S2). As a result, the charging and discharging of all the output capacitors C 1 , C 2 , … C n are restricted.

[0024] Next, the control unit 7 sequentially switches the semiconductor switches Q 1 , Q 2 , … Q n to the ON state, that is, the conducting state (sequentially, that is, shifting the timing of turning them ON). As a result, the output capacitors C 1 , C 2 , … C n are also sequentially charged or discharged, and therefore, an overcurrent generated by charging or discharging all the output capacitors C 1 , C 2 , … C n simultaneously can be suppressed.

[0025] For example, when each semiconductor switch Q 1 , Q 2 , … Q n has a conduction direction in the same direction as the charging direction of the output capacitors C 1 , C 2 , … C n , and it is assumed that the load current (this corresponds to the output current of the power supply device 1 to the DC / DC converter 2 to the output unit 6) has increased rapidly due to a sudden change in the load R (see S1). In this case, the control unit 7 turns off all the semiconductor switches Q 1 , Q 2 , … Q n simultaneously, that is, switches them to the non-conducting state (see S2), and as a result, all the output capacitors C 1 , C 2 , … C nThe charging is restricted. Next, the control unit 7 sequentially switches the semiconductor switches Q 1 , Q 2 , …Q n to ON, that is, to the conducting state (see S3), whereby the output capacitors C 1 , C 2 , …C n are also sequentially charged. Therefore, it is possible to avoid a large inrush current from flowing due to all the output capacitors C 1 , C 2 , …C n being charged simultaneously (that is, to suppress overcurrent).

[0026] Also, for example, when each semiconductor switch Q 1 , Q 2 , …Q n has a conduction direction opposite to the charging direction of the output capacitors C 1 , C 2 , …C n , and assuming that the load current suddenly decreases due to a sudden change in the load R (see S1). In this case, the control unit 7 simultaneously switches all the semiconductor switches Q 1 , Q 2 , …Q n to OFF, that is, to the non-conducting state (see S2), whereby the discharge of all the output capacitors C 1 , C 2 , …C n is restricted. Next, the control unit 7 sequentially switches the semiconductor switches Q 1 , Q 2 , …Q n to ON, that is, to the conducting state (see S3), whereby the output capacitors C 1 , C 2 , …C n are also sequentially discharged. Therefore, it is possible to avoid a large reverse current from flowing into the switching element of the DC / DC converter circuit 4, for example, due to all the output capacitors C 1 , C 2 , …C n being discharged simultaneously (that is, to suppress overcurrent).

[0027] FIG. 4 shows a conceptual diagram of a specific example of a power supply device including an overcurrent suppression circuit of the present disclosure.

[0028] The power supply device 10 includes a DC / DC converter 20 and a DC power supply unit 30 connected to the input side of the DC / DC converter 20. A load R is connected to the output side of the power supply device 10. Note that the voltage of the DC power supply unit 30, and thus the input voltage of the DC / DC converter 20, is Vin, the output voltage of the DC / DC converter 20 is Vout(t), and the current flowing through the load R is i R (t), where the symbol t represents time (the same applies hereinafter).

[0029] The DC / DC converter 20 includes a DC / DC converter circuit 40 supplied with a DC current from the DC power supply unit 30 and an overcurrent suppression circuit 50 connected to the output side of the DC / DC converter circuit 40. Note that this DC / DC converter 20 is a step-down type, but the present disclosure can also be applied to other types of DC / DC converters.

[0030] The DC / DC converter circuit 40 includes a high-side FET (Field Effect Transistor) Q_H as a high-side switching element on the input side of the DC / DC converter circuit 40, a low-side FET Q_L as a low-side switching element on the ground side of the DC / DC converter circuit 40, and an output inductor L between the midpoint of the high-side FET Q_H and the low-side FET Q_L and the output side of the DC / DC converter circuit 40. The inductor current flowing through the output inductor L is i L (t).

[0031] The overcurrent suppression circuit 50 includes an output unit 60 that receives a DC current from the DC / DC converter circuit 40 and outputs the DC current to the load R, and a control unit 70 that controls the output unit 60. Note that the output unit 60 also has a smoothing function for stabilizing the output of the power supply device 10.

[0032] The output unit 60 includes a plurality of semiconductor switches Q 1 、Q 2 、…Q n(n is an integer of 2 or more), and each semiconductor switch Q 1 、Q 2 、…Q n and an output capacitor C 1 、C 2 、…C n (n is an integer of 2 or more). In the illustrated example, the semiconductor switches Q 1 、Q 2 、…Q n are FETs Q 1 、Q 2 、…Q n and the FETs Q 1 、Q 2 、…Q n have a conduction direction in the same direction as the charging direction of the output capacitors C 1 、C 2 、…C n . Therefore, when the FETs Q 1 、Q 2 、…Q n are switched to OFF, the charging of the output capacitors C 1 、C 2 、…C n is restricted.

[0033] Each FET Q 1 、Q 2 、…Q n is connected in parallel with a rectifier D 1 、D 2 、…D n (n is an integer of 2 or more) having a forward direction opposite to the conduction direction of each. In the illustrated example, the rectifiers D 1 、D 2 、…D n are the internal body diodes of the corresponding FETs Q 1 、Q 2 、…Q n . Therefore, when the FETs Q 1 、Q 2 、…Q n are turned OFF, the output capacitors C 1 、C 2 、…C n are respectively connected to the body diodes D 1 、D 2 、…D nIt can discharge through. Note that the semiconductor switch Q 1 , Q 2 , …Q n is, for example, a bipolar transistor or the like, the rectifier D 1 , D 2 , …D n can be a discrete diode or the like.

[0034] The control unit 70 includes a plurality of timer circuits T 1 , Q 2 , …Q n respectively assigned to each of the FETs Q 1 , T 2 , …T n (n is an integer of 2 or more). The timer circuits T 1 , T 2 , …T n have different setting times, and the intervals between the setting times that elapse in order are constant or at least partially different. For example, if the setting times of the timer circuits T 1 , T 2 , …T n are T’ 1 , T’ 2 , …T’ n , then (T’ n -T’ n-1 ) can be all the same, or at least partially different, that is, at least one of all (T’ n -T’ n-1 ) is different from the others (including the case where all (T’ n -T’ n-1 ) are different from each other).

[0035] In the illustrated example, the control unit 70 further includes an amplifier circuit 71 that amplifies the potential difference across both ends of a shunt resistor (resistance value Rdet) as a current detector inserted in the power supply line between the output unit 60 and the load R, a differentiator circuit 72 that extracts the variation component of the output voltage vdet(t) of the amplifier circuit 71, and a comparator 73 that compares the output voltage vdiff(t) of the differentiator circuit 72 with a reference voltage Vref. The output terminal of the comparator 73 is connected to the timer circuits T 1 , T 2 , …T nVia, each FET Q 1 , Q 2 , …Q n is connected to the gate terminals of.

[0036] Here, if the output voltage vdet(t) of the amplifier circuit 71 has an amplification factor of A, vdet(t)=A×Rdet×i R (t) (Equation 1) is represented by.

[0037] Also, the output voltage vdiff(t) of the differentiator circuit 72 is vdiff(t)=dvdet(t) / dt (Equation 2) is represented by.

[0038] And when vdiff(t)>Vref, the timer circuits T 1 , T 2 , …T n are activated, and in response, the FETs Q 1 , Q 2 , …Q n are turned off for a certain period of time. Note that the value of Vref is set to a value such that vdiff(t)>Vref does not occur under steady state or a minute load step change.

[0039] Figure 5 shows a time chart of an example of the operation of the power supply device 10 shown in Figure 4.

[0040] First, assume that there has been no load step change and it has been in a steady state until a certain point in time (t 0 ). In this case, the load current i R (t) is a steady current and there is almost no current fluctuation. Therefore, since the output voltage of the differentiator circuit is vdiff(t)≒0V, vdiff(t)<Vref and the timer circuits T 1 , T 2 , …T n are not activated, and the FETs Q 1 , Q 2 , …Q n are always in the ON state. Therefore, the output capacitors C 1 , C 2 , …Cn It always repeats charging and discharging, and the voltage ripple is suppressed.

[0041] Next, at a certain point in time (t 0 ), a sudden change in load occurs, and it is assumed that the load current i R (t) suddenly increases. In this case, since dvdet(t) / dt increases, vdiff(t) also increases. As a result, since vdiff(t)>Vref holds, the timer circuits T 1 , T 2 , …T n are activated, and the FETs Q 1 , Q 2 , …Q n all become OFF states (at t 0 ).

[0042] The DC / DC converter circuit 40 cannot respond in time and cannot pass a large current, but the output capacitors C 1 , C 2 , …C n can supply current by discharging the charge stored in them to the load side (from t 0 to t 1 ). In this case, although the FETs Q 1 , Q 2 , …Q n are in the OFF state, the charges are supplied through the corresponding body diodes D 1 , D 2 , …D n .

[0043] Due to the discharge of the output capacitors C 1 , C 2 , …C n , the voltage across each output capacitor C 1 , C 2 , …C n drops, and Vout(t) decreases. After that, the response of the DC / DC converter circuit 40 gradually catches up, and the inductor current i L (t) increases (after t 0 ).

[0044] The inductor current i L(t) increases, and i L (t) = i R (t). After that (t 1 ), even though the output capacitors C 1 , C 2 , … C n need to be charged, the inductor current i L (t) tries to increase further, but since the FETs Q 1 , Q 2 , … Q n are in the OFF state, the output capacitors C 1 , C 2 , … C n are not instantaneously charged simultaneously. And after the FETs Q 1 , Q 2 , … Q n turn OFF, for example, at t 1 seconds later, the FET Q 1 is switched to the ON state, at t 2 seconds later, the FET Q 2 is switched to the ON state ··· at t n seconds later, the FET Q n is switched to the ON state. By sequentially turning on the FETs Q 1 , Q 2 , … Q n , the charging period can be dispersed, so that a large inrush current can be restricted from flowing during a sudden load change.

[0045] In this way, the DC / DC converter 20 including the overcurrent suppression circuit 50 of this example and the DC / DC converter circuit 40 placed in front of the overcurrent suppression circuit 50, or the power supply device 10 including the DC / DC converter 20 and the DC power supply unit 30, can avoid the operation from being stopped due to overcurrent protection, for example, because the overcurrent suppression circuit 50 restricts a large inrush current from flowing during a sudden load change.

[0046] Fig. 6 shows a detailed time chart of an example of the operation of the power supply device 10 shown in Fig. 4.

[0047] In this example, the load current i R (t) is 0 seconds (t0 ) to t d During Δi R changes only within seconds, and Δi R is the current fluctuation range such that vdiff(t) > Vref holds. Also, the output capacitors C 1 , C 2 , … C n are all assumed to have the same capacitance of C [F].

[0048] The load current i R (t) has an initial value of i R (0) [A], and at t d seconds later, i R (t d ) = i R (0) + Δi R (Equation 3) becomes.

[0049] At time t d , the output voltage vdet(t) of the amplifier circuit 71 is, according to (Equation 1), vdet(t d ) = A × Rdet × i R (t d ) and the output voltage vdiff(t) of the differential circuit 72 is, according to (Equation 2), vdiff(t d ) = dvdet(t d ) / dt.

[0050] Due to the precondition, vdiff(t d ) > Vref holds, so the FETs Q 1 , Q 2 , … Q n all turn off simultaneously (however, only the FET Q 1 is shown).

[0051] On the other hand, the DC / DC converter circuit 40 operates to increase the inductor current i L (t) after the load current suddenly decreases.

[0052] i L (t) = i R (t d ) at time tr is represented using the crossover frequency f bw [Hz] of the DC / DC converter circuit 40 t r = 1 / 4f bw (Equation 4) holds. Therefore, i L (t r ) = i R (t d ) holds.

[0053] During this t r seconds, the output capacitors C 1 , C 2 , … C n discharge electric charges to the load R. At this time, since all of the FETs Q 1 , Q 2 , … Q n are in the OFF state, the current flowing from the power supply line to the output capacitors C 1 , C 2 , … C n is blocked. However, since current flows from the output capacitors C 1 , C 2 , … C n to the power supply line through the corresponding body diodes D 1 , D 2 , … D n , the load R can be supplied with electric charges.

[0054] Since the time from the occurrence of a sudden change in the load until v diff(t) > V ref is very short, the total amount of electric charge Δq released during this period is Δq ≒ Δi R × t r / 2 (Equation 5) can be approximated as.

[0055] t r seconds after, the DC / DC converter circuit 40 tries to supply a current greater than the load current to charge the output capacitors C 1 , C 2 , … C n . However, since the FETs Q 1 , Q 2 , … Q n are in the OFF state, the output capacitors C1 , C 2 , …C n will not be charged immediately.

[0056] And at time t 1 (t r ) seconds, the FET Q 1 is switched to the ON state, and accordingly, the charging of the output capacitor C 1 is started.

[0057] The output capacitors C 1 , C 2 , …C n all have the same capacitance, so the amount of charge required for charging is Δq / n.

[0058] Let the time (point in time) when the output capacitor C 1 is fully charged be t 1 ’, and let the maximum value of the current flowing through the output capacitor C 1 ’ - t 1 ) seconds be Im1. 1

[0059] (t 1 ’ - t 1 L ) seconds, if the waveform related to the charging of i L (t) is approximated by a triangle, the area of the triangle is equal to Δq / n. Therefore, expressing Im1 using Δq, Δq / n = Im1 × (t 1 ’ - t 1 ) / 2 (Equation 6) Im1 = 2Δq / n(t 1 ’ - t 1 ) (Equation 7) is obtained.

[0060] Therefore, if the time when it becomes Im1 is tm1, i L (tm1) is the load current + the charging current to the output capacitor C 1 , so i L (tm1) = i R (t d ) + Im1 (Equation 8) is obtained.

[0061] Output capacitor C 1 After the charging of the output capacitor C is completed, the FET Q 2 is switched to the ON state to charge the output capacitor C 2 in the same manner. The output capacitor C n is sequentially charged up to the output capacitor C

[0062] Output capacitor C 2 ~C n Since the capacitances of all of the output capacitors C

[0063] are equal, the currents required for charging are also equal, and the maximum value of the inrush current becomes the current value shown in (Equation 8).

[0064] Therefore, according to the present disclosure, the inrush current related to capacitor charging can be limited to the current value shown in (Equation 8).

[0065] FIG. 7 shows a conceptual diagram of another specific example of a power supply device including an overcurrent suppression circuit of the present disclosure.

[0066] The configuration of the power supply device 100 in this example is basically the same as the configuration of the power supply device 10 in the example shown in FIG. 4, but the FET Q 1 , Q 2 ,...Q n and the body diodes D 1 , D 2 ,...D n are different in the configuration where the directions are reversed, and in the configuration additionally including an inversion circuit between the differentiating circuit and the comparator. That is, each FET Q 1 , Q 2 ,...Q n has a conduction direction opposite to the charging direction of the output capacitors C 1 , C 2 ,...C n .

[0067] An example of the operation of the overcurrent suppression circuit 500 in this example will be briefly described below. Also in this example, in the steady state, FET Q 1 , Q 2 , …Q n is always in the ON state, and the output capacitors C 1 , C 2 , …C n can always repeat charging and discharging.

[0068] First, assume that the load current i R (t) suddenly decreases due to a sudden change in the load R.

[0069] Then, the output voltage of the differentiating circuit 702 that extracts the variation in the output voltage vdet(t) of the amplifier circuit 701 that amplifies the potential difference across both ends of the shunt resistor (resistance value Rdet) as a current detector inserted in the power supply line between the output section 600 and the load R rises (vdiff(t)), and the output voltage of the inverting circuit 704 to which this voltage is input rises (-vdiff(t)).

[0070] The output voltage of the inverting circuit 704 is input to the comparator 703 and compared with the reference voltage Vref.

[0071] When the output voltage of the inverting circuit 704 exceeds the reference voltage Vref (or threshold value), the timer circuits T 1 , T 2 , …T n are activated, and accordingly, the FETs Q 1 , Q 2 , …Q n are switched to the OFF state. Note that although the FETs Q 1 , Q 2 , …Q n are switched to the OFF state, the excessive inductor current i L (t) due to the sudden decrease in the load current flows in the forward direction through the body diodes D 1 , D 2 , …D n whose forward direction is opposite to the conduction direction of the FETs Q 1 , D 2 , …D nthrough the output capacitor C 1 , C 2 , …C n can be charged.

[0072] Timer circuits T 1 , T 2 , …T n each have different setting times. Assuming that the setting times of the timer circuits T 1 , T 2 , …T n increase in this order, the FETs Q 1 , Q 2 , …Q n will be sequentially switched to the ON state in this order. Therefore, the output capacitors C 1 , C 2 , …C n will discharge sequentially without discharging the charges all at once, so that the reverse flow of excessive current can be suppressed.

[0073] Therefore, the DC / DC converter 200 including the overcurrent suppression circuit 500 of this example and the DC / DC converter circuit 400 placed in front of the overcurrent suppression circuit 500 can operate as follows, for example.

[0074] When the load current i R (t) suddenly decreases, since the DC / DC converter circuit 400 cannot keep up with the response, the inductor current i L (t) does not decrease suddenly but decreases gradually.

[0075] During that time, the excessive inductor current i L (t) is charged to the output capacitors C 1 , C 2 , …C n .

[0076] When the inductor current i L (t) and the load current i R (t) become equal, the charges charged to the output capacitors C 1 , C 2 , …C n are discharged, but the load current i RWhen (t) is small, a phenomenon occurs where no charge flows to the load R and it flows backward into the DC / DC converter circuit 400.

[0077] In particular, when the load current i R (t) rapidly drops to near 0 A and the reverse current is large, there is a risk that the switching elements (high-side FET Q_H, low-side FET Q_L) inside the DC / DC converter circuit 400 will malfunction.

[0078] However, the overcurrent suppression circuit 500 in this example, when the load current i R (t) suddenly decreases, switches all the FETs Q 1 、Q 2 、…Q n to the OFF state to prevent the charge from flowing out of the output capacitors C 1 、C 2 、…C n Then, gradually switching the FETs Q 1 、Q 2 、…Q n to the ON state can prevent the current from flowing backward from the output capacitors C 1 、C 2 、…C n all at once.

[0079] In this way, the DC / DC converter 200 including the overcurrent suppression circuit 500 of this example and the DC / DC converter circuit 400 placed in front of the overcurrent suppression circuit 500, or the power supply device 100 including the DC / DC converter 200 and the DC power supply unit 300, since the overcurrent suppression circuit 500 restricts the large amount of reverse current from flowing during sudden load changes, for example, the failure of the switching elements of the DC / DC converter circuit 400 can be avoided.

[0080] Note that the control circuit according to the above embodiment can be configured using so-called hardware resources (information processing devices, computers), and those having the configuration illustrated in FIG. 8 can be used. For example, the hardware resource 1000 can include a processor 1001, a memory 1002, a network interface 1003, etc., which are interconnected by an internal bus 1004.

[0081] However, the configuration shown in FIG. 8 is not intended to limit the hardware configuration of the hardware resource 1000. The hardware resource 1000 may include hardware not shown (for example, an input / output interface). For the processor 1001, for example, a CPU (Central Processing Unit), an MPU (Micro Processor Unit), a GPU (Graphics Processing Unit), etc. can be used.

[0082] Also, for the memory 1002, for example, a RAM (Random Access Memory), a ROM (Read Only Memory), an HDD (Hard Disk Drive), an SSD (Solid State Drive), etc. can be used. Here, the memory 1002 can store a predetermined threshold value regarding the above-described predetermined physical quantity, and can also store a control program for performing the above-described control.

[0083] Furthermore, for the network interface 1003, for example, a LAN (Local Area Network) card, a network adapter, a network interface card, etc. can be used.

[0084] Furthermore, the functions of the hardware resources 1000 are realized by a processing module. The processing module is realized, for example, by the processor 1001 executing a program stored in the memory 1002. Also, the program can be downloaded via a network or updated using a storage medium storing the program. Furthermore, the above processing module may be realized by a semiconductor chip. That is, the functions performed by the above processing module may be realized as long as software is executed in some hardware.

[0085] Some or all of the above embodiments may be described as follows in the appended claims, but are not limited thereto. [Appendix 1] An overcurrent suppression circuit including an output unit that inputs and outputs a direct current and a control unit. The output unit includes a plurality of semiconductor switches connected in parallel and an output capacitor connected in series to each semiconductor switch. The control unit is configured to perform control to switch the plurality of semiconductor switches to a non-conducting state and then sequentially switch them to a conducting state when a sudden change in the load current occurs from the output unit. [Appendix 2] In the above overcurrent suppression circuit, The control unit includes a plurality of timer circuits having different setting times. The plurality of timer circuits are respectively assigned to one semiconductor switch. [Appendix 3] In the above overcurrent suppression circuit, The timer circuit is configured to start when a sudden change in the load current occurs, turn off the semiconductor switch assigned to the timer circuit, and turn on the semiconductor switch again after the elapse of the setting time of the timer circuit. [Appendix 4] In the above overcurrent suppression circuit, The control unit is configured to execute control when a sudden change in the load current occurs when the differential value of the voltage obtained from the load current is greater than a predetermined reference voltage value. [Appendix 5] In the above overcurrent suppression circuit, The semiconductor switch has a conduction direction that is the same as the charging direction of the output capacitor. The sudden change in the load current is a sudden increase in the load current. [Appendix 6] In the above overcurrent suppression circuit, The semiconductor switch has a conduction direction that is opposite to the charging direction of the output capacitor. The sudden change in the load current is a sudden decrease in the load current. [Appendix 7] In the above overcurrent suppression circuit, The output section includes a rectifier, particularly a diode, that is connected in parallel to each semiconductor switch and has a forward direction opposite to the conduction direction of the semiconductor switch. [Appendix 8] In the above overcurrent suppression circuit, The semiconductor switch is a field-effect transistor, and the rectifier is the body diode of the field-effect transistor. [Appendix 9] In the above overcurrent suppression circuit, The semiconductor switch is a bipolar transistor, and the rectifier is a discrete diode. [Appendix 10] In the above overcurrent suppression circuit, The control unit is configured to perform control to sequentially switch the conduction states of the plurality of semiconductor switches at regular time intervals or at least partially different time intervals. [Appendix 11] In the above overcurrent suppression circuit, The intervals between the setting times of the plurality of timer circuits that elapse in sequence are constant or at least partially different. [Appendix 12] In the above overcurrent suppression circuit, The control unit includes a comparator that compares the differential value of the voltage obtained from the load current with the predetermined reference voltage value. [Appendix 13] In the above overcurrent suppression circuit, The control unit includes a differential circuit for generating a differential value of the voltage obtained from the load current via an amplifier circuit as needed, and includes an amplifier circuit as needed. [Appendix 14] In the above overcurrent suppression circuit, The load current is the current detected by a current detector, particularly a shunt resistor, connected to the output side of the overcurrent suppression circuit. [Appendix 15] A DC / DC converter including the overcurrent suppression circuit of the present disclosure and a DC / DC converter circuit placed in front of the overcurrent suppression circuit (connected to the input side of the overcurrent suppression circuit). [Appendix 16] In the above DC / DC converter, The DC / DC converter circuit includes a high-side switching element (such as a field effect transistor) on the input side of the DC / DC converter circuit, a low-side switching element (such as a field effect transistor) on the ground side of the DC / DC converter circuit, and an output inductor between the midpoint of the high-side switching element and the low-side switching element and the output side of the DC / DC converter circuit. [Appendix 17] A power supply device including the DC / DC converter of the present disclosure and a DC power supply unit placed in front of the DC / DC converter (connected to the input side of the DC / DC converter). [Appendix 18] In the above power supply device, The DC power supply unit is an AC / DC converter. Note that "AC" is an abbreviation for "Alternating Current". [Appendix 19] An overcurrent suppression method in a DC / DC converter (or a power supply device including a DC / DC converter). The DC / DC converter is a DC / DC converter circuit, and a plurality of semiconductor switches connected in parallel, an output capacitor connected in series to each semiconductor switch, and a control unit, and includes an overcurrent suppression circuit that outputs the DC current input from the DC / DC converter circuit as a DC load current to a load. including. In the overcurrent suppression method, when a sudden change occurs in the load current, the control unit switches the plurality of semiconductor switches to a non-conducting state and then sequentially switches them to a conducting state. [Appendix 20] In the above overcurrent suppression method, The control unit performs control to sequentially switch the conduction states of the plurality of semiconductor switches at regular time intervals or at least partially different time intervals. [Appendix 21] In the above overcurrent suppression method, When the differential value of the voltage obtained from the load current is greater than a predetermined reference voltage value, the control unit executes control when a sudden change in the load current occurs. [Appendix 22] In the above overcurrent suppression method, The sudden change in the load current is a sudden increase in the load current, The semiconductor switch has a conduction direction in the same direction as the charging direction of the output capacitor. [Appendix 23] In the above overcurrent suppression method, The sudden change in the load current is a sudden decrease in the load current, The semiconductor switch has a conduction direction opposite to the charging direction of the output capacitor. [Appendix 24] A control program for a DC / DC converter (or a power supply device including a DC / DC converter). The DC / DC converter includes a DC / DC converter circuit, and a plurality of semiconductor switches connected in parallel and an output capacitor connected in series to each semiconductor switch, and an overcurrent suppression circuit that outputs the DC current input from the DC / DC converter circuit to a load as a DC load current and includes. When a sudden change occurs in the load current, the control program causes the computer to execute control to switch the plurality of semiconductor switches to a non-conducting state and then sequentially switch them to a conducting state. [Appendix 25] The above control program causes the computer to execute control to sequentially switch the conduction states of the plurality of semiconductor switches at regular time intervals or at least partially different time intervals. [Appendix 26] The above control program causes the computer to execute control when a sudden change in the load current occurs when the differential value of the voltage obtained from the load current is greater than a predetermined reference voltage value. [Appendix 27] In the above control program, the sudden change in the load current is a sudden increase in the load current, and the semiconductor switch has a conduction direction in the same direction as the charging direction of the output capacitor. [Appendix 28] In the above control program, the sudden change in the load current is a sudden decrease in the load current, and the semiconductor switch has a conduction direction in the opposite direction to the charging direction of the output capacitor. [Appendix 29] The above DC / DC converter is a step-down DC / DC converter.

[0086] Within the framework of the entire disclosure of the present invention (including the claims), further modifications and adjustments of the embodiments or examples can be made based on its basic technical idea. Also, within the framework of the entire disclosure of the present invention, various combinations or selections (including partial deletion) of various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) are possible. That is, the present invention naturally includes all various deformations and modifications that could be made by those skilled in the art in accordance with the entire disclosure including the claims and the technical idea.

Explanation of Reference Numerals

[0087] 1, 10, 100 Power supply device 2, 20, 200 DC / DC converter 3, 30, 300 DC power supply unit 4, 40, 400 DC / DC converter circuit 5, 50, 500 Overcurrent suppression circuit 6, 60, 600 Output unit 7, 70, 700 Control unit 71, 701 Amplification circuit 72, 702 Differentiation circuit 73, 703 Comparator 704 Inversion circuit C 1 、C 2 、…C n Output capacitor D1 , D 2 , …D n (Body) Diode Q 1 , Q 2 , …Q n FET T 1 , T 2 , …T n Timer circuit R load L output inductor i R Load current i L Inductor current 1000 Hardware resources 1001 Processor 1002 Memory 1003 Network interface 1004 Internal bus

Claims

1. An overcurrent suppression circuit including an output unit that inputs and outputs a direct current, and a control unit, wherein the output unit includes a plurality of semiconductor switches connected in parallel and an output capacitor connected in series to each semiconductor switch, and the control unit is configured to perform control to switch the plurality of semiconductor switches to a non-conducting state and then sequentially switch them to a conducting state when a sudden change in the load current from the output unit occurs. An overcurrent suppression circuit characterized by the above.

2. In the overcurrent suppression circuit according to Claim 1, the control unit includes a plurality of timer circuits having different setting times, and the plurality of timer circuits are respectively assigned to one semiconductor switch. An overcurrent suppression circuit characterized by the above.

3. In the overcurrent suppression circuit according to Claim 2, the timer circuit is configured to start when a sudden change in the load current occurs, turn off the semiconductor switch assigned to the timer circuit, and turn on the semiconductor switch again after the elapse of the setting time of the timer circuit. An overcurrent suppression circuit characterized by the above.

4. In the overcurrent suppression circuit according to Claim 1, the control unit is configured to execute control when a sudden change in the load current occurs when the differential value of the voltage obtained from the load current is greater than a predetermined reference voltage value. An overcurrent suppression circuit characterized by the above.

5. In the overcurrent suppression circuit according to Claim 1, the semiconductor switch has a conduction direction in the same direction as the charging direction of the output capacitor, and the sudden change in the load current is a sudden increase in the load current. An overcurrent suppression circuit characterized by the above.

6. In the overcurrent suppression circuit according to Claim 1, the semiconductor switch has a conduction direction opposite to the charging direction of the output capacitor, and the sudden change in the load current is a sudden decrease in the load current. An overcurrent suppression circuit characterized by the above.

7. In the overcurrent suppression circuit according to Claim 1, the output unit includes a rectifier connected in parallel to each semiconductor switch and having a forward direction opposite to the conduction direction of the semiconductor switch. An overcurrent suppression circuit characterized by the above.

8. A DC / DC converter including the overcurrent suppression circuit according to any one of Claims 1 to 7 and a DC / DC converter circuit placed in front of the overcurrent suppression circuit.

9. A power supply device including the DC / DC converter according to claim 8 and a DC power supply unit provided in front of the DC / DC converter.

10. A DC / DC converter circuit, and a plurality of semiconductor switches connected in parallel, an output capacitor connected in series to each semiconductor switch, and a control unit, and an overcurrent suppression circuit that outputs the DC current input from the DC / DC converter circuit to a load as a DC load current An overcurrent suppression method in a DC / DC converter including: when a sudden change occurs in the load current, the control unit switches the plurality of semiconductor switches to a non-conducting state and then sequentially switches them to a conducting state An overcurrent suppression method, characterized by the above.

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