Electronic device, electronic component, method for manufacturing electronic device, and method for manufacturing electronic component

Abstract

To solve the problem in which: for a semiconductor device configured by pasting surfaces of chips to each other on each of which a semiconductor element is formed, technique is expected which can suppress increase in the size of the semiconductor device while installing a test terminal.SOLUTION: An electronic device comprises: a first chip that is provided, on a first principal surface of a first substrate, with a first semiconductor element, a first insulating layer, a first wiring layer, and a first connection electrode on a different layer from the first wiring layer; and a second chip that is provided, on a second principal surface of a second substrate, with a second semiconductor element, a second insulating layer, a second wiring layer, and a second connection electrode on a different layer from the second wiring layer. The first principal surface and the second principal surface face each other, with the first insulating layer, first wiring layer, first connection electrode, second insulating layer, second wiring layer, and second connection electrode therebetween. The first chip and the second chip are fixed so that the first connection electrode and the second connection electrode are electrically connected to each other. A terminal electrically connected to the first wiring layer is exposed in the first chip on the opposite side of the second chip.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an electronic device (semiconductor device) in which a plurality of chips each having a semiconductor element are integrated. [Background technology]

[0002] In recent years, in order to miniaturize electronic devices and improve their performance, multiple chips equipped with semiconductor elements are stacked. Electronic devices in which multiple chips are stacked may be provided with test terminals for testing electrical characteristics. Patent Document 1 discloses a method for arranging test terminals in an electronic device in which two chips are stacked. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-46569 A Summary of the Invention [Problem to be solved by the invention]

[0004] Patent Document 1 describes a method for arranging test pads in a semiconductor device in which a surface of one semiconductor chip on which a semiconductor element is formed is bonded to a surface of the other semiconductor chip on which a semiconductor element is not formed. According to the test pad arranging method of Patent Document 1, it is possible to inspect the chips using a wafer tester, so it is said that there is no need to use a dedicated tester. However, Patent Document 1 did not consider a method for arranging test pads for a semiconductor device configured by bonding the surfaces on which the semiconductor elements of both chips are formed together.

[0005] Therefore, there was a demand for technology that could install test terminals for evaluating electrical characteristics while preventing the size of electronic devices (semiconductor devices) formed by bonding the surfaces of each chip on which the semiconductor elements are formed from increasing. [Means for solving the problem]

[0006] A first aspect of the present invention is an electronic device comprising: a first chip having a first semiconductor element, a first insulating layer, a first wiring layer, and a first connection electrode that is a different layer from the first wiring layer, which are provided on a first main surface of a first substrate; and a second chip having a second semiconductor element, a second insulating layer, a second wiring layer, and a second connection electrode that is a different layer from the second wiring layer, which are provided on a second main surface of a second substrate, wherein the first chip and the second chip are fixed together so that the first main surface and the second main surface face each other with the first insulating layer, the first wiring layer, the first connection electrode, the second insulating layer, the second wiring layer, and the second connection electrode sandwiched therebetween, and the first connection electrode and the second connection electrode are electrically connected, and the first chip is electrically connected to the first wiring layer and has a terminal exposed on the opposite side of the second chip.

[0007] A second aspect of the present invention is a method for manufacturing an electronic device, comprising: a first chip preparation step of preparing a first chip having a first semiconductor element, a first insulating layer, a first wiring layer, and a first connection electrode in a different layer from the first wiring layer on a first main surface of a first substrate, and a terminal electrically connected to the first wiring layer exposed on the opposite side of the first main surface; a second chip preparation step of preparing a second chip having a second semiconductor element, a second insulating layer, a second wiring layer, and a second connection electrode in a different layer from the second wiring layer on a second main surface of a second substrate; and a fixing step of fixing the first chip and the second chip so that the first main surface and the second main surface face each other with the first insulating layer, the first wiring layer, the first connection electrode, the second insulating layer, the second wiring layer, and the second connection electrode sandwiched therebetween, and so that the first connection electrode and the second connection electrode are electrically connected. Effect of the Invention

[0008] According to the present invention, for an electronic device (semiconductor device) constructed by bonding together the surfaces of each chip on which a semiconductor element is formed, it is possible to prevent the electronic device (semiconductor device) from becoming larger while providing test terminals for evaluating electrical characteristics. [Brief description of the drawings]

[0009] [Figure 1] 1A is a schematic plan view of an electronic device according to an embodiment, FIG. 1B is a schematic cross-sectional view of the electronic device taken along line AA in FIG. 1A, and FIG. 1C is a schematic cross-sectional view of an electronic component according to an embodiment. [Diagram 2] 1A is a schematic cross-sectional view of a first chip, and FIG. 1B is a schematic cross-sectional view of a second chip. [Diagram 3] (a) A diagram showing the manufacturing process of the first chip. (b) A diagram showing the manufacturing process of the first chip subsequent to FIG. 3(a). (c) A diagram showing the manufacturing process of the first chip subsequent to FIG. 3(b). (d) A diagram showing the manufacturing process of the first chip subsequent to FIG. 3(c). (e) A diagram showing the manufacturing process of the first chip subsequent to FIG. 3(d). [Figure 4] 4(a) A diagram showing the manufacturing process of the second chip, (b) A diagram showing the manufacturing process of the second chip subsequent to FIG. 4(a), (c) A diagram showing the manufacturing process of the second chip subsequent to FIG. 4(b), (d) A diagram showing the manufacturing process of the second chip subsequent to FIG. 4(c). [Diagram 5] 5(a) is a diagram showing a manufacturing process of an electronic device, (b) is a diagram showing a manufacturing process of an electronic device subsequent to Fig. 5(a), (c) is a diagram showing a manufacturing process of an electronic device subsequent to Fig. 5(b), and (d) is a diagram showing a manufacturing process of an electronic device subsequent to Fig. 5(c). [Figure 6] 1A is a diagram showing a state in which the electrical characteristics of an electronic device are evaluated, and FIG. [Figure 7] FIG. 1 is a plan view showing a state in which a plurality of electronic devices are formed on a wafer. [Figure 8] 1A is a schematic cross-sectional view of an electronic device according to a second embodiment, and FIG. [Figure 9] (a) A schematic diagram for explaining an apparatus according to embodiment 3. (b) A schematic diagram showing an example of a photoelectric conversion system according to embodiment 3. (c) A schematic diagram showing an example of an in-vehicle photoelectric conversion system according to embodiment 3. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] An electronic device (semiconductor device) according to an embodiment of the present invention, a method for manufacturing the electronic device (semiconductor device), etc. will be described with reference to the drawings. The embodiment described below is merely an example, and those skilled in the art can appropriately modify and implement the detailed configuration without departing from the spirit of the present invention.

[0011] In the drawings referred to in the following description of the embodiments, elements denoted by the same reference numerals have the same functions unless otherwise noted. When a plurality of identical elements are arranged in a drawing, the reference numerals and their descriptions may be omitted.

[0012] In addition, since the drawings may be represented diagrammatically for the convenience of illustration and explanation, the shape, size, arrangement, etc. of the elements depicted in the drawings may not strictly correspond to the actual objects.

[0013] [Embodiment 1] (composition) Fig. 1(a) is a schematic plan view showing an electronic device 800 as an electronic device (semiconductor device) according to this embodiment. The electronic device 800 is viewed in a direction perpendicular to its main surface (the normal direction of the main surface), and not only the external appearance but also the positions of a first connection electrode 150 and a second connection electrode 250 provided inside the device are illustrated. Fig. 1(b) is a schematic cross-sectional view of the electronic device 800 cut along the line AA shown in Fig. 1(a).

[0014] As shown in the figure, the electronic device 800 has a configuration in which a first chip 100 and a second chip 200 are integrated together. A schematic cross-sectional view of the first chip 100 is shown in Fig. 2(a), and a schematic cross-sectional view of the second chip 200 is shown in Fig. 2(b).

[0015] 2(a), the first chip 100 includes a first substrate 110, which is, for example, a semiconductor substrate. A semiconductor element 120 is formed on a first main surface MS1 side of the first substrate 110. Although shown diagrammatically in the figure, the semiconductor element 120 may include, for example, a number of transistors and diodes.

[0016] A first insulating layer 130, a first wiring layer 140, a test terminal TP, and a first connection electrode 150 are further provided on the side of the first main surface MS1 of the first substrate 110. The first wiring layer 140, the test terminal TP, and the first connection electrode 150 are formed using, for example, aluminum or copper.

[0017] The first wiring layer 140 is shown in the figure as a single layer, but may be a multilayer wiring structure in which multiple wiring layers are stacked. The first insulating layer 130 may be made of, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or the like, and may function as an interlayer insulating layer in the multilayer wiring structure. The multilayer wiring structure may include vias and plugs that connect wiring in different layers. When the first wiring layer 140 is a multilayer wiring structure, it is preferable to provide the test terminal TP in the same layer as any of the wiring layers of the multilayer wiring, but in some cases it may be provided in a different layer.

[0018] The semiconductor element 120, the first wiring layer 140, and the first connection electrode 150 are electrically connected to form an electronic circuit. The first connection electrode 150 is formed in a layer different from the first wiring layer 140, is exposed on the surface of the first chip 100, and is electrically connected to a second connection electrode 250 provided on the second chip 200 as described below.

[0019] The first chip 100 is provided with a through hole TH1 that penetrates the first substrate 110. The through hole TH1 extends into the first insulating layer 130 to expose the test terminal TP. In this specification, unless otherwise specified, the inside of a through hole is not treated to be conductive.

[0020] 2(b), the second chip 200 includes a second substrate 210, which is, for example, a semiconductor substrate. A semiconductor element 220 is formed on the second main surface MS2 side of the second substrate 210. Although shown diagrammatically in the figure, the semiconductor element 220 may include, for example, a number of transistors and diodes.

[0021] A second insulating layer 230, a second wiring layer 240, and a second connection electrode 250 are further provided on the second main surface MS2 side of the second substrate 210. The second wiring layer 240 and the second connection electrode 250 are formed using, for example, aluminum or copper. The second wiring layer 240 is shown as a single layer in the figure, but may be a multilayer wiring structure in which multiple wiring layers are stacked. For example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, etc. are used for the second insulating layer 230, and it may function as an interlayer insulating layer in the multilayer wiring structure. The multilayer wiring structure may be configured to include vias and plugs that connect wiring of different layers.

[0022] The semiconductor element 220, the second wiring layer 240, and the second connection electrode 250 are electrically connected to form an electronic circuit. The second connection electrode 250 is formed in a layer different from the second wiring layer 240, is exposed on the surface of the second chip 200, and is electrically connected to the first connection electrode 150 provided on the first chip 100 as described later.

[0023] 1(b), in the electronic device 800, the first chip 100 and the second chip 200 are integrated with the semiconductor element 120 of the first chip 100 and the semiconductor element 220 of the second chip 200 facing each other with an insulating layer and a wiring layer sandwiched between them. That is, the first chip and the second chip are fixed so that the first main surface MS1 and the second main surface MS2 face each other with the first insulating layer, the first wiring layer, the first connection electrode, the second insulating layer, the second wiring layer, and the second connection electrode sandwiched between them, and the first chip and the second chip are fixed so that the first connection electrode and the second connection electrode are electrically connected.

[0024] When the first chip and the second chip are fixed, the first connection electrode 150 and the second connection electrode 250 can be mechanically and electrically bonded by thermocompression without the use of an adhesive, etc. Also, the first insulating layer 130 and the second insulating layer 230 can be formed of the same material and their surfaces activated by a method such as plasma irradiation, whereby the first insulating layer 130 and the second insulating layer 230 can be directly bonded at low temperatures.

[0025] Here, a method of accessing the test terminal TP with a tester probe to evaluate the electrical characteristics of the chip will be considered. Let us consider a method of accessing the test terminal TP by drilling a hole in the first insulating layer 130 from the contact surface side of the first chip 100 and the second chip 200, instead of accessing through the through hole TH1 penetrating the first substrate 110 as in the present embodiment. In that case, it is necessary to arrange both chips so that at least a part of the first chip 100 protrudes beyond the outer edge of the second chip 200 in a plan view, and to form a hole in the first insulating layer 130 so that the test terminal TP can be accessed at the protruding part. Then, the electronic device becomes larger by the amount that the first chip 100 protrudes beyond the outer edge of the second chip 200, and the cost increases by the amount of the increased area of ​​the substrate.

[0026] In contrast, in the electronic device 800 according to the present embodiment, as shown in FIG. 1(a), the projected area of ​​the first chip 100 provided with the test terminal TP can be made smaller than the projected area of ​​the second chip 200 in a plan view, and the cost of the substrate can be reduced. Moreover, the first chip 100 is included in the second chip 200 in a plan view, and both chips are laid out so that the first chip 100 does not protrude from the outer edge of the second chip 200. In the electronic device 800 according to the present embodiment, the test terminal TP can be accessed through the through hole TH1 from the side opposite to the main surface MS1 (the main surface on the side where the semiconductor element 120 is provided) of the first substrate 110. Thus, according to the present embodiment, when the first chip 100 provided with the test terminal TP and the second chip 200 are integrated by being laid out in a manner that the semiconductor elements face each other, the electronic device 800 can be made compact.

[0027] 1(c) shows a schematic cross-sectional view of an electronic component 900 according to an embodiment. The electronic component 900 includes a circuit board 600 and an electronic device 800 mounted on the circuit board 600. The circuit board 600 can be, for example, a rigid board such as a glass epoxy board or a ceramic board, a flexible board such as a flexible printed board, or a rigid-flexible board that is a combination of these.

[0028] 1(b), the electronic device 800 used in this embodiment has external connection terminals BP provided on the first chip 100, which are electrically connected to the first wiring layer 140. The external connection terminals BP, like the test terminals TP, are exposed so as to be accessible from the opposite side to the main surface MS1 (the main surface on the side where the semiconductor element 120 is provided) of the first substrate 110. That is, the first chip 100 has through holes TH2 penetrating the first substrate 110, and the through holes TH2 extend (extend) into the first insulating layer 130 to expose the external connection terminals BP.

[0029] In the electronic component 900, the external connection terminal BP is electrically connected to the circuit board 600 by a connection member 500. As the connection member 500, for example, a conductive wire such as gold, copper, or aluminum is used, and the external connection terminal BP and the circuit board 600 are connected by a general wire bonding method. Note that in this example, the external connection terminal BP is provided separately from the test terminal TP, but the test terminal TP may be configured to also serve the function of the external connection terminal BP.

[0030] In electronic component 900 according to this embodiment, test terminals TP and external connection terminals BP can be accessed via through holes TH1 and TH2 from the opposite side to main surface MS1 (the main surface on the side where semiconductor elements 120 are provided) of first substrate 110. Thus, according to this embodiment, when first chip 100 having test terminals TP and external connection terminals BP and second chip 200 are integrated by being laid out with the semiconductor elements facing each other, electronic device 800 and electronic component 900 can be configured to be small in size.

[0031] To give an example of components of electronic device 800 and electronic component 900 according to the present embodiment, first chip 100 is an image sensor, and second chip 200 is a chip including at least one of a memory circuit or a logic circuit. Alternatively, first chip 100 is a memory chip, and second chip 200 is a logic chip. The above is an example, and the electronic device (semiconductor device) or electronic component of the embodiment may be configured by combining other types of chips.

[0032] (Manufacturing method) A method for manufacturing an electronic device and an electronic component according to the present embodiment will be described with reference to the drawings. Here, an example will be described in which the same terminal TM functions as a test terminal for determining the quality of a first chip, a test terminal for determining the quality of an electronic device, and an external connection terminal for connecting the electronic device to a circuit board. It goes without saying that each function may be performed by a separate terminal.

[0033] (Method of manufacturing the first chip) First, a manufacturing method of the first chip 100 (first chip preparation process) will be described with reference to Fig. 3(a) to Fig. 3(e). Each figure shows a schematic cross section of the first chip 100 at each stage of the manufacturing process. Although Fig. 3(a) to Fig. 3(e) show only a single first chip 100, it is also possible to form a plurality of first chips 100 on the same wafer and cut them apart later.

[0034] 3(a), a semiconductor element 120, a first insulating layer 130, a first wiring layer 140, a terminal TM, and a first connection electrode 150 are sequentially formed on a main surface MS1 (first main surface) of a first substrate 110. For the first substrate 110, a single crystal semiconductor substrate such as silicon can be used.

[0035] A first semiconductor element 120 such as a transistor or a diode is provided on a main surface MS1 which is one of the main surfaces of the first substrate 110. When an insulating substrate such as glass or resin is used instead of a semiconductor substrate for the first substrate 110, a TFT (thin film transistor) may be provided as the first semiconductor element 120 on the main surface MS1 of the insulating substrate.

[0036] A first insulating layer 130 is provided on the first semiconductor element 120 and on the main surface MS1 on which the first semiconductor element 120 is not provided. For example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or the like is used as the first insulating layer 130. Contact plugs (not shown) electrically connected to the first semiconductor element 120 are disposed in the first insulating layer 130. A conductive material such as tungsten is embedded in the contact plugs. A first wiring layer 140 electrically connected to the first semiconductor element 120 via the contact plugs is provided inside the first insulating layer 130.

[0037] The first wiring layer 140 is shown as a single layer in the figure, but may be a multilayer wiring structure in which multiple wiring layers are stacked. The first insulating layer 130 may function as an interlayer insulating layer in the multilayer wiring structure. The multilayer wiring structure may be configured to include vias and plugs that connect wiring in different layers. The first wiring layer 140 is made of a metal material such as aluminum or copper, and a barrier metal such as Ti, Ta, TiN, or TaN may be provided at the interface between the first wiring layer 140 and the first insulating layer 130 to suppress diffusion of metal into the first insulating layer 130.

[0038] From the viewpoint of reducing the number of processes, it is preferable to form the terminal TM in the same layer and with the same material as any of the layers of the multilayer wiring constituting the first wiring layer 140. A first insulating layer 130, a first connection electrode 150, and a first insulating layer 130 are sequentially laminated on the first wiring layer 140 and the terminal TM. At least three insulating layers are arranged between the first semiconductor element 120 and the first wiring layer 140, between the first wiring layer 140 and the first connection electrode 150, and on the first connection electrode 150, but for convenience of illustration, these are not distinguished and are shown as the first insulating layer 130.

[0039] The semiconductor element 120, the first wiring layer 140, and the first connection electrode 150 are electrically connected to form an electronic circuit. A dummy pattern that is not electrically connected to the circuit may be formed in the same layer as the first connection electrode 150 and used as an anchor to increase the bonding strength when bonding the first chip 100 and the second chip 200.

[0040] Next, as shown in FIG. 3(b), the first carrier substrate 300 is bonded onto the first insulating layer 130 via the first temporary bonding layer 310. The first temporary bonding layer 310 may be a thermal peeling type adhesive whose adhesive strength decreases when heated. When a light-transmitting substrate is used as the first carrier substrate 300, the first temporary bonding layer 310 may be a UV peeling type adhesive whose adhesive strength decreases when irradiated with ultraviolet light. The first carrier substrate 300 may be, for example, a single crystal semiconductor substrate such as silicon, an insulating substrate such as glass or ceramic, or a metal substrate.

[0041] Next, as shown in Fig. 3(c), the surface of the first substrate 110 opposite to the main surface MS1 is polished by back grinding or CMP to thin the first substrate 110 to a thickness of about 50 µm to 200 µm. Note that Fig. 3(c) and subsequent Figs. 3(a) and 3(b) are shown upside down.

[0042] 3(d), a through hole TH is formed penetrating the first substrate 110 from the surface opposite to the main surface MS1 of the first substrate 110, and the through hole TH is further extended to a part of the first insulating layer 130 to expose the terminal TM. Specifically, when the first substrate 110 is a silicon substrate, a through hole can be formed in the silicon substrate by dry etching using the Bosch method. After the through hole TH is formed in the first substrate 110, the first insulating layer 130 between the first substrate 110 and the terminal TM is removed by reactive ion etching (RIE) to extend the through hole TH and expose the surface of the terminal TM.

[0043] 3(e), a tester probe PR is inserted into the hole with the terminal TM exposed at the bottom and brought into contact with the terminal TM to evaluate the electrical performance of the first chip 100. Through the electrical performance evaluation, the first chip 100 which is a non-defective product is selected and used for bonding with the second chip 200. When multiple first chips 100 are formed on the same wafer, the electrical performance evaluation is performed on each chip on the wafer, and later, when the chips are cut into pieces, the first chips 100 which are non-defective products can be selected and used.

[0044] At the stage of Figure 3(e), the first chip 100 in the form shown in Figure 2(a) is not completed, but the subsequent processes will be described with reference to Figures 5(a) to 5(c) in the manufacturing method of the electronic device described later.

[0045] (Method of manufacturing the second chip) Next, a method for manufacturing second chip 200 (second chip preparation process) will be described with reference to Figures 4(a) to 4(d). Each figure shows a schematic cross section of second chip 200 at each stage of the manufacturing process. Although Figures 4(a) to 4(d) show only a single second chip 200, it is also possible to form a plurality of second chips 200 on the same wafer and cut them apart later.

[0046] 4(a), a semiconductor element 220, a second insulating layer 230, and a second wiring layer 240 are sequentially formed on a main surface MS2 (second main surface) of a second substrate 210. For the second substrate 210, for example, a single crystal semiconductor substrate such as silicon can be used.

[0047] Semiconductor elements 220 such as transistors and diodes are provided on a main surface MS2 which is one of the main surfaces of the second substrate 210. When an insulating substrate such as glass or resin is used instead of a semiconductor substrate for the second substrate 210, a TFT (thin film transistor) may be disposed as the second semiconductor element 220 on the main surface MS2 of the insulating substrate.

[0048] A second insulating layer 230 is provided on the second semiconductor element 220 and on the main surface MS2 on which the second semiconductor element 220 is not provided. For example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, etc. are used as the second insulating layer 230. A contact plug (not shown) electrically connected to the second semiconductor element 220 is disposed in the second insulating layer 230. A conductive material such as tungsten is embedded in the contact plug. A second wiring layer 240 electrically connected to the semiconductor element 220 via the contact plug is provided inside the second insulating layer 130.

[0049] The second wiring layer 240 is shown as a single layer in the figure, but may be a multilayer wiring structure in which multiple wiring layers are stacked. The second insulating layer 230 may function as an interlayer insulating layer in the multilayer wiring structure. The multilayer wiring structure may be configured to include vias and plugs that connect wiring of different layers. The second wiring layer 140 is made of a metal material such as aluminum or copper, and a barrier metal such as Ti, Ta, TiN, or TaN may be provided at the interface between the second wiring layer 240 and the second insulating layer 230 to suppress diffusion of metal into the second insulating layer 230. A test point TSP electrically connected to the second wiring layer 240 is provided in the second insulating layer 230, and a part of the second insulating layer 230 is removed so that the test point TSP is exposed.

[0050] 4(b), the probe PR of a tester is inserted into the hole where the test point TSP is exposed, and brought into contact with the test point TSP to perform an electrical performance evaluation of the second chip 200. Through the electrical performance evaluation, the second chip 200 which is a non-defective product is selected and used for bonding with the first chip 100. When multiple second chips 200 are formed on the same wafer, the electrical performance evaluation is performed on each chip on the wafer, and later, when each chip is cut, the second chip 200 which is a non-defective product can be selected and used.

[0051] 4(c), a third insulating layer 235 is provided on the exposed test points TSP and the second insulating layer 230. By covering the test points TSP that are in contact with the probes PR with the third insulating layer 235, it is possible to prevent corrosion of the second wiring layer 240 in a later process and to prevent small pieces generated by contact with the probes PR from becoming foreign matter and becoming a source of contamination.

[0052] As with the second insulating layer 230, silicon oxide, silicon nitride, or the like can be used for the third insulating layer 235. It is preferable to use the same type of insulating material as the first insulating layer 130 provided on the outermost surface of the first chip 100 for the third insulating layer 235 of the second chip 200, since this makes it possible to easily bond the first insulating layer 130 and the third insulating layer 235 directly. For example, when silicon oxide is used for the first insulating layer 130, it is preferable to use silicon oxide of the same composition for the third insulating layer 235.

[0053] A second connection electrode 250 is provided inside the third insulating layer 235. The semiconductor element 220, the second wiring layer 240, and the second connection electrode 250 are electrically connected to configure an electronic circuit. A dummy pattern that is not electrically connected to the circuit may be formed in the same layer as the second connection electrode 250 and used as an anchor to increase the bonding strength when bonding the first chip 100 and the second chip 200.

[0054] 4(d), third insulating layer 235 is polished by CMP to expose second connection electrode 250, completing second chip 200. At this time, by polishing so that the step between second connection electrode 250 and third insulating layer 235 is as flat as possible, the yield when bonding first chip 100 and second chip 200 can be improved.

[0055] In addition, in Figure 4(d), the insulating layer added later is shown as the third insulating layer 235 and distinguished from the second insulating layer 230, but in Figure 2(b) referred to above, both insulating layers are shown collectively as the second insulating layer 230.

[0056] (Electronic device and electronic component manufacturing methods) A method for manufacturing an electronic device 800 by bonding a first chip 100 selected as a good chip to a second chip 200 formed on a wafer, and a method for manufacturing an electronic component 900 by mounting the electronic device 800 on a circuit board 600 will be described in order.

[0057] First, the first chip 100 selected as a non-defective product in the process of Fig. 3(e) is bonded to the second carrier substrate 400 via the second temporary adhesive layer 410. That is, as shown in Fig. 5(a), the second carrier substrate 400 is bonded to the surface of the first chip 100 opposite to the surface to which the first carrier substrate 300 is bonded via the second temporary adhesive layer 410. As the second temporary adhesive layer 410, a thermal peeling type adhesive whose adhesive strength decreases when heated is used, but when a light-transmitting substrate is used as the second carrier substrate 400, a UV peeling type adhesive whose adhesive strength decreases when irradiated with ultraviolet light may be used.

[0058] Next, as shown in FIG. 5(b), heat or ultraviolet light is applied to the first carrier substrate 300 to eliminate the adhesive force of the first temporary bonding layer 310, and the first carrier substrate 300 is peeled off from the first chip 100 to expose the first insulating layer 130. When a thermal peeling adhesive is used for both the first temporary bonding layer 310 and the second temporary bonding layer 410, a thermal peeling adhesive whose adhesive force decreases at a higher temperature than that of the first temporary bonding layer 310 is used as the second temporary bonding layer 410. By doing so, in the step of thermally peeling off the first carrier substrate 300 shown in FIG. 5(b), the adhesive force of the second temporary bonding layer is suppressed from decreasing, and the first chip 100 is prevented from peeling off from the second carrier substrate 400.

[0059] Next, as shown in FIG. 5(c), the first insulating layer 130 is polished by CMP to expose the first connection electrode 150. In this way, after the first carrier substrate 300 is peeled off from the first chip 100, the first insulating layer 130 is polished to expose the first connection electrode 150, and the residue of the first temporary bonding layer 310 is removed from the surface of the first connection electrode 150 and the first insulating layer 130. Therefore, in the subsequent step of bonding the first chip 100 and the second chip 200, a decrease in yield due to the residue of the temporary bonding layer 310 can be suppressed. In addition, in the above polishing, by polishing so that the step between the first connection electrode 150 and the first insulating layer 130 is as small as possible, the yield of the step of bonding the first chip 100 and the second chip 200 can be improved.

[0060] Next, as shown in Fig. 5(d), a step of bonding the first chip 100 and the second chip 200 is carried out. Here, an example of a direct bonding method is shown, but bonding may also be performed using bumps such as solder bumps or microbumps. In that case, after the step of Fig. 5(c), a bump member (not shown) may be separately formed on the surface of either the first connection electrode 150 or the second connection electrode 250, and then the bump member may be melted to bond them.

[0061] When directly bonding the first chip 100 and the second chip 200 formed on a wafer, first, the outermost surface of the first chip 100 is washed by two-fluid washing using pure water or spin washing to remove foreign matter attached to the surface. Next, the adhesive force of the second temporary adhesive layer 410 is lost and the first chip 100 is peeled off from the second carrier substrate 400. At that time, heat or ultraviolet light is applied depending on the type of the second temporary adhesive layer 410. After that, plasma is irradiated to the main surface of the first chip 100 on the side where the first connection electrode 150 is exposed, and the surface is activated.

[0062] Similarly, the outermost surface of the second chip 200 formed on the wafer is washed by two-fluid washing using pure water or spin washing to remove foreign matter adhering to the surface. Then, the main surface of the second chip 100 on the side where the second connection electrode 250 is exposed is irradiated with plasma to activate the surface.

[0063] After cleaning and activating the surfaces of both chips, the main surface of the first chip 100 (the main surface on the side where the first connection electrode 150 is located) and the main surface of the second chip 200 (the main surface on the side where the second connection electrode 250 is located) are quickly made to face each other, and the first connection electrode 150 and the second connection electrode 250 are aligned. Then, a load is applied from the surface BS1 while the first connection electrode 150 and the second connection electrode 250, and the first insulating layer 130 and the third insulating layer 235 are in contact with each other. As a result, the first insulating layer 130 and the third insulating layer 235 are pressure-bonded at room temperature. After that, a load is applied from the surface BS1 side for a predetermined time while heating to about 250°C to 400°C. As a result, the first connection electrode 150 and the second connection electrode 250 are bonded by thermal diffusion, and direct bonding (thermocompression bonding) is completed.

[0064] In the above-mentioned direct bonding process, the first chip 100 determined to be a non-defective product is aligned and bonded to the second chip 200 determined to be a non-defective product among the second chips formed on the wafer. As a result, as shown in Fig. 7, a plurality of electronic devices 800, each having a non-defective first chip 100 mounted on a non-defective second chip 200, are formed on the wafer 200W.

[0065] In the above example, the diced first chip 100 is peeled off from the second carrier substrate 400, and then the first chip 100 and the second chip 200 are bonded to each other, but the bonding procedure is not limited to this. The diced first chip 100 may be aligned and bonded to the second chip 200 while the second carrier substrate 400 is still attached, and then the second carrier substrate 400 may be peeled off. In this case, the first insulating layer 130 and the third insulating layer 235 are bonded at room temperature, and then the adhesive force of the second temporary adhesive layer 410 is eliminated by applying heat or ultraviolet light, and the second carrier substrate 400 is peeled off. Then, a load is applied from the surface BS1 side of the first substrate 110 for a predetermined time while applying heat of about 250°C to 400°C, and the first connection electrode 150 and the second connection electrode 250 may be bonded to each other.

[0066] In particular, when the first chip 100 is thinned to a thickness of 200 μm or less, the ends of the first chip 100 may be damaged when the first chip 100 is transported to a predetermined position on the second chip 200. By transporting the first chip 100 with the second carrier substrate 400 attached, the possibility of damage can be reduced.

[0067] Although not shown, if the first chip 100 is a back-illuminated image sensor, a color filter and a microlens are formed on the back surface (surface BS1) of the first chip 100 after the step of Fig. 5(d). As shown in Fig. 7, if the first chips 100 are arranged with gaps on a wafer on which the second chips 200 are arranged in a matrix, the steps between the first chips 100 may affect the processing of the color filters and the microlenses. In such a case, it is preferable to fill the gaps between the first chips 100 with resin or silicon oxide to make them flat before forming the color filters and the microlenses.

[0068] 6(a), a probe PR of a tester is brought into contact with a test terminal TP exposed through a through hole TH penetrating the first substrate 110, and the electrical characteristics of the electronic device 800 are evaluated. That is, the quality of each of the multiple electronic devices 800 formed on the wafer 200W shown in FIG. 7 is determined. The wafer 200W is cut by dicing or scribing, and good electronic devices 800 can be taken out as individual pieces.

[0069] Then, as shown in Fig. 6(b), a non-defective electronic device 800 is placed on and electrically connected to a circuit board 600. Fig. 6(b) shows an example in which the portion used as the test terminal TP in the process of Fig. 6(a) is also used as the external connection terminal CP of the first wiring layer 140, and the external connection terminal CP is electrically connected to the electrode 610 of the circuit board 600 by the connection member 500. In this manner, the electronic component 900 according to the embodiment is completed.

[0070] [Embodiment 2] An electronic device (semiconductor device) and electronic components according to embodiment 2 will be described with reference to the drawings, but descriptions of matters common to embodiment 1 will be simplified or omitted. Fig. 8(a) shows a schematic cross-sectional view of an electronic device 800 according to embodiment 2 cut in a direction perpendicular to the main surface.

[0071] In the first embodiment, the semiconductor element 120, the first insulating layer 130, the first wiring layer 140, the test terminal TP, and the first connection electrode 150 are provided on the main surface MS1 of the substrate 110 of the first chip 100. Then, a through hole is provided penetrating the first substrate 110, and the through hole is further extended into the first insulating layer 130 to expose the test terminal TP. Then, the configuration was such that a probe of a tester can access (make contact with) the test terminal TP from outside through the through hole.

[0072] 8(a), the second embodiment is common to the first embodiment in that a semiconductor element 120, a first insulating layer 130, a first wiring layer 140, and a first connection electrode 150 are provided on a main surface MS1 of a substrate 110 of a first chip 100. However, unlike the first embodiment in which a test terminal TP is provided by exposing a point to be tested in the same layer as the first wiring layer 140, a test terminal OTP is provided on the outer surface of the substrate 110 opposite to the main surface MS1. If a point to be electrically tested in the first wiring layer 140 is a point TX, the test terminal OTP is electrically connected to the point TX through a via VIA.

[0073] An insulating layer INS, such as silicon oxide, is provided between the test terminal OTP and the first substrate 110. As with the first wiring layer 140, aluminum or copper is used as the material for the test terminal OTP, but a barrier metal such as Ti, Ta, TiN, or TaN may be provided at the interface between the test terminal OTP and the insulating layer INS.

[0074] To manufacture such a structure, for example, after performing the same steps as those shown in Figs. 3(a) to 3(d) described in the first embodiment, an insulating film such as silicon oxide is formed on the side of the through hole TH and the outer surface of the first substrate 110 (the main surface opposite to the main surface MS1). Then, the side of the through hole TH is covered with a conductive material by a method such as sputtering or plating to form a via VIA. The test terminal OTP on the outer surface of the first substrate 110 and the point PX are electrically connected by the via VIA. In some cases, the inside of the formed via VIA may be filled with an insulating material (not shown) such as resin to suppress deterioration of the first semiconductor element 120 due to the intrusion of moisture or chemical substances.

[0075] In the electronic device 800 according to this embodiment, as shown in FIG. 1(a), the projected area of ​​the first chip 100 provided with the test terminal OTP can be made smaller than the projected area of ​​the second chip 200 in a plan view, and the cost of the substrate can be reduced. Moreover, the first chip 100 is included in the second chip 200 in a plan view, and both chips are laid out so that the first chip 100 does not protrude from the outer edge of the second chip 200. In the electronic device 800 according to this embodiment, the test terminal OTP provided on the surface opposite to the main surface MS1 (the main surface on the side where the semiconductor element 120 is provided) of the first substrate 110 can be easily accessed. Thus, according to this embodiment, when the first chip 100 provided with the test terminal and the second chip 200 are integrated by being laid out in a direction in which the semiconductor elements face each other, the electronic device 800 can be made small.

[0076] Furthermore, according to this embodiment, the test terminal OTP is extended to the outer surface of the first substrate 110, so that the tester probe can easily contact the terminal when evaluating electrical characteristics, and damage to the first insulating layer 130 can be suppressed compared to embodiment 1.

[0077] Then, as shown in Fig. 8(b), a non-defective electronic device 800 is placed on and electrically connected to the circuit board 600. Fig. 8(b) shows an example in which the portion used as the test terminal OTP during the electrical characteristic evaluation is also used as the external connection terminal CP, and the external connection terminal CP is electrically connected to the electrode of the circuit board 600 by the connection member 500. In this manner, the electronic component 900 according to this embodiment is completed.

[0078] [Embodiment 3] As a third embodiment, a system including an electronic device in which the first chip 100 is an image sensor and the second chip 200 is a chip including at least one of a memory circuit and a logic circuit will be described. Fig. 9(a) is a schematic diagram for explaining an apparatus 9191 including a semiconductor device 930 including the electronic device according to the above-mentioned embodiment. The apparatus 9191 including the semiconductor device 930 will be described in detail.

[0079] The semiconductor device 930 includes a semiconductor device 910 in which a first chip as a photoelectric conversion device and a second chip including at least one of a memory circuit and a logic circuit are integrated. The semiconductor device 930 can include a package 920 that houses the semiconductor device 910 in addition to the semiconductor device 910. The package 920 can include a base to which the semiconductor device 910 is fixed, and a lid such as glass that faces the semiconductor device 910. The package 920 can further include a bonding member such as a bonding wire or a bump that connects a terminal provided on the base and a terminal provided on the semiconductor device 910.

[0080] The device 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 is, for example, a lens, a shutter, or a mirror provided in correspondence with the semiconductor device 930. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0081] The processing device 960 processes the signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0082] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) included in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit included in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0083] The device 9191 is also suitable for electronic devices such as information terminals (e.g., smartphones and wearable devices) with a photographing function and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operation.

[0084] The device 9191 may be a transport device such as a vehicle, a ship, or an aircraft. The mechanical device 990 in the transport device may be used as a moving device. The device 9191 as a transport device is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) by using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0085] According to the above-described embodiment, a good chip whose characteristics have been inspected using a test terminal is used, so that it is possible to obtain an image with good characteristics, and furthermore, the device can be made smaller and lighter.

[0086] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment can be improved. For example, by mounting the semiconductor device 930 on a transport equipment, excellent performance can be obtained when photographing the outside of the transport equipment and measuring the external environment. Therefore, in manufacturing and selling the transport equipment, it is advantageous to decide to mount the semiconductor device according to this embodiment on the transport equipment in order to improve the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that uses information obtained by the semiconductor device to perform driving assistance and / or automatic driving of the transport equipment. Note that the implementation in vehicles, ships, aircraft, etc. is not limited to application to equipment used for transportation purposes, and can also be suitably implemented in drones and the like that perform aerial photography for various purposes including inspection of buildings and agricultural facilities and monitoring of natural phenomena. Moreover, the photoelectric conversion system and the moving object of this embodiment will be described with reference to FIG. 9(b) and FIG. 9(c).

[0087] FIG. 9(b) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 8 has a photoelectric conversion device 80. The photoelectric conversion device 80 is a photoelectric conversion device as an electronic device described in the above embodiment. The photoelectric conversion system 8 has an image processing unit 801 that performs image processing on a plurality of image data acquired by the photoelectric conversion device 80, and a parallax acquisition unit 802 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the photoelectric conversion system 8. The photoelectric conversion system 8 also has a distance acquisition unit 803 that calculates a distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire distance information to an object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 804 may determine the possibility of a collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware or a software module, or may be realized by a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or the like.

[0088] The photoelectric conversion system 8 is connected to a vehicle information acquisition device 810, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 8 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 804. The photoelectric conversion system 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the judgment result of the collision judgment unit 804. For example, when the judgment result of the collision judgment unit 804 indicates that there is a high possibility of a collision, the control ECU 820 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., and vibrating the seat belt or steering wheel.

[0089] In this embodiment, the surroundings of the vehicle, for example the front or rear, are imaged by the photoelectric conversion system 8. Fig. 9(c) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 850). A vehicle information acquisition device 810 sends an instruction to the photoelectric conversion system 8 or the photoelectric conversion device 80. This configuration can further improve the accuracy of distance measurement.

[0090] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from lanes, and the like. Furthermore, the photoelectric conversion system can be applied not only to vehicles such as the vehicle itself, but also to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies, but also to devices that widely use object recognition, such as intelligent transport systems (ITS). According to the above-mentioned embodiment, a good chip whose characteristics have been inspected using a test terminal is used, so that good images can be obtained, and the device can be made small and lightweight, making it suitable for mounting on a moving body.

[0091] [Other embodiments] The present invention is not limited to the above-described embodiment, and many modifications are possible within the technical spirit of the present invention. For example, the above-described different embodiments may be combined in whole or in part.

[0092] For example, in the above-described embodiment, one first chip with a small projected area is placed so as to be enclosed in a second chip with a large projected area in a plan view, but the number of chips placed on the second chip does not have to be one as long as it is enclosed in the second chip in a plan view. As long as each chip placed on the second chip has a terminal exposed on the opposite side of the second chip that is electrically connected to the first wiring layer, the same effect as the above-described embodiment can be achieved.

[0093] The photoelectric conversion device to which the present invention is applied is not limited to a specific form, and for example, the light receiving section may be either a front-illuminated type or a back-illuminated type. The image signal output from the photoelectric conversion device may be an analog signal or a digital signal. Furthermore, the use of the photoelectric conversion device according to the embodiment is not limited to imaging, and may also be applied to, for example, a distance measuring device (a device for measuring distance using focus detection or TOF (Time Of Flight)), a photometric device (a device for measuring the amount of incident light, etc.), etc.

[0094] This specification discloses at least the following: [Item 1] a first chip including a first semiconductor element, a first insulating layer, a first wiring layer, and a first connection electrode that is a different layer from the first wiring layer, the first chip being provided on a first main surface of a first substrate; a second chip including a second semiconductor element, a second insulating layer, a second wiring layer, and a second connection electrode that is a different layer from the second wiring layer, the second chip being provided on a second main surface of a second substrate; the first chip and the second chip are fixed together such that the first main surface and the second main surface face each other with the first insulating layer, the first wiring layer, the first connection electrode, the second insulating layer, the second wiring layer, and the second connection electrode sandwiched therebetween, and the first connection electrode and the second connection electrode are electrically connected; the first chip is electrically connected to the first wiring layer and has a terminal exposed on an opposite side to the second chip; 1. An electronic device comprising: [Matter 2] the terminal is provided in the same layer as the first wiring layer, and is exposed on the opposite side of the second chip through a through hole penetrating the first substrate and a part of the first insulating layer; 2. The electronic device according to item 1, [Matter 3] the terminal is provided on a main surface of the first substrate opposite to the first main surface, and is electrically connected to the first wiring layer via a conductive material provided in a through hole penetrating the first substrate and a portion of the first insulating layer. 2. The electronic device according to item 1, [Matter 4] The first insulating layer and the second insulating layer are bonded together. 4. The electronic device according to any one of claims 1 to 3. [Matter 5] The first insulating layer and the second insulating layer are made of the same type of insulating material. 5. The electronic device according to any one of claims 1 to 4. [Matter 6] The first connection electrode and the second connection electrode are joined together. 6. An electronic device according to any one of claims 1 to 5. [Matter 7] When the electronic device is viewed in a plan view from a direction perpendicular to the first main surface, a projected area of ​​the first chip is smaller than a projected area of ​​the second chip, and the first chip is included in the second chip. 7. The electronic device according to any one of claims 1 to 6. [Matter 8] The first chip is a chip having an image sensor, and the second chip is a chip having at least one of a memory circuit and a logic circuit. 8. An electronic device according to any one of claims 1 to 7. [Matter 9] The image sensor is a back-illuminated image sensor, and at least one of a color filter and a microlens is provided on a main surface of the first substrate opposite to the first main surface. 9. The electronic device according to item 8, [Matter 10] An electronic device according to any one of claims 1 to 9, a circuit board on which the electronic device is mounted, The terminal and the circuit board are electrically connected. An electronic component characterized by: [Matter 11] a first chip preparation process for preparing a first chip in which a first semiconductor element, a first insulating layer, a first wiring layer, and a first connection electrode that is a different layer from the first wiring layer are provided on a first main surface of a first substrate, and a terminal electrically connected to the first wiring layer is exposed on the side opposite to the first main surface; a second chip preparation process for preparing a second chip including a second semiconductor element, a second insulating layer, a second wiring layer, and a second connection electrode that is a different layer from the second wiring layer, on a second main surface of a second substrate; a fixing process of fixing the first chip and the second chip such that the first main surface and the second main surface face each other with the first insulating layer, the first wiring layer, the first connection electrode, the second insulating layer, the second wiring layer, and the second connection electrode sandwiched therebetween, and the first connection electrode and the second connection electrode are electrically connected; A method for manufacturing an electronic device comprising: [Matter 12] In the first tip preparation step, After forming the first semiconductor element, the first insulating layer, the first wiring layer, and the first connection electrode on the first main surface of the first substrate, forming a through hole penetrating the first substrate and a portion of the first insulating layer and extending to a portion of the first wiring layer, and exposing a portion of the first wiring layer to form the terminal; 12. The method for producing an electronic device according to item 11. [Matter 13] In the first tip preparation step, After forming the first semiconductor element, the first insulating layer, the first wiring layer, and the first connection electrode on the first main surface of the first substrate, forming a through hole penetrating a portion of the first substrate and the first insulating layer and extending to a portion of the first wiring layer, providing a conductive material along the through hole, and providing the terminal electrically connected to the conductive material on a main surface of the first substrate opposite to the first main surface; 12. The method for producing an electronic device according to item 11. [Matter 14] In the fixing step, the first connection electrode and the second connection electrode are joined by thermocompression bonding. 14. The method for producing an electronic device according to any one of items 11 to 13, [Matter 15] In the fixing step, the first insulating layer and the second insulating layer are pressure-bonded at room temperature. 15. The method for producing an electronic device according to any one of items 11 to 14, [Matter 16] In the first tip preparation step, contacting the terminals with a probe of a tester to test electrical characteristics of the first chip; 16. The method for producing an electronic device according to any one of items 11 to 15, [Matter 17] the first chip determined to be a non-defective product by the test is fixed to the second chip in the fixing step; 17. The method for producing an electronic device according to item 16, [Matter 18] In the second chip preparation step, A plurality of the second chips are provided on the same wafer. 18. A method for producing an electronic device according to any one of items 11 to 17, [Matter 19] In the second chip preparation step, testing electrical characteristics of the second chips provided on the same wafer; the second chip determined to be a non-defective product by the test is fixed to the first chip in the fixing step; 20. The method for producing an electronic device according to item 18, [Matter 20] After the fixing step, a probe of a tester is brought into contact with the terminal to test electrical characteristics of the electronic device. 20. A method for producing an electronic device according to any one of items 11 to 19, [Matter 21] An electronic device is manufactured by the method for manufacturing an electronic device according to any one of items 11 to 20, Mounting the electronic device on a circuit board; The terminal and the circuit board are electrically connected. A method for manufacturing an electronic component comprising the steps of: [Explanation of symbols]

[0095] 100···first chip / 110···first substrate / 120···semiconductor element / 130···first insulating layer / 140···first wiring layer / 150···first connection electrode / 200···second chip / 200W···wafer / 210···second substrate / 220···semiconductor element / 230···second insulating layer / 235···third insulating layer / 240···second wiring layer / 250···second connection electrode / 300···first carrier substrate / 310· ··First temporary bonding layer / 400···Second carrier substrate / 410···Second temporary adhesive layer / 500···Connection material / 600···Circuit board / 800···Electronic device / 900···Electronic component / BP···External connection terminal / CP···External connection terminal / MS1···Main surface / MS2···Main surface / PR···Probe / TH1···Through hole / TH2···Through hole / TM···Terminal / TP···Test terminal / TSP···Test point

Claims

1. a first chip including a first semiconductor element, a first insulating layer, a first wiring layer, and a first connection electrode that is a different layer from the first wiring layer, the first chip being provided on a first main surface of a first substrate; a second chip including a second semiconductor element, a second insulating layer, a second wiring layer, and a second connection electrode that is a different layer from the second wiring layer, the second chip being provided on a second main surface of a second substrate; the first chip and the second chip are fixed together such that the first main surface and the second main surface face each other with the first insulating layer, the first wiring layer, the first connection electrode, the second insulating layer, the second wiring layer, and the second connection electrode sandwiched therebetween, and the first connection electrode and the second connection electrode are electrically connected; the first chip is electrically connected to the first wiring layer and has a terminal exposed on an opposite side to the second chip; 1. An electronic device comprising:

2. the terminal is provided in the same layer as the first wiring layer, and is exposed on the opposite side of the second chip through a through hole penetrating the first substrate and a part of the first insulating layer; 2. The electronic device according to claim 1 .

3. the terminal is provided on a main surface of the first substrate opposite to the first main surface, and is electrically connected to the first wiring layer via a conductive material provided in a through hole penetrating the first substrate and a portion of the first insulating layer; 2. The electronic device according to claim 1 .

4. The first insulating layer and the second insulating layer are bonded to each other.

4. An electronic device according to claim 1, wherein the first and second electrodes are electrically connected to the first and second electrodes.

5. The first insulating layer and the second insulating layer are made of the same type of insulating material.

4. An electronic device according to claim 1, wherein the first and second electrodes are electrically connected to the first and second electrodes.

6. The first connection electrode and the second connection electrode are joined together.

4. An electronic device according to claim 1, wherein the first and second electrodes are electrically connected to the first and second electrodes.

7. When the electronic device is viewed in a plan view from a direction perpendicular to the first main surface, a projected area of ​​the first chip is smaller than a projected area of ​​the second chip, and the first chip is included in the second chip.

4. An electronic device according to claim 1, wherein the first and second electrodes are electrically connected to the first and second electrodes.

8. the first chip is a chip having an image sensor, and the second chip is a chip having at least one of a memory circuit and a logic circuit; 4. An electronic device according to claim 1, wherein the first and second electrodes are electrically connected to the first and second electrodes.

9. the image sensor is a back-illuminated image sensor, and at least one of a color filter and a microlens is provided on a main surface of the first substrate opposite to the first main surface; 9. The electronic device according to claim 8.

10. An electronic device according to any one of claims 1 to 3; a circuit board on which the electronic device is mounted, The terminal and the circuit board are electrically connected. An electronic component characterized by:

11. a first chip preparation process for preparing a first chip in which a first semiconductor element, a first insulating layer, a first wiring layer, and a first connection electrode in a different layer from the first wiring layer are provided on a first main surface of a first substrate, and a terminal electrically connected to the first wiring layer is exposed on the side opposite to the first main surface; a second chip preparation process for preparing a second chip provided with a second semiconductor element, a second insulating layer, a second wiring layer, and a second connection electrode that is a different layer from the second wiring layer on a second main surface of a second substrate; a fixing step of fixing the first chip and the second chip such that the first main surface and the second main surface face each other with the first insulating layer, the first wiring layer, the first connection electrode, the second insulating layer, the second wiring layer, and the second connection electrode sandwiched therebetween, and the first connection electrode and the second connection electrode are electrically connected; A method for manufacturing an electronic device comprising:

12. In the first tip preparation step, After forming the first semiconductor element, the first insulating layer, the first wiring layer, and the first connection electrode on the first main surface of the first substrate, forming a through hole penetrating a portion of the first substrate and the first insulating layer and extending to a portion of the first wiring layer, and exposing a portion of the first wiring layer to form the terminal; The method for manufacturing an electronic device according to claim 11 .

13. In the first tip preparation step, After forming the first semiconductor element, the first insulating layer, the first wiring layer, and the first connection electrode on the first main surface of the first substrate, forming a through hole penetrating a portion of the first substrate and the first insulating layer and extending to a portion of the first wiring layer, providing a conductive material along the through hole, and providing the terminal electrically connected to the conductive material on a main surface of the first substrate opposite to the first main surface; The method for manufacturing an electronic device according to claim 11 .

14. In the fixing step, the first connection electrode and the second connection electrode are joined by thermocompression bonding. The method for manufacturing an electronic device according to any one of claims 11 to 13.

15. In the fixing step, the first insulating layer and the second insulating layer are pressure-bonded to each other at room temperature. The method for manufacturing an electronic device according to any one of claims 11 to 13.

16. In the first tip preparation step, contacting the terminals with probes of a tester to test electrical characteristics of the first chip; The method for manufacturing an electronic device according to any one of claims 11 to 13.

17. the first chip determined to be a non-defective product by the test is fixed to the second chip in the fixing step; 17. The method for producing an electronic device according to claim 16.

18. In the second tip preparation step, A plurality of the second chips are provided on the same wafer. The method for manufacturing an electronic device according to any one of claims 11 to 13.

19. In the second tip preparation step, testing electrical characteristics of the second chips provided on the same wafer; the second chip determined to be a non-defective product by the test is fixed to the first chip in the fixing step; 20. The method for producing an electronic device according to claim 18.

20. After the fixing step, a probe of a tester is brought into contact with the terminal to test electrical characteristics of the electronic device. The method for manufacturing an electronic device according to any one of claims 11 to 13.

21. An electronic device is manufactured by the method for manufacturing an electronic device according to any one of claims 11 to 13, Mounting the electronic device on a circuit board; The terminal and the circuit board are electrically connected. A method for manufacturing an electronic component comprising the steps of:

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