Semiconductor device and printing device

Abstract

To provide a semiconductor device capable of reducing the risk of erroneous data being transferred between two connected external memories.SOLUTION: A semiconductor device includes: a first controller; a second controller; and a data buffer in which data of a first memory is stored by the first controller and data of a second memory is stored by the second controller. The first controller has a DMA master that executes data transfer between the first memory and the data buffer by DMA. The second controller has a clock controller that outputs a clock pulse that specifies data transfer timing between the second memory and the data buffer. The clock controller stops outputting the clock pulse when at least the number of data of the data buffer satisfies a predetermined condition.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a printing device. [Background technology]

[0002] Patent Document 1 describes a memory module that includes a NAND flash memory, an SDRAM, and a control circuit with a built-in data buffer that temporarily holds data transferred between the NAND flash memory and the SDRAM. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2011-192299 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the memory module described in Patent Document 1, when multiple circuits including a control circuit access the SDRAM, data transfer between the control circuit and the SDRAM may be delayed, which may cause data to be written to the SDRAM to be lost due to overflowing data in the data buffer, or data read from the SDRAM may not be transferred to the data buffer, causing the data buffer to become empty, resulting in the transfer of erroneous data to the SDRAM or NAND flash memory. [Means for solving the problem]

[0005] One aspect of the semiconductor device according to the present invention is a first controller capable of communicating with the first memory; a second controller capable of communicating with the second memory; a data buffer in which the data of the first memory is stored by the first controller and the data of the second memory is stored by the second controller; The first controller is a DMA master for performing data transfer between the first memory and the data buffer by DMA; The second controller is a clock controller that outputs a clock pulse that defines a timing of data transfer between the second memory and the data buffer; The clock controller includes: When at least the number of data in the data buffer satisfies a predetermined condition, the output of the clock pulse is stopped.

[0006] One aspect of the printing device according to the present invention is to One aspect of the semiconductor device; A printing unit that prints on a medium, The semiconductor device includes: The printer further includes a print control circuit that outputs a control signal for the printing unit. [Brief description of the drawings]

[0007] [Figure 1] FIG. 2 is a diagram illustrating a functional configuration of the semiconductor device according to the present embodiment. [Diagram 2] FIG. 1 is a diagram illustrating a configuration of a specific example of a semiconductor device. [Diagram 3] FIG. 2 is a diagram illustrating a detailed configuration example of a DMA controller, an SPI master, and a data buffer. [Figure 4] FIG. 11 is a diagram illustrating an example of a timing chart when data transfer from the serial NAND flash memory to the shift register is interrupted. [Diagram 5] FIG. 11 is a diagram illustrating an example of a timing chart when data transfer from the double buffer to the serial NAND flash memory is interrupted. [Figure 6]FIG. 11 is a flowchart showing an example of a processing procedure by a DMA controller in data transfer from a DRAM to a serial NAND flash memory. [Figure 7] FIG. 11 is a flowchart showing an example of a processing procedure by an SPI master in data transfer from a DRAM to a serial NAND flash memory. [Figure 8] FIG. 11 is a flowchart showing an example of a processing procedure by a DMA controller in transferring data from a serial NAND flash memory to a DRAM. [Figure 9] FIG. 11 is a flowchart showing an example of a processing procedure by an SPI master in data transfer from a serial NAND flash memory to a DRAM. [Figure 10] 1 is an external perspective view of a printing apparatus according to an embodiment of the present invention. [Figure 11] FIG. 2 is a diagram illustrating a functional configuration of a printing apparatus according to the present embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Preferred embodiments of the present invention will be described below with reference to the drawings. The drawings are used for the convenience of explanation. Note that the embodiments described below do not unduly limit the contents of the present invention described in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0009] 1. Semiconductor Devices 1-1. Functional configuration of semiconductor device Fig. 1 is a diagram showing the functional configuration of a semiconductor device 1A according to the present embodiment. As shown in Fig. 1, the semiconductor device 1A includes a first controller 2A, a second controller 3A, a data buffer 4A, and a processor 5A.

[0010] The first controller 2A can communicate with the first memory 100A. The second controller 3A can communicate with the second memory 200A. The data buffer 4A stores data of the first memory 100A by the first controller 2A, and stores data of the second memory 200A by the second controller 3A. The data buffer 4A may include a first buffer 41A and a second buffer 42A.

[0011] The processor 5A instructs the first controller 2A to read data from the first memory 100A or write data to the first memory 100A. The processor 5A also instructs the second controller 3A to read data from the second memory 200A or write data to the second memory 200A. The processor 5A outputs to the second controller 3A designation information that designates the number of data for each data transfer between the second controller 3A and the second memory 200A.

[0012] The first controller 2A controls data transfer between the first memory 100A and the data buffer 4A. The first controller 2A controls data transfer between the first memory 100A and the first buffer 41A, and may also control data transfer between the first buffer 41A and the second buffer 42A. The first controller 2A has a DMA master 21A. The DMA master 21A performs data transfer between the first memory 100A and the data buffer 4A by DMA. DMA is an abbreviation for Direct Memory Access.

[0013] The second controller 3A controls data transfer between the second memory 200A and the data buffer 4A. The second controller 3A controls data transfer between the second memory 200A and the second buffer 42A, and may also control data transfer between the second buffer 42A and the first buffer 41A.

[0014] The second controller 3A has a clock controller 31A. The clock controller 31A outputs a clock pulse that defines the timing of data transfer between the second memory 200A and the data buffer 4A. The clock controller 31A stops outputting the clock pulse when at least the number of data in the data buffer 4A satisfies a predetermined condition. The clock controller 31A may stop outputting the clock pulse when at least the number of data in the first buffer 41A satisfies a first condition and the number of data in the second buffer 42A satisfies a second condition.

[0015] The clock controller 31A stops outputting the clock pulses when the number of data in the data buffer 4A becomes equal to or greater than a predetermined number of data, as a predetermined condition, after the processor 5A instructs the second controller 3A to read data. The clock controller 31A may stop outputting the clock pulses when the number of data in the first buffer 41A becomes equal to or greater than a first number of data and the number of data in the second buffer 42A becomes equal to or greater than a second number of data, as a predetermined condition, after the processor 5A instructs the second controller 3A to read data. Furthermore, after stopping outputting the clock pulses, the clock controller 31A resumes outputting the clock pulses when the number of data in the data buffer 4A becomes smaller than the predetermined number of data as a result of the first controller 2A transferring data from the data buffer 4A to the first memory 100A.

[0016] The clock controller 31A stops outputting the clock pulses when the number of data in the data buffer 4A becomes equal to or less than a predetermined number of data as a predetermined condition after the processor 5A instructs the second controller 3A to write data. The clock controller 31A may stop outputting the clock pulses when the number of data in the first buffer 41A becomes equal to or less than a third number of data and the number of data in the second buffer 42A becomes equal to or less than a fourth number of data as a predetermined condition after the processor 5A instructs the second controller 3A to write data. Furthermore, the clock controller 31A resumes outputting the clock pulses after stopping outputting the clock pulses when the number of data in the data buffer 4A becomes greater than the predetermined number of data as a result of the first controller 2A transferring data from the first memory 100A to the data buffer 4A.

[0017] Even if the number of data in the data buffer 4A satisfies a specified condition, the clock controller 31A does not have to stop outputting clock pulses when the data transferred from the second memory 200A to the data buffer 4A or the data to be transferred from the data buffer 4A to the second memory 200A is the last data based on the number of data specified in the designation information.

[0018] A specific configuration example of the semiconductor device 1A of this embodiment will be described in detail below.

[0019] 1-2. Specific configuration examples of semiconductor device Fig. 2 is a diagram showing a configuration of a semiconductor device 1 as a specific example of the semiconductor device 1A. The semiconductor device 1 is an SoC having a function as a system, and is realized as a one-chip IC. SoC is an abbreviation for System on Chip, and IC is an abbreviation for Integrated Circuit. As shown in Fig. 2, the semiconductor device 1 is connected to a DRAM 100 and a serial NAND flash memory 200. DRAM is an abbreviation for Dynamic Random Access Memory.

[0020] The DRAM 100 is a volatile memory that allows high speed random access and functions as a main storage device. The DRAM 100 may be an SDRAM. SDRAM is an abbreviation for Synchronous Dynamic Random Access Memory.

[0021] The serial NAND flash memory 200 is a NAND type flash memory that can be controlled by SPI, and functions as an auxiliary storage device. SPI is an abbreviation for Serial Peripheral Interface. Compared to NOR type flash memory, NAND type flash memory has faster data writing speed and is suitable for high integration and large capacity. The serial NAND flash memory 200 can input and output data in page units, with 2 kilobytes or 4 kilobytes of memory as one page.

[0022] 2, the semiconductor device 1 includes a CPU 5, a data transfer circuit 10, a clock signal generation circuit 11, n functional circuits 12-1 to 12-n, a DRAM controller 13, and a system bus 14. n is an integer equal to or greater than 1. CPU is an abbreviation for Central Processing Unit.

[0023] The clock signal generating circuit 11 generates a plurality of clock signals (not shown) and supplies each of the plurality of clock signals to the CPU 5, the data transfer circuit 10, the functional circuits 12-1 to 12-n, and the DRAM controller 13. For example, the clock signal generating circuit 11 oscillates a quartz oscillator (not shown) connected to the semiconductor device 1 to generate an oscillation signal, converts the frequency of the oscillation signal to a desired frequency using a PLL circuit, and further divides the frequency to generate a plurality of clock signals. The CPU 5, the data transfer circuit 10, the functional circuits 12-1 to 12-n, and the DRAM controller 13 each operate in synchronization with the supplied clock signal. For example, the clock signal generating circuit 11 generates a clock signal CLK and supplies it to the data transfer circuit 10, and the data transfer circuit 10 operates in synchronization with the clock signal CLK.

[0024] The CPU 5 executes programs stored in the DRAM 100, and performs various processes using the DRAM 100 as a working area.

[0025] The functional circuits 12-1 to 12-n are circuits that perform different processes such as image processing, control processing, etc. Various functions are realized by the functional circuits 12-1 to 12-n.

[0026] The CPU 5, the data transfer circuit 10, the functional circuits 12-1 to 12-n, and the DRAM controller 13 are connected to a system bus .

[0027] The DRAM controller 13 mediates data transfer between the CPU 5, the data transfer circuit 10, and each of the functional circuits 12-1 to 12-n and the DRAM 100 outside the semiconductor device 1. The DRAM controller 13 also mediates data transfer between the CPU 5, the data transfer circuit 10, and each of the functional circuits 12-1 to 12-n and the DRAM 100. That is, when a data transfer request to the DRAM 100 is received from any of the CPU 5, the data transfer circuit 10, and the functional circuits 12-1 to 12-n via the system bus 14, the DRAM controller 13 determines whether to execute the data transfer or put the data transfer on hold. For example, when a data transfer request to the DRAM 100 is received from the data transfer circuit 10 while the functional circuit 12-1 is executing data transfer to the DRAM 100, the DRAM controller 13 executes the data transfer with the higher priority and puts the data transfer with the lower priority on hold.

[0028] The data transfer circuit 10 transfers data from the DRAM 100 to the serial NAND flash memory 200 and Data is transferred from the internal clock 200 to the DRAM 100.

[0029] The data transfer circuit 10 executes data transfer between the DRAM 100 and the serial NAND flash memory 200 by DMA via the DRAM controller 13. In data transfer from the DRAM 100 to the serial NAND flash memory 200, the DRAM controller 13 reads data stored in the DRAM 100 and outputs it to the system bus 14, and the data transfer circuit 10 acquires the data on the system bus 14 and writes it to the serial NAND flash memory 200. In data transfer from the serial NAND flash memory 200 to the DRAM 100, the data transfer circuit 10 reads data stored in the serial NAND flash memory 200 and outputs it to the system bus 14, and the DRAM controller 13 acquires the data on the system bus 14 and writes it to the DRAM 100.

[0030] The data transfer circuit 10 includes a DMA controller 2, an SPI master 3, a data buffer 4, a register 6, a sequencer 7, a command selector 8, and an interrupt controller 9.

[0031] The DMA controller 2 is capable of communicating with the DRAM 100, and controls data transfer between the DRAM 100 and the data buffer 4 by DMA.

[0032] The SPI master 3 can communicate with the serial NAND flash memory 200 and controls data transfer between the serial NAND flash memory 200 and the data buffer 4. The SPI master 3 outputs a chip select signal CSX, a clock signal SCK, and an input data signal SI to the serial NAND flash memory 200 in accordance with the SPI standard, and receives an output data signal SO output from the serial NAND flash memory 200. Specifically, the SPI master 3 transitions the chip select signal CSX from high level to low level to start data communication with the serial NAND flash memory 200. The SPI master 3 outputs the input data signal SI in synchronization with the clock signal SCK, together with the clock signal SCK that specifies the timing of data transfer, in accordance with the SPI standard. The serial NAND flash memory 200 captures each bit of data of the input data signal SI at each edge of the clock signal SCK and performs reading and writing of data. The serial NAND flash memory 200 outputs the read data to the SPI master 3 as an output data signal SO. The SPI master 3 transitions the chip select signal CSX from low level to high level to terminate data communication with the serial NAND flash memory 200 .

[0033] In the data buffer 4, data from the DRAM 100 is stored by the DMA controller 2, and data from the serial NAND flash memory 200 is stored by the SPI master 3.

[0034] The CPU 5 instructs the DMA controller 2 to read data from the DRAM 100 or write data to the DRAM 100. Specifically, the CPU 5 sets data such as the direction of the DMA transfer, the start address, and the amount of data in the register 6. The command selector 8 outputs the data set in the register 6 to the DMA controller 2 as DMA setting data DMASET. Furthermore, when the CPU 5 sets the start bit of the DMA transfer in the register 6 to on, the command selector 8 outputs a DMA start signal to the DMA controller 2. When the start signal is input, the DMA controller 2 executes a data transfer between the DRAM 100 and the CPU 5 by DMA based on the DMA setting data DMASET.

[0035] Furthermore, the CPU 5 instructs the SPI master 3 to read data from the serial NAND flash memory 200 or to write data to the serial NAND flash memory 200. Specifically, the CPU 5 sets data such as the direction, start address, and number of data of the serial data transfer between the SPI master 3 and the serial NAND flash memory 200 in the register 6. The command selector 8 generates a command CMD for executing the serial data transfer based on the data set in the register 6, and outputs the generated command CMD to the SPI master 3. Alternatively, the CPU 5 sets a command sequence for realizing the serial data transfer between the SPI master 3 and the serial NAND flash memory 200 in the sequencer 7. The command selector 8 outputs the command sequence set in the sequencer 7 as the command CMD to the SPI master 3. Furthermore, when the CPU 5 sets the start bit of the serial data transfer in the register 6 to on, the command selector 8 outputs a start signal of the serial data transfer to the SPI master 3. When the start signal is input, the SPI master 3 executes serial data transfer with the serial NAND flash memory 200 based on the command CMD.

[0036] For example, when the CPU 5 causes the data transfer circuit 10 to transfer data from the DRAM 100 to the serial NAND flash memory 200, it instructs the DMA controller 2 to read data from the DRAM 100 and instructs the SPI master 3 to write data to the serial NAND flash memory 200. When the CPU 5 causes the data transfer circuit 10 to transfer data from the serial NAND flash memory 200 to the DRAM 100, it instructs the DMA controller 2 to write data to the DRAM 100 and instructs the SPI master 3 to read data from the serial NAND flash memory 200.

[0037] As described above, the CPU 5, the data transfer circuit 10, and the functional circuits 12-1 to 12-n transfer data to and from the DRAM 100 via the DRAM controller 13. Therefore, if a data transfer request is made from a circuit with a higher priority while the data transfer circuit 10 is transferring data to and from the DRAM 100, the data transfer between the data transfer circuit 10 and the DRAM 100 is interrupted. That is, the data transfer between the DRAM 100 and the data buffer 4 is interrupted. Therefore, if the data transfer from the DRAM 100 to the data buffer 4 is interrupted during the data transfer from the DRAM 100 to the serial NAND flash memory 200, the data to be transferred from the data buffer 4 to the serial NAND flash memory 200 will be lost, and there is a risk that erroneous data will be written to the serial NAND flash memory 200. Furthermore, if the data transfer from the data buffer 4 to the DRAM 100 is interrupted during data transfer from the serial NAND flash memory 200 to the DRAM 100, the data that should have been transferred from the serial NAND flash memory 200 to the data buffer 4 will be lost, and there is a risk that the necessary data will not be written to the DRAM 100.

[0038] Therefore, when at least the amount of data in the data buffer 4 satisfies a predetermined condition during data transfer between the SPI master 3 and the serial NAND flash memory 200, the SPI master 3 fixes the clock signal SCK to a low or high level to stop the output of clock pulses to the serial NAND flash memory 200 and interrupt the data transfer. Also, when the amount of data in the data buffer 4 no longer satisfies the predetermined condition, the SPI master 3 resumes the output of clock pulses to the serial NAND flash memory 200 and resumes the data transfer by alternately changing the clock signal SCK between a low level and a high level. In the following description, "stopping the output of the clock signal SCK pulses" means "stopping the output of the clock pulses by fixing the clock signal SCK to a low or high level". Also, "stopping the output of the clock signal SCK pulses" means "stopping the output of the clock pulses by fixing the clock signal SCK to a low or high level". "Resume clock pulse output" means "resume output of clock pulses by alternately changing the clock signal SCK between low and high levels."

[0039] Specifically, the SPI master 3 stops the pulse output of the clock signal SCK when the number of data in the data buffer 4 becomes equal to or greater than a predetermined number of data after the CPU 5 instructs the SPI master 3 to read data from the serial NAND flash memory 200. After the SPI master 3 stops the pulse output of the clock signal SCK, the SPI master 3 resumes the pulse output of the clock signal SCK when the number of data in the data buffer 4 becomes smaller than the predetermined number of data as a result of the data being transferred from the data buffer 4 to the DRAM 100 by the DMA controller 2. Furthermore, the SPI master 3 stops the pulse output of the clock signal SCK when the number of data in the data buffer 4 becomes equal to or smaller than a predetermined number of data after the CPU 5 instructs the SPI master 3 to write data to the serial NAND flash memory 200. After the SPI master 3 stops the pulse output of the clock signal SCK, the SPI master 3 resumes the pulse output of the clock signal SCK when the number of data in the data buffer 4 becomes larger than the predetermined number of data as a result of the data being transferred from the DRAM 100 to the data buffer 4 by the DMA controller 2.

[0040] Even if the number of data in the data buffer 4 satisfies a predetermined condition, the SPI master 3 does not need to stop outputting pulses of the clock signal SCK when the data transferred from the serial NAND flash memory 200 to the data buffer 4 or the data to be transferred from the data buffer 4 to the serial NAND flash memory 200 is the last data based on the number of data specified by the command CMD.

[0041] Upon completion of the data transfer between the DRAM 100 and the serial NAND flash memory 200, the interrupt controller 9 outputs an interrupt signal to the CPU 5. Upon receiving the interrupt signal, the CPU 5 instructs the data transfer circuit 10 to transfer the next data as necessary.

[0042] The DMA controller 2 is an example of the "first controller 2A" in FIG. 1. The SPI master 3 is an example of the "second controller 3A" in FIG. 1. The data buffer 4 is an example of the "data buffer 4A" in FIG. 1. The CPU 5 is an example of the "processor 5A" in FIG. 1. The DRAM 100 is an example of the "first memory 100A" in FIG. 1. The serial NAND flash memory 200 is an example of the "second memory 200A" in FIG. 1. The command CMD is an example of the "specification information" described in FIG. 1.

[0043] 1-3.Detailed configuration example of DMA controller, SPI master and data buffer Next, a detailed configuration example of the DMA controller 2, the SPI master 3, and the data buffer 4 will be described. FIG.

[0044] The data buffer 4 includes a FIFO buffer 41, a double buffer 42, a shift register 43, and selectors 44, 45, 46, and 47.

[0045] The FIFO buffer 41 is a buffer capable of storing a predetermined number of data of a predetermined size in a FIFO manner. FIFO is an abbreviation for First In First Out. In the following, the FIFO buffer 41 will be described as being capable of storing 128 pieces of 8-bit data.

[0046] The double buffer 42 is a buffer capable of storing two pieces of data of a predetermined size. In the following description, the double buffer 42 is capable of storing two pieces of 8-bit data. It will be described as such.

[0047] The shift register 43 shifts 1-bit, 2-bit, or 4-bit data read by the SPI master 3 from the serial NAND flash memory 200, and stores data of a predetermined size. In the following, the shift register 43 will be described as being capable of storing 8-bit data.

[0048] The selector 44 selects either the data output from the DMA read master 211 or the data output from the double buffer 42, and outputs it to the FIFO buffer 41. The selector 45 selects whether the data output from the FIFO buffer 41 is to be output to the double buffer 42 or the DMA write master 212. The selector 46 selects whether the data in the double buffer 42 is to be output to the data output controller 33 or the FIFO buffer 41. The selector 47 selects either the data output from the FIFO buffer 41 or the data output from the shift register 43, and outputs it to the double buffer 42.

[0049] Specifically, when the data transfer circuit 10 executes data transfer from the DRAM 100 to the serial NAND flash memory 200, the selector 44 selects the data output from the DMA read master 211 and outputs it to the FIFO buffer 41. The selector 45 also outputs the data output from the FIFO buffer 41 to the double buffer 42. The selector 46 also outputs the data in the double buffer 42 to the data output controller 33. The selector 47 also selects the data output from the FIFO buffer 41 and outputs it to the double buffer 42.

[0050] On the other hand, when the data transfer circuit 10 executes data transfer from the serial NAND flash memory 200 to the DRAM 100, the selector 44 selects the data output from the double buffer 42 and outputs it to the FIFO buffer 41. The selector 45 also outputs the data output from the FIFO buffer 41 to the DMA write master 212. The selector 46 also outputs the data in the double buffer 42 to the FIFO buffer 41. The selector 47 also selects the data output from the shift register 43 and outputs it to the double buffer 42.

[0051] The DMA controller 2 includes a DMA master 21 and a DMA buffer controller 22 .

[0052] The DMA master 21 executes data transfer between the DRAM 100 and the FIFO buffer 41 by DMA via the system bus 14. In the following description, it is assumed that the system bus 14 is a 64-bit bus, and the DMA master 21 executes data transfer between the DRAM 100 and the FIFO buffer 41 in 64-bit units. The DMA master 21 includes a DMA read master 211 and a DMA write master 212.

[0053] The DMA read master 211 reads 64-bit data from the DRAM 100 to the system bus 14 via the DRAM controller 13, and transfers the read 64-bit data to the FIFO buffer 41. The FIFO buffer 41 divides the 64-bit data into eight pieces of 8-bit data and stores them in order. The DMA read master 211 operates when the CPU 5 issues an instruction to read data from the DRAM 100.

[0054] The DMA write master 212 acquires eight pieces of data from the top of the FIFO buffer 41, combines the eight pieces of data, and outputs the combined data as 64-bit data to the system bus 14. The 4-bit data is written to the DRAM 100 via the DRAM controller 13. The DMA write master 212 operates when the CPU 5 issues an instruction to write data to the DRAM 100.

[0055] The DMA buffer controller 22 controls the FIFO buffer 41 and the selectors 44 and 45 to control the data transfer between the DRAM 100 and the FIFO buffer 41. The DMA buffer controller 22 includes a data counter 221.

[0056] The data counter 221 counts the number of data stored in the FIFO buffer 41. That is, the data counter 221 sets the initial value of the count value cnt to 0, increments the count value cnt by 1 every time a piece of data is newly stored in the FIFO buffer 41, and decrements the count value cnt by 1 every time a piece of data is newly transferred from the FIFO buffer 41.

[0057] The DMA buffer controller 22 controls the data transfer between the DRAM 100 and the FIFO buffer 41 based on the count value cnt of the data counter 221 .

[0058] Specifically, when the CPU 5 issues an instruction to read data from the DRAM 100, if the count value cnt is 120 or less, i.e., if the number of data items in the FIFO buffer 41 is 120 or less, the DMA buffer controller 22 causes the DMA read master 211 to execute a 64-bit data transfer from the DRAM 100 to the FIFO buffer 41. Also, if the count value cnt is 121 or more, i.e., if the number of data items in the FIFO buffer 41 is 121 or more, the DMA buffer controller 22 causes the DMA read master 211 to suspend the 64-bit data transfer from the DRAM 100 to the FIFO buffer 41 until the count value cnt becomes 120 or less.

[0059] On the other hand, when the CPU 5 issues an instruction to write data to the DRAM 100, if the count value cnt is 8 or more, i.e., if eight or more pieces of data exist in the FIFO buffer 41, the DMA buffer controller 22 causes the DMA write master 212 to execute a 64-bit data transfer from the FIFO buffer 41 to the DRAM 100. Also, if the count value cnt is 7 or less, i.e., if eight or more pieces of data do not exist in the FIFO buffer 41, the DMA buffer controller 22 causes the DMA write master 212 to suspend the 64-bit data transfer from the FIFO buffer 41 to the DRAM 100 until the count value cnt becomes 8 or more.

[0060] In addition, the DMA buffer controller 22 controls the data transfer between the FIFO buffer 41 and the double buffer 42 .

[0061] Specifically, when the CPU 5 issues an instruction to read data from the DRAM 100, the DMA buffer controller 22 transfers the top data in the FIFO buffer 41 to the double buffer 42 if the count value cnt is 1 or greater and the status signal readyS is at a high level. In addition, the DMA buffer controller 22 does not transfer data from the FIFO buffer 41 to the double buffer 42 if the count value cnt is 0 or the status signal readyS is at a low level.

[0062] On the other hand, when the CPU 5 issues an instruction to write data to the DRAM 100, the DMA buffer controller 22 transfers the first data in the double buffer 42 to the FIFO buffer 41 if the count value cnt is equal to or less than 127 and the status signal validS is at a high level. When cnt is 128, or when the status signal validS is at a low level, data transfer from the double buffer 42 to the FIFO buffer 41 is not performed.

[0063] Furthermore, the DMA buffer controller 22 generates status signals validD and readyD which are signals indicating the status of the FIFO buffer 41. Specifically, the DMA buffer controller 22 generates a high-level status signal validD when the count value cnt is 1 or greater, and generates a low-level status signal validD when the count value cnt is 0. Furthermore, the DMA buffer controller 22 generates a high-level status signal readyD when the count value cnt is 127 or less, and generates a low-level status signal readyD when the count value cnt is 128.

[0064] The SPI master 3 includes a clock controller 31, a chip select controller 32, a data output controller 33, a data input controller 34, a state machine 35, and an SPI buffer controller 36.

[0065] The clock controller 31 controls the output of the clock signal SCK to the serial NAND flash memory 200. Specifically, when reading or writing data from or to the serial NAND flash memory 200, the clock controller 31 outputs a clock pulse by alternately changing the clock signal SCK between low and high levels, and in other cases, the clock controller 31 does not output a clock pulse by fixing the clock signal SCK to a low or high level.

[0066] The chip select controller 32 controls the output of a chip select signal CSX to the serial NAND flash memory 200. Specifically, the chip select controller 32 outputs a low-level chip select signal CSX when reading or writing data from or to the serial NAND flash memory 200, and outputs a high-level chip select signal CSX in other cases.

[0067] The data output controller 33 controls the output of the input data signal SI to the serial NAND flash memory 200. Specifically, when reading data from the serial NAND flash memory 200, the data output controller 33 outputs the input data signal SI including address data and the like.

[0068] The data input controller 34 controls the input of the output data signal SO output from the serial NAND flash memory 200. Specifically, when reading data from the serial NAND flash memory 200, the data input controller 34 inputs the output data signal SO including the data to be read to the shift register 43.

[0069] The state machine 35 controls the output timing of the clock signal SCK, the chip select signal CSX, and the input data signal SI, and the input timing of the output data signal SO, in accordance with the SPI standard.

[0070] The SPI buffer controller 36 controls the double buffer 42 , the shift register 43 , and the selectors 46 and 47 , thereby controlling the data transfer between the serial NAND flash memory 200 and the double buffer 42 .

[0071] Specifically, when the CPU 5 issues an instruction to read data from the serial NAND flash memory 200, if there is no data in the shift register 43, the SPI buffer controller 36 instructs the state machine 35 to The SPI buffer controller 36 executes data transfer from the serial NAND flash memory 200 to the shift register 43. When there is no data in the double buffer 42, the SPI buffer controller 36 transfers the data transferred from the serial NAND flash memory 200 to the shift register 43 to the double buffer 42. When the number of data in the double buffer 42 is 1 or more and the status signal readyD is at a high level, the SPI buffer controller 36 transfers the data in the double buffer 42 to the FIFO buffer 41, and transfers the data transferred from the serial NAND flash memory 200 to the shift register 43 to the double buffer 42. When the number of data in the double buffer 42 is 1 or more and the status signal readyD is at a low level, the SPI buffer controller 36 does not transfer data from the double buffer 42 to the FIFO buffer 41 or from the shift register 43 to the double buffer 42.

[0072] Then, when data exists in the shift register 43, the number of data in the double buffer 42 is 1 or more, and the status signal readyD is at a low level, the SPI buffer controller 36 causes the state machine 35 to suspend the data transfer from the serial NAND flash memory 200 to the shift register 43. That is, when data exists in the shift register 43, if a first condition is satisfied that the number of data in the FIFO buffer 41 is a first data number of 128 or more, and a second condition is satisfied that the number of data in the double buffer 42 is a second data number of 1 or more, the clock controller 31 stops the pulse output of the clock signal SCK in response to an instruction from the state machine 35, thereby suspending the data transfer from the serial NAND flash memory 200 to the shift register 43. In other words, after the CPU 5 instructs the SPI master 3 to read data from the serial NAND flash memory 200, the clock controller 31 stops the pulse output of the clock signal SCK when the number of data in the data buffer 4 is a predetermined data number of 130 or more, as a predetermined condition.

[0073] FIG. 4 shows an example of a timing chart when data transfer from the serial NAND flash memory 200 to the shift register 43 is interrupted. In the example of FIG. 4, the first read data is transferred in the period from time t1 to time t2, and the transfer of the second read data starts at time t2. The transfer of the nth read data starts at time t3, and during the transfer of the nth read data, the status signal readyD changes from high level to low level at time t4. As a result, at time t5 after the transfer of the nth read data is completed, a predetermined condition is met and the pulse output of the clock signal SCK stops. Thereafter, at time t6, the status signal readyD changes from low level to high level. As a result, at time t7, the pulse output of the clock signal SCK is resumed and the transfer of the n+1th read data starts. Thereafter, the last read data is transferred in the period from time t8 to time t9, and the transfer of all read data is completed.

[0074] However, if the data in the shift register 43 is the last data of the data transfer based on the number of data specified by the command CMD, the SPI buffer controller 36 causes the state machine 35 to continue the data transfer from the serial NAND flash memory 200 to the double buffer 42. That is, even if the first condition that the number of data in the FIFO buffer 41 is equal to or greater than the first number of data, 128, is satisfied and the second condition that the number of data in the double buffer 42 is equal to or greater than the second number of data, 1, is satisfied, if the data in the shift register 43 is the last data of the data transfer, the clock controller 31 does not stop the pulse output of the clock signal SCK. This allows the serial data communication between the SPI master 3 and the serial NAND flash memory 200 to end normally.

[0075] The SPI buffer controller 36 also supports serial NAND flash memory After the data transfer from the serial NAND flash memory 200 to the shift register 43 is interrupted, when the status signal readyD changes from low level to high level as a result of the DMA write master 212 transferring data from the FIFO buffer 41 to the DRAM 100, that is, when the number of data in the FIFO buffer 41 becomes smaller than 128, the data transfer from the serial NAND flash memory 200 to the shift register 43 is resumed. That is, when the number of data in the FIFO buffer 41 becomes smaller than 128, the clock controller 31 resumes the pulse output of the clock signal SCK in response to an instruction from the state machine 35, whereby the data transfer from the serial NAND flash memory 200 to the shift register 43 is resumed. In other words, after stopping the pulse output of the clock signal SCK, when the number of data in the data buffer 4 becomes smaller than 130 as a result of data being transferred from the data buffer 4 to the DRAM 100, the clock controller 31 resumes the pulse output of the clock signal SCK.

[0076] On the other hand, when the CPU 5 issues an instruction to write data to the serial NAND flash memory 200, if the number of data items in the double buffer 42 is two, the SPI buffer controller 36 causes the state machine 35 to transfer data from the double buffer 42 to the serial NAND flash memory 200. The SPI buffer controller 36 also causes the state machine 35 to transfer data from the double buffer 42 to the serial NAND flash memory 200 if the number of data items in the double buffer 42 is one and the data in the double buffer 42 is the last data of the data transfer or the status signal validD is at a high level.

[0077] Furthermore, when the number of data in the double buffer 42 is 1 or less and the status signal validD is at a low level, the SPI buffer controller 36 causes the state machine 35 to suspend the data transfer from the double buffer 42 to the serial NAND flash memory 200. That is, when the first condition that the number of data in the FIFO buffer 41 is 0 or less, which is the third data number, is satisfied and the second condition that the number of data in the double buffer 42 is 1 or less, which is the fourth data number, is satisfied, the clock controller 31 stops the pulse output of the clock signal SCK in response to an instruction from the state machine 35, thereby suspending the data transfer from the double buffer 42 to the serial NAND flash memory 200. In other words, after the CPU 5 instructs the SPI master 3 to write data to the serial NAND flash memory 200, the clock controller 31 stops the pulse output of the clock signal SCK when the number of data in the data buffer 4 becomes 1 or less, which is the predetermined data number, as a predetermined condition.

[0078] FIG. 5 shows an example of a timing chart when data transfer from the double buffer 42 to the serial NAND flash memory 200 is interrupted. In the example of FIG. 5, the first write data is transferred in the period from time t1 to time t2, and the transfer of the second write data starts at time t2. The transfer of the nth write data starts at time t3, and during the transfer of the nth write data, the status signal validD changes from high level to low level at time t4. As a result, at time t5 after the transfer of the nth write data is completed, a predetermined condition is met and the pulse output of the clock signal SCK stops. Thereafter, at time t6, the status signal validD changes from low level to high level. As a result, at time t7, the pulse output of the clock signal SCK is resumed and the transfer of the n+1th write data starts. Thereafter, the last write data is transferred in the period from time t8 to time t9, and the transfer of all the write data is completed.

[0079] However, even if the first condition that the number of data in the FIFO buffer 41 is equal to or less than the third number of data, 0, is satisfied and the second condition that the number of data in the double buffer 42 is equal to or less than the fourth number of data, 1, is satisfied, the data in the double buffer 42 may be the last data in the data transfer. If the data is the last data, the clock controller 31 does not stop outputting the pulses of the clock signal SCK. As a result, the last data is written to the serial NAND flash memory 200, and the serial data communication between the SPI master 3 and the serial NAND flash memory 200 ends normally.

[0080] Furthermore, after interrupting the data transfer from the double buffer 42 to the serial NAND flash memory 200, the SPI buffer controller 36 resumes the data transfer from the double buffer 42 to the serial NAND flash memory 200 when the status signal validD changes from low level to high level as a result of data being transferred from the DRAM 100 to the FIFO buffer 41 by the DMA read master 211, that is, when the number of data in the FIFO buffer 41 becomes greater than 0. That is, when the number of data in the FIFO buffer 41 becomes greater than 0, the clock controller 31 resumes the pulse output of the clock signal SCK in response to an instruction from the state machine 35, whereby the data transfer from the double buffer 42 to the serial NAND flash memory 200 is resumed. In other words, after stopping the pulse output of the clock signal SCK, the clock controller 31 resumes the pulse output of the clock signal SCK when the number of data in the data buffer 4 becomes greater than 0 as a result of data being transferred from the DRAM 100 to the data buffer 4.

[0081] Furthermore, the SPI buffer controller 36 generates status signals validS and readyS which are signals indicating the status of the double buffer 42, and outputs them to the DMA buffer controller 22. Specifically, the SPI buffer controller 36 generates a high-level status signal validS when data exists in the double buffer 42, and generates a low-level status signal validS when no data exists in the double buffer 42. The SPI buffer controller 36 also generates a high-level status signal readyS when the number of data in the double buffer 42 is less than two, and generates a low-level status signal readyS when the number of data in the double buffer 42 is two.

[0082] DMA controller 2 is an example of "first controller 2A" in FIG. 1. SPI master 3 is an example of "second controller 3A" in FIG. 1. DMA master 21 is an example of "DMA master 21A" in FIG. 1. Clock controller 31 is an example of "clock controller 31A" in FIG. 1. FIFO buffer 41 is an example of "first buffer 41A" in FIG. 1. Double buffer 42 is an example of "second buffer 42A" in FIG. 1.

[0083] 1-4. Procedure for transferring data from DRAM to serial NAND flash memory Next, a process performed by the DMA controller 2 and the SPI master 3 to transfer data from the DRAM 100 to the serial NAND flash memory 200 will be described.

[0084] 6 is a flow chart showing an example of a procedure of processing by the DMA controller 2. As shown in FIG. 6, first, in step S1, the DMA controller 2 initializes the count value cnt of the data counter 221 to 0, and also initializes the end flag endflg to 0.

[0085] Next, in step S3, the DMA controller 2 determines whether the count value cnt is 0. If the count value cnt is not 0 in step S2, the DMA controller 2 sets the status signal validD to a high level in step S3. If the count value cnt is 0 in step S2, the DMA controller 2 sets the status signal validD to a low level in step S4.

[0086] If the count value cnt is 0, then in step S5, the DMA controller 2 determines whether or not the status signal readyS is at a high level. If the status signal readyS is at a high level in step S5, the DMA controller 2 transfers the first data in the FIFO buffer 41 to the double buffer 42 in step S6, and decrements the count value cnt by 1 in step S7. Then, in step S8, if the data transferred in step S6 is the last data, the DMA controller 2 ends the process.

[0087] If the status signal readyS is at a low level in step S5, then in step S9, the DMA controller 2 determines whether or not the count value cnt is equal to or greater than 121. If the count value cnt is equal to or greater than 121 in step S9, the DMA controller 2 repeats the processes from step S2 onwards.

[0088] If the count value cnt is 0 in step S2, if the data transferred in step S6 is not the last data in step S8, or if the count value cnt is not 121 or greater in step S9, the DMA controller 2 determines in step S10 whether the end flag endflg is 0. If the end flag endflg is 0 in step S10, and if DRAM access is possible in step S11, the DMA controller 2 transfers 64-bit data from the DRAM 100 to the FIFO buffer 41 in step S12, and increments the count value cnt by 8 in step S13.

[0089] Then, in step S14, if the data transferred in step S12 is the last data, the DMA controller 2 sets the end flag endflg to 1 in step S15, and repeats the processes from step S2 onwards.

[0090] In step S10, if the end flag endflg is 1, the DMA controller 2 skips steps S11 to S15 and performs steps S2 and onward again. In addition, in step S11, if the DRAM cannot be accessed, the DMA controller 2 skips steps S12 to S15 and performs steps S2 and onward again.

[0091] Fig. 7 is a flow chart showing an example of a procedure of processing by the SPI master 3. As shown in Fig. 7, first, in step S51, the SPI master 3 judges whether the number of data in the double buffer 42 is 1 or less. If the number of data in the double buffer 42 is 1 or less in step S51, the SPI master 3 sets the status signal readyS to a high level in step S52. If the number of data in the double buffer 42 is 2 in step S51, the SPI master 3 sets the status signal readyS to a low level in step S53.

[0092] If the number of data in the double buffer 42 is 1 or less, then in step S54, the SPI master 3 determines whether or not the status signal validD is at a low level. If the status signal validD is at a high level in step S54, in step S55, the SPI master 3 stores the top data of the FIFO buffer 41 in the double buffer 42. If the status signal validD is at a low level in step S54, in step S56, the SPI master 3 determines whether or not the data in the double buffer 42 is the last data.

[0093] If the number of data in the double buffer 42 is 2 in step S51, if the status signal validD is at a high level in step S54, or if the data in the double buffer 42 is the last data in step S56, the SPI master 3 transfers the data in the double buffer 42 to the serial NAND flash memory 200 in step S58. Send.

[0094] Then, in step S59, if the data transferred in step S58 is the last data, the SPI master 3 ends the process.

[0095] If the data in the double buffer 42 is not the last data in step S56, the SPI master 3 interrupts the data transfer from the double buffer 42 to the serial NAND flash memory 200 in step S57, and repeats the processes from step S51 onwards.

[0096] In this way, the DMA controller 2 and the SPI master 3 cooperate to perform a predetermined process according to the procedures in FIGS. 6 and 7, thereby achieving data transfer from the DRAM 100 to the serial NAND flash memory 200.

[0097] 1-5. Procedure for transferring data from serial NAND flash memory to DRAM Next, a process performed by the DMA controller 2 and the SPI master 3 to transfer data from the serial NAND flash memory 200 to the DRAM 100 will be described.

[0098] 8 is a flow chart showing an example of a procedure of processing by the DMA controller 2. As shown in FIG. 8, first, in step S101, the DMA controller 2 initializes the count value cnt of the data counter 221 to zero.

[0099] Next, in step S102, the DMA controller 2 determines whether the count value cnt is 7 or less. If the count value cnt is not 7 or less in step S2, then in step S103, if DRAM access is possible, the DMA controller 2 transfers the head data of the FIFO buffer 41 to the DRAM 100 in step S104, and decrements the count value cnt by 8 in step S105.

[0100] Then, in step S106, if the data transferred in step S104 is the last data, the DMA controller 2 ends the process.

[0101] If DRAM access is not possible in step S103, or if the data transferred in step S104 is not the last data in step S106, then in step S107, the DMA controller 2 determines whether the count value cnt is 128 or not.

[0102] If the count value cnt is 128 in step S107, the DMA controller 2 sets the status signal readyD to a low level in step S108, and repeats the processes from step S102 onwards.

[0103] If the count value cnt is equal to or less than 7 in step S102, or if the count value cnt is not 128 in step S107, the DMA controller 2 sets the status signal readyD to a high level in step S109.

[0104] Next, in step S110, the DMA controller 2 determines whether or not the status signal validS is at a high level. If the status signal validS is at a low level in step S110, the DMA controller 2 repeats the processes from step S102 onwards.

[0105] If the status signal validS is at a high level in step S110, the DMA controller 2 stores the data in the double buffer 42 in the FIFO buffer 41 in step S111, decrements the count value cnt by 1 in step S112, and The process is repeated.

[0106] Fig. 9 is a flow chart showing an example of a procedure of processing by the SPI master 3. As shown in Fig. 9, first, in step S151, the SPI master 3 initializes the end flag endflg to 0. Next, in step S152, the SPI master 3 judges whether the number of data in the double buffer 42 is 1 or more. If the number of data in the double buffer 42 is 1 or more in step S152, the SPI master 3 sets the status signal validS to a high level in step S153. Also, if the number of data in the double buffer 42 is 0 in step S152, the SPI master 3 sets the status signal validS to a low level in step S154.

[0107] If the number of data in the double buffer 42 is 1 or more, then in step S155, the SPI master 3 determines whether the status signal readyD is at a low level or not. If the status signal readyD is at a high level in step S155, the SPI master 3 transfers the data in the double buffer 42 to the FIFO buffer 41 in step S159. Then, in step S160, the SPI master 3 ends the process if the data transferred in step S159 is the last data.

[0108] If the number of data in the double buffer 42 is 0 in step S152, or if the data transferred in step S159 is not the last data in step S160, the SPI master 3 determines in step S161 whether the number of data in the shift register 43 is 0. If the number of data in the shift register 43 is 1 in step S161, the SPI master 3 transfers the data in the shift register 43 to the double buffer 42 in step S162, and repeats the processes from step S152 onwards.

[0109] If the status signal readyD is at a low level in step S155, then in step S156 the SPI master 3 determines whether the number of data in the shift register 43 is 1. If the number of data in the shift register 43 is 1 in step S156, then in step S157 the SPI master 3 determines whether the data in the shift register 43 is the last data.

[0110] In step S156, if the number of data in shift register 43 is 0, in step S157, if the data in shift register 43 is the last data, or in step S161, if the number of data in shift register 43 is 0, in step S163, the SPI master 3 determines whether the end flag endflg is 0 or not.

[0111] If the end flag endflg is 0 in step S163, then in step S164, the SPI master 3 transfers the data in the serial NAND flash memory 200 to the shift register 43. Then, in step S165, if the data transferred in step S164 is the last data, the SPI master 3 sets the end flag endflg to 1 and repeats the processes from step S152 onwards.

[0112] If the end flag endflg is 1 in step S163, or if the data transferred in step S164 is not the last data in step S165, the SPI master 3 repeats the processes from step S152 onwards.

[0113] If the data in the shift register 43 is not the last data in step S157, the SPI master 3 interrupts the data transfer from the serial NAND flash memory 200 to the shift register 43 in step S158, and repeats the processes from step S152 onwards.

[0114] In this way, the DMA controller 2 and the SPI master 3 cooperate to perform a predetermined process according to the procedures in FIGS. 8 and 9, thereby achieving data transfer from the serial NAND flash memory 200 to the DRAM 100.

[0115] 1-6.Effects According to the semiconductor device 1 of this embodiment, when the data transfer by DMA between the DRAM 100 and the data buffer 4 is delayed and the number of data in the data buffer 4 satisfies a predetermined condition, the pulse output of the clock signal SCK to the serial NAND flash memory 200 is stopped and the data transfer between the serial NAND flash memory 200 and the data buffer 4 is interrupted, thereby reducing the risk of transferring erroneous data. Specifically, according to the semiconductor device 1 of this embodiment, when the data transfer by DMA between the DRAM 100 and the FIFO buffer 41 is delayed and the number of data in the FIFO buffer 41 satisfies a first condition and the number of data in the double buffer 42 satisfies a second condition, the pulse output of the clock signal SCK to the serial NAND flash memory 200 is stopped and the data transfer between the serial NAND flash memory 200 and the double buffer 42 is interrupted, thereby reducing the risk of transferring erroneous data.

[0116] In particular, according to the semiconductor device 1 of this embodiment, when the data transfer from the FIFO buffer 41 to the DRAM 100 is delayed and the number of data in the FIFO buffer 41 becomes 128 and the number of data in the double buffer 42 becomes 1 or more, the pulse output of the clock signal SCK to the serial NAND flash memory 200 is stopped and the data transfer from the serial NAND flash memory 200 to the double buffer 42 is interrupted, thereby reducing the risk of data overflowing from the FIFO buffer 41 and data written to the DRAM 100 being lost. Furthermore, in the semiconductor device 1 of this embodiment, when the number of data in the FIFO buffer 41 becomes 127 or less due to the data transfer from the FIFO buffer 41 to the DRAM 100 after the data transfer from the serial NAND flash memory 200 to the double buffer 42 is interrupted, the pulse output of the clock signal SCK to the serial NAND flash memory 200 is resumed and the data transfer from the serial NAND flash memory 200 to the double buffer 42 is resumed. Therefore, according to the semiconductor device 1 of this embodiment, when the data transfer from the FIFO buffer 41 to the DRAM 100 is delayed, there is no need to restart the data transfer from the serial NAND flash memory 200 to the DRAM 100 from the beginning, thereby reducing the risk of a decrease in data transfer performance.

[0117] Furthermore, according to the semiconductor device 1 of this embodiment, when the data transfer from the DRAM 100 to the FIFO buffer 41 is delayed and the number of data in the FIFO buffer 41 becomes 0 and the number of data in the double buffer 42 becomes 1 or less, the pulse output of the clock signal SCK to the serial NAND flash memory 200 is stopped and the data transfer from the double buffer 42 to the serial NAND flash memory 200 is interrupted, thereby reducing the risk of erroneous data being transferred from the emptied double buffer 42 to the serial NAND flash memory 200. Furthermore, in the semiconductor device 1 of this embodiment, when the number of data in the FIFO buffer 41 becomes 1 or more due to the data transfer from the DRAM 100 to the FIFO buffer 41 after the data transfer from the double buffer 42 to the serial NAND flash memory 200 is interrupted, the pulse output of the clock signal SCK to the serial NAND flash memory 200 is resumed and the data transfer from the double buffer 42 to the serial NAND flash memory 200 is resumed. Therefore, according to the semiconductor device 1 of this embodiment, if the data transfer from the DRAM 100 to the FIFO buffer 41 is delayed, there is no need to restart the data transfer from the DRAM 100 to the serial NAND flash memory 200 from the beginning, reducing the risk of a decrease in data transfer performance.

[0118] Furthermore, in the semiconductor device 1 of this embodiment, even if the number of data in the data buffer 4 satisfies a predetermined condition, when the data transferred from the serial NAND flash memory 200 to the data buffer 4 is the last data, all data to be transferred from the serial NAND flash memory 200 to the data buffer 4 has already been transferred, so there is no risk of the data in the data buffer 4 overflowing and being overwritten, and it is not necessary to stop the pulse output of the clock signal SCK to the serial NAND flash memory 200. Even if the number of data in the data buffer 4 satisfies a predetermined condition, when the data transferred from the data buffer 4 to the serial NAND flash memory 200 is the last data, there is no risk of erroneous data being transferred from the data buffer 4 to the serial NAND flash memory 200, so it is not necessary to stop the pulse output of the clock signal SCK to the serial NAND flash memory 200. Therefore, according to the semiconductor device 1 of this embodiment, even if the number of data in the data buffer 4 satisfies a predetermined condition, when the data transferred from the serial NAND flash memory 200 to the data buffer 4 or the data to be transferred from the data buffer 4 to the serial NAND flash memory 200 is the last data, the pulse output of the clock signal SCK to the serial NAND flash memory 200 is not stopped, thereby reducing the risk that communication between the data buffer 4 and the serial NAND flash memory 200 will remain stopped and unable to be restored.

[0119] 2.Printing device 2-1. Overview of the printing device The printing device 300 of this embodiment will be described with reference to Fig. 10. Fig. 10 is a perspective view of the appearance of the printing device 300 of this embodiment.

[0120] 10, the printing device 300 includes a device main body 312 that is generally rectangular parallelepiped in shape. The device main body 312 includes a recording device 313 that prints on a medium, and an image reading device 314 that is provided on the recording device 313 and can read an original document or the like. For example, an image read by the image reading device 314 is printed by the recording device 313 on paper, which is an example of a medium. In the XYZ coordinate system, the X direction indicates the conveyance direction of the original document in the image reading device 314, the Y direction indicates the width direction of the original document, and the Z direction indicates the height direction of the image reading device 314.

[0121] The image reading device 314 includes an ADF unit 327 that is an automatic document feeder. ADF is an abbreviation for Auto Document Feeder. The ADF unit 327 is provided rotatably around a rotation axis J on the rear side of the device body 312, which is the +Y axis direction side, as a fulcrum, and is configured as an opening / closing body that can be opened and closed relative to the upper part of the device body 312.

[0122] The ADF section 327 includes an original transport section 328 having a drive mechanism for transporting an original, an original placement surface 340, and an original discharge surface 342. The original transport section 328 is provided with a cover 344 that covers at least a part of the original transport path. The original placed on the original placement surface 340 is fed into the image reading device 314 by the original transport section 328 and read, and then discharged and placed on the original discharge surface 342. Note that an example of an original in this embodiment is a photograph, a document, or the like.

[0123] An operation unit 316 is provided at the top of the front side in the -Y axis direction of the device body 312, and the operation unit 316 is configured with a power button, print setting buttons, a display panel, etc. for operating the printing device 300.

[0124] A rear-side tray 324 on which paper is placed is provided on the rear side, which is the +Y-axis direction side, of the device main body 312. The paper placed on the rear-side tray 324 is fed to a printing unit (not shown) in the recording device 313, and is printed by the printing unit using an inkjet method.

[0125] A paper storage section 326 for storing a plurality of papers is provided on the bottom side, which is the -Z axis direction side, of the front tray 322. The paper storage section 326 is provided at the bottom of the device body 312 so as to be slidable in the Y axis direction, and is configured to be detachable from the device body 312. The paper placed in the paper storage section 326 is fed to a printing section in the recording device 313 and printed.

[0126] A drawer section 320 that is attached to a front tray 322 and can slide in the Y-axis direction is provided on the front side of the device body 312. Paper that has been fed to the printing section from a rear tray 324 or paper storage section 326 and printed on is discharged from an opening 318 provided on the front side of the device body 312, and placed on the front tray 322 or the drawer section 320 that has been drawn out from the front tray 322.

[0127] The printing device 300 of this embodiment can feed paper placed on the front tray 322 and the drawer unit 320 from the opening 318 into the inside of the recording device 313, and print using the printing unit. Therefore, the front tray 322 and the drawer unit 320 have a function as a support surface for paper discharged from inside the recording device 313 to the outside, and a function as a support surface for paper fed into the inside of the recording device 313.

[0128] 2-2. Functional configuration of the printing device The printing device 300 of this embodiment includes the semiconductor device 1 described above. FIG. 11 is a diagram showing a functional configuration of the printing device 300 of this embodiment. In FIG. 11, the same components as those in FIG. 2 are denoted by the same reference numerals. As shown in FIG. 11, the printing device 300 includes the semiconductor device 1, the DRAM 100, and the serial NAND flash memory 200 shown in FIG. 2. The printing device 300 also includes an external connector 110, a printing unit 120, an image reading unit 130, and a display unit 140.

[0129] The external connector 110 is a connector that is connected to an external device, and may be, for example, a USB connector that is connected to a personal computer, a USB memory, etc. For example, image data for printing is transmitted from the external device connected to the external connector 110.

[0130] The printing unit 120 is provided inside the recording device 313 shown in FIG. 10, and performs printing on paper by an inkjet method.

[0131] The image reading unit 130 is provided inside the image reading device 314 shown in Fig. 10, and reads an image of a document by a line sensor. The line sensor may be a CMOS line sensor or a CCD line sensor. CMOS is an abbreviation for Complementary Metal-Oxide-Semiconductor, and CCD is an abbreviation for Charge Coupled Device.

[0132] The display unit 140 is a display panel provided in the operation unit 316 shown in FIG. 10, and displays various types of information.

[0133] 2, the semiconductor device 1 includes a CPU 5, a data transfer circuit 10, a clock signal generation circuit 11, a DRAM controller 13, and a system bus 14. The semiconductor device 1 also includes a print image processing circuit 15, a scan image processing circuit 16, an external interface circuit 17, a print control circuit 18, a scan control circuit 19, and a display control circuit 20 as the functional circuits 12-1 to 12-n shown in FIG.

[0134] CPU 5, data transfer circuit 10, clock signal generation circuit 11, DRAM controller The print image processing circuit 13 , the scan image processing circuit 16 , the external interface circuit 17 , the print control circuit 18 , the scan control circuit 19 and the display control circuit 20 are connected to a system bus 14 .

[0135] The clock signal generation circuit 11 generates a plurality of clock signals and supplies each of the plurality of clock signals to the CPU 5, the data transfer circuit 10, the DRAM controller 13, the print image processing circuit 15, the scan image processing circuit 16, the external interface circuit 17, the print control circuit 18, and the scan control circuit 19. The CPU 5, the data transfer circuit 10, the DRAM controller 13, the print image processing circuit 15, the scan image processing circuit 16, the external interface circuit 17, the print control circuit 18, and the scan control circuit 19 each operate in synchronization with the supplied clock signal.

[0136] The CPU 5 instructs the data transfer circuit 10, print image processing circuit 15, scan image processing circuit 16, external interface circuit 17, print control circuit 18, scan control circuit 19 and display control circuit 20 to operate.

[0137] The external interface circuit 17 receives image data for printing sent from an external device connected to the external connector 110 , and writes the received image data into the DRAM 100 via the DRAM controller 13 .

[0138] The scan control circuit 19 controls the image reading unit 130 , and writes the image data read by the image reading unit 130 into the DRAM 100 via the DRAM controller 13 .

[0139] The scan image processing circuit 16 reads the image data read by the image reading unit 130 from the DRAM 100 and other data necessary for image processing via the DRAM controller 13, and performs image processing such as contrast enhancement and sharpness enhancement on the read image data. Then, the scan image processing circuit 16 writes the processed image data to the DRAM 100 via the DRAM controller 13.

[0140] The print image processing circuit 15 reads out image data for printing and other data required for image processing from the DRAM 100 via the DRAM controller 13, and performs image processing such as resolution conversion, color conversion, halftone processing, and rasterization on the read image data. The image data for printing is image data received from an external device by the external interface circuit 17, or image data that has been image-processed by the scan image processing circuit 16. The print image processing circuit 15 then writes the image data that has been image-processed to the DRAM 100 via the DRAM controller 13.

[0141] The print control circuit 18 reads out the image data processed by the print image processing circuit 15 and other data necessary for printing from the DRAM 100 via the DRAM controller 13, and generates and outputs various control signals for driving and controlling the print unit 120 based on the read image data. The control signals generated by the print control circuit 18 are supplied to the print unit 120, and the print unit 120 executes printing in accordance with the control signals.

[0142] The display control circuit 20 reads image data to be displayed on the display unit 140 and other data necessary for display from the DRAM 100 via the DRAM controller 13, and generates and outputs various signals for driving and controlling the display unit 140 based on the read image data. The various signals generated by the display control circuit 20 are supplied to the display unit 140, and the display unit 140 displays an image according to the various signals.

[0143] As described above, the data transfer circuit 10 transfers the DRAM data to the DRAM controller 13. Data is transferred between the M100 and the serial NAND flash memory 200. The serial NAND flash memory 200 stores binary codes of the programs executed by the CPU 5, image data to be displayed on the display unit 140, font data for printing, lookup tables used in color conversion processing, initial setting data for printing and scanning, etc. These various data are transferred to the DRAM 100 when the printing device 300 is started up.

[0144] Data transfer between the data transfer circuit 10, print image processing circuit 15, scan image processing circuit 16, external interface circuit 17, print control circuit 18, scan control circuit 19 and display control circuit 20 and the DRAM 100 is mediated by the DRAM controller 13 and is each executed by DMA.

[0145] According to the printing device 300 of this embodiment, the semiconductor device 1 reduces the risk of erroneous data being transferred between the DRAM 100 and the serial NAND flash memory 200, thereby reducing malfunctions of the printing unit 120 and the image reading unit 130.

[0146] Although the embodiments have been described above, the present invention is not limited to these embodiments, and can be embodied in various forms without departing from the spirit and scope of the present invention. For example, the above-described embodiments can be appropriately combined.

[0147] The present invention includes configurations that are substantially the same as the configurations described in the embodiments, for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effects. The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that achieve the same effects as the configurations described in the embodiments, or configurations that can achieve the same purpose. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments.

[0148] The present invention is not limited to the present embodiment, and various modifications are possible within the scope of the present invention.

[0149] For example, in each of the above embodiments, an inkjet printer has been described as an example of a printing device according to the present invention, but the printing device according to the present invention is not limited to an inkjet printer and may be, for example, a thermal printer.

[0150] The following can be derived from the above-described embodiment.

[0151] One aspect of the semiconductor device is a first controller capable of communicating with the first memory; a second controller capable of communicating with the second memory; a data buffer in which the data of the first memory is stored by the first controller and the data of the second memory is stored by the second controller; The first controller is a DMA master for performing data transfer between the first memory and the data buffer by DMA; The second controller is a clock controller that outputs a clock pulse that defines a timing of data transfer between the second memory and the data buffer; The clock controller includes: When at least the number of data in the data buffer satisfies a predetermined condition, the output of the clock pulse is stopped.

[0152] According to this semiconductor device, if DMA data transfer between the first memory and the data buffer is delayed and the number of data in the data buffer meets a predetermined condition, the output of the clock pulse that determines the timing of data transfer between the second memory and the data buffer is stopped and data transfer between the second memory and the data buffer is interrupted, thereby reducing the risk of erroneous data being transferred.

[0153] One aspect of the semiconductor device is a processor for instructing the second controller to read data from the second memory; The clock controller includes: After the processor instructs the second controller to read data, the output of the clock pulse may be stopped when the number of data in the data buffer becomes equal to or exceeds a predetermined number of data, which is the predetermined condition.

[0154] According to this semiconductor device, if data transfer from the data buffer to the first memory is delayed and the number of data in the data buffer exceeds a predetermined number of data, the output of clock pulses to the second memory is stopped and data transfer from the second memory to the data buffer is interrupted, thereby reducing the risk of data overflowing from the data buffer and data written to the first memory being lost.

[0155] In one embodiment of the semiconductor device, The clock controller includes: After the output of the clock pulse is stopped, if the number of data in the data buffer becomes smaller than the predetermined number of data as a result of the first controller transferring data from the data buffer to the first memory, the output of the clock pulse may be resumed.

[0156] In this semiconductor device, after stopping the output of clock pulses to the second memory and interrupting the data transfer from the second memory to the data buffer, if the number of data in the data buffer becomes smaller than a predetermined number of data due to the data transfer from the data buffer to the first memory, the output of clock pulses to the second memory is resumed and the data transfer from the second memory to the data buffer is resumed. Therefore, according to this semiconductor device, when the data transfer from the data buffer to the first memory is delayed, it is not necessary to restart the data transfer from the second memory to the first memory from the beginning, reducing the risk of a decrease in data transfer performance.

[0157] One aspect of the semiconductor device is a processor for instructing the second controller to write data to the second memory; The clock controller includes: After the processor instructs the second controller to write data, if the number of data in the data buffer becomes equal to or less than a predetermined number of data, which is the predetermined condition, the output of the clock pulse may be stopped.

[0158] According to this semiconductor device, if the data transfer from the first memory to the data buffer is delayed and the number of data in the data buffer falls below a predetermined number of data, the output of clock pulses to the second memory is stopped and the data transfer from the data buffer to the second memory is interrupted, thereby reducing the risk of erroneous data being transferred from the now-empty data buffer to the second memory.

[0159] In one embodiment of the semiconductor device, The clock controller includes: After the output of the clock pulse is stopped, if the first controller transfers data from the first memory to the data buffer so that the number of data in the data buffer becomes greater than the predetermined number of data, the output of the clock pulse may be resumed.

[0160] In this semiconductor device, after stopping the output of clock pulses to the second memory and interrupting the data transfer from the data buffer to the second memory, if the number of data in the data buffer becomes greater than a predetermined number of data due to the data transfer from the first memory to the data buffer, the output of clock pulses to the second memory is resumed and the data transfer from the data buffer to the second memory is resumed. Therefore, according to this semiconductor device, when the data transfer from the first memory to the data buffer is delayed, it is not necessary to restart the data transfer from the first memory to the second memory from the beginning, reducing the risk of a decrease in data transfer performance.

[0161] One aspect of the semiconductor device is a processor that outputs to the second controller designation information that designates a number of pieces of data for each data transfer between the second controller and the second memory; The clock controller includes: Even if the number of data in the data buffer satisfies the specified condition, if the data transferred from the second memory to the data buffer or the data to be transferred from the data buffer to the second memory is the last data based on the number of data specified in the designation information, the output of the clock pulse does not have to be stopped.

[0162] In this semiconductor device, even if the number of data in the data buffer satisfies a predetermined condition, when the data transferred from the second memory to the data buffer is the last data, all data to be transferred from the second memory to the data buffer has already been transferred, so there is no risk of the data in the data buffer overflowing and being overwritten, and there is no need to stop the output of clock pulses to the second memory. Also, even if the number of data in the data buffer satisfies a predetermined condition, when the data to be transferred from the data buffer to the second memory is the last data, there is no risk of erroneous data being transferred from the data buffer to the second memory, so there is no need to stop the output of clock pulses to the second memory. Therefore, according to this semiconductor device, even if the number of data in the data buffer satisfies a predetermined condition, when the data transferred from the second memory to the data buffer or the data to be transferred from the data buffer to the second memory is the last data, the output of clock pulses to the second memory is not stopped, thereby reducing the risk that communication between the data buffer and the second memory will remain stopped and cannot be restored.

[0163] In one embodiment of the semiconductor device, the data buffer includes a first buffer and a second buffer; the first controller controls data transfer between the first memory and the first buffer, and controls data transfer between the first buffer and the second buffer; the second controller controls data transfer between the second memory and the second buffer, and controls data transfer between the second buffer and the first buffer; The clock controller includes: The output of the clock pulse may be stopped when at least the number of data in the first buffer satisfies a first condition and the number of data in the second buffer satisfies a second condition. stomach.

[0164] According to this semiconductor device, when DMA data transfer between the first memory and the first buffer is delayed such that the amount of data in the first buffer satisfies a first condition and the amount of data in the second buffer satisfies a second condition, the output of clock pulses to the second memory is stopped and data transfer between the second memory and the second buffer is interrupted, thereby reducing the risk of erroneous data being transferred.

[0165] One aspect of the semiconductor device is a processor for instructing the second controller to read data from the second memory; The clock controller includes: After the processor instructs the second controller to read data, the output of the clock pulse may be stopped when the specified condition is that the number of data in the first buffer is equal to or greater than a first number of data and the number of data in the second buffer is equal to or greater than a second number of data.

[0166] According to this semiconductor device, if the data transfer from the first buffer to the first memory is delayed and the number of data in the first buffer becomes equal to or greater than the first number of data and the number of data in the second buffer becomes equal to or greater than the second number of data, the output of clock pulses to the second memory is stopped and the data transfer from the second memory to the second buffer is interrupted, thereby reducing the risk of data overflowing from the first buffer and data written to the first memory being lost.

[0167] One aspect of the semiconductor device is a processor for instructing the second controller to write data to the second memory; The clock controller includes: After the processor instructs the second controller to write data, if the specified condition is that the number of data in the first buffer becomes a third number of data or less and the number of data in the second buffer becomes a fourth number of data or less, the output of the clock pulse may be stopped.

[0168] According to this semiconductor device, if the data transfer from the first memory to the first buffer is delayed and the number of data in the first buffer becomes the third number of data or less and the number of data in the second buffer becomes the fourth number of data or less, the output of clock pulses to the second memory is stopped and the data transfer from the second buffer to the second memory is interrupted, thereby reducing the risk of erroneous data being transferred from the now empty second buffer to the second memory.

[0169] One aspect of the printing device is One aspect of the semiconductor device; A printing unit that prints on a medium, The semiconductor device includes: The printer further includes a print control circuit that outputs a control signal for the printing unit.

[0170] According to this printing device, the semiconductor device reduces the risk of erroneous data being transferred between the first memory and the second memory, thereby reducing malfunctions of the printing section. [Explanation of symbols]

[0171] 1,1A...semiconductor device, 2...DMA controller, 2A...first controller, 3...SPI master, 3A...second controller, 4,4A...data buffer, 5...CPU, 5A...processor, 6...register, 7...sequencer, 8...command selector, 9...interrupt controller, 10...data transfer circuit, 11...clock signal generation circuit, 12-1 to 12-n...functional circuit, 13...DRAM controller, 14...system bus, 21, 21A...DMA master, 22...DMA buffer controller, 31, 31A...clock controller, 32...chip select controller, 33...data output controller, 34...data input controller, 35...state machine, 36...SPI buffer controller, 41...FIFO buffer, 41A...first buffer, 42 ...double buffer, 42A...second buffer, 43...shift register, 44,45,46,47...selector, 100...DRAM, 100A...first memory, 200...serial NAND flash memory, 200A...second memory, 211...DMA read master, 212...DMA write master, 300...printing device, 312...device main body, 313...recording device, 314...image reading device, 316...operation unit, 318...opening, 320...drawer unit, 322...front tray, 324...rear tray, 326...paper storage unit, 327...ADF unit, 328...original transport unit, 340...original placement surface, 342...original ejection surface, 344...cover

Claims

1. a first controller in communication with the first memory; a second controller capable of communicating with the second memory; a data buffer in which the data of the first memory is stored by the first controller and the data of the second memory is stored by the second controller; The first controller is a DMA master for performing data transfer between the first memory and the data buffer by DMA; The second controller is a clock controller that outputs a clock pulse that defines a timing of data transfer between the second memory and the data buffer; The clock controller includes: stopping the output of the clock pulse when at least the number of data in the data buffer satisfies a predetermined condition; Semiconductor device.

2. a processor for instructing the second controller to read data from the second memory; The clock controller includes: after the processor instructs the second controller to read data, when the number of data in the data buffer becomes equal to or greater than a predetermined number of data as the predetermined condition, output of the clock pulse is stopped; The semiconductor device according to claim 1 .

3. The clock controller includes: after the output of the clock pulse is stopped, when the number of data in the data buffer becomes smaller than the predetermined number of data as a result of the first controller transferring data from the data buffer to the first memory, the output of the clock pulse is resumed; The semiconductor device according to claim 2 .

4. a processor for instructing the second controller to write data to the second memory; The clock controller includes: after the processor instructs the second controller to write data, when the number of data in the data buffer becomes equal to or less than a predetermined number of data as the predetermined condition, output of the clock pulse is stopped; The semiconductor device according to claim 1 .

5. The clock controller includes: after the output of the clock pulse is stopped, when the number of data in the data buffer becomes larger than the predetermined number of data as a result of data being transferred from the first memory to the data buffer by the first controller, the output of the clock pulse is resumed; The semiconductor device according to claim 4.

6. a processor that outputs to the second controller designation information that designates a number of data for each data transfer between the second controller and the second memory; The clock controller includes: even if the number of data in the data buffer satisfies the predetermined condition, when the data transferred from the second memory to the data buffer or the data to be transferred from the data buffer to the second memory is the last data based on the number of data specified by the specification information, output of the clock pulse is not stopped. The semiconductor device according to claim 1 .

7. the data buffer includes a first buffer and a second buffer; the first controller controls data transfer between the first memory and the first buffer, and controls data transfer between the first buffer and the second buffer; the second controller controls data transfer between the second memory and the second buffer, and controls data transfer between the second buffer and the first buffer; The clock controller includes: stopping the output of the clock pulse when at least the number of data in the first buffer satisfies a first condition and the number of data in the second buffer satisfies a second condition; The semiconductor device according to claim 1 .

8. a processor for instructing the second controller to read data from the second memory; The clock controller includes: after the processor issues an instruction to the second controller to read data, when the predetermined condition is that the number of data in the first buffer is equal to or greater than a first number of data and the number of data in the second buffer is equal to or greater than a second number of data, output of the clock pulse is stopped; The semiconductor device according to claim 7.

9. a processor for instructing the second controller to write data to the second memory; The clock controller includes: after the processor issues an instruction to write data to the second controller, when the predetermined condition is satisfied, that is, the number of data in the first buffer becomes equal to or less than a third number of data and the number of data in the second buffer becomes equal to or less than a fourth number of data, output of the clock pulse is stopped; The semiconductor device according to claim 7.

10. A semiconductor device according to any one of claims 1 to 9, A printing unit that prints on a medium, The semiconductor device includes: Further comprising a print control circuit that outputs a control signal for the printing unit. Printing device.

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