Light source device and distance measuring device

Abstract

To provide a light source device capable of improving the uniformity of light emission in a plurality of semiconductor light-emitting elements.SOLUTION: Light source devices each include: a first reflection mirror, a first semiconductor resonator including a first activation layer, a second reflection mirror, and a first electrode in this order on a side of a first surface of a semiconductor substrate; and a plurality of semiconductor light-emitting elements having a second electrode on a second surface on the side opposite to the first surface of the semiconductor substrate. A power supply pad is for supplying power to the plurality of semiconductor light-emitting elements. A wiring connects each of the plurality of semiconductor light-emitting elements with the power supply pad. The plurality of semiconductor light-emitting elements are divided into a plurality of groups each having at least one semiconductor light-emitting element in accordance with a distance from the power supply pad. The plurality of semiconductor light-emitting elements are constructed so that the resistance value between the first and second electrodes is larger as the distance, of the semiconductor light-emitting element in the group, from the power supply pad is shorter.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a light source device and a distance measuring device.

Background Art

[0002] Conventionally, as a distance measuring device for measuring the distance to an object, a ToF (Time of Flight) type LiDAR (Light Detection and Ranging) system is known. As a light source for the LiDAR system, a VCSEL (Vertical Cavity Surface Emitting LASER) is preferably used because it has advantages such as little wavelength dependence on temperature.

[0003] The light source for the LiDAR system may be configured to be capable of supporting flash driving in which a plurality of semiconductor light emitting elements are arranged in an array and emit light simultaneously over the entire surface, because the greater the power of the light source, the longer the distance that can be measured. Also, the light source for the LiDAR system may be configured to be capable of supporting sequential driving in which one row or several rows are sequentially emitted. For example, Patent Document 1 describes an example in which the number of semiconductor light emitting elements is 100 to 1000, and that the output increases by increasing the number of semiconductor light emitting elements.

[0004] Here, since the power consumption of the light source for the LiDAR system increases as the output of the semiconductor light emitting element increases, a device has been devised to reduce the element resistance in order to reduce power consumption. For example, Patent Document 2 discloses an example of reducing the element resistance by increasing the doping concentration of the upper mirror, which is the current path in the semiconductor light emitting element.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0006] However, when a light source device having a plurality of semiconductor light-emitting elements is configured using the above conventional technology, the light emission from each semiconductor light-emitting element may not be uniform.

[0007] Therefore, an object of the present invention is to provide a light source device capable of improving the uniformity of light emission in a plurality of semiconductor light-emitting elements.

MEANS FOR SOLVING THE PROBLEMS

[0008] According to one disclosure of the present specification, each of them has, on the side of the first surface of the semiconductor substrate, a first mirror, a first semiconductor resonator including a first active layer, a second mirror, and a first electrode, in this order, and has a second electrode on the second surface of the semiconductor substrate opposite to the first surface, a plurality of semiconductor light-emitting elements, a power supply pad for supplying power to the plurality of semiconductor light-emitting elements, and wiring for connecting each of the plurality of semiconductor light-emitting elements and the power supply pad. The plurality of semiconductor light-emitting elements are divided into a plurality of groups each having at least one of the semiconductor light-emitting elements according to the distance from the power supply pad, and the semiconductor light-emitting elements in the group with a shorter distance from the power supply pad are configured such that the resistance value between the first electrode and the second electrode becomes larger. A light source device is provided.

EFFECTS OF THE INVENTION

[0009] According to the present invention, a light source device capable of improving the uniformity of light emission in a plurality of semiconductor light-emitting elements can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]

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[0011] [First Embodiment] A VCSEL array (light source device) 100 according to the first embodiment will be described. The VCSEL array 100 includes a plurality of VCSELs 1 arranged in an array, and is a semiconductor laser that emits laser light from each VCSEL 1. Here, the array state means a state in which a plurality of VCSELs 1 are two-dimensionally arranged according to a predetermined pattern.

[0012] In the following description, the first direction (row direction) when arranging a plurality of VCSELs 1 in an array is referred to as the X direction. The second direction (column direction) when arranging a plurality of VCSELs 1 in an array is referred to as the Y direction. The direction intersecting the X direction and the Y direction is referred to as the Z direction. The X direction, the Y direction, and the Z direction are typically orthogonal to each other.

[0013] The VCSEL array 100 includes, for example, as shown in FIG. 1, a plurality of VCSELs 1 as a plurality of semiconductor light-emitting elements, a plurality of anode wirings 101 as wirings, and a plurality of anode power supply pads 102 as power supply pads. In FIG. 1, four on one side in the Y direction and three on the other side in the Y direction among the plurality of VCSELs 1 are illustrated.

[0014] Each of the plurality of VCSELs 1 is a vertical cavity surface emitting laser having a distributed Bragg reflector (DBR). The plurality of VCSELs 1 are arranged in an array over a plurality of rows and a plurality of columns. For example, 20 VCSELs 1 are arranged in a row along the Y direction, and a bundle of 20 such arrangements in the Y direction is arranged 20 along the X direction. As a result, a total of 400 (20×20) VCSELs 1 are arranged in an array, and when viewed from the Z direction, it forms a rectangular shape as a whole.

[0015] The plurality of anode wirings 101 are wirings that connect each of the plurality of VCSELs 1 and the anode power supply pads 102. The plurality of anode wirings 101 each extend along the Y direction and are provided side by side along the X direction. One anode wiring 101 is electrically connected to 20 VCSELs 1 along the Y direction. In other words, 20 VCSELs 1 along the Y direction are connected in parallel to one anode wiring 101. And 20 such anode wirings 101 are provided side by side along the X direction. In this way, the plurality of anode wirings 101 are configured as sequential anode wirings. Each anode wiring 101 supplies current to 20 VCSELs 1 connected in parallel.

[0016] The anode power supply pad 102 is a part for connecting an Au wire (not shown). The anode power supply pad 102 is a power supply pad for supplying power to a plurality of VCSELs 1, and is provided at one end of the anode wiring 101 in the Y direction. The anode power supply pad 102 has a role of supplying the current supplied from the outside through the Au wire to the anode wiring 101.

[0017] In the VCSEL array 100 configured as described above, when current is supplied from the outside to 20 anode power supply pads 102 through Au wires, 400 VCSELs 1 can be made to emit light. Note that, by sequentially supplying current from the outside to the 20 anode power supply pads 102, sequential driving can be performed in which each column emits light with a shifted timing.

[0018] Here, the plurality of VCSELs 1 according to the first embodiment are configured to include a VCSEL 1A as a semiconductor light emitting element and a VCSEL 1B as a semiconductor light emitting element. In the following description, when there is no need to particularly distinguish between the VCSEL 1A and the VCSEL 1B, they may simply be described as "VCSEL 1".

[0019] As shown in Fig. 2(b), VCSEL1B includes an n-type GaAs substrate 10 as a semiconductor substrate, a first DBR 20 as a first mirror, a semiconductor resonator 30 as a first semiconductor resonator, and a second DBR 40 as a second mirror. Further, VCSEL1B includes an insulating film 50, an upper ring electrode 60 as a first electrode, and a back surface electrode 70 as a second electrode. The first DBR 20, the semiconductor resonator 30, the second DBR 40, and the upper ring electrode 60 are stacked in this order on the first surface of the n-type GaAs substrate 10. The back surface electrode 70 is provided on the second surface opposite to the first surface of the n-type GaAs substrate 10. Although these members are in direct contact in Fig. 2(b), other members may be provided therebetween. Also, the above description is an explanation of the structure and does not limit the manufacturing order of each member. Note that (b) of Fig. 2 is a cross-sectional view taken along V2-V2 of Fig. 1.

[0020] The n-type GaAs substrate 10 is a substrate made of n-type GaAs single crystal. The n-type GaAs substrate 10 has a first surface on which various members are stacked and a second surface located on the opposite side of the first surface in the Z direction.

[0021] The first DBR 20 is provided on the first surface of the n-type GaAs substrate 10. The first DBR 20 is composed of a pair of an Al 0.1 GaAs layer and an Al 0.9 GaAs layer, and 35 pairs of such are stacked. Here, λc is the center wavelength of the high reflection band of the second DBR 40 and is, for example, 940 nm.

[0022] The semiconductor resonator 30 is provided on the first DBR 20 and is composed of an n-type AlGaAs layer, a first active layer, and a p-type layer from the first DBR 20 side. The first active layer is an undoped layer and has three quantum well layers 31 therein. Each of the three quantum well layers 31 is composed of an InGaAs well layer with a thickness of 8 nm and an AlGaAs barrier layer with a thickness of 10 nm sandwiching it.

[0023] The second DBR 40 is provided on the semiconductor resonator 30 and is composed of a pair of an Al 0.1 GaAs layer and an Al 0.9 GaAs layer, with 20 pairs of such layers stacked. A current confinement layer 41 with a thickness of 30 nm is provided in the second DBR 40. In the manufacturing process, a part of the current confinement layer 41 is oxidized from the mesa lateral directions (X direction, Y direction) by exposure to a water vapor atmosphere. The current confinement layer 41 is divided into an oxidized region with a predetermined width from the mesa sidewall and a non-oxidized region near the mesa center. Since the current injected into the VCSEL 1B flows only through the non-oxidized region, only the central part of the VCSEL 1B emits laser oscillation. An upper ring electrode 60 is in electrical contact with the second DBR 40. A part of the uppermost Al 0.1 GaAs layer of the second DBR 40 is replaced by a GaAs contact layer with a thickness of 50 nm and a carrier concentration of 1×10 19 cm -3 . This improves the electrical contact property between the second DBR 40 and the upper ring electrode 60. Note that a part of the in-plane of the chip surface of the semiconductor resonator 30 and the second DBR 40, which are the layers above the first DBR 20, is removed during the manufacturing process, and the remaining part is configured in a mesa shape.

[0024] The insulating film 50 covers the mesa-shaped semiconductor resonator 30 and the second DBR 40, etc., and suppresses their alteration.

[0025] The upper ring electrode 60 is provided on the second DBR 40 and is electrically connected to the anode wiring 101. The upper ring electrode 60 has an annular conductive pattern, and the central opening serves as a circular window for light extraction. The upper ring electrode 60 makes an ohmic contact with the second DBR 40 through a part where a part of the insulating film 50 is removed.

[0026] The back electrode 70 has conductivity and is provided on the second surface of the n-type GaAs substrate 10. The back electrode 70 makes an ohmic contact with the n-type GaAs substrate 10.

[0027] When a current is applied to the upper ring electrode 60 through the anode wiring 101 in the VCSEL 1B configured as described above, the current flows through the semiconductor resonator 30 via the upper ring electrode 60, and light is generated in the semiconductor resonator 30 as a result. Then, the light generated in the semiconductor resonator 30 resonates between the first DBR 20 and the second DBR 40 to cause laser oscillation, and the laser-oscillated light is emitted along the Z direction from the central opening of the upper ring electrode 60.

[0028] Next, the VCSEL 1A will be described. The VCSEL 1A is different from the VCSEL 1B in that it includes a semiconductor layer 80, and has the same configuration as the VCSEL 1B in other respects. That is, as shown in Fig. 2(a), the VCSEL 1A includes an n-type GaAs substrate 10, a first DBR 20, a semiconductor resonator 30, a second DBR 40, an insulating film 50, an upper ring electrode 60, a back electrode 70, and a semiconductor layer 80. The first DBR 20, the semiconductor resonator 30, the second DBR 40, the semiconductor layer 80, and the upper ring electrode 60 are laminated in this order on the first surface of the n-type GaAs substrate 10. The back electrode 70 is provided on the second surface of the n-type GaAs substrate 10 opposite to the first surface. Note that Fig. 2(a) is a cross-sectional view taken along the line V1-V1 of Fig. 1. Since the n-type GaAs substrate 10, the first DBR 20, the semiconductor resonator 30, the second DBR 40, the insulating film 50, the upper ring electrode 60, and the back electrode 70 have the same configuration as the above-described VCSEL 1B, detailed description thereof will be omitted.

[0029] The semiconductor layer 80 is for setting the resistance value (device resistance value) between the upper ring electrode 60 and the back electrode 70 of the VCSEL 1A to a value different from the resistance value between the upper ring electrode 60 and the back electrode 70 of the VCSEL 1B. The semiconductor layer 80 is provided between the upper ring electrode 60 and the second DBR 40. In other words, the semiconductor layer 80 is laminated on the side opposite to the semiconductor resonator 30 of the second DBR 40 in the Z direction. By having the semiconductor layer 80, the VCSEL 1A has a larger series resistance component between the upper ring electrode 60 and the second DBR 40 than the VCSEL 1B. That is, the VCSEL 1A is formed such that the distance between the upper ring electrode 60 and the back electrode 70 is longer than that of the VCSEL 1B, and due to this longer distance, the resistance value between the upper ring electrode 60 and the back electrode 70 is larger than that of the VCSEL 1B. The resistance value of the VCSEL 1A can be changed by changing the material, composition, and film thickness of the semiconductor layer 80.

[0030] As described above, the VCSEL 1A has the semiconductor layer 80 between the upper ring electrode 60 and the second DBR 40, while the VCSEL 1B does not have the semiconductor layer 80 between the upper ring electrode 60 and the second DBR 40. In other words, the VCSEL 1A has a predetermined thickness where the film thickness of the semiconductor layer 80 is greater than 0, while the VCSEL 1B has a film thickness of 0 for the semiconductor layer 80. As a result, the resistance values between the upper ring electrode 60 and the back electrode 70 of the VCSEL 1A and the VCSEL 1B are different from each other. Let the first resistance value between the upper ring electrode 60 and the back electrode 70 of the VCSEL 1A be R1, and the second resistance value between the upper ring electrode 60 and the back electrode 70 of the VCSEL 1B be R2. Then, R1 > R2. That is, the VCSEL 1A has a larger resistance value than the VCSEL 1B.

[0031] FIG. 3 is a diagram showing material examples of the semiconductor layer 80 and their various electrical characteristics. In the figure, the increase rate of the device resistance value indicates the increase rate of the resistance value per 1 μm thickness. Note that the doping concentration in each material is 1×10 17 cm -3is assumed. By disposing the semiconductor layer 80 on the second DBR 40, the resistance of the VCSEL 1A can be increased. As the semiconductor layer 80, from the side closer to the second DBR 40, AlInP with a carrier concentration of 1×10 17 cm -3 is laminated with a thickness of 0.38 μm, and on top of that, a two-layer structure is adopted with a GaAs contact layer having a thickness of 50 nm and a carrier concentration of 1×10 19 cm -3 . The thickness of the semiconductor layer 80 is preferably selected as an integer multiple of λc / 2 in order to suppress the optical influence caused by adding this layer. In the first embodiment, by setting the thickness of the AlInP layer to 403 nm, the optical film thickness of the semiconductor layer 80 is set to 3×λc / 2. With such a configuration, the resistance value of the VCSEL 1A can be made 1.33 times that of the resistance value of the VCSEL 1B.

[0032] In the VCSEL array 100, by devising the arrangement of two types of VCSELs 1A and 1B with different resistance values, the current injected into each of the VCSELs 1A and 1B is configured to be more uniform. Here, the plurality of VCSELs 1 are divided into a plurality of groups according to the wiring resistance between them and the anode power supply pad 102. For example, the plurality of VCSELs 1 can be divided into a plurality of groups according to the distance between them and the anode power supply pad 102. The plurality of groups can be constituted by, for example, a first group and a second group. The first group can be a group composed of VCSELs 1 that are closer to the anode power supply pad 102 than the second group. The second group can be a group composed of VCSELs 1 that are farther from the anode power supply pad 102 than the first group. Here, the VCSELs 1 included in the first group and the VCSELs 1 included in the second group have different resistance values from each other. That is, the VCSELs 1 included in the second group have a smaller resistance value than the VCSELs 1 included in the first group. In other words, the VCSELs 1 included in the first group have a larger resistance value than the VCSELs 1 included in the second group. In this way, the VCSELs in the group with a shorter distance from the anode power supply pad 102 are configured to have a larger resistance value. For example, the VCSELs in the group with a smaller wiring resistance between them and the anode power supply pad 102 are configured to have a larger resistance value. Specifically, the VCSELs in the first group, which are close to the anode power supply pad 102, are constituted by VCSELs 1A, and the VCSELs in the second group, which are far from the anode power supply pad 102, are constituted by VCSELs 1B. More specifically, as shown in FIG. 1, among the 20 VCSELs along the Y direction, the VCSELs in the first group from the 1st to the 6th, which are closer to the anode power supply pad 102, are constituted by VCSELs 1A. And the remaining VCSELs in the second group from the 6th to the 20th are constituted by VCSELs 1B.

[0033] FIG. 4 is a plan view showing a configuration example of a VCSEL array 900 according to a comparative example. As shown in FIG. 4, the VCSEL array 900 according to the comparative example is configured by using one type of VCSEL1B for all VCSELs (400 pieces) and arranged in an array. In the VCSEL array 900 according to the comparative example, when the interval between VCSEL1Bs is narrowed and arranged at a high density for reasons such as reduction of chip cost, it is difficult to thicken the wiring for supplying power to each VCSEL1B. For this reason, the VCSEL1B located far from the anode power supply pad 102 and having a long current path has a larger voltage drop due to the wiring resistance than the VCSEL1B located near the anode power supply pad 102. For this reason, the voltage applied between the anode and the cathode of the VCSEL1B decreases, and as a result, the amount of injected current decreases. Then, since the current injected into each VCSEL1B of the VCSEL array 900 becomes non-uniform, various adverse effects occur. For example, the input power increases to flow a predetermined current through the VCSEL1B having the minimum current, and the light amount of each VCSEL1B varies within the VCSEL array 900. As a result, in the case of a distance measurement application, the signal in the dark portion becomes weak. For this reason, the ratio of the signal to the noise in the light receiving portion becomes small and the distance measurement accuracy varies. In addition, in the case of an illumination application, various adverse effects such as affecting the illuminance unevenness in the plane occur.

[0034] In contrast, in the VCSEL array 100 according to the first embodiment, the VCSELs 1A in the first group with a high resistance value are arranged closer to the anode power supply pad 102 than the VCSELs 1B in the second group with a low resistance value. In other words, the current path from the anode power supply pad 102 to the high-resistance VCSEL 1A is shorter than the current path from the anode power supply pad 102 to the low-resistance VCSEL 1B. With this configuration, the resistance values of the respective VCSELs 1A and 1B including the resistance value of the anode wiring 101 can be made closer to each other. As a result, even if a voltage drop occurs due to the wiring resistance, the current injected into each of the VCSELs 1A and 1B can be made more uniform, and the spread of the current distribution can be suppressed. Here, the current distribution represents the distribution of the current values of the current injected into each VCSEL in the VCSEL array. Since the spread of the current distribution can be suppressed, the variation in the amount of light of each of the VCSELs 1A and 1B is suppressed, and thereby the uniformity of light emission in each of the VCSELs 1A and 1B can be improved. Due to the uniformity of light emission by each of the VCSELs 1A and 1B, the variation in the lifetime of each of the VCSELs 1A and 1B is also suppressed. Further, since the spread of the current distribution is suppressed, the input power to the VCSEL array 100 is reduced. In this way, the effect of the decrease in the input power due to the suppression of the spread of the current distribution is greater than the effect of the increase in the input power due to raising a part of the resistance. Furthermore, regarding the heat generation of the VCSEL array 100, since the amount of heat generation is proportional to the product of the first power of the resistance and the square of the current value, from the viewpoint of the amount of heat generation, the effect of the decrease in the current value due to the suppression of the spread of the current distribution is large.

[0035] FIG. 5 is a diagram showing the current distribution in each VCSEL array. In FIG. 5, the vertical axis represents the current value, and the horizontal axis represents the nth VCSEL counted from the side closer to the anode power supply pad 102 in one array (20 VCSELs 1 in one row). In FIG. 5, L2 is the current distribution of one array in the VCSEL array 100 according to the first embodiment. Note that FIG. 5 also shows the current distribution L1 of one array in the VCSEL array 900 according to the comparative example.

[0036] In the VCSEL array 900 according to the comparative example, the ratio of the maximum MAX to the minimum MIN of the current values of the currents flowing through each VCSEL 1B in one array is 0.63 (L1 in FIG. 5). Also, in the VCSEL array 900, when the minimum current value required for one VCSEL 1B is 0.06 A, estimating the current value required for one array considering the variation in the current values results in 1.44 A, and the input power is 7.29 W. On the other hand, in the VCSEL array 100 according to the first embodiment, the ratio of the maximum to the minimum of the current values of the currents flowing through each VCSEL 1A, 1B in one array is 0.76 (L2 in FIG. 5). Also, in the VCSEL array 100, when the minimum current value required for one VCSEL 1A, 1B is 0.06 A, estimating the current value required for one array considering the variation in the current values results in 1.33 A, and the input power is 6.70 W. Thus, since the ratio of the maximum to the minimum of the current values of the VCSEL array 100 is closer to 1.0 compared to the VCSEL array 900 according to the comparative example, the spread of the current distribution can be suppressed. Also, the VCSEL array 100 can reduce the current value required for one array and suppress the input power compared to the VCSEL array 900 according to the comparative example.

[0037] Next, a method for manufacturing the VCSEL array 100 including two types of VCSELs 1A and 1B will be described. FIG. 6 is a cross-sectional view showing a configuration example of an epitaxial wafer including an epitaxial growth portion. As shown in FIG. 6, first, a first DBR 20, a semiconductor resonator 30, a second DBR 40, an AlInP resistance layer 181 and a second p-type GaAs contact layer 182 that constitute a semiconductor layer 80 are sequentially epitaxially grown on an n-type GaAs substrate 10. Note that the uppermost layer of the second DBR 40 is a first p-type GaAs contact layer 180.

[0038] Next, the manufacturing process will be described with reference to FIGS. 7 and 8. FIGS. 7 and 8 extract and show the cross-sections of two VCSELs 1A and 1B in a portion where the VCSEL 1A and the VCSEL 1B are arranged adjacent to each other in the Y direction of FIG. 1, but the same manufacturing process is possible for other portions.

[0039] First, an SiOx layer 183 serving as a hard mask during dry etching is formed on the second p-type GaAs contact layer 182 by plasma CVD (Fig. 7(a)).

[0040] Next, the SiOx layer 183 is patterned by photolithography technology and wet etching technology. This pattern serves as a hard mask during dry etching (Fig. 7(b)).

[0041] Next, a mesa structure is formed by dry etching technology. When forming the mesa structure, the second DBR 40 including the second p-type GaAs contact layer 182, the AlInP resistance layer 181, and the first p-type GaAs contact layer 180 is etched. Further, the semiconductor resonator 30 is etched, and a part of the first DBR 20 is also etched. When it is desired to arrange the VCSELs 1 at a high density, it is preferable to make the sidewall angle of the mesa structure approach perpendicular to the n-type GaAs substrate 10. On the other hand, in the films formed on the sidewalls of the mesa structure such as the insulating film 50 and the anode wiring 101, when the step break due to the mesa step has an adverse effect on the device characteristics, the sidewall angle is preferably smaller than perpendicular. Therefore, the sidewall angle is appropriately selected by changing the etching conditions according to the required specifications and performance.

[0042] Next, heat treatment is performed in a water vapor atmosphere to selectively oxidize a part of the second DBR 40 from the mesa sidewall to form a current confinement layer 41 (Fig. 7(c)).

[0043] Next, a resist R having a resist opening is formed on the upper part of the VCSEL 1B by photolithography technology to selectively expose the SiOx layer 183 on the upper part of the VCSEL 1B (Fig. 7(d)).

[0044] Next, the SiOx layer 183 in the region with the resist opening is selectively etched by wet etching using buffered hydrofluoric acid. Further, the second p-type GaAs contact layer 182 is selectively etched with a citric acid-based etchant, and subsequently, the AlInP resistance layer 181 is selectively etched with a hydrochloric acid-based etchant (Fig. 7(e)). Thereafter, the resist pattern is removed once (Fig. 7(f)).

[0045] Next, by photolithography, a resist R having a resist opening is formed on the top of the VCSEL 1A to selectively expose the SiOx layer 183 on the top of the VCSEL 1A (Fig. 8(g)).

[0046] Next, the SiOx layer 183 in the region with the resist opening is selectively etched by wet etching using buffered hydrofluoric acid (Fig. 8(h)), and thereafter, the resist pattern is removed (Fig. 8(i)).

[0047] Next, an insulating film 50 is formed to cover the mesa structure, and an opening is formed in the insulating film 50 by photolithography and etching techniques. The upper ring electrode 60 and the anode wiring 101 are formed by photolithography, vacuum evaporation, and lift-off techniques, and an emission port is formed. Next, after polishing the back surface of the n-type GaAs substrate 10, a back surface electrode 70 is formed on the back surface side of the n-type GaAs substrate 10 (Fig. 8(j)).

[0048] By proceeding with the above steps, two types of VCSELs, namely, the VCSEL 1A having the semiconductor layer 80 including the AlInP resistance layer 181 and the VCSEL 1B not having the semiconductor layer 80, can be manufactured.

[0049] In this embodiment, an example in which the VCSEL 1B does not have the semiconductor layer 80 has been described, but the present invention is not limited thereto. Regarding the two types of VCSELs, the VCSEL 1A and 1B, the current distribution can be improved as compared with the comparative example by changing the resistance value. Specifically, in the VCSEL 1B, it may have a semiconductor layer 80 thinner than that of the VCSEL 1A. The same applies to the following embodiments.

[0050] In addition, in this embodiment, an example in which the power supply pad 102 is provided at one end of the anode wiring 101 in the Y direction has been described, but the present invention is not limited to this, and the power supply pad 102 may be provided at both ends of the anode wiring 101 in the Y direction. Even in that case, the arrangement of the VCSEL1A and VCSEL1B is the same with respect to the power supply pad 102. Specifically, the VCSEL1A may be arranged on the side closer to the power supply pad 102, and the VCSEL1B may be arranged on the side farther from the power supply pad 102 (the center of the array). The same applies to the following embodiments.

[0051] [Second Embodiment] Next, a VCSEL array 100A (not shown) according to the second embodiment will be described. The VCSEL array 100A according to the second embodiment includes three types of VCSELs 1A, 1Aa, and 1B having different resistance values from each other.

[0052] The resistance values between the upper ring electrode 60 and the back electrode 70 of the VCSEL1A, VCSEL1Aa, and VCSEL1B are different from each other. Let the first resistance value between the upper ring electrode 60 and the back electrode 70 of the VCSEL1A be R1, and the second resistance value between the upper ring electrode 60 and the back electrode 70 of the VCSEL1B be R2. Then, when the third resistance value between the upper ring electrode 60 and the back electrode 70 of the VCSEL1Aa is R3, R1 > R3 > R2. That is, the resistance value of the VCSEL1Aa is smaller than the resistance value of the VCSEL1A and larger than the resistance value of the VCSEL1B.

[0053] In the VCSEL1Aa, the semiconductor layer 80 is formed from the side closer to the second DBR40 with a thickness of 0.25 μm and a carrier concentration of 1×10 17 cm -3 of an AlInP layer, and a thickness of 50 nm and a carrier concentration of 1×10 19 cm -3The GaAs contact layer is a two-layer structure. The optical film thickness of the semiconductor layer 80 is λc. With this configuration, the resistance value of VCSEL1Aa is 1.2 times that of VCSEL1B. In VCSEL1A, the semiconductor layer 80 has a four-layer structure in which an AlInP layer and a GaAs contact layer similar to those of the semiconductor layer 80 of VCSEL1Aa are repeatedly stacked twice from the side closer to the second DBR40. The optical film thickness of the semiconductor layer 80 is 2×λc. With this configuration, the resistance value of VCSEL1A is 1.4 times that of VCSEL1B.

[0054] The plurality of VCSELs 1 are divided into three groups (first to third groups) according to the distance from the anode power supply pad 102. The third group is arranged between the first group and the second group. The third group is composed of VCSEL1Aa whose resistance value is smaller than that of VCSEL1A in the first group and larger than that of VCSEL1B in the second group. In this way, the VCSEL array 100A is configured such that the closer the group of VCSELs is to the anode power supply pad 102, the larger the resistance value of the VCSEL. That is, in descending order of resistance value, from the anode power supply pad 102, VCSEL1A in the first group, VCSEL1Aa in the third group, and VCSEL1B in the second group are arranged. Specifically, among the 20 VCSELs along the Y direction, the first to fourth VCSELs in the first group close to the anode power supply pad 102 are composed of VCSEL1A with the largest resistance value. Also, the fifth to ninth VCSELs in the third group are composed of VCSEL1Aa with the next largest resistance value, and the tenth to twentieth VCSELs in the second group are composed of VCSEL1B with the smallest resistance value.

[0055] In the VCSEL array 100A, the ratio of the maximum to the minimum of the current values of the currents flowing through each of the VCSELs 1A, 1Aa, and 1B is 0.86 (L3 in FIG. 5). Thus, the VCSEL array 100A according to the second embodiment can suppress the spread of the current distribution more than the VCSEL array 100 (L2 in FIG. 5) according to the first embodiment. In the VCSEL array 100A according to the second embodiment, when the minimum current value required for each VCSEL is 0.06 A, the input power is 6.35 W. Thereby, the VCSEL array 100A can reduce the input power as compared with the input power (6.70 W) of the VCSEL array 100 according to the first embodiment composed of two types of VCSELs.

[0056] Next, a method for manufacturing a VCSEL array 100A including three types of VCSELs 1A, 1Aa, and 1B according to the second embodiment will be described. In the second embodiment, compared with the case of manufacturing two types of VCSELs 1A and 1B according to the first embodiment, the semiconductor layer 80 has a four-layer structure at the epitaxial growth stage. FIG. 9 is a cross-sectional view showing a configuration example of an epitaxial wafer including an epitaxial growth portion.

[0057] As the semiconductor layer 80, as shown in FIG. 9, an AlInP resistance layer 181, a second p-type GaAs contact layer 182, an AlInP resistance layer 183a, and a third p-type GaAs contact layer 184 are epitaxially grown in this order.

[0058] As shown in Fig. 10, for VCSEL1B, the third p-type GaAs contact layer 184, AlInP resistance layer 183a, the second p-type GaAs contact layer 182, and AlInP resistance layer 181 are removed by etching. That is, for VCSEL1B, all of the semiconductor layer 80 is removed. For VCSEL1Aa, the third p-type GaAs contact layer 184 and AlInP resistance layer 183a are removed by etching, and the second p-type GaAs contact layer 182 and AlInP resistance layer 181 are left. That is, for VCSEL1Aa, a part of the semiconductor layer 80 is removed. For VCSEL1A, all of the layers constituting the semiconductor layer 80 are left. Thereby, three types of VCSEL1A, 1Aa, and 1B with different resistance values can be manufactured. In the second embodiment, VCSEL1A, 1Aa, and 1B do not have an arrangement where they are adjacent to each other as shown in Fig. 10. However, in Fig. 10, for the purpose of explaining the cross-sectional structure, three types of VCSELs with different resistances are illustrated side by side for convenience.

[0059] [Third Embodiment] Next, the VCSEL array 100B according to the third embodiment will be described. Fig. 11 is a plan view showing a configuration example of the VCSEL array 100B according to the third embodiment. The VCSEL array 100B according to the third embodiment includes VCSEL2A and VCSEL2B, which are different from VCSEL1A and VCSEL1B according to the first embodiment. Hereinafter, VCSEL2A and VCSEL2B will be described in detail. In the following description, the same components as those of VCSEL1A and VCSEL1B according to the first embodiment are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0060] The VCSEL array 100B includes, for example, as shown in Fig. 11, a plurality of VCSEL2s, an anode wiring 101, and an anode power supply pad 102. In Fig. 11, among the plurality of VCSEL2s connected to each anode wiring 101, four on one side in the Y direction and three on the other side in the Y direction are illustrated.

[0061] Twenty VCSEL2s are arranged in a single row along the Y direction, and twenty bundles of such arrangements in the Y direction are arranged along the X direction. As a result, a total of 400 (20 × 20) VCSEL2s are arranged in an array, forming a rectangular shape as a whole when viewed from the Z direction.

[0062] The anode wirings 101 are each provided so as to extend along the Y direction and a plurality of them are arranged side by side along the X direction. One anode wiring 101 is electrically connected to twenty VCSEL2s along the Y direction. And twenty such anode wirings 101 are arranged side by side along the X direction. Each anode wiring 101 supplies current to the twenty VCSEL2s connected in parallel.

[0063] In the VCSEL array 100B configured as described above, when current is supplied from the outside to the twenty anode power supply pads 102 via Au wires, the 400 VCSEL2s can be made to emit light. Note that, by sequentially supplying current from the outside to the twenty anode power supply pads 102, sequential driving can be performed in which each row emits light with a shifted timing.

[0064] Here, the VCSEL array 100B according to the third embodiment is configured to include a VCSEL2A and a VCSEL2B as a plurality of VCSEL2s. In the following description, when there is no particular need to distinguish between the VCSEL2A and the VCSEL2B, they may simply be referred to as "VCSEL2".

[0065] As shown in FIG. 12, the VCSEL 2A includes an n-type GaAs substrate 10, a first DBR 20, a semiconductor resonator 30, a second DBR 40, an insulating film 50, an upper ring electrode 60, and a back surface electrode 70. The VCSEL 2A further includes an ITO (Indium Tin Oxide) layer 90 as a transparent conductive film. The first DBR 20, the semiconductor resonator 30, the second DBR 40, the insulating film 50, the ITO layer 90, and the upper ring electrode 60 are stacked in this order on the first surface of the n-type GaAs substrate 10. The back surface electrode 70 is provided on the second surface of the n-type GaAs substrate 10 opposite to the first surface. Note that FIG. 12 is a cross-sectional view taken along line V1-V1 of FIG. 11. In FIG. 12, these members are in direct contact with each other in the VCSEL 2A, but other members may be provided therebetween. Also, the above description is an explanation of the structure and does not limit the manufacturing order of each member.

[0066] The semiconductor resonator 30 and the second DBR 40 are processed into a mesa shape, and an insulating film 50 is provided on the side surface and the upper surface of this mesa. Further, an ITO layer 90 is formed on the insulating film 50. That is, the ITO layer 90 covers the mesa-shaped semiconductor resonator 30 and the second DBR 40 from above the insulating film 50.

[0067] In the upper surface of the second DBR 40, a central portion of the insulating film 50 is partially removed, and in the removed portion, the ITO layer 90 is in contact with the upper surface of the second DBR 40. The portion where the insulating film 50 is removed is referred to as an "insulating opening". The shape of this insulating opening is, for example, a square, and the width of the insulating opening is represented by d2 (see FIG. 12). The ITO layer 90 is provided between the upper ring electrode 60 and the second DBR 40 and is in contact with the upper surface of the second DBR 40 in the insulating opening. Also, the upper ring electrode 60 is in electrical contact with a part of the ITO layer 90. The optical film thickness of the ITO layer 90 is λc / 2.

[0068] The second DBR 40 has, on its outermost layer, a thickness of 50 nm and a carrier concentration of 1×10 19 cm -3It has a GaAs contact layer (not shown) that improves the electrical contact with the ITO layer 90.

[0069] In the third embodiment, the resistance value is changed by changing the area where the GaAs contact layer of the second DBR 40 and the ITO layer 90 are in contact. Specifically, the contact area is changed by changing the width d2 of the insulating opening, and the amount of current flowing into the second DBR 40 is adjusted. For example, by relatively reducing the width d2 of the insulating opening, the contact area is reduced, thereby increasing the resistance value and reducing the amount of current flowing into the second DBR 40. On the other hand, by relatively increasing the width d2 of the insulating opening, the contact area is increased, thereby reducing the resistance value and increasing the amount of current flowing into the second DBR 40.

[0070] FIG. 13 is a diagram showing the relationship (calculation results and measured values) between the width d2 of the insulating opening and the resistance value. The horizontal axis in FIG. 13 is the width d2 of the insulating opening, and the vertical axis shows the relative resistance value when the resistance value when the width d2 of the insulating opening is 10.6 μm is set to 1.0. Here, as shown in FIG. 13, when d2 = 7.5 μm, the resistance value changes to 1.15 times, and when d2 = 20 μm, the resistance value changes to 0.93 times. Also, according to FIG. 13, it can be confirmed that the measured values also follow the calculation results. Note that if the insulating opening is located inside the non-oxidized region, the insulating opening may have an adverse effect on the light emitted from the VCSEL 2A. When this becomes a problem, it is desirable to set the width d2 of the insulating opening to be larger than the width d1 of the non-oxidized region. Note that the VCSEL 2B is configured in the same manner as the VCSEL 2A except that the width d2 of the insulating opening is different.

[0071] By adjusting the width d2 of the insulation opening of VCSEL2A, the contact area between the ITO layer 90 and the second DBR 40 in VCSEL2A is made smaller than the contact area between the ITO layer 90 and the second DBR 40 in VCSEL2B. As a result, if the first resistance value between the upper ring electrode 60 and the back electrode 70 of VCSEL2A is R1 and the second resistance value between the upper ring electrode 60 and the back electrode 70 of VCSEL2B is R2, then R1 > R2. That is, VCSEL2A has a larger resistance value than VCSEL2B. For example, based on FIG. 13, the width d2 of the insulation opening of VCSEL2A is set to 10.6 μm, and the width d2 of the insulation opening of VCSEL2B is set to 16.8 μm. At this time, the width d1 of the non-oxidized region of the current constriction layer 41 is 10.6 μm. When designed in this way, the resistance value of VCSEL2A becomes about 1.07 times that of VCSEL2B.

[0072] In the VCSEL array 100B, by devising the arrangement of two types of VCSELs 2A and 2B with different resistance values, the current injected into each of the VCSELs 2A and 2B is made more uniform. Here, the plurality of VCSELs 2 are divided into two groups (the first and second groups) according to the distance from the anode power supply pad 102. The VCSEL array 100B is configured such that the resistance value of the VCSEL in the group with a shorter distance from the anode power supply pad 102 is larger. Specifically, the VCSELs of the first group with a short distance from the anode power supply pad 102 are composed of VCSEL2A, and the VCSELs of the second group with a long distance from the anode power supply pad 102 are composed of VCSEL2B. More specifically, as shown in FIG. 11, among the 20 VCSELs along the Y direction, the first to fifth VCSELs of the first group close to the anode power supply pad 102 are composed of VCSEL2A with a large resistance value. And the remaining sixth to twentieth VCSELs of the second group are composed of VCSEL2B with a small resistance value.

[0073] FIG. 14 is a diagram showing the current distribution in each VCSEL array. In FIG. 14, the vertical axis represents the current value, and the horizontal axis represents the n-th VCSEL counted from the side closer to the anode power supply pad 102 in one array. In FIG. 14, L5 is the current distribution of one array in the VCSEL array 100B according to the third embodiment. Note that FIG. 14 also shows the current distribution L4 of one array in the VCSEL array according to the comparative example. The VCSEL array according to the comparative example is formed by one type of VCSEL 2B for all VCSELs (400 pieces) and arranged in an array.

[0074] In the VCSEL array according to the comparative example, the ratio of the maximum MAX to the minimum MIN of the current values of the currents flowing through each VCSEL 2B is 0.80 (L4 in FIG. 14). On the other hand, in the VCSEL array 100B according to the third embodiment, the ratio of the maximum to the minimum of the current values of the currents flowing through each VCSEL 2A, 2B is 0.86 (L5 in FIG. 14). Thereby, since the ratio of the maximum to the minimum of the current values of the VCSEL array 100B is closer to 1.0 compared to the VCSEL array 900 according to the comparative example, the spread of the current distribution can be suppressed. Also, in the VCSEL array of the comparative example, when the injection current amount into one array is adjusted so that the lowest current density injected into each VCSEL 2B becomes 20 kA / cm 2 or more, the input power is 90.4 mW (0.49 A). In the VCSEL array 100B of the third embodiment, when the injection current amount into one array is adjusted so that the lowest current density injected into each VCSEL 2A, 2B becomes 20 kA / cm 2 or more, the input power is 90.2 mW (0.48 A). From this, it can be seen that the VCSEL array 100B of the third embodiment can also reduce the power input to the array.

[0075] The VCSEL array 100B has the feature that, without increasing the number of epitaxial layers or the like as in the first embodiment, it is possible to simultaneously realize multiple types of VCSELs 2 only by changing the width d2 of the insulation opening on the photomask. Therefore, the VCSEL array 100B can have more than two types of widths d2 of the insulation opening without being limited to two types. On the other hand, compared with the VCSEL array 100 of the first embodiment, the VCSEL array 100B has a limited variable width of the width d2 of the insulation opening, so the amount of change in the resistance value becomes smaller.

[0076] [Fourth Embodiment] Next, the VCSEL array 100C according to the fourth embodiment will be described. The VCSEL array 100C according to the fourth embodiment is configured to include six types of VCSELs 2A, 2Aa1, 2Aa2, 2Aa3, 2Aa4, and 2B having different resistance values from each other. When the current value changes abruptly at the boundary between the VCSEL 2A and the VCSEL 2B as in the change in the current value (L5 in FIG. 14) of the VCSEL array 100B according to the third embodiment, the current distribution can be made smoother by finely setting the resistance value of each VCSEL 2. FIG. 15 is a plan view showing a configuration example of the VCSEL array 100C according to the fourth embodiment. The plurality of VCSELs 2 include six types of VCSELs 2 having different resistance values from each other, and are divided into six groups (first to sixth groups) according to the distance from the anode power supply pad 102. The VCSEL array 100C is configured such that the resistance value of the VCSEL in the group with a shorter distance from the anode power supply pad 102 is larger. Specifically, in order from the one closer to the anode power supply pad 102, it is composed of the VCSEL 2A of the first group, the VCSEL 2Aa1 of the second group, and the VCSEL 2Aa2 of the third group, one by one. Then, following the VCSEL 2Aa2 of the third group, it is composed of the VCSEL 2Aa3 of the fourth group and the VCSEL 2Aa4 (not shown) of the fifth group, and the 6th to 20th are composed of the VCSEL 2B of the sixth group.

[0077] In the VCSEL array 100C according to the fourth embodiment, as shown in FIG. 16, the width d2 of the insulation opening has the relationship of VCSEL2B > VCSEL2Aa4 > VCSEL2Aa3 > VCSEL2Aa2 > VCSEL2Aa1 > VCSEL2A. That is, the width d2 of the insulation opening becomes smaller as it is closer to the anode power supply pad 102. For this reason, the resistance values have the relationship of VCSEL2A > VCSEL2Aa1 > VCSEL2Aa2 > VCSEL2Aa3 > VCSEL2Aa4 > VCSEL2B, and the resistance values of the VCSELs in the group closer to the anode power supply pad 102 become larger. Thereby, the resistance values of the respective VCSELs 2 can be changed stepwise in a fine manner. As a result, compared with the VCSEL array 100B (L5 in FIG. 14), the VCSEL array 100C can reduce the ratio of the maximum to the minimum of the current values of the current flowing through each VCSEL 2 and can further suppress the spread of the current distribution (L6 in FIG. 14).

[0078] [Fifth Embodiment] Next, the VCSEL array 100D according to the fifth embodiment will be described. The VCSEL array 100D has short and high peak value pulse characteristics suitable for LiDAR. Here, Japanese Patent Application Laid-Open No. 2022-176886 describes a configuration using a saturable absorption layer or the like (hereinafter, also referred to as "high peak value VCSEL"). By combining this configuration of the high peak value VCSEL with a configuration that makes the current values more uniform, problems peculiar to the high peak value VCSEL can be solved.

[0079] As described in Japanese Patent Application Laid-Open No. 2022-176886, the high peak value VCSEL is characterized in that it can output an optical pulse with a pulse width of about several hundred ps and a high peak value at the start of oscillation, which is effective for improving the ranging distance and ranging accuracy of the LiDAR system.

[0080] On the other hand, high-peak-value VCSELs have a unique characteristic that the timing of pulse generation changes depending on the current density at the start of oscillation. FIG. 17 is a diagram showing the relationship between the current density and the pulse generation timing. In FIG. 17, the vertical axis represents the light intensity, and the horizontal axis represents the time. FIG. 18 is a diagram showing the relationship between the current density and the pulse delay time. In FIG. 18, the vertical axis represents the pulse delay time, and the horizontal axis represents the current density. As shown in FIGS. 17 and 18, when the current density is 21 to 29 kA / cm 2 a deviation in the pulse generation timing of 1.27 ns occurs.

[0081] Therefore, when a plurality of high-peak-value VCSELs are arrayed, if the current injected into each high-peak-value VCSEL becomes non-uniform, the light emission timing of each high-peak-value VCSEL will be different. For this reason, as the time change of the light intensity of the entire array, it becomes wider than the pulse width of the high-peak-value VCSEL, and there arises a problem that the merit as a LiDAR system decreases.

[0082] Therefore, by making the current more uniform, when high-peak-value VCSELs are arrayed, it is possible to suppress the deviation of the oscillation start timing within the VCSEL array. Also, it is possible to suppress an increase in the optical pulse width when the light from each VCSEL is combined by an optical system or the like.

[0083] FIG. 20 is a cross-sectional view showing a configuration example of the high-peak-value VCSEL 3A according to the fifth embodiment, for example, a cross-sectional view taken along the line V1-V1 in FIG. 19. The high-peak-value VCSEL 3A according to the fifth embodiment is denoted by the same reference numerals as the same components as those of the VCSEL 2A according to the fourth embodiment, and the detailed description thereof is omitted. The high-peak-value VCSEL 3A is different from the VCSEL 2A in that the barrier layer sandwiching the quantum well layer 31 is composed of a GaAs layer. Further, the high-peak-value VCSEL 3A is different from the VCSEL 2A in that it has a spacer layer 110 including a saturable absorption layer 111. The spacer layer 110 is provided inside the first DBR 20 (inside the first mirror). With this configuration, the high-peak-value VCSEL 3A can emit an optical pulse having a short and high peak value. In the fifth embodiment, the width d2 of the insulating opening of the high-peak-value VCSEL 3A is 10.4 μm, and the width d2 of the insulating opening of the high-peak-value VCSEL 3B is 16.8 μm. Thereby, the high-peak-value VCSEL 3A has a higher resistance value than the high-peak-value VCSEL 3B.

[0084] FIG. 19 is a plan view showing a configuration example of the VCSEL array 100D according to the fifth embodiment. The plurality of VCSELs 3 are divided into two groups (the first and second groups) according to the distance from the anode power supply pad 102. The VCSEL array 100D is configured such that the resistance value of the VCSEL in the group with a shorter distance from the anode power supply pad 102 is larger. Specifically, the VCSELs in the first group with a short distance from the anode power supply pad 102 are composed of high-peak-value VCSELs 3A, and the VCSELs in the second group with a long distance from the anode power supply pad 102 are composed of high-peak-value VCSELs 3B. More specifically, the first to fifth VCSELs in the first group close to the anode power supply pad 102 are composed of high-peak-value VCSELs 3A, and the remaining sixth to twentieth VCSELs in the second group are composed of high-peak-value VCSELs 3B.

[0085] With this configuration, the current injected into the high-peak VCSELs 3A and 3B can be made more uniform, and the deviation in the emission timing of the high-peak VCSELs 3A and 3B can be suppressed. By arraying, the optical output can be increased, and high pulses with a peak value of about several hundred ps generated by the high-peak VCSELs 3A and 3B can be properly used. Here, the current value injected into one array is adjusted so that the minimum current density is 20 kA / cm 2 or more. In this case, in the comparative example in which one array is composed of all the same high-peak VCSELs 3B, the maximum current density is 25.1 kA / cm 2 and the pulse delay time difference in one array is 1.07 ns. On the other hand, in the VCSEL array 100D according to the fifth embodiment, since one array is composed of the high-peak VCSELs 3A and 3B, the maximum current density is 23.3 kA / cm 2 and the pulse delay time difference in one array can be suppressed to 0.76 ns.

[0086] [Sixth Embodiment] Next, the VCSEL array 100E according to the sixth embodiment will be described. FIG. 21 is a plan view showing a configuration example of the VCSEL array 100E according to the sixth embodiment. The VCSEL array 100E according to the sixth embodiment includes VCSELs 4A and 4B, which are different from the VCSELs 1A and the like according to the first to fifth embodiments. Hereinafter, the VCSELs 4A and 4B will be described in detail. In the following description, the same components as those of the VCSELs 1A and the like according to the first to fifth embodiments are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

[0087] The VCSEL array 100E includes, for example, as shown in FIG. 21, a plurality of VCSELs 4, an anode wiring 101, and an anode power supply pad 102. In FIG. 21, among the plurality of VCSELs 4 connected to each anode wiring 101, four on one side in the Y direction and three on the other side in the Y direction are illustrated.

[0088] Twenty VCSELs 4 are arranged in a single row along the Y direction, and twenty bundles of such arrangements in the Y direction are arranged along the X direction. As a result, a total of 400 (20 × 20) VCSELs 4 are arranged in an array, and when viewed from the Z direction, they form a rectangular shape as a whole.

[0089] The anode wirings 101 each extend along the Y direction and are provided in a plurality side by side along the X direction. One anode wiring 101 is electrically connected to twenty VCSELs 4 along the Y direction. And twenty such anode wirings 101 are provided side by side along the X direction. Each anode wiring 101 supplies current to twenty VCSELs 4 connected in parallel.

[0090] In the VCSEL array 100B configured in this way, when current is supplied from the outside to the twenty anode power supply pads 102 via Au wires, the 400 VCSELs 4 can be made to emit light. Note that, by sequentially supplying current from the outside to the twenty anode power supply pads 102, sequential driving can be performed in which each row emits light with a shifted timing.

[0091] Here, the VCSEL array 100E according to the sixth embodiment is configured to include a VCSEL 4A and a VCSEL 4B as a plurality of VCSELs 4. In the following description, when there is no particular need to distinguish between the VCSEL 4A and the VCSEL 4B, they may simply be referred to as "VCSEL 4".

[0092] As shown in Fig. 22(b), the VCSEL 4B includes an n-type GaAs substrate 10, a first DBR 20, a semiconductor resonator 30, a second DBR 40, an insulating film 50, an upper ring electrode 60, and a back surface electrode 70. The first DBR 20, the semiconductor resonator 30, the second DBR 40, and the upper ring electrode 60 are stacked in this order on the first surface of the n-type GaAs substrate 10. The back surface electrode 70 is provided on the second surface of the n-type GaAs substrate 10 opposite to the first surface. In the VCSEL 4B, the semiconductor resonator 30 and the second DBR 40 are mesa-processed. Although these members are in direct contact with each other in Fig. 22(b), other members may be provided therebetween. Also, the above description is an explanation of the structure and does not limit the manufacturing order of each member. Note that (b) in Fig. 22 is a cross-sectional view taken along V2-V2 of Fig. 21.

[0093] Next, the VCSEL 4A will be described. The VCSEL 4A is configured in the same manner as the above-described VCSEL 4B. That is, as shown in Fig. 22(a), the VCSEL 4A includes an n-type GaAs substrate 10, a first DBR 20, a semiconductor resonator 30, a second DBR 40, an insulating film 50, an upper ring electrode 60, and a back surface electrode 70. The first DBR 20, the semiconductor resonator 30, the second DBR 40, and the upper ring electrode 60 are stacked in this order on the first surface of the n-type GaAs substrate 10. The back surface electrode 70 is provided on the second surface of the n-type GaAs substrate 10 opposite to the first surface. In the VCSEL 4A, the semiconductor resonator 30 and the second DBR 40 are mesa-processed. Note that (a) in Fig. 22 is a cross-sectional view taken along V1-V1 of Fig. 21.

[0094] Then, the size of the mesa of VCSEL4A is smaller than that of the mesa of VCSEL4B. That is, the width d2 of the mesa of VCSEL4A is narrower than the width d4 of the mesa of VCSEL4B. As a result, as shown in Fig. 22(a), the width d1 of the non-oxidized region of the current confinement layer 41 of VCSEL4A becomes narrower than the width d3 of the non-oxidized region of the current confinement layer 41 of VCSEL4B. This is because when oxidation is performed in the same manner on the same wafer, the oxidation distance from the mesa edge becomes almost the same. Since the current path within the mesa is restricted by the non-oxidized region of the current confinement layer 41, by making the non-oxidized region of VCSEL4A smaller than that of VCSEL4B, the current path can be made thinner, and the resistance value of VCSEL4A can be made larger than that of VCSEL4B.

[0095] Fig. 23 is a diagram showing the relationship between the area of the non-oxidized region of the current confinement layer 41 and the resistance value. In Fig. 23, the horizontal axis represents the area of the non-oxidized region of the current confinement layer 41, and the vertical axis represents the relative resistance value when the resistance value when the area of the non-oxidized region of the current confinement layer 41 is 300 μm 2 is set to 1.0. The width d3 of the non-oxidized region of VCSEL4B is 17.3 μm, that is, the non-oxidized region area is approximately 300 μm 2 is set, and the width d1 of the non-oxidized region of VCSEL4A is 15.1 μm, that is, the non-oxidized region area is approximately 227 μm 2 is set. In this case, the resistance value of VCSEL4A becomes 1.27 times that of VCSEL4B.

[0096] The plurality of VCSELs 4 are divided into two groups (the first and second groups) according to the distance from the anode power supply pad 102. The VCSEL array 100E is configured such that the resistance value of the VCSEL in the group with a shorter distance from the anode power supply pad 102 is larger. Specifically, the VCSELs in the first group with a short distance from the anode power supply pad 102 are composed of VCSELs 4A, and the VCSELs in the second group with a long distance from the anode power supply pad 102 are composed of VCSELs 4B. More specifically, as shown in FIG. 21, the first group of VCSELs from the 1st to the 7th closest to the anode power supply pad 102 are composed of VCSELs 4A with a large resistance value. The remaining second group of VCSELs from the 8th to the 20th are composed of VCSELs 4B with a small resistance value.

[0097] With this configuration, the current distribution of the VCSEL array 100E becomes the same as L3 shown in FIG. 5. Compared with the case where the array is composed of only one type of VCSEL 4B as in the comparative example (L1 shown in FIG. 5), the spread of the current distribution of the VCSEL array 100E can be suppressed. Further, by suppressing the spread of the current distribution, the amount of current required for the VCSEL array 100E can be reduced, and the input power can also be reduced.

[0098] [Seventh Embodiment] Next, the VCSEL array 100F according to the seventh embodiment will be described. The VCSEL array 100F according to the seventh embodiment is configured to include three types of VCSELs 4A, 4Aa, and 4B having different resistance values from each other, as shown in FIG. 24.

[0099] In the seventh embodiment, the width of the non-oxidized region of the VCSEL 4B is 17.3 μm, and the area of the non-oxidized region is 300 μm 2 . Also, the width of the non-oxidized region of the VCSEL 4A is 14.2 μm, and the area of the non-oxidized region is 203 μm 2 . Also, the width of the non-oxidized region of the VCSEL 4Aa is 15.8 μm, and the area of the non-oxidized region is 250 μm 2As a result, the resistance value of VCSEL4A becomes 1.40 times that of VCSEL4B, and the resistance value of VCSEL4Aa becomes 1.17 times that of VCSEL4B.

[0100] The plurality of VCSEL4s are divided into three groups (first to third groups) according to the distance from the anode power supply pad 102. The VCSEL array 100F is configured such that the resistance value of the VCSEL in the group with a shorter distance from the anode power supply pad 102 is larger. Specifically, as shown in FIG. 24, the first group of VCSELs from the first to the fourth closest to the anode power supply pad 102 are composed of VCSEL4A with the largest resistance value. Then, the third group of VCSELs from the fifth to the ninth are VCSEL4Aa with the next largest resistance value, and the second group of VCSELs from the tenth to the twentieth are composed of VCSEL4B with the smallest resistance value.

[0101] In this case, the current distribution of the VCSEL array 100F according to the seventh embodiment has a tendency substantially similar to L3 (see FIG. 5). Compared with the case where the array is composed of one type of VCSEL4B as in the comparative example (current distribution L1 in FIG. 5), the spread of the current distribution of the VCSEL array 100F can be suppressed. Also, by suppressing the spread of the current distribution, the amount of current required for the VCSEL array 100F is reduced, and the input power is also reduced. Thus, in the VCSEL array 100F, by increasing the types of resistance values of the VCSELs and appropriately setting the magnification and arrangement of each resistance value, the spread of the current distribution can be suppressed and the input power can be made small.

[0102] [Eighth Embodiment] Next, a 100G VCSEL array (not shown) according to the eighth embodiment will be described. The 100G VCSEL array according to the eighth embodiment has a configuration in which the width of the non-oxidized region of the VCSEL 4 is set in more stages to change the resistance value of the VCSEL 4 step by step. FIG. 25 is a diagram showing the relationship between the non-oxidized region and the resistance value of each VCSEL 4. The plurality of VCSELs 4 are divided into 14 groups (first to fourteenth groups) according to the distance from the anode power supply pad 102. The 100G VCSEL array is configured such that the resistance value of the VCSEL in the group with a shorter distance from the anode power supply pad 102 is larger. Specifically, as shown in FIG. 25, fourteen types of VCSELs 4 are arranged in groups such that the resistance value of the VCSEL 4 gradually increases as it approaches the anode power supply pad 102. In the 100G VCSEL array, for example, the maximum magnification of the resistance value is 1.53 times, and the width of its non-oxidized region is 13.5 μm.

[0103] FIG. 26 is a diagram showing the current distribution in the 100G VCSEL array. In FIG. 26, L8 is the current distribution of one array in the 100G VCSEL array according to the eighth embodiment. Note that FIG. 26 also shows the current distribution L7 of one array in the VCSEL array according to the comparative example. The VCSEL array according to the comparative example is formed by arranging all 400 VCSELs with one type of VCSEL 4 in an array. As shown in FIG. 26, the ratio of the maximum to the minimum of the current value of the current flowing through each VCSEL 4 in the 100G VCSEL array is 0.97 (L8 in FIG. 26), and it can be seen that the spread of the current distribution can be suppressed compared with the VCSEL array according to the comparative example (L7 in FIG. 26).

[0104] Furthermore, according to the VCSEL array 100G, in the manufacturing process, various types can be manufactured simultaneously only by changing the width of the mesa of the VCSEL 4 on the photomask. Also, when compared with the change amount of the resistance value of the VCSEL array 100B of the third embodiment, the change amount of the resistance value of the VCSEL array 100G can be increased. In the VCSEL array 100G, by appropriately increasing the types of resistance values more than the example shown in FIG. 25, it is also possible to make the ratio of the maximum to the minimum of the current value closer to 1.

[0105] Note that since the VCSEL array 100G changes the width of the non-oxidized region, the oscillation mode, FFP (Far Field Pattern), and current density distribution may affect the assumed usage conditions. In such a case, it is preferable to adopt a method such as suppressing the change of the non-oxidized region to a small extent by combining with other embodiments. In that case, instead of defining the resistance value by the length of the current path from the anode power supply pad 102, it is conceivable to define the resistance value of the VCSEL based on the current value actually applied to the VCSEL. Specifically, by arranging VCSELs with a high resistance value at locations with a high current value, the current distribution of the entire array can be made smoother.

[0106] [Embodiment 9] Next, the VCSEL array 100H according to the ninth embodiment will be described. FIG. 27 is a plan view showing a configuration example of the VCSEL array 100H according to the ninth embodiment. The VCSEL array 100H according to the ninth embodiment includes VCSELs 5A and 5B that are different from the VCSEL 1A etc. according to the first to eighth embodiments. Hereinafter, the VCSELs 5A and 5B will be described in detail. In the following description, the same components as those of the VCSEL 1A etc. according to the first to eighth embodiments are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0107] The VCSEL array 100H includes, for example, as shown in FIG. 27, a plurality of VCSELs 5, an anode wiring 101, and an anode power supply pad 102. In FIG. 27, among the plurality of VCSELs 5 connected to each anode wiring 101, four on one side in the Y direction and three on the other side in the Y direction are illustrated.

[0108] Twenty VCSELs 5 are arranged in a row along the Y direction, and a bundle of these 20 arrays in the Y direction is arranged in 20 arrays along the X direction. As a result, a total of 400 (20 × 20) VCSELs 5 are arranged in an array, and when viewed from the Z direction, the whole forms a rectangular shape.

[0109] The anode wirings 101 are each provided so as to extend along the Y direction and a plurality of them are arranged side by side along the X direction. One anode wiring 101 is electrically connected to 20 VCSELs 5 along the Y direction. And 20 such anode wirings 101 are arranged side by side along the X direction. Each anode wiring 101 supplies current to 20 VCSELs 5 connected in parallel.

[0110] The VCSEL array 100H configured in this way can cause 400 VCSELs 5 to emit light when current is supplied from the outside to 20 anode power supply pads 102 via Au wires. Note that, by sequentially supplying current from the outside to the 20 anode power supply pads 102, sequential driving can be performed in which each column emits light with a shifted timing.

[0111] Here, the VCSEL array 100H according to the ninth embodiment is configured to include a VCSEL 5A and a VCSEL 5B as the plurality of VCSELs 5. In the following description, when there is no need to particularly distinguish between the VCSEL 5A and the VCSEL 5B, they may simply be described as "VCSEL 5".

[0112] As shown in Fig. 28(b), the VCSEL 5B includes an n-type GaAs substrate 10, a first DBR 20, a semiconductor resonator 30, a second DBR 40, an insulating film 50, an upper ring electrode 60, and a back surface electrode 70. The first DBR 20, the semiconductor resonator 30, the second DBR 40, and the upper ring electrode 60 are stacked in this order on the first surface of the n-type GaAs substrate 10. The back surface electrode 70 is provided on the second surface of the n-type GaAs substrate 10 opposite to the first surface. Although these members are in direct contact in Fig. 28(b), other members may be provided therebetween. Further, the above description is an explanation of the structure and does not limit the manufacturing order of each member. Note that (b) of Fig. 28 is a cross-sectional view taken along line V2-V2 of Fig. 27.

[0113] Next, the VCSEL 5A will be described. The VCSEL 5A is different from the VCSEL 5B in that it has a proton implantation region 120, and has the same configuration as the VCSEL 5B in other respects. That is, as shown in Fig. 28(a), the VCSEL 5A includes an n-type GaAs substrate 10, a first DBR 20, a semiconductor resonator 30, a second DBR 40, an insulating film 50, an upper ring electrode 60, and a back surface electrode 70. The first DBR 20, the semiconductor resonator 30, the second DBR 40, and the upper ring electrode 60 are stacked in this order on the first surface of the n-type GaAs substrate 10. The back surface electrode 70 of the VCSEL 5A is provided on the second surface of the n-type GaAs substrate 10 opposite to the first surface. Note that (a) of Fig. 28 is a cross-sectional view taken along line V1-V1 of Fig. 27.

[0114] In the ninth embodiment, as a means for changing the resistance value, a proton implantation region 120 is provided. The proton implantation region 120 is provided in a part of the second DBR 40 of the VCSEL 5A. Thereby, in the current path flowing from the upper ring electrode 60 to the current constriction layer 41 in the VCSEL 5A, the carrier density in the second DBR 40 can be decreased, so that the resistance value can be increased compared to the VCSEL 5B.

[0115] As a specific method for forming the proton injection region 120, for example, the method disclosed in Japanese Patent Application Laid-Open No. 2021-136319 can be used. Here, as described in the third embodiment, in the VCSEL 2 having the ITO layer 90 on the upper part, since the current path approaches the mesa center, when the proton injection region 120 is provided for such a configuration, the resistance value can be efficiently increased. In the ninth embodiment, since the light absorption rate of the second DBR 40 also changes by injecting protons into the proton injection region 120, the extraction efficiency changes. Therefore, when it is desired to suppress the spread of the light quantity distribution in the array, it is desirable to design the arrangement of the VCSELs in the array in consideration of not only the current distribution but also the light quantity distribution.

[0116] As described above, the VCSEL 5A has the proton injection region 120 in the second DBR 40, while the VCSEL 5B does not have the proton injection region 120 in the second DBR 40. With this configuration, the resistance values between the upper ring electrode 60 and the back surface electrode 70 of the VCSEL 5A and the VCSEL 5B are different from each other. Let the resistance value between the upper ring electrode 60 and the back surface electrode 70 of the VCSEL 5A be R1, and the resistance value between the upper ring electrode 60 and the back surface electrode 70 of the VCSEL 5B be R2. Then, R1 > R2. That is, since the VCSEL 5A has the proton injection region 120, its resistance value is larger than that of the VCSEL 5B.

[0117] The plurality of VCSELs 5 are divided into two groups (the first and second groups) according to the distance from the anode power supply pad 102. The VCSEL array 100H is configured such that the resistance value of the VCSEL in the group with a shorter distance from the anode power supply pad 102 is larger. Specifically, the VCSELs in the first group with a short distance from the anode power supply pad 102 are composed of VCSEL 5A, and the VCSELs in the second group with a long distance from the anode power supply pad 102 are composed of VCSEL 5B. More specifically, as shown in FIG. 27, the first to fifth VCSELs in the first group closer to the anode power supply pad 102 are composed of VCSEL 5A with a large resistance value. And the remaining sixth to twentieth VCSELs in the second group are composed of VCSEL 5B with a small resistance value. The VCSEL array 100H can make the current injected into each of the VCSELs 5A and 5B more uniform by devising the arrangement of the two types of VCSELs 5A and 5B with different resistance values.

[0118] [Embodiment 10] Next, an example of applying the VCSEL array 100 to the SWIR (Short Wavelength Infrared Region) band will be described. FIG. 29 is a cross-sectional view showing a configuration example of the VCSEL array 100M according to the tenth embodiment.

[0119] The VCSEL array 100M includes the VCSEL array 100 of the first embodiment and the VCSEL chip 200, and has a configuration in which the VCSEL chip 200 is bonded on the VCSEL array 100.

[0120] The VCSEL chip 200 oscillates by optical excitation and, as shown in FIG. 29, includes a lower mirror 201 as a third mirror and a semiconductor resonator 202 as a second semiconductor resonator including a second active layer. Further, the VCSEL chip 200 includes an upper mirror 203 as a fourth mirror, an InP substrate 206, and an AR (Anti Reflection) coat 207. On the VCSEL array 100, the lower mirror 201, the semiconductor resonator 202, the upper mirror 203, the InP substrate 206, and the AR coat 207 are laminated in this order. The lower mirror 201 is composed of 7 pairs of alternating layers of SiO 2 and TiO 2 with an optical thickness of 1 / 4λc. The semiconductor resonator 202 includes an InGaAsP optical absorption layer 204 and a five-layer quantum well layer 205 composed of InGaAs with a thickness of 8 nm (only one layer is shown in the figure). The quantum well layer 205 is excited by the light of the first wavelength emitted from the VCSEL array 100. The upper mirror 203 is composed of an alternating layer of InP / InGaAsP with an optical thickness of 1 / 4λc. The upper mirror 203 is configured to have a lower reflectivity than the lower mirror 201. Therefore, the light of the second wavelength oscillated by the VCSEL chip 200 is taken out through the InP substrate 206. The AR coat 207 prevents reflection. Note that the light of the second wavelength is light with a wavelength different from that of the light of the first wavelength.

[0121] The VCSEL array 100 emits light with a wavelength of 940 nm, for example, to the VCSEL chip 200, and the VCSEL chip 200 absorbs the light passing through the lower mirror 201 by the InGaAsP optical absorption layer 204 in the semiconductor resonator 202. Electrons and holes are generated by the absorbed light, and when they enter the quantum well layer 205 and reach a density exceeding the transparent carrier density, gain occurs. In this way, laser oscillation occurs in the VCSEL chip 200 of the VCSEL array 100M, and laser light in the 1550 nm band is emitted.

[0122] In the VCSEL array 100M, among the plurality of anode wirings 101 that make up the VCSEL array 100, by selecting the energized anode wiring 101, the portion that emits light at a wavelength of 1550 nm can be selected. And with a configuration that suppresses the spread of the current distribution in the VCSEL array 100, while suppressing the spread of the emission intensity distribution of the VCSELs 1A and 1B that make up the VCSEL array 100, the space for wiring between the VCSELs 1A and 1B can be minimized. As a result, the VCSEL array 100M can reduce the chip size. The reduction of the chip size leads to the reduction of the chip cost, as well as the reduction of the size and cost of the optical system including the lens.

[0123] The VCSEL chip 200 on the side excited by light with a wavelength of 940 nm was a VCSEL in the 1550 nm wavelength band, but it is not limited to this. For example, it may be an LED or a VCSEL array that is excited by light with a wavelength of 940 nm and emits light in the 1900 nm wavelength band.

[0124] Also, although an example was shown in which the exciting VCSEL array is the VCSEL array 100 described in the first embodiment, the same effects can be obtained with the configurations described in the second to tenth embodiments. In any case, it has the effect of minimizing the wiring space and reducing the VCSEL chip size.

[0125] [11th Embodiment] Next, the distance measuring device 300 according to the 11th embodiment will be described. The distance measuring device 300 is, for example, a LiDAR that uses the VCSEL array 100 according to the first embodiment or the like as a light source unit.

[0126] As shown in FIG. 30, the distance measuring device 300 includes an overall control unit 310, a surface emitting laser array driver 320, a surface emitting laser array 330, a light emitting side optical system 340, a light receiving side optical system 350, a light receiving image sensor 360, and a distance data processing unit 370.

[0127] The overall control unit 310 is composed of an information processing device including a microcomputer and a logic circuit, etc., and has a function as a central processing device that controls the operations of each part and the operations in the distance measuring device 300 such as various arithmetic processes.

[0128] The surface emitting laser array driver 320 is a driving unit that receives a driving signal from the overall control unit 310, generates a driving current for the surface emitting laser array 330 to oscillate, and outputs the driving current to the surface emitting laser array 330.

[0129] The surface emitting laser array 330 is configured by mounting the VCSEL array described in the first to tenth embodiments on a package.

[0130] The light emitting side optical system 340 is an optical system that emits the laser light generated by the surface emitting laser array 330 toward the distance measuring target range.

[0131] The light receiving side optical system 350 is an optical system that guides the laser light reflected by the measurement object OJ included in the distance measuring target range to the light receiving image sensor 360. Note that the light emitting side optical system 340 and the light receiving side optical system 350 are represented by a single convex lens-shaped member in FIG. 30, but they are not composed of only a single convex lens system, but are composed of a lens group combining a plurality of lenses.

[0132] The light receiving image sensor 360 is, for example, a light receiving device in which CMOS (Complementary Metal - Oxide Semiconductor) optical sensors are arranged in an array. Also, the light receiving image sensor 360 may be a light receiving device in which SPAD (Single Photon Avalanche Diode) optical sensors are arranged in an array.

[0133] Based on the signal from the light-receiving image sensor 360, the distance data processing unit 370 functions as a distance information acquisition unit that generates information regarding the distance to the measurement object OJ existing within the distance measurement target range and outputs the generated information. The distance data processing unit 370 acquires information regarding the distance to the measurement object OJ based on, for example, the time difference between the timing when light is emitted from the surface-emitting laser array 330 and the timing when the light-receiving image sensor 360 receives the light. Note that the distance data processing unit 370 only needs to be electrically connected to the light-receiving image sensor 360, and it may be arranged within the same package as the light-receiving image sensor 360, or it may be arranged within a different package from the light-receiving image sensor 360.

[0134] Next, the operation of the distance measurement device 300 will be described. First, a drive signal is output from the overall control unit 310 to the surface-emitting laser array driver 320. In response to this drive signal, the surface-emitting laser array driver 320 outputs a drive current with a predetermined current value to the surface-emitting laser array 330 to oscillate the surface-emitting laser array 330. The laser light generated by the surface-emitting laser array 330 is emitted toward the measurement object OJ through the light-emitting side optical system 340, and the light reflected by the measurement object OJ enters the light-receiving image sensor 360 through the light-receiving side optical system 350. The light-receiving image sensor 360 converts the optical signal of the incident light into an electrical signal and outputs the converted electrical signal to the distance data processing unit 370. The distance data processing unit 370 calculates distance information based on the time difference between the timing when light is emitted from the surface-emitting laser array 330 and the timing when the light-receiving image sensor 360 receives the light, and generates three-dimensional information based on this distance information. The distance data processing unit 370 outputs the generated three-dimensional information to the overall control unit 310.

[0135] The distance measurement device 300 can be applied in the automotive field for controls such as preventing collisions with other vehicles and for autonomous driving while following other vehicles. Furthermore, the distance measurement device 300 can be used in moving bodies (mobile devices) such as ships, aircraft, or industrial robots, as well as in mobile body detection systems. Additionally, the distance measurement device 300 can be widely applied to devices that three-dimensionally recognize objects, including distance information.

[0136] Further, by using the three-dimensional information including the depth, the distance measuring device 300 can display a virtual object on the real world without a sense of incongruity in the image capturing device, the image processing device, and the display device. Further, the distance measuring device 300 can also be applied to a device that stores the three-dimensional information together with the image information and adds a function of correcting the blurriness or the like in the captured video after shooting.

[0137] [Modified Embodiment] The present invention is not limited to the above-described embodiments, and various modifications are possible. For example, an example in which a part of the configuration of any one of the embodiments is added to another embodiment or an example in which a part of the configuration of another embodiment is replaced is also an embodiment of the present invention.

[0138] For example, a semiconductor layer 80 and a proton implantation region 120 may be further provided for the VCSEL 2A having the ITO layer 90, or a semiconductor layer 80 and a proton implantation region 120 may be provided for the high peak value VCSEL 3A. Further, a semiconductor layer 80 and a proton implantation region 120 may be provided for the VCSEL 4A in which the width of the non-oxidized region of the current constriction layer 41 is different, or a semiconductor layer 80 may be further provided for the VCSEL 5A having the proton implantation region 120. In this way, the means for changing the resistance value may be appropriately combined. Thereby, the types of resistance of the VCSELs in the VCSEL array can be increased, and the spread of the current distribution can be further suppressed.

[0139] Further, a semiconductor layer 80 may be further provided for the VCSELs 3A and 3B in which the width of the non-oxidized region of the current constriction layer 41 is different, or a semiconductor layer 80 may be further provided for the high peak value VCSEL 3A. Thereby, the types of resistance of the VCSELs in the VCSEL array can be increased, and the spread of the current distribution can be further suppressed.

[0140] Further, the plurality of VCSELs may be configured to include at least two types of VCSELs among the VCSEL 1A, VCSEL 2A, VCSEL 3A, VCSEL 4A, and VCSEL 5A.

[0141] Also, although an example in which VCSEL1A has the semiconductor layer 80 between the upper ring electrode 60 and the second DBR 40 and VCSEL1B does not have the semiconductor layer 80 between the upper ring electrode 60 and the second DBR 40 has been shown, the present invention is not limited thereto. For example, each of VCSEL1A and VCSEL1B may have the semiconductor layer 80 between the upper ring electrode 60 and the second DBR 40, and the film thickness of the semiconductor layer 80 of VCSEL1A may be made thicker than the film thickness of the semiconductor layer 80 of VCSEL1B.

[0142] Also, although an example in which the VCSEL array is configured to include 400 VCSELs has been described, the number of VCSELs is not limited to these, and other numbers may be used.

[0143] Also, each embodiment has described a sequential anode wiring configuration in which the arrays that emit light simultaneously are in each row, but the present invention is not limited thereto. For example, the present invention is similarly applicable when the arrays that emit light simultaneously are in each of two rows, three rows, four or more rows. Further, for example, the present invention is similarly applicable to a flash-type anode wiring configuration in which the entire surface emits light simultaneously. Specifically, for example, when 20 arrays are arranged in the Y direction and 20 arrays are arranged in the X direction and the anode wiring is uniformly connected to all of them, the current injection amount at the center of the VCSEL array tends to be smaller than that on the outer side. Even in such a configuration, if the resistance value of the VCSEL on the side closer to the current path from the anode power supply pad 102 is R1 and the resistance value of the VCSEL on the far side is R2, the first to tenth embodiments are appropriately applied singly or in combination so that R1 > R2. Thereby, the spread of the current distribution of the entire array can be suppressed. Further, by increasing the types of resistors and appropriately arranging the VCSELs, the spread of the current distribution can be further suppressed.

[0144] Also, regarding the current constriction structure, although an example in which an oxidized constriction layer formed by selectively oxidizing a part of the semiconductor layer has been described, the present invention is not limited thereto. The current constriction structure may be formed by other methods such as ion implantation.

[0145] Also, although an example having the proton implantation region 120 in the second DBR 40 which is a P-type semiconductor has been described, the present invention is not limited thereto. For example, instead of protons, donor impurities having a hole compensation effect may be ion-implanted. Further, when the second DBR 40 is an N-type semiconductor, acceptor impurities having an electron compensation effect may be ion-implanted instead of protons.

[0146] Also, although an example in which both the semiconductor resonator 30 and the second DBR 40 are mesa-processed has been described for the VCSELs 4A and 4B, the present invention is not limited thereto, and at least the second DBR 40 may be mesa-processed.

[0147] The disclosure of the above embodiment includes the following configurations. (Configuration 1) A plurality of semiconductor light-emitting elements each having, on the side of the first surface of the semiconductor substrate, a first mirror, a first semiconductor resonator including a first active layer, a second mirror, and a first electrode in this order, and having a second electrode on the second surface of the semiconductor substrate opposite to the first surface; A power supply pad for supplying power to the plurality of semiconductor light-emitting elements; Wiring for connecting each of the plurality of semiconductor light-emitting elements to the power supply pad, The plurality of semiconductor light-emitting elements are divided into a plurality of groups each having at least one of the semiconductor light-emitting elements according to the distance from the power supply pad, The semiconductor light-emitting elements in the group having a shorter distance from the power supply pad are configured such that the resistance value between the first electrode and the second electrode becomes larger. A light source device characterized by the above. (Configuration 2) A plurality of semiconductor light-emitting elements each having, on the side of the first surface of the semiconductor substrate, a first mirror, a first semiconductor resonator including a first active layer, a second mirror, and a first electrode in this order, and having a second electrode on the second surface of the semiconductor substrate opposite to the first surface; A power supply pad for supplying power to the plurality of semiconductor light-emitting elements; Wiring for connecting each of the plurality of semiconductor light-emitting elements to the power supply pad, The plurality of semiconductor light-emitting elements are each divided into a plurality of groups, each having at least one of the semiconductor light-emitting elements, according to the length of the current path between the semiconductor light-emitting elements and the power supply pad, The semiconductor light-emitting elements in the group with a shorter current path length between the semiconductor light-emitting elements and the power supply pad are configured such that the resistance value between the first electrode and the second electrode is larger, A light source device characterized by this. (Configuration 3) The plurality of groups include a first group and a second group having semiconductor light-emitting elements with a resistance value smaller than that of the semiconductor light-emitting elements in the first group, The light source device according to Configuration 1 or 2, characterized by this. (Configuration 4) The plurality of groups include the first group, the second group, and a third group having semiconductor light-emitting elements with a resistance value smaller than that of the semiconductor light-emitting elements in the first group and larger than that of the semiconductor light-emitting elements in the second group, The third group is arranged between the first group and the second group, The light source device according to Configuration 3, characterized by this. (Configuration 5) The plurality of semiconductor light-emitting elements have a transparent conductive film between the first electrode and the second mirror, The light source device according to any one of Configurations 1 to 4, characterized by this. (Configuration 6) The plurality of semiconductor light-emitting elements have a saturable absorption layer in the first mirror, The light source device according to any one of Configurations 1 to 5, characterized by this. (Configuration 7) The semiconductor light-emitting elements in the first group are formed such that the distance between the first electrode and the second electrode is longer than that of the second semiconductor light-emitting element in the group, and because the distance is longer than that of the semiconductor light-emitting elements in the second group, the resistance value between the first electrode and the second electrode is larger than that of the semiconductor light-emitting elements in the second group, The light source device according to Configuration 3 or 4, characterized in that (Configuration 8) The contact area between the transparent conductive film and the second mirror in the semiconductor light emitting elements of the first group among the plurality of groups is smaller than the contact area between the transparent conductive film and the second mirror in the semiconductor light emitting elements of the second group among the plurality of groups The light source device according to Configuration 5, characterized in that (Configuration 9) At least the second mirror of the plurality of semiconductor light emitting elements is processed into a mesa shape, and the width of the mesa of the semiconductor light emitting elements of the first group is narrower than the width of the mesa of the semiconductor light emitting elements of the second group The light source device according to any one of Configurations 3, 4, 7, and 8, characterized in that (Configuration 10) The semiconductor light emitting elements of the first group have a proton implantation region in the second mirror, and by having the proton implantation region, the resistance value between the first electrode and the second electrode is larger than that of the semiconductor light emitting elements of the second group The light source device according to any one of Configurations 3, 4, 7, and 8, characterized in that (Configuration 11) On the side opposite to the first semiconductor resonator of the second mirror, there are a third mirror, a second semiconductor resonator including a second active layer, and a fourth mirror in this order The second active layer is excited by light of a first wavelength emitted from the plurality of semiconductor light emitting elements and emits light of a second wavelength different from the first wavelength The light source device according to any one of Configurations 1 to 10, characterized in that (Configuration 12) Each has, on the side of the first surface of the semiconductor substrate, a first mirror, a first semiconductor resonator including a first active layer, a second mirror, and a first electrode in this order, and a second electrode on the second surface opposite to the first surface of the semiconductor substrate, and a plurality of semiconductor light emitting elements A power supply pad for supplying power to the plurality of semiconductor light emitting elements Wiring for connecting each of the plurality of semiconductor light emitting elements to the power supply pad, and The plurality of semiconductor light-emitting elements are divided into a plurality of groups each having at least one of the semiconductor light-emitting elements according to the wiring resistance between the power supply pads, and the semiconductor light-emitting elements in the group with a smaller wiring resistance between the power supply pads are configured such that the resistance value between the first electrode and the second electrode is larger. A light source device characterized by the above. (Configuration 13) The plurality of semiconductor light-emitting elements have a saturable absorption layer in the first mirror. A light source device according to Configuration 5, characterized by the above. (Configuration 14) The plurality of groups include a first group and a second group having semiconductor light-emitting elements with a resistance value smaller than that of the semiconductor light-emitting elements in the first group. The semiconductor light-emitting elements in the first group are formed such that the distance between the first electrode and the second electrode is longer than that of the second semiconductor light-emitting elements in the group, and the longer distance results in a larger resistance value between the first electrode and the second electrode than that of the semiconductor light-emitting elements in the second group. A light source device according to Configuration 13, characterized by the above. (Configuration 15) The contact area between the transparent conductive film and the second mirror in the semiconductor light-emitting elements of the first group is smaller than the contact area between the transparent conductive film and the second mirror in the semiconductor light-emitting elements of the second group. A light source device according to Configuration 14, characterized by the above. (Configuration 16) At least the second mirror of the plurality of semiconductor light-emitting elements is processed into a mesa shape, and the width of the mesa of the semiconductor light-emitting elements in the first group is narrower than the width of the mesa of the semiconductor light-emitting elements in the second group. A light source device according to Configuration 15, characterized by the above. (Configuration 17) The semiconductor light-emitting element of the first group has a proton implantation region in the second mirror, and by having the proton implantation region, the resistance value between the first electrode and the second electrode is larger than that of the semiconductor light-emitting element of the second group. The light source device according to Configuration 16, characterized by the above. (Configuration 18) The light source device according to any one of Configurations 1 to 17, a light receiving device that receives the light emitted from the light source device and reflected by the measurement object, and a distance information acquisition unit that acquires information regarding the distance to the measurement object based on the time difference between the timing at which light is emitted from the light source device and the timing at which the light receiving device receives the light. The distance measurement device, characterized by the above.

Explanation of Signs

[0148] 1 to 7... VCSEL 10... n-type GaAs substrate 20... First DBR 30... Semiconductor resonator 31... Quantum well layer 40... Second DBR 41... Current constriction layer 50... Insulating film 60... Upper ring electrode 70... Back surface electrode 80... Semiconductor layer 90... ITO layer 100... VCSEL array 101... Anode wiring 102... Anode power supply pad 110... Spacer layer 111... Saturable absorption layer 120... Proton implantation region 200... VCSEL chip 300... Distance measurement device

Claims

1. A plurality of semiconductor light-emitting elements, each having, on the side of the first surface of a semiconductor substrate, a first mirror, a first semiconductor resonator including a first active layer, a second mirror, and a first electrode in this order, and having a second electrode on a second surface of the semiconductor substrate opposite to the first surface; A power supply pad for supplying power to the plurality of semiconductor light-emitting elements; Wiring for connecting each of the plurality of semiconductor light-emitting elements to the power supply pad; The plurality of semiconductor light-emitting elements are divided into a plurality of groups each having at least one of the semiconductor light-emitting elements according to the distance from the power supply pad; The semiconductor light-emitting elements in a group with a shorter distance from the power supply pad are configured such that the resistance value between the first electrode and the second electrode is larger. A light source device characterized by the above.

2. A plurality of semiconductor light-emitting elements, each having, on the side of the first surface of a semiconductor substrate, a first mirror, a first semiconductor resonator including a first active layer, a second mirror, and a first electrode in this order, and having a second electrode on a second surface of the semiconductor substrate opposite to the first surface; A power supply pad for supplying power to the plurality of semiconductor light-emitting elements; Wiring for connecting each of the plurality of semiconductor light-emitting elements to the power supply pad; The plurality of semiconductor light-emitting elements are divided into a plurality of groups each having at least one of the semiconductor light-emitting elements according to the length of the current path between the power supply pad; The semiconductor light-emitting elements in a group with a shorter length of the current path from the power supply pad are configured such that the resistance value between the first electrode and the second electrode is larger. A light source device characterized by the above.

3. The plurality of groups include a first group and a second group having semiconductor light-emitting elements with a resistance value smaller than that of the semiconductor light-emitting elements in the first group. The light source device according to claim 1 or 2, characterized by the above.

4. The plurality of groups include the first group, the second group, and a third group having semiconductor light-emitting elements with a resistance value smaller than that of the semiconductor light-emitting elements in the first group and larger than that of the semiconductor light-emitting elements in the second group, and the third group is disposed between the first group and the second group. The light source device according to claim 3, characterized by the above.

5. The plurality of semiconductor light-emitting elements have a transparent conductive film between the first electrode and the second mirror. The light source device according to claim 1 or 2, characterized in that...

6. The plurality of semiconductor light emitting elements have a saturable absorption layer in the first reflector. The light source device according to claim 1 or 2, characterized in that...

7. The semiconductor light emitting elements of the first group are formed such that the distance between the first electrode and the second electrode is longer than that of the second semiconductor light emitting elements of the group, and the resistance value between the first electrode and the second electrode is larger than that of the second group of semiconductor light emitting elements because the distance is longer than that of the second group of semiconductor light emitting elements. The light source device according to claim 3, characterized in that...

8. The contact area between the transparent conductive film and the second reflector in the semiconductor light emitting elements of the first group among the plurality of groups is smaller than the contact area between the transparent conductive film and the second reflector in the semiconductor light emitting elements of the second group among the plurality of groups. The light source device according to claim 5, characterized in that...

9. At least the second reflector of the plurality of semiconductor light emitting elements is processed into a mesa shape, and the width of the mesa of the semiconductor light emitting elements of the first group is narrower than the width of the mesa of the semiconductor light emitting elements of the second group. The light source device according to claim 3, characterized in that...

10. The semiconductor light emitting elements of the first group have a proton implantation region in the second reflector, and having the proton implantation region makes the resistance value between the first electrode and the second electrode larger than that of the second group of semiconductor light emitting elements. The light source device according to claim 3, characterized in that...

11. On the side opposite to the first semiconductor resonator of the second reflector, there are a third reflector, a second semiconductor resonator including a second active layer, and a fourth reflector in this order. The second active layer is excited by light of a first wavelength emitted from the plurality of semiconductor light emitting elements and emits light of a second wavelength different from the first wavelength. The light source device according to claim 1 or 2, characterized in that...

12. A plurality of semiconductor light emitting elements, each having a first reflector, a first semiconductor resonator including a first active layer, a second reflector, and a first electrode in this order on the side of the first surface of the semiconductor substrate, and having a second electrode on the second surface opposite to the first surface of the semiconductor substrate. A power supply pad for supplying power to the plurality of semiconductor light emitting elements. Wiring for connecting each of the plurality of semiconductor light emitting elements to the power supply pad. The plurality of semiconductor light-emitting elements are divided into a plurality of groups each having at least one of the semiconductor light-emitting elements according to the wiring resistance between the power supply pads, and the semiconductor light-emitting elements in the group with a smaller wiring resistance between the power supply pads are configured such that the resistance value between the first electrode and the second electrode becomes larger. A light source device characterized by this.

13. The plurality of semiconductor light-emitting elements have a saturable absorption layer in the first mirror. A light source device according to claim 5, characterized by this.

14. The plurality of groups include a first group and a second group having semiconductor light-emitting elements with a resistance value smaller than that of the semiconductor light-emitting elements in the first group, and the distance between the first electrode and the second electrode of the semiconductor light-emitting elements in the first group is formed longer than that of the second semiconductor light-emitting elements in the group, and the distance being longer than that of the semiconductor light-emitting elements in the second group causes the resistance value between the first electrode and the second electrode to be larger than that of the semiconductor light-emitting elements in the second group. A light source device according to claim 13, characterized by this.

15. The contact area between the transparent conductive film and the second mirror in the semiconductor light-emitting elements of the first group is smaller than the contact area between the transparent conductive film and the second mirror in the semiconductor light-emitting elements of the second group. A light source device according to claim 14, characterized by this.

16. At least the second mirror of the plurality of semiconductor light-emitting elements is processed into a mesa shape, and the width of the mesa of the semiconductor light-emitting elements in the first group is narrower than the width of the mesa of the semiconductor light-emitting elements in the second group. A light source device according to claim 15, characterized by this.

17. The semiconductor light-emitting elements in the first group have a proton implantation region in the second mirror, and having the proton implantation region causes the resistance value between the first electrode and the second electrode to be larger than that of the semiconductor light-emitting elements in the second group. A light source device according to claim 16, characterized by this.

18. A light source device according to any one of claims 1, 2, or 12, a light receiving device that receives light emitted from the light source device and reflected by a measurement object, and a distance information acquisition unit that acquires information regarding the distance to the measurement object based on the time difference between the timing when light is emitted from the light source device and the timing when the light receiving device receives the light. A distance measuring device characterized by this.

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