Power supply control device and image forming apparatus

Abstract

To reduce an inrush current.SOLUTION: An image forming apparatus 1 is provided with a DC / DC converter 36 which steps down a DC 24 V voltage as a first voltage inputted to an input terminal VIN to DC 5 V voltage as a second voltage and outputs it to an output terminal VOUT when an enable terminal voltage applied to an enable terminal EN is higher than a predetermined enable terminal threshold, a voltage divider circuit 44 that divides the DC 24 V voltage and applies it to the enable terminal EN of the DC / DC converter 36 as an enable terminal voltage, resistors 48, 52, and 54 for setting the voltage division ratio, which is the ratio of the enable terminal voltage to the DC 24 V voltage in the voltage division circuit 44, transistors 46 and 50, and a DC 24 V voltage, and an image forming unit 9 for forming an image on a sheet of paper.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a power control device and an image forming apparatus, and is suitable for application to, for example, an image forming apparatus having a power saving mode.

Background Art

[0002] Conventionally, in the normal operation mode, the voltage of 100 [V] of the commercial power supply is reduced to 24 [V] and supplied to a drive system load and a DC / DC converter for a control system load, and the DC / DC converter reduces the voltage of 24 [V] to 5 [V] and supplies it to the control system load. On the other hand, in the power saving mode, a power control device has been proposed that reduces the voltage of 100 [V] of the commercial power supply from 24 [V] to 9 [V] and supplies it to a drive system load and a DC / DC converter, and the DC / DC converter reduces the voltage of 9 [V] to 5 [V] and supplies it to the control system load (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In such a power control device having a DC / DC converter, it is desirable to reduce the inrush current of the input current to the DC / DC converter when the DC / DC converter outputs a voltage.

[0005] The present invention has been made in consideration of the above points, and intends to propose a power control device and an image forming apparatus capable of reducing the inrush current.

Means for Solving the Problems

[0006] In order to solve such problems, in the power control device of the present invention, when the terminal voltage applied to the terminal for controlling enable is higher than a predetermined threshold value, a step-down unit that steps down the first voltage input to the first path to the second voltage and outputs it to the second path, a voltage dividing circuit that divides the first voltage and applies it as the terminal voltage to the terminal of the step-down unit, and a voltage dividing ratio setting unit that sets a voltage dividing ratio, which is the ratio of the terminal voltage to the first voltage in the voltage dividing circuit, are provided.

[0007] Further, in the image forming apparatus of the present invention, when the terminal voltage applied to the terminal for controlling enable is higher than a predetermined threshold value, a step-down unit that steps down the first voltage input to the first path to the second voltage and outputs it to the second path, a voltage dividing circuit that divides the first voltage and applies it as the terminal voltage to the terminal of the step-down unit, a voltage dividing ratio setting unit that sets a voltage dividing ratio, which is the ratio of the terminal voltage to the first voltage in the voltage dividing circuit, and an image forming unit that forms an image on a medium are provided.

[0008] In the present invention, the first voltage can be made sufficiently high at the time when the step-down unit starts outputting the second voltage, and the inrush current flowing toward the step-down unit when the step-down unit starts outputting the second voltage can be suppressed.

Advantages of the Invention

[0009] According to the present invention, the first voltage can be made sufficiently high at the time when the step-down unit starts outputting the second voltage, and the inrush current flowing toward the step-down unit when the step-down unit starts outputting the second voltage can be suppressed. Thus, a power control device and an image forming apparatus capable of reducing the inrush current can be realized.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments for carrying out the invention (hereinafter referred to as embodiments) will be described with reference to the drawings.

[0012] [1. First Embodiment] [1-1. Overall Configuration of the Image Forming Apparatus] As shown in FIG. 1, the image forming apparatus 1 is a color electrophotographic printer that prints a desired color image on a sheet of paper having a size such as A3 size or A4 size. The image forming apparatus 1 is overall controlled by a control unit 4 composed of a CPU (Central Processing Unit), a ROM (Read Only Memory), and a RAM (Random Access Memory). The image forming apparatus 1 also controls the power supply by a power control device 30 mounted inside. Incidentally, hereinafter, the right end portion in FIG. 1 is defined as the front of the image forming apparatus 1, and the vertical direction, the horizontal direction, and the front-rear direction when viewed facing this front are defined and described. Also, hereinafter, a position close to the paper cassette 12 when viewed from an arbitrary position on the conveyance path where the paper is conveyed, or the direction toward the paper cassette 12 is called upstream, and the opposite position or direction is also called downstream.

[0013] The image forming apparatus 1 has three operation modes: a power saving mode, a sleep mode, and a normal operation mode. The power saving mode is a type of power saving mode and is a mode for suppressing the power consumption of the image forming apparatus 1. The sleep mode is a type of power saving mode and is a mode for further suppressing the power consumption of the image forming apparatus 1 compared to the power saving mode. The normal operation mode is an operation mode during the operation of the image forming apparatus 1 after the sleep mode is released, including an initial mode, a printing mode, or a standby mode. The image forming apparatus 1 reduces the power consumption by shifting from the normal operation mode to the power saving mode in a standby state without a print job. Further, when a certain time elapses with a timer after the image forming apparatus 1 shifts to the power saving mode, it shifts to an even lower power sleep mode. When the image forming apparatus 1 receives a print job in the power saving mode or the sleep mode, it returns from the power saving mode or the sleep mode to the normal operation mode.

[0014] The image forming apparatus 1 is also composed of a paper feeding unit 8, an image forming unit 9, a fixing unit 10, and a paper discharging unit 11. The paper feeding unit 8 includes a paper cassette 12 for storing paper, a pickup roller 13a, a separation roller 13b, and a paper feeding roller 13c for feeding the paper stored in the paper cassette 12, and registration rollers 14a and 14b for conveying the fed paper to the image forming unit 9.

[0015] The image forming unit 9 is provided above the paper cassette 12 in the image forming apparatus 1 and has a transfer belt 15, image forming units 16 (image forming units 16K, 16Y, 16M, and 16C), LED heads 17 (LED heads 17K, 17Y, 17M, and 17C), toner cartridges 18 (toner cartridges 18K, 18Y, 18M, and 18C), and transfer rollers 19 (transfer rollers 19K, 19Y, 19M, and 19C).

[0016] The transfer belt 15 is an endless belt stretched so as to go around rollers arranged one by one in the front-rear direction with the central axis oriented in the left-right direction. As it travels with the rotation of the rollers, it conveys the sheet received from the resist rollers 14a and 14b by placing it on the upper surface and transporting it rearward.

[0017] The four image forming units 16 (image forming units 16K, 16Y, 16M, and 16C (hereinafter, these are also collectively referred to as the image forming unit 16)) are arranged in order from the front side to the rear side above the transfer belt 15. That is, the image forming units 16 of each color are arranged in a so-called tandem system. The image forming units 16K, 16Y, 16M, and 16C respectively correspond to the colors black (K), yellow (Y), magenta (M), and cyan (C). Also, the image forming units 16K, 16Y, 16M, and 16C are similarly configured to each other, and only the colors of the corresponding toners are different from each other.

[0018] The LED heads 17K, 17Y, 17M, and 17C (hereinafter, these are also collectively referred to as the LED head 17) are provided so as to respectively correspond to the image forming units 16K, 16Y, 16M, and 16C. This LED head 17 is configured in a slender rectangular parallelepiped shape in the left-right direction, and a plurality of LEDs (Light Emitting Diodes) are arranged inside it along the left-right direction, and each LED is caused to emit light in a light emission pattern corresponding to the image data supplied from a head control unit (not shown). The image forming unit 16 is extremely close to this LED head 17, and an exposure process is performed by the light from the LED head 17.

[0019] Also, above each of the image forming units 16K, 16Y, 16M, and 16C, toner cartridges 18K, 18Y, 18M, and 18C (hereinafter, these are also collectively referred to as the toner cartridge 18) are provided respectively. The toner cartridge 18 is a hollow container long in the left-right direction, and each color of powdery toner is accommodated therein, and a predetermined agitation mechanism is incorporated.

[0020] At four positions directly below the respective image forming units 16K, 16Y, 16M, and 16C, transfer rollers 19K, 19Y, 19M, and 19C (hereinafter, these are also collectively referred to as transfer roller 19) are provided. That is, each image forming unit 16 sandwiches the upper portion of the transfer belt 15 between it and each transfer roller 19. Incidentally, the transfer roller 19 is configured to be chargeable.

[0021] The image forming unit 16 has a charging roller 20, a toner supply roller 21, a developing roller 22, and a photosensitive drum 23. The charging roller 20 uniformly charges the surface of the photosensitive drum 23 with a high voltage. The toner supply roller 21 supplies toner to the developing roller 22. The developing roller 22 develops the electrostatic latent image formed on the surface of the photosensitive drum 23 with the toner carried by the developing roller 22. The photosensitive drum 23 is a member that carries the electrostatic latent image on its surface (surface layer portion), and transfers the toner image developed on the surface of the photosensitive drum 23 to paper.

[0022] The fixing unit 10 is arranged on the downstream side of the image forming unit 9 and has a fixing roller 24, a heater 25, and a temperature detection sensor 26. The fixing roller 24 fixes the toner image transferred to the paper. The heater 25 is provided inside the fixing roller 24 and is, for example, a halogen lamp or a ceramic heater. The temperature detection sensor 26 is a thermistor that detects the surface temperature of the fixing roller 24. The paper discharge unit 11 has a discharge roller 27 that discharges the paper on which fixing has been completed to the outside of the image forming apparatus 1.

[0023] [1-2. Configuration of Power Control Device] As shown in FIG. 2, the power control device 30 mainly includes a low-voltage power supply 32, a DC / DC converter 36, and a control unit 4. The low-voltage power supply 32 operates when a voltage of 100 [V] is supplied from a commercial power supply (not shown), and outputs a 24V voltage DC24V, which is a first DC voltage, and a control unit supply voltage 5VS. This 24V voltage DC24V is a DC voltage of 24 [V], and is supplied to various drive system loads such as motors that operate when a DC voltage of 24 [V] is applied in the image forming apparatus 1. Also, the 24V voltage DC24V is input to the input terminal VIN of the DC / DC converter 36 via a fuse 34. The control unit supply voltage 5VS is a DC voltage of 5 [V], and is supplied to the control unit 4 in any of the normal operation mode, power save mode, and sleep mode of the image forming apparatus 1. Therefore, the control unit 4 operates in any of the normal operation mode, power save mode, and sleep mode. Also, when the image forming apparatus 1 is powered on, the control unit supply voltage 5VS rises earlier than the 24V voltage DC24V. For this reason, the basic terminal initial setting of the control unit 4 is performed before the 24V voltage DC24V rises.

[0024] A voltage dividing circuit 44 composed of resistors 38, 40, and 42 is connected to the input terminal VIN of the DC / DC converter 36. A voltage obtained by dividing the 24V voltage DC24V by the voltage dividing circuit 44 is applied as an enable terminal voltage to the enable terminal EN of the DC / DC converter 36. Hereinafter, the ratio (i.e., ratio) of the voltage output from the voltage dividing circuit 44 to the voltage applied to the voltage dividing circuit 44 is referred to as a voltage division ratio. That is, in the case of the power control device 30, the ratio of the enable terminal voltage to the 24V voltage DC24V is the voltage division ratio. Also, hereinafter, the resistor 38 is also referred to as a first resistance portion, and the resistors 40 and 42 are also referred to as a second resistance portion.

[0025] A transistor 46 is connected in parallel with a resistor 42 such that the collector terminal and the emitter terminal of the transistor 46 are connected to both ends of the resistor 42. An EN_CONT signal Sen as a voltage division ratio setting signal pulled up to 24 [V] at 24V DC voltage DC24V is input to the base terminal of the transistor 46 via a resistor 54. Therefore, when the EN_CONT signal Sen is at a high level, the transistor 46 turns on and a short circuit occurs between the resistor 40 and the ground which is the reference potential of 0V. As a result, the voltage division ratio becomes lower compared to the state where there is no short circuit between the resistor 40 and 0V. On the other hand, when the EN_CONT signal Sen is at a low level, the transistor 46 turns off and the resistor 42 exists between the resistor 40 and 0V. Therefore, the voltage division ratio becomes higher compared to the state where there is a short circuit between the resistor 40 and 0V. For this reason, when the 24V DC voltage DC24V is at a predetermined value, the enable terminal voltage becomes lower when the EN_CONT signal Sen is at a high level compared to when it is at a low level.

[0026] The DC / DC converter 36 performs DC / DC conversion on the 24V DC voltage DC24V input to the input terminal VIN and outputs a 5V DC voltage DC5V which is a second DC voltage from the output terminal VOUT. This 5V DC voltage DC5V is a DC voltage of 5 [V] and is supplied to various control system loads that operate when a 5 [V] DC voltage is applied in the image forming apparatus 1. Also, the 5V DC voltage DC5V is connected to the base terminal of the transistor 50 via a resistor 48. The base terminal of the transistor 50 is connected to 0V via a resistor 52. Also, the emitter terminal of the transistor 50 is connected to 0V. Furthermore, the collector terminal of the transistor 50 is connected to a resistor 54.

[0027] The DC / DC converter 36 turns on / off the output voltage from the output terminal VOUT with 1.2 [V] as the threshold value (also called the enable terminal threshold value) with respect to the enable terminal voltage. That is, when the enable terminal voltage is higher than 1.2 [V], the DC / DC converter 36 outputs a 5 V DC voltage, DC5V, from the output terminal VOUT. On the other hand, when the enable terminal voltage is less than 1.2 [V], the DC / DC converter 36 does not output a 5 V DC voltage, DC5V, from the output terminal VOUT.

[0028] Here, the resistor 38 has a resistance value of 100 [kΩ], the resistor 40 as the first resistor has a resistance value of 8.2 [kΩ], and the resistor 42 as the second resistor has a resistance value of 16 [kΩ].

[0029] When the EN_CONT signal Sen is at the Low level, the voltage division ratio as the first voltage division ratio is (8.2k + 16k) / (100k + 8.2k + 16k) ≒ 0.1948. Also, 1.2 [V] / 0.1948 ≒ 6.16 [V]. Therefore, when the 24 V DC voltage, DC24V, starts rising from 0 [V] and reaches 6.16 [V], the enable terminal voltage becomes 1.2 [V], which is the enable terminal threshold value. Hereinafter, the voltage value (6.16 [V]) of the 24 V DC voltage, DC24V, for the enable terminal voltage to become 1.2 [V], which is the enable terminal threshold value, when the EN_CONT signal Sen is at the Low level, is also called the low voltage side 5VON threshold voltage.

[0030] On the other hand, when the EN_CONT signal Sen is at the High level, the voltage division ratio as the second voltage division ratio is 8.2k / (100k + 8.2k) ≒ 0.0758. Also, 1.2 [V] / 0.0758 ≒ 15.8 [V]. Therefore, when the 24 V DC voltage, DC24V, starts rising from 0 [V] and reaches 15.8 [V], the enable terminal voltage becomes 1.2 [V], which is the enable terminal threshold value. Hereinafter, the voltage value (15.8 [V]) of the 24 V DC voltage, DC24V, for the enable terminal voltage to become 1.2 [V], which is the enable terminal threshold value, when the EN_CONT signal Sen is at the High level, is also called the high voltage side 5VON threshold voltage.

[0031] Also, hereinafter, the threshold value of the voltage value of the 24V voltage DC24V for the enable terminal voltage to become 1.2 [V], which is the enable terminal threshold value, is also called the 5VON threshold setting. Therefore, when the EN_CONT signal Sen is at the Low level, the 5VON threshold setting is set to the low voltage side 5VON threshold voltage. On the other hand, when the EN_CONT signal Sen is at the High level, the 5VON threshold setting is set to the high voltage side 5VON threshold voltage.

[0032] The control unit 4 outputs a 24VLOW-P signal Slp as a voltage value drop signal and inputs it to the 24VLOW-P terminal of the low voltage power supply 32. Here, when the control unit 4 sets the image forming apparatus 1 to the power save mode, by setting the 24VLOW-P signal Slp to the High level, the 24V voltage DC24V is reduced from 24 [V] to 8 [V] as the power saving voltage value. When the 24V voltage DC24V drops to 8 [V], the loss of the low voltage power supply 32 decreases and the low voltage power supply 32 becomes power saving, so the power consumption of the image forming apparatus 1 decreases. On the other hand, when the image forming apparatus 1 is not in the power save mode but in the normal operation mode, the control unit 4 sets the 24VLOW-P signal Slp to the Low level to make the 24V voltage DC24V 24 [V].

[0033] Also, the control unit 4 outputs a POWERSAVE-N signal Spsn and inputs it to the POWERSAVE-N terminal of the low voltage power supply 32. When the control unit 4 sets the image forming apparatus 1 to the sleep mode, by setting the POWERSAVE-N signal Spsn to the Low level, the 24V voltage DC24V is set to 0 [V] (that is, the output is stopped).

[0034] As described above, this control unit 4 operates by being supplied with the control unit supply voltage 5VS from the low voltage power supply 32 in any of the operation modes of the normal operation mode, the power save mode, and the sleep mode.

[0035] [1-3. Operation of Image Forming Apparatus] Fig. 3 shows the time chart of the power control device 30 in the sleep mode, normal operation mode, and power save mode, which are the operation modes of the image forming apparatus 1.

[0036] [1-3-1. Explanation of the entire time chart] In Fig. 3, the vertical axis represents the voltage value or current value, and the horizontal axis represents the passage of time. It shows six types of waveforms: the EN_CONT signal Sen, the POWERSAVE-N signal Spsn, the 24VLOW-P signal Slp, the 24V voltage DC24V, the 24V input current, and the 5V voltage DC5V.

[0037] The 5VON threshold setting is shown superimposed on the waveform of the 24V voltage DC24V. When the 24V voltage DC24V becomes higher than the 5VON threshold setting, the enable terminal voltage exceeds the enable terminal threshold of 1.2 [V]. The 24V input current is the current value of the current flowing from the low-voltage power supply 32 to the input terminal VIN of the DC / DC converter 36 when the DC / DC converter 36 starts the output of the 5V voltage DC5V.

[0038] Also, on the horizontal axis of Fig. 3, the case where the image forming apparatus 1 transitions in the order of the sleep mode, normal operation mode, and power save mode is shown.

[0039] Specifically, at time point T0, the image forming apparatus 1 is in the sleep mode. When the sleep mode is released at time point T1, the image forming apparatus 1 enters the initial mode and starts the warm-up operation. After a predetermined time has elapsed, it shifts to the print mode. Subsequently, at time point T5, the image forming apparatus 1 shifts from the normal operation mode to the power save mode.

[0040] [1-3-2. Operation] At time point T0 in the initial state, the image forming apparatus 1 is in the sleep mode, and since the control unit 4 outputs a Low-level POWERSAVE-N signal Spsn, the 24V voltage DC24V and the 5V voltage DC5V are 0 [V]. Further, the control unit 4 outputs a Low-level 24VLOW-P signal Slp. Furthermore, since the EN_CONT signal Sen is at a Low level because the 24V voltage DC24V which is pulled up is 0 [V], the 5VON threshold setting is set to the low-voltage side 5VON threshold voltage of 6.16 [V].

[0041] When, for example, a print job is received at time point T1, in order to return the image forming apparatus 1 from the sleep mode to the normal operation mode, the control unit 4 outputs a High-level POWERSAVE-N signal Spsn. For this reason, the 24V voltage DC24V starts to rise from 0 [V] toward 24 [V].

[0042] When the 24V voltage DC24V rises to about 0.7 [V] at time point T2, the EN_CONT signal Sen becomes High level and the transistor 46 turns ON because the 24V voltage DC24V which is pulled up has risen to 0.7 [V]. For this reason, the 5VON threshold setting switches to the setting of the high-voltage side 5VON threshold voltage of 15.8 [V].

[0043] Furthermore, when the 24V voltage DC24V rises further and exceeds the high-voltage side 5VON threshold voltage of 15.8 [V] at time point T3, the enable terminal voltage exceeds the enable terminal threshold of 1.2 [V], and the DC / DC converter 36 starts to operate, so the 5V voltage DC5V starts to rise from 0 [V] toward 5 [V].

[0044] When the DC / DC converter 36 starts outputting a 5V DC voltage (time point T3), an inrush current flows from the low-voltage power supply 32 towards the input terminal VIN of the DC / DC converter 36. At this time, since the 24V DC voltage is in a sufficiently high state of 15.8 [V] or more and the DC / DC converter 36 starts outputting a 5V DC voltage, the peak of the 24V input current does not increase and does not reach the point of blowing the fuse 34.

[0045] When the 5V DC voltage rises to about 0.7 [V] at time point T4, the transistor 50 turns ON, the EN_CONT signal Sen switches to the Low level, and the transistor 46 turns OFF. Therefore, the 5V ON threshold setting switches to the setting of the low-voltage side 5V ON threshold voltage of 6.16 [V].

[0046] When the printing of the print job is completed, at time point T5, in order to shift the image forming apparatus 1 from the normal operation mode to the power saving mode, the control unit 4 outputs a high-level 24V LOW-P signal Slp. Therefore, the 24V DC voltage starts to drop from 24 [V] towards 8 [V]. Also at this time, since the voltage value of the 24V DC voltage does not fall below the low-voltage side 5V ON threshold voltage of 6.16 [V], the 5V DC voltage is maintained at 5 [V].

[0047] [1-4. Effects, etc.] By the way, the power supply control device 30 can reduce the power consumption of the low-voltage power supply 32 and as a result reduce the power consumption of the image forming apparatus 1 by reducing the voltage applied from the low-voltage power supply 32 to the DC / DC converter 36 for the control system load in the power saving mode to a voltage lower than 24 [V]. However, when the voltage applied from the low-voltage power supply 32 to the DC / DC converter 36 is reduced, if the 5V ON threshold setting is a fixed value, when the voltage is output from the DC / DC converter 36 during the return from the power saving mode to the normal operation mode, the inrush current of the input current flowing from the low-voltage power supply 32 to the DC / DC converter 36 increases. In that case, for example, the life of the fuse 34 becomes short.

[0048] On the other hand, the power supply control device 30 divides the 24V voltage DC24V applied to the input terminal VIN of the DC / DC converter 36 by the voltage dividing circuit 44 and applies it as an enable terminal voltage to the enable terminal EN of the DC / DC converter 36.

[0049] Also, when the power supply control device 30 returns from the sleep mode to the normal operation mode, when the 24V voltage DC24V rises from 0 [V] to a certain extent (time point T2 (Fig. 3)), the EN_CONT signal Sen is set to the High level to turn on the transistor 46 and short-circuit the resistor 42, thereby reducing the voltage division ratio of the enable terminal voltage with respect to the 24V voltage DC24V.

[0050] As a result, the power supply control device 30 sets the 5VON threshold setting, which is the threshold value of the 24V voltage DC24V for the enable terminal voltage to become the enable terminal threshold of 1.2 [V], to 15.8 [V], which is the high voltage side 5VON threshold voltage. Therefore, when the 24V voltage DC24V rising from 0 [V] to 24 [V] becomes higher than the high voltage side 5VON threshold voltage of 15.8 [V], the enable terminal voltage becomes higher than the enable terminal threshold of 1.2 [V], so the DC / DC converter 36 starts to output 5V voltage DC5V (time point T3 (Fig. 3)). In this way, when the power supply control device 30 returns from the sleep mode to the normal operation mode, when the output of the DC / DC converter 36 changes from the off state to the on state, the 5VON threshold setting is set to 15.8 [V], which is the high voltage side 5VON threshold voltage, at a time point before the off-state DC / DC converter 36 starts to output.

[0051] Therefore, when the DC / DC converter 36 starts outputting the 5V voltage DC5V (time point T3 (Fig. 3)), the power control device 30 can set the 24V voltage DC24V to a sufficiently high state of 15.8 [V] or higher. As a result, when the DC / DC converter 36 starts outputting the 5V voltage DC5V (time point T3 (Fig. 3)), the power control device 30 can suppress the peak of the inrush current (24V input current (Fig. 3)) flowing from the low-voltage power supply 32 to the input terminal VIN of the DC / DC converter 36, prevent the fuse 34 from blowing, and prevent the reduction in the life of the fuse 34.

[0052] On the other hand, when the power control device 30 returns from the sleep mode to the normal operation mode, as the 24V voltage DC24V rises and the 5V voltage DC5V rises from 0 [V] (time point T4 (Fig. 3)), the EN_CONT signal Sen is set to the Low level to turn off the transistor 46 and the resistor 42 is not short-circuited, thereby increasing the voltage division ratio of the enable terminal voltage with respect to the 24V voltage DC24V.

[0053] As a result, the power control device 30 sets the 5VON threshold to 6.16 [V], which is the low-voltage side 5VON threshold voltage. Therefore, when the 24V voltage DC24V is higher than 6.16 [V], which is the low-voltage side 5VON threshold voltage, the enable terminal voltage becomes higher than 1.2 [V], which is the enable terminal threshold, so the DC / DC converter 36 maintains the output of the 5V voltage DC5V.

[0054] Therefore, when the power control device 30 shifts from the normal operation mode to the power save mode and inputs the High-level 24VLOW-P signal Slp from the control unit 4 to the low-voltage power supply 32 (time point T5 (Fig. 3)) to reduce the power consumption by reducing the 24V voltage DC24V from 24 [V] to 8 [V], the power control device 30 can keep the 24V voltage DC24V higher than the low-voltage side 5VON threshold voltage and maintain 5 [V] of the 5V voltage DC5V. As a result, the power control device 30 can continue to apply the 5V voltage DC5V to the control system load inside the image forming apparatus 1 while saving more power in the power save mode than in the normal operation mode.

[0055] According to the above configuration, when the enable terminal voltage, which is the terminal voltage applied to the enable terminal EN as a terminal for controlling enable in the image forming apparatus 1, is higher than the enable terminal threshold value as a predetermined threshold value, the DC / DC converter 36 steps down the 24V voltage DC24V, which is the first voltage input to the input terminal VIN as the first path, to the 5V voltage DC5V as the second voltage and outputs it to the output terminal VOUT as the second path, the voltage dividing circuit 44 that divides the 24V voltage DC24V and applies it to the enable terminal EN of the DC / DC converter 36 as the enable terminal voltage, and resistors 48, 52, and 54, transistors 46 and 50, and the 24V voltage DC24V that set the voltage division ratio, which is the ratio of the enable terminal voltage to the 24V voltage DC24V in the voltage dividing circuit 44, and the image forming unit 9 that forms an image on the paper as a medium are provided.

[0056] Thereby, the image forming apparatus 1 can make the 24V voltage DC24V in a sufficiently high state when the DC / DC converter 36 starts the output of the 5V voltage DC5V, and can suppress the inrush current flowing toward the DC / DC converter 36 when the DC / DC converter 36 starts the output of the 5V voltage DC5V.

[0057] [2. Second Embodiment] [2-1. Configuration of Image Forming Apparatus] As shown in FIG. 1, the image forming apparatus 101 according to the second embodiment is different from the image forming apparatus 1 according to the first embodiment in that it has a control unit 104 that replaces the control unit 4 and a power supply control device 130 that replaces the power supply control device 30, but is otherwise configured in the same manner.

[0058] [2-2. Configuration of Power Supply Control Device] As shown in FIG. 4, in which members corresponding to those in FIG. 2 are denoted by the same reference numerals, the power supply control device 130 according to the second embodiment is different from the power supply control device 30 according to the first embodiment in that the resistors 48, 52, and 54 and the transistor 50 are omitted, and the control unit 104 outputs an EN_CONT signal Sen from the EN_CONT signal output terminal PE and inputs it to the base terminal of the transistor 46, but is otherwise configured in the same manner.

[0059] Similar to the power supply control device 30 according to the first embodiment, when the EN_CONT signal Sen is at the Low level, when the 24V voltage DC24V reaches the low voltage side 5VON threshold voltage of 6.16 [V], the enable terminal voltage becomes the enable terminal threshold of 1.2 [V]. On the other hand, when the EN_CONT signal Sen is at the High level, when the 24V voltage DC24V reaches the high voltage side 5VON threshold voltage of 15.8 [V], the enable terminal voltage becomes the enable terminal threshold of 1.2 [V]. Therefore, when the control unit 104 sets the 5VON threshold to the low voltage side 5VON threshold voltage, it inputs the Low level EN_CONT signal Sen to the base terminal of the transistor 46. On the other hand, when the control unit 104 sets the 5VON threshold to the high voltage side 5VON threshold voltage, it inputs the High level EN_CONT signal Sen to the base terminal of the transistor 46.

[0060] [2-3. Operation of the Image Forming Apparatus] [2-3-1. Explanation of the Entire Time Chart] FIG. 5, in which parts corresponding to those in FIG. 3 are denoted by the same reference numerals, shows the time chart of the power supply control device 130 in the sleep mode, the normal operation mode, and the power save mode. Similar to the first embodiment, the horizontal axis in FIG. 5 shows the case where the image forming apparatus 101 transitions in the order of the sleep mode, the normal operation mode, and the power save mode.

[0061] Specifically, at time point T0, the image forming apparatus 101 is in the sleep mode. When the sleep mode is released at time point T11, the image forming apparatus 101 enters the initial mode and starts the warm-up operation. After a predetermined time has elapsed, it shifts to the printing mode. Subsequently, at time point T14, the image forming apparatus 101 shifts from the normal operation mode to the power save mode.

[0062] [2-3-2. Operation] At time point T0 which is the initial state, the image forming apparatus 101 is in the sleep mode. Since the control unit 104 outputs the Low-level POWERSAVE-N signal Spsn, the 24V voltage DC24V and the 5V voltage DC5V are 0 [V]. Also, the control unit 104 outputs the Low-level 24VLOW-P signal Slp. Furthermore, since the control unit 104 outputs the Low-level EN_CONT signal Sen, the 5VON threshold setting is set to the low voltage side 5VON threshold voltage of 6.16 [V].

[0063] When, for example, a print job is received at time point T11, prior to the 24V voltage DC24V reaching 24 [V], the control unit 104 outputs the High-level EN_CONT signal Sen, and the transistor 46 turns ON. For this reason, the 5VON threshold setting switches to the setting of the high voltage side 5VON threshold voltage of 15.8 [V].

[0064] After a predetermined time has elapsed, at time point T12, in order to return the image forming apparatus 101 from the sleep mode to the normal operation mode, the control unit 104 outputs the High-level POWERSAVE-N signal Spsn. For this reason, the 24V voltage DC24V starts to rise from 0 [V] towards 24 [V].

[0065] When the 24V voltage DC24V rises and exceeds the high voltage side 5VON threshold voltage of 15.8 [V] at time point T13, the enable terminal voltage exceeds the enable terminal threshold of 1.2 [V], and the DC / DC converter 36 starts to operate. Therefore, the 5V voltage DC5V starts to rise from 0 [V] towards 5 [V].

[0066] When the DC / DC converter 36 starts to output a 5V voltage DC5V (at time point T13), an inrush current flows from the low-voltage power supply 32 toward the input terminal VIN of the DC / DC converter 36. At this time, since the 24V voltage DC24V is in a sufficiently high state of 15.8 [V] or more and the DC / DC converter 36 starts to output a 5V voltage DC5V, the peak of the 24V input current does not increase and does not reach the point of blowing the fuse 34.

[0067] When the printing of the print job is completed, at time point T14, in order to shift the image forming apparatus 101 from the normal operation mode to the power save mode, the control unit 104 outputs a Low-level EN_CONT signal Sen, and the transistor 46 turns OFF. For this reason, the 5VON threshold setting switches to the setting of 6.16 [V], which is the low-voltage side 5VON threshold voltage.

[0068] After a predetermined time has elapsed, at time point T15, the control unit 104 outputs a High-level 24VLOW-P signal Slp. For this reason, the 24V voltage DC24V starts to drop from 24 [V] toward 8 [V]. Also at this time, since the voltage value of the 24V voltage DC24V does not fall below 6.16 [V], which is the low-voltage side 5VON threshold voltage, the 5V voltage DC5V is maintained at 5 [V].

[0069] [2-4. Effects, etc.] In the above configuration, the power supply control device 130 divides the 24V voltage DC24V applied to the input terminal VIN of the DC / DC converter 36 by the voltage dividing circuit 44 and applies it as an enable terminal voltage to the enable terminal EN of the DC / DC converter 36.

[0070] Also, when the power control device 130 resumes from the sleep mode to the normal operation mode, the control unit 104 outputs a high-level EN_CONT signal Sen (at time point T11 (Fig. 5)) to turn on the transistor 46 and short-circuit the resistor 42, so as to lower the voltage division ratio of the enable terminal voltage with respect to the 24V DC voltage DC24V. Thereby, the power control device 130 sets the 5VON threshold to 15.8 [V], which is the high-voltage side 5VON threshold voltage.

[0071] Therefore, when the DC / DC converter 36 starts to output the 5V DC voltage DC5V (at time point T13 (Fig. 5)), the power control device 130 can keep the 24V DC voltage DC24V at a sufficiently high level of 15.8 [V] or more. Thereby, when the DC / DC converter 36 starts to output the 5V DC voltage DC5V (at time point T13 (Fig. 5)), the power control device 130 can suppress the peak of the inrush current (24V input current (Fig. 5)) flowing from the low-voltage power supply 32 to the input terminal VIN of the DC / DC converter 36, prevent the fuse 34 from blowing, and prevent the fuse 34 from deteriorating in life.

[0072] On the other hand, when the power control device 130 shifts to the power save mode after resuming from the sleep mode to the normal operation mode, the control unit 104 outputs a low-level EN_CONT signal Sen (at time point T14 (Fig. 5)) to turn off the transistor 46 and not short-circuit the resistor 42, so as to increase the voltage division ratio of the enable terminal voltage with respect to the 24V DC voltage DC24V. Thereby, the power control device 130 sets the 5VON threshold to 6.16 [V], which is the low-voltage side 5VON threshold voltage.

[0073] Therefore, when the power control device 130 shifts from the normal operation mode to the power save mode, when the control unit 104 inputs the high-level 24VLOW-P signal Slp to the low-voltage power supply 32 (time point T15 (FIG. 5)) and reduces the 24V voltage DC24V from 24 [V] to 8 [V] to reduce power consumption, the 24V voltage DC24V is made higher than the low-voltage side 5VON threshold voltage, and the 5 [V] of the 5V voltage DC5V can be maintained. As a result, the power control device 130 can continue to apply the 5V voltage DC5V to the control system load inside the image forming apparatus 101 while saving more power in the power save mode than in the normal operation mode.

[0074] In addition to this, compared with the power control device 30, the power control device 130 can set the 5VON threshold setting to the high-voltage side 5VON threshold voltage during the period of the normal operation mode from the time when the DC / DC converter 36 starts to operate at time point T13 (FIG. 5) and the 5V voltage DC5V starts to rise from 0 [V] to 5 [V] until the control unit 104 outputs the low-level EN_CONT signal Sen at time point T14 (FIG. 5) and switches the 5VON threshold setting to the low-voltage side 5VON threshold voltage.

[0075] Therefore, for the power control device 130, for example, when an abnormality occurs in the low-voltage power supply 32 and the 24V voltage DC24V decreases, when it falls below the high-voltage side 5VON threshold voltage of 15.8 [V], which is earlier than falling below the low-voltage side 5VON threshold voltage of 6.16 [V], the output of the 5V voltage DC5V from the DC / DC converter 36 can be stopped.

[0076] In other respects as well, the power control device 130 according to the second embodiment can achieve the same operational effects as the power control device 30 according to the first embodiment.

[0077] [3. Third Embodiment] [3-1. Configuration of Image Forming Apparatus] As shown in FIG. 1, the image forming apparatus 201 according to the third embodiment is different from the image forming apparatus 101 according to the second embodiment in that it has a control unit 204 in place of the control unit 104 and a power control device 230 in place of the power control device 130, but is otherwise configured in the same manner.

[0078] [3-2. Configuration of Power Control Device] As shown in FIG. 6, in which members corresponding to those in FIG. 4 are denoted by the same reference numerals, the power control device 230 according to the third embodiment is different from the power control device 130 according to the second embodiment in that a resistor 68 is added and a main board 64 and a power supply board 66 are provided, but is otherwise configured in the same manner. The control unit 204 is composed of a main control unit 60 and a power control unit 62.

[0079] The main control unit 60 is mounted on the main board 64 on which the DC / DC converter 36 is mounted. This main control unit 60 operates when a 5V voltage DC5V is supplied from the output terminal VOUT of the DC / DC converter 36. Also, during the normal operation mode when the 5V voltage DC5V is supplied (i.e., when the main control unit 60 is powered on), the main control unit 60 keeps the open-drain EN_CONT signal output terminal PE in an open state. On the other hand, when the main control unit 60 shifts from the normal operation mode to the power save mode while the 5V voltage DC5V is supplied, it outputs a Low-level EN_CONT signal Sen from the EN_CONT signal output terminal PE and inputs it to the base terminal of the transistor 46. This EN_CONT signal Sen is pulled up to 24 [V] with a 24V voltage DC24V via the resistor 68. Therefore, while the 5V voltage DC5V is not supplied to the main control unit 60 (i.e., when the main control unit 60 is powered off), the EN_CONT signal Sen becomes High level. Further, the main control unit 60 outputs a 24VLOW-P signal Slp and inputs it to the 24VLOW-P terminal of the low-voltage power supply 32.

[0080] The power supply control unit 62 is mounted on a power supply board 66 on which a low-voltage power supply 32 is mounted, which is a board different from the main board 64 and is arranged separately from the main board 64, and is connected to the main board 64 by a signal line (not shown). This power supply control unit 62 operates by being supplied with a control unit supply voltage 5VS from the low-voltage power supply 32 in any of the normal operation mode, power save mode, and sleep mode of the image forming apparatus 201. Further, the power supply control unit 62 outputs a POWERSAVE-N signal Spsn based on the signal state from the main control unit 60 and inputs it to the POWERSAVE-N terminal of the low-voltage power supply 32.

[0081] Similar to the power supply control device 130 according to the second embodiment, when the EN_CONT signal Sen is at a Low level and the 24V voltage DC24V reaches the low-voltage side 5VON threshold voltage of 6.16 [V], the enable terminal voltage becomes the enable terminal threshold of 1.2 [V]. On the other hand, when the EN_CONT signal Sen is at a High level and the 24V voltage DC24V reaches the high-voltage side 5VON threshold voltage of 15.8 [V], the enable terminal voltage becomes the enable terminal threshold of 1.2 [V]. For this reason, when the main control unit 60 sets the 5VON threshold to the low-voltage side 5VON threshold voltage, it inputs the Low-level EN_CONT signal Sen to the base terminal of the transistor 46. On the other hand, when the main control unit 60 sets the 5VON threshold to the high-voltage side 5VON threshold voltage, it opens the EN_CONT signal output terminal PE and inputs the pulled-up High-level EN_CONT signal Sen to the base terminal of the transistor 46.

[0082] [3-3. Operation of the Image Forming Apparatus] [3-3-1. Explanation of the Entire Time Chart] FIG. 7, which is provided with the same reference numerals at the locations corresponding to FIG. 5, shows the time chart of the power supply control device 230 in the sleep mode, normal operation mode, and power save mode. Similar to the second embodiment, the horizontal axis in FIG. 7 shows the case where the image forming apparatus 201 transitions in the order of the sleep mode, normal operation mode, and power save mode.

[0083] Specifically, at time point T0, the image forming apparatus 201 is in the sleep mode. When the sleep mode is released at time point T21, the image forming apparatus 201 enters the initial mode and starts the warm-up operation. After a predetermined time has elapsed, it shifts to the printing mode. Subsequently, at time point T25, the image forming apparatus 201 shifts from the normal operation mode to the power save mode.

[0084] [3-3-2. Operation] At time point T0 which is the initial state, the image forming apparatus 201 is in the sleep mode, and since the power control unit 62 outputs the Low level POWERSAVE-N signal Spsn, the 24V voltage DC24V and the 5V voltage DC5V are 0 [V].

[0085] For example, when a print job is received at time point T21, in order to return the image forming apparatus 201 from the sleep mode to the normal operation mode, the power control unit 62 outputs the High level POWERSAVE-N signal Spsn. For this reason, the 24V voltage DC24V starts to rise from 0 [V] towards 24 [V].

[0086] When the 24V voltage DC24V rises to about 0.7 [V] at time point T22, the EN_CONT signal Sen becomes High level because the 24V voltage DC24V which is pulled up has risen to 0.7 [V], and the transistor 46 turns ON. For this reason, the 5VON threshold setting switches to the setting of the high voltage side 5VON threshold voltage which is 15.8 [V].

[0087] When the 24V voltage DC24V rises and exceeds the high voltage side 5VON threshold voltage which is 15.8 [V] at time point T23, the enable terminal voltage exceeds the enable terminal threshold which is 1.2 [V], and the DC / DC converter 36 starts to operate. For this reason, the 5V voltage DC5V starts to rise from 0 [V] towards 5 [V].

[0088] When the DC / DC converter 36 starts to output a 5V DC voltage (time point T23), an inrush current flows from the low-voltage power supply 32 towards the input terminal VIN of the DC / DC converter 36. At this time, since the 24V DC voltage is in a sufficiently high state of 15.8 [V] or more and the DC / DC converter 36 starts to output a 5V DC voltage, the peak of the 24V input current does not increase and does not cause the fuse 34 to blow.

[0089] When the 5V DC voltage reaches 5 [V] at time point T24, the main control unit 60 is powered on, and the EN_CONT signal output terminal PE is opened by the main control unit 60, so that the EN_CONT signal Sen maintains a High level.

[0090] When the printing of the print job is completed, at time point T25, in order to shift the image forming apparatus 201 from the normal operation mode to the power save mode, the main control unit 60 outputs a Low-level EN_CONT signal Sen, and the transistor 46 turns OFF. For this reason, the 5VON threshold setting switches to the setting of the low-voltage side 5VON threshold voltage of 6.16 [V].

[0091] After a predetermined time has elapsed, at time point T26, the main control unit 60 outputs a High-level 24VLOW-P signal Slp. For this reason, the 24V DC voltage starts to decrease from 24 [V] towards 8 [V]. Also at this time, since the voltage value of the 24V DC voltage does not fall below the low-voltage side 5VON threshold voltage of 6.16 [V], the 5V DC voltage is maintained at 5 [V].

[0092] Thus, the image forming apparatus 201 mounts the main control unit 60 and the power supply control unit 62 on different substrates. The main control unit 60 is operated by supplying a 5V DC voltage DC5V from the output terminal VOUT of the DC / DC converter 36, and the power supply control unit 62 is always operated by supplying a control unit supply voltage 5VS from the low-voltage power supply 32. Also, the image forming apparatus 201 outputs an EN_CONT signal Sen from the open-drain EN_CONT signal output terminal PE in the main control unit 60 and inputs it to the base terminal of the transistor 46, and the EN_CONT signal Sen is pulled up by a 24V DC voltage DC24V.

[0093] Therefore, the image forming apparatus 201 can be configured such that the main control unit 60 only needs to supply a 5V DC voltage DC5V by the DC / DC converter 36 without supplying the control unit supply voltage 5VS from the low-voltage power supply 32. Thereby, the image forming apparatus 201 can eliminate the need to supply the control unit supply voltage 5VS from the low-voltage power supply 32 mounted on the power supply board 66 to the main control unit 60 mounted on the main board 64 disposed at a position separated from the power supply board 66.

[0094] In other respects as well, the power supply control device 230 according to the third embodiment can achieve the same operational effects as the power supply control device 130 according to the second embodiment.

[0095] [4. Other Embodiments] Note that in the above-described embodiments, the cases where the image forming apparatuses 1, 101, and 201 constitute the voltage dividing circuit 44 by the resistors 38, 40, and 42 have been described. The present invention is not limited to this, and the image forming apparatuses 1, 101, and 201 may further add other resistors to the voltage dividing circuit 44.

[0096] Also, in the above-described embodiments, the image forming apparatuses 1, 101, and 201 have been described for the case where the transistor 46 is connected to both ends of the resistor 42 having a resistance value of 16 [kΩ], and the transistor 46 is turned on to short-circuit the resistor 42, thereby changing the voltage division ratio of the voltage division circuit 44. The present invention is not limited to this. The image forming apparatuses 1, 101, and 201 may arrange a variable resistor instead of the resistor 42 and change the voltage division ratio of the voltage division circuit 44 by changing the resistance value of the variable resistor.

[0097] Furthermore, in the above-described embodiments, the image forming apparatuses 1, 101, and 201 have been described for the case where the transistor 46 is connected to both ends of the resistor 42 having a resistance value of 16 [kΩ]. The present invention is not limited to this. The image forming apparatuses 1, 101, and 201 may set the resistance value of the resistor 40 to 16 [kΩ], set the resistance value of the resistor 42 to 20 [kΩ], and then connect the transistor 46 to both ends of the resistor 40.

[0098] Furthermore, in the above-described embodiments, the image forming apparatuses 1, 101, and 201 have been described for the case where the transistor 46 is connected to both ends of the resistor 42. The present invention is not limited to this. The image forming apparatuses 1, 101, and 201 may connect a FET (Field Effect Transistor) to both ends of the resistor 42.

[0099] Furthermore, in the above-described third embodiment, the image forming apparatus 201 has been described for the case where the 24VLOW-P signal Slp is input from the main control unit 60 to the low-voltage power supply 32. The present invention is not limited to this. The image forming apparatus 201 may output a command signal from the main control unit 60 to the power supply control unit 62, and based on the command signal, input the 24VLOW-P signal Slp from the power supply control unit 62 to the low-voltage power supply 32.

[0100] Furthermore, in the above-described embodiments, the case where the present invention is applied to the image forming apparatuses 1, 101, and 201 which are color printers has been described. The present invention is not limited to this, and for example, the present invention may be applied to other various image forming apparatuses having various functions and equipped with a power saving mode, such as an MFP (Multi Function Peripheral) having functions of a copying machine and a facsimile machine.

[0101] Furthermore, in the above-described embodiments, the case where the present invention is applied to the image forming apparatuses 1, 101, and 201 has been described. The present invention is not limited to this, and the present invention may be applied to various apparatuses that operate with AC power supplied from a commercial power source and are equipped with a power saving mode.

[0102] Furthermore, the present invention is not limited to the above-described embodiments and other embodiments. That is, the present invention applies to embodiments that arbitrarily combine a part or all of the above-described embodiments and the above-described other embodiments. Also, the present invention applies to embodiments in which a part of the configuration described in any of the above-described embodiments and other embodiments is extracted and replaced or diverted with a part of the configuration of any of the above-described embodiments and other embodiments, or embodiments in which a part of the extracted configuration is added to any of the embodiments.

[0103] Furthermore, in the first embodiment described above, the power control device 30 as a power control device is configured by the DC / DC converter 36 as a step-down unit, the voltage dividing circuit 44 as a voltage dividing circuit, and the resistors 48, 52, and 54, the transistors 46 and 50, and the 24V voltage DC24V as a voltage division ratio setting unit. In the second embodiment, the power control device 130 as a power control device is configured by the DC / DC converter 36 as a step-down unit, the voltage dividing circuit 44 as a voltage dividing circuit, and the control unit 104 and the transistor 46 as a voltage division ratio setting unit. In the third embodiment, the case where the power control device 230 as a power control device is configured by the DC / DC converter 36 as a step-down unit, the voltage dividing circuit 44 as a voltage dividing circuit, and the main control unit 60, the resistor 68, the transistor 46, and the 24V voltage DC24V as a voltage division ratio setting unit has been described. The present invention is not limited to this, and the power control device may be configured by a step-down unit, a voltage dividing circuit, and a voltage division ratio setting unit having various other configurations.

Industrial Applicability

[0104] The present invention can be used, for example, in an image forming apparatus supplied with power from a commercial power source.

Explanation of Reference Numerals

[0105] 1, 101, 201... Image forming apparatus, 4, 104, 204... Control unit, 8... Paper feeding unit, 9... Image forming unit, 10... Fixing unit, 11... Paper discharging unit, 12... Paper cassette, 13a... Pickup roller, 13b... Separation roller, 13c... Paper feeding roller, 14a, 14b... Registration roller, 15... Transfer belt, 16... Image forming unit, 17... LED head, 18... Toner cartridge, 19... Transfer roller, 20... Charging roller, 21... Toner supply roller, 22... Developing roller, 23... Photoconductor drum, 24... Fixing roller, 25... Heater, 26... Temperature detection sensor, 27... Discharge roller, 30, 130, 230... Power control device, 32... Low voltage power supply, 34... Fuse, 36... DC / DC converter, VIN... Input terminal, EN... Enable terminal, VOUT... Output terminal, 38, 40, 42, 48, 52, 54, 68... Resistor, 44... Voltage dividing circuit, 46, 50... Transistor, 5VS... Control unit supply voltage, Sen... EN_CONT signal, Spsn... POWERSAVE-N signal, Slp... 24VLOW-P signal, DC24V... 24V voltage, DC5V... 5V voltage, 60... Main control unit, 62... Power control unit, 64... Main board, 66... Power supply board, PE... EN_CONT signal output terminal.

Claims

1. When the terminal voltage applied to the terminal for controlling the enable is higher than a predetermined threshold value, a step-down unit that steps down the first voltage input to the first path to a second voltage and outputs it to the second path; A voltage dividing circuit that divides the first voltage and applies it as the terminal voltage to the terminal of the step-down unit; A voltage division ratio setting unit that sets a voltage division ratio, which is the ratio of the terminal voltage to the first voltage in the voltage dividing circuit A power supply control device having the above.

2. The voltage dividing circuit is set to a first voltage division ratio and a second voltage division ratio lower than the first voltage division ratio as the voltage division ratio, When the output of the step-down unit to the second path changes from the off state to the on state, the voltage division ratio setting unit sets the second voltage division ratio at a time point before the time when the step-down unit in the off state starts to output. The power supply control device according to claim 1.

3. The voltage division ratio setting unit, After the time when the step-down unit in the off state starts to output to the second path and before the time when the first voltage starts to decrease when shifting to the power saving state, the voltage division ratio is set from the second voltage division ratio to the first voltage division ratio. The power supply control device according to claim 2.

4. The voltage division ratio setting unit sets the voltage division ratio according to the output states of the first voltage in the first path and the second voltage in the second path. The power supply control device according to claim 1.

5. The voltage division ratio setting unit sets the voltage division ratio by outputting a voltage division ratio setting signal for setting the voltage division ratio from a control unit. The power supply control device according to claim 1.

6. The voltage dividing circuit is set to a first voltage division ratio and a second voltage division ratio lower than the first voltage division ratio as the voltage division ratio, When the output of the step-down unit to the second path changes from the off state to the on state when shifting to the normal operation mode, the control unit sets the second voltage division ratio at a time point before the time when the step-down unit in the off state starts to output. The power supply control device according to claim 5.

7. The control unit, When shifting from the normal operation state to the power saving state, outputs a voltage value decrease signal for decreasing the voltage value of the first voltage to the power saving voltage value with respect to the power supply that outputs the first voltage to the first path, The voltage value obtained by dividing the power saving voltage value by the voltage dividing circuit with the second voltage division ratio is higher than the threshold value. The power supply control device according to claim 6.

8. The voltage dividing circuit, a first resistor provided between the first path and the terminal; a second resistor provided between the terminal and a reference potential; which are configured; the voltage division ratio setting unit sets the voltage division ratio by adjusting a resistance value of the second resistor; The power supply control device according to claim 1.

9. the second resistor is composed of at least a first resistor and a second resistor connected in series between the terminal and the reference potential; the voltage division ratio setting unit sets the voltage division ratio by switching whether or not the second resistor is in a short-circuited state; The power supply control device according to claim 8.

10. a step-down unit that steps down a first voltage input to a first path to a second voltage and outputs the second voltage to a second path when a terminal voltage applied to a terminal for controlling enable is higher than a predetermined threshold value; a voltage division circuit that divides the first voltage and applies the divided voltage as the terminal voltage to the terminal of the step-down unit; a voltage division ratio setting unit that sets a voltage division ratio, which is a ratio of the terminal voltage to the first voltage, in the voltage division circuit; an image forming unit that forms an image on a medium An image forming apparatus having the above components.

Images