Semiconductor device and method for manufacturing semiconductor device

Abstract

To improve the property of writing to a semiconductor device.SOLUTION: A gate electrode 63 has at least one first recessed part 301. A part of a second charge laminate film 78 is buried in the at least one first recessed part 301.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.

Background Art

[0002] For example, Japanese Patent Application Laid-Open No. 2023-17387 (Patent Document 1) discloses a memory constituted by a semiconductor device. This memory includes a plurality of memory cells, and each memory cell includes a first gate electrode, a second gate electrode, and an integrated sidewall structure disposed between the first electrode gate electrode and the second gate electrode.

[0003] In this semiconductor device, charges during a writing operation to the semiconductor device (memory) are accumulated in the vicinity of the side portion of the first gate electrode and in the integrated sidewall structure. Accordingly, the conventional semiconductor device is a device that increases the amount of charge accumulation during a writing operation.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] A semiconductor device according to one aspect of the present disclosure includes a semiconductor layer, a first region, a second region, a channel region, a gate electrode, and a charge storage film. The semiconductor layer has a main surface. The first region is a region of a first conductivity type formed on the main surface. The second region is a region of the first conductivity type formed on the main surface and spaced apart from the first region in a second direction orthogonal to a first direction which is the thickness direction of the semiconductor layer. The channel region is a region of a second conductivity type formed between the first region and the second region on the main surface. The gate electrode is disposed to face the channel region. The charge storage film stores charges. The charge storage film is formed on the gate electrode when the gate electrode is viewed in a plan view from the first direction. At least one first recess is formed in the gate electrode. A part of the charge storage film is embedded in at least one first recess.

[0006] A method for manufacturing a semiconductor device according to one aspect of the present disclosure includes preparing a semiconductor layer having a main surface, forming a gate electrode and a charge storage film that stores charges, forming a first region of a first conductivity type and a second region of the first conductivity type on the main surface, and forming a channel region of a second conductivity type on the main surface. The second region is a region spaced apart from the first region in a second direction orthogonal to a first direction which is the thickness direction of the semiconductor layer. The channel region is a region formed between the first region and the second region on the main surface. The gate electrode is formed to face the channel region. At least one first recess is formed on the surface of the gate electrode. The charge storage film is formed on the gate electrode when the gate electrode is viewed in a plan view from the first direction. Forming the charge storage film includes embedding a part of the charge storage film in at least one first recess.

Brief Description of the Drawings

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[0008] <First Embodiment> [Perspective view of semiconductor device] FIG. 1 is a schematic perspective view of a semiconductor device 1 according to the present embodiment. In the present embodiment, the semiconductor device 1 is an analog LSI. The semiconductor device 1 includes a memory circuit 2 and a logic circuit 3 as components of a circuit of an LSI (Large Scale Integrated circuits). In the memory circuit 2, for example, a memory element (OTP: One-Time Programmable) that can write information (data) only once but cannot erase the information can be formed. Further, in the memory circuit 2, for example, a memory element (MTP: Multi-Time Programmable) that can write information (data) a plurality of times can be formed. Note that the semiconductor device 1 may be, for example, a chip-shaped LSI.

[0009] As shown in FIG. 1, the thickness direction of the semiconductor device 1 is also referred to as the Z-axis direction. Also, two axes orthogonal to the Z-axis direction are the X-axis direction and the Y-axis direction. The Z-axis direction corresponds to the "first direction" of the present disclosure. The X-axis direction corresponds to the "second direction" of the present disclosure. The Y-axis direction corresponds to the "third direction" of the present disclosure.

[0010] [Block diagram of semiconductor device 1] FIG. 2 is a block diagram showing the overall configuration of the memory circuit 2. As shown in FIG. 2, it includes a memory array 5 and a peripheral circuit 6. The memory array 5 is configured by being arranged in a matrix (= m × n). For example, m = 1024 and n = 1024. Thus, the memory array 5 includes a plurality of memory cells 4. In FIG. 2, one memory cell 4 is shown with hatching.

[0011] The memory cell 4 has a capacity in the kilobit order. Here, the kilobit order means 1K (kilo) bits or more and less than 1M (mega) bits. Note that the memory cell 4 may have a capacity in the megabit order or the gigabit order.

[0012] Also, in the example of FIG. 2, some rows and columns of the matrix-shaped memory cells 4 are omitted, and the omitted parts are indicated by "···". Also, a part of the bit lines BL and the word lines WL is omitted, and the omitted parts are indicated by "···".

[0013] The peripheral circuit 6 includes a first peripheral circuit 7 (peripheral circuit - X) and a second peripheral circuit 8 (peripheral circuit - Y). The first peripheral circuit 7 applies a predetermined gate voltage to a plurality (m) of word lines WL1 to WLm. The word lines WL1 to WLm extend in the X-axis direction (row direction). The second peripheral circuit 8 applies a predetermined drain voltage to a plurality (n) of word lines WL1 to WLn. The word lines WL1 to WLm extend in the Y-axis direction (column direction).

[0014] Hereinafter, the word lines WL1 to WLm and the bit lines BL1 to BLn may be referred to as the word line WL and the bit line BL, respectively. The word line WL and the bit line BL are provided in the same number as the number of memory cells 4 in the row direction (X-axis direction) and the column direction (Y-axis direction), respectively.

[0015] The logic circuit 3 is formed with arithmetic elements such as CMOS transistors, for example. The arithmetic elements calculate and output the information read from the memory cells 4 of the memory circuit 2.

[0016] [Structure of Memory Cell 4] FIG. 3 is a plan view of the memory cell 4 when viewed in a plan view from the Z-axis direction. FIG. 4 is a cross-sectional view taken along line X1-X1 of FIG. 3. The memory cell 4 of the semiconductor device 1 includes a semiconductor layer 9. The semiconductor layer 9 is formed of, for example, silicon. The semiconductor layer 9 may be composed of other materials (for example, silicon carbide (SiC), etc.). The semiconductor layer 9 may also be referred to as a semiconductor chip, a semiconductor substrate, or an epitaxial layer. For example, the semiconductor layer 9 may be an impurity-free single crystal chip.

[0017] The semiconductor layer 9 has a first main surface 10 and a second main surface 11 on the opposite side thereof. The first main surface 10 corresponds to the "main surface" of the present disclosure. The Z-axis direction is also the thickness direction of the semiconductor layer 9.

[0018] A p-type (second conductivity type) back gate region 12 is formed in the surface layer portion of the second main surface 11 of the semiconductor layer 9. The back gate region 12 is formed over the entire second main surface 11 of the semiconductor layer 9. The p-type impurity concentration of the back gate region 12 is, for example, 1×10 16 cm -3 or more and 1×10 19 cm -3 or less.

[0019] On the first main surface 10 side of the semiconductor layer 9, an element isolation portion 13 is formed. In this embodiment, the element isolation portion 13 partitions a memory cell region 14 in which each memory cell 4 is disposed. That is, the element isolation portion 13 insulates and separates adjacent memory cell regions 14. Each memory cell region 14 is surrounded by the element isolation portion 13. In FIG. 3, two adjacent memory cell regions 14 are shown. The memory cell region 14 in FIG. 3 may include a first memory cell region 14A and a second memory cell region 14B. The memory cells 4 disposed in the first memory cell region 14A and the second memory cell region 14B have the same transistor structure.

[0020] The element isolation portion 13 surrounding each memory cell region 14 is formed in a rectangular shape in a plan view from the Z-axis direction. This rectangular shape has a pair of long side portions (a first long side portion 15A and a second long side portion 15B) along the X-axis direction and a pair of short side portions (a first short side portion 16A and a second short side portion 16B) along the Y-axis direction. Also, the memory cell region 14 may be formed in a rectangular shape in a plan view that is, for example, longitudinally in the X-axis direction, in a plan view from the Z-axis direction.

[0021] The element isolation portion 13 includes a STI (Shallow Trench Isolation) structure. Specifically, the element isolation portion 13 includes a trench 17 and an insulator 18 embedded in the trench 17. The insulator 18 has a protruding portion 19 that protrudes upward with respect to the first main surface 10 of the semiconductor layer 9. Note that the element isolation portion 13 may be another element isolation structure such as a LOCOS oxide film or a DTI (Deep Trench Isolation) structure. Also, although not shown, the element isolation portion 13 may include a structure that separates the memory circuit 2 and the logic circuit 3.

[0022] In each memory cell region 14, a p-type well region 20 is formed in the surface layer portion of the first main surface 10 of the semiconductor layer 9. The well region 20 is a p-type impurity region. The p-type impurity concentration of the well region 20 is higher than the p-type impurity concentration of the back gate region 12. The p-type impurity concentration of the well region 20 is, for example, 1×10 16 cm-3 1×10 or less 19 cm -3 is as follows.

[0023] The bottom of the well region 20 is electrically connected to the back gate region 12. In FIG. 4, for clarity of the concentration difference between the well region 20 and the back gate region 12, “p+” is indicated in the well region 20 and “p” is indicated in the back gate region 12. Note that “p+” and “p” do not indicate specific concentration ranges.

[0024] The well region 20 is formed deeper than the trench 17 and partially covers the bottom walls of both the trench 17 of the first long side portion 15A, the second long side portion 15B and the first short side portion 16A, the second short side portion 16B of the element isolation portion 13. Thereby, the well region 20 is formed over the entire memory cell region 14. The well region 20 may be formed in a region on the first main surface 10 side with respect to the bottom wall of the trench 17, different from the structure shown in FIG. 4. In this case, the boundary between the well region 20 and the back gate region 12 is located between the bottom wall of the trench 17 and the first main surface 10.

[0025] In the surface layer portion of the well region 20, a first region 21 of the first conductivity type and a second region 22 of the first conductivity type are formed to be separated from each other in the X-axis direction. In the present embodiment, the first conductivity type is an n-type. Also, the second conductivity type described later is a p-type.

[0026] The first region 21 and the second region 22 are n-type impurity regions. The n-type impurity concentrations of the first region 21 and the second region 22 may be equal to each other or different from each other. For example, the n-type impurity concentrations of the first region 21 and the second region 22 are, for example, 1×10 19 cm -3 1×10 or more 22 cm -3The following is the case. In FIG. 4, for the purpose of clarifying the concentration difference between the first region 21 and the second region 22 and the first low-concentration impurity region 26 and the second low-concentration impurity region 27, which will be described later, "n+" is indicated in the first region 21 and the second region 22. "n+" does not indicate a specific concentration range.

[0027] Referring to FIG. 3, the boundary portion between the first region 21 and the well region 20 is defined as the first boundary portion 23. The first boundary portion 23 is a linear portion extending from the first long side portion 15A to the second long side portion 15B. The first region 21 is formed in a rectangular shape (quadrilateral shape) in plan view, which is partitioned by the first boundary portion 23, the first long side portion 15A, the second long side portion 15B, and the first short side portion 16A.

[0028] The first region 21 extends in the X-axis direction from the first short side portion 16A of the element isolation portion 13 toward the second short side portion 16B. The first region 21 has ends at the first long side portion 15A and the second long side portion 15B, respectively, in the X-axis direction. As a result, the first region 21 is formed over the entire length from the first long side portion 15A to the second long side portion 15B in the Y-axis direction.

[0029] The boundary portion between the second region 22 and the well region 20 is defined as the second boundary portion 24. The second boundary portion 24 is a linear portion extending from the first long side portion 15A to the second long side portion 15B. The second region 22 is formed in a rectangular shape (quadrilateral shape) in plan view, which is partitioned by the second boundary portion 24, the first long side portion 15A, the second long side portion 15B, and the second short side portion 16B.

[0030] The second region 22 extends in the X-axis direction from the second short side portion 16B of the element isolation portion 13 toward the first short side portion 16A. The second region 22 has ends at the first long side portion 15A and the second long side portion 15B, respectively, in the Y-axis direction. As a result, the second region 22 is formed over the entire length from the first long side portion 15A to the second long side portion 15B in the Y-axis direction.

[0031] In the surface portion of the well region 20, the region between the first region 21 and the second region 22 is a channel region 25 where an n-type channel is formed. The channel region 25 is formed of a part of the p-type portion of the well region 20.

[0032] One of the first region 21 and the second region 22 is a source region, and the other is a drain region. Which of the first region 21 and the second region 22 is the source region and which is the drain region is defined by the direction in which charge flows when data is written to the semiconductor device 1 (memory).

[0033] For example, when writing data, if the first region 21 is set as a reference voltage (e.g., 0 V) and a positive voltage is applied to the second region 22 with respect to the reference voltage, the electrons induced in the p-type channel region 25 flow from the first region 21 toward the second region 22. In this case, the first region 21 is the source region and the second region 22 is the drain region.

[0034] On the other hand, if the second region 22 is set as a reference voltage (e.g., 0 V) and a positive voltage is applied to the first region 21 with respect to the reference voltage, the electrons induced in the p-type channel region 25 flow from the second region 22 toward the first region 21. In this case, the second region 22 is the source region and the first region 21 is the drain region.

[0035] In the surface portion of the well region 20, an n-type (first conductivity type) first low-concentration impurity region 26 and an n-type (first conductivity type) second low-concentration impurity region 27 are formed. The first low-concentration impurity region 26 and the second low-concentration impurity region 27 are n-type impurity regions. The n-type impurity concentrations of the first low-concentration impurity region 26 and the second low-concentration impurity region 27 may be equal to each other. The n-type impurity concentrations of the first low-concentration impurity region 26 and the second low-concentration impurity region 27 are lower than those of the n-type impurity regions of the first region 21 and the second region 22.

[0036] Referring to FIG. 3, the first low-concentration impurity region 26 is formed between the first region 21 and the channel region 25. The boundary portion between the first low-concentration impurity region 26 and the well region 20 is defined as the third boundary portion 28. The third boundary portion 28 is a linear portion extending from the first long side portion 15A to the second long side portion 15B.

[0037] The first low-concentration impurity region 26 is formed in a strip shape extending from the first long side portion 15A to the second long side portion 15B. The first low-concentration impurity region 26 protrudes from the tip of the first region 21 (the first boundary portion 23) in the X-axis direction toward the second region 22. Referring to FIG. 4, the depth of the first low-concentration impurity region 26 from the first main surface 10 is shallower than the depth of the first region 21 from the first main surface 10. The first low-concentration impurity region 26 may be referred to as the first LDD (Lightly Doped Drain) region.

[0038] Referring to FIG. 3, the second low-concentration impurity region 27 is formed between the second region 22 and the channel region 25. The boundary portion between the second low-concentration impurity region 27 and the well region 20 is defined as the fourth boundary portion 29. The fourth boundary portion 29 is a linear portion extending from the first long side portion 15A to the second long side portion 15B.

[0039] The second low-concentration impurity region 27 is formed in a strip shape extending from the first long side portion 15A to the second long side portion 15B. The second low-concentration impurity region 27 protrudes from the tip of the second region 22 (the second boundary portion 24) in the X-axis direction toward the first region 21. Referring to FIG. 4, the depth of the second low-concentration impurity region 27 from the first main surface 10 may be shallower than the depth of the second region 22 from the first main surface 10. The second low-concentration impurity region 27 may be referred to as the second LDD (Lightly Doped Drain) region.

[0040] Referring to FIG. 4, in the X-axis direction, the first region 21 and the first low-concentration impurity region 26 are exposed from the first main surface 10 on one side of the channel region 25. Also, the second region 22 and the second low-concentration impurity region 27 are exposed from the first main surface 10 on the other side of the channel region 25.

[0041] On the first main surface 10 of the semiconductor layer 9, a planar gate structure 30 is formed. The planar gate structure 30 is disposed at a position where a channel can be formed in the channel region 25. That is, the planar gate structure 30 is disposed between the first region 21 and the second region 22 (between the source and the drain). Thereby, the memory cell 4 is formed as a single memory transistor structure 45 including the planar gate structure 30. In this embodiment, the single memory transistor structure 45 may be defined as a transistor including a pair of first regions 21 and second regions 22 and a pair of planar gate structures 30 formed adjacent to each other therebetween.

[0042] An end portion (a first side portion 35 described later) of the planar gate structure 30 in the X-axis direction is disposed so as to be continuous or overlap with the first boundary portion 23 in the Z-axis direction. Alternatively, the first side portion 35 may be disposed so as to be continuous or overlap with the third boundary portion 28) in the Z-axis direction.

[0043] Referring to FIG. 3, the planar gate structure 30 is formed across a plurality of memory cell regions 14 and has a common structure in the plurality of memory cells 4. For example, in FIG. 3, it extends in a strip shape along the Y-axis direction so as to cross the element isolation portion 13 between the memory cell regions 14 (the first memory cell region 14A and the second memory cell region 14B) adjacent to each other in the Y-axis direction. Therefore, the planar gate structure 30 is continuously formed so as to alternately cover the element isolation portion 13 and the memory cell regions 14.

[0044] The planar gate structure 30 includes a gate insulating film 32 and a gate electrode body 33. The gate insulating film 32 is formed on the first main surface 10 of the semiconductor layer 9. The gate insulating film 32 is formed of, for example, an oxide of the semiconductor layer 9. Specifically, the gate insulating film 32 is made of an oxide formed in a film shape by oxidizing the surface layer portion of the first main surface 10. The gate insulating film 32 is, for example, a silicon oxide film (SiO 2It consists of . The gate insulating film 32 has a thickness of 7 nm or more and 13 nm or less. The gate insulating film 32 may have a constant thickness along the first main surface 10.

[0045] The gate electrode body 33 is formed on the gate insulating film 32. The gate electrode body 33 faces the channel region 25 with the gate insulating film 32 interposed therebetween. The gate electrode body 33 is formed of, for example, conductive polysilicon. The gate electrode body 33 has a second side portion 34 and a first side portion 35 opposite to the second side portion 34 in the X-axis direction.

[0046] Referring to FIG. 3, the gate electrode body 33 has a first end portion 36 and a second end portion 37 facing each other in the Y-axis direction. The gate electrode body 33 is formed in a strip shape defined by the second side portion 34, the first side portion 35, the first end portion 36, and the second end portion 37 in a plan view from the Z-axis direction. In FIG. 3, a part of the gate electrode body 33 extending in the Y-axis direction is omitted by dividing it with a wavy line on both the upper and lower sides of the memory cell region 14.

[0047] Referring to FIG. 4, the length of the gate electrode body 33 in the X-axis direction is, for example, 0.4 μm or more and 1 μm or less. The length of the gate electrode body 33 in the X-axis direction may be defined as the distance between the second side portion 34 and the first side portion 35 of the gate electrode body 33.

[0048] A first insulating film 74 is formed on the second side portion 34 and the channel region 25. Also, a second insulating film 75 is formed on the first side portion 35 and the channel region 25. The cross sections of the first insulating film 74 and the second insulating film 75 are substantially L-shaped.

[0049] The first insulating film 74 and the second insulating film 75 are made of oxides of the semiconductor layer 9 and the gate electrode body 33. Specifically, the first insulating film 74 and the second insulating film 75 are made of oxides formed in a film shape by oxidizing the surface layer portion of the first main surface 10 and the side walls of the gate electrode body 33. The first insulating film 74 and the second insulating film 75 are made of, for example, a silicon oxide film. In the example of FIG. 4, each of the first insulating film 74 and the second insulating film 75 has a first extending portion extending in the X-axis direction and a second extending portion extending in the Z-axis direction. Then, by combining the first extending portion and the second extending portion, each of the first insulating film 74 and the second insulating film 75 has an L-shaped cross section. As shown in FIG. 3, the gate electrode body 33, the first insulating film 74, and the second insulating film 75 are collectively also referred to as the "gate electrode 63". The gate electrode 63 is disposed to face the channel region 25. Further, the gate electrode 63 (gate electrode body 33) extends in the Y-axis direction.

[0050] The first charge storage film 70 and the second charge storage film 78 are respectively formed adjacent to the outside of the first insulating film 74 and the second insulating film 75. Specifically, the first charge storage film 70 and the second charge storage film 78 are respectively formed on the first extending portion of the first insulating film 74 and on the first extending portion of the second insulating film 75.

[0051] When writing data into the semiconductor device 1 (memory), electrons (hot electrons HE) generated by impact ionization in the vicinity of the source region are injected into and stored in the first charge storage film 70 and the second charge storage film 78. The first charge storage film 70 and the second charge storage film 78 are made of an insulating material different from that of the first insulating film 74 and the second insulating film 75, and are made of, for example, a silicon nitride film (SiN film).

[0052] The first charge storage film 70 and the second charge storage film 78 each have an L-shaped cross section along the surfaces of the first insulating film 74 and the second insulating film 75. In the example of FIG. 4, each of the first charge storage film 70 and the second charge storage film 78 has a first extension portion extending in the X-axis direction and a second extension portion extending in the Z-axis direction (see FIG. 7 described later). Then, by combining the first extension portion and the second extension portion, each of the first charge storage film 70 and the second charge storage film 78 has an L-shaped cross section.

[0053] The first insulating spacer 71 and the second insulating spacer 79 are each formed adjacent to the outside of the first charge storage film 70 and the second charge storage film 78. Specifically, the first insulating spacer 71 and the second insulating spacer 79 are each formed on the first extension portion of the first charge storage film 70 and the first extension portion of the second charge storage film 78.

[0054] The first insulating spacer 71 and the second insulating spacer 79 are made of, for example, silicon oxide. The first insulating spacer 71 and the second insulating spacer 79 face the first insulating film 74 and the second insulating film 75 with the first charge storage film 70 and the second charge storage film 78 interposed therebetween, respectively.

[0055] With such a configuration, the first charge storage film 70 is surrounded by insulators (the first insulating film 74 and the first insulating spacer 71). At the same time, the second charge storage film 78 is surrounded by insulators (the second insulating film 75 and the second insulating spacer 79). Therefore, the gate-source voltage V can be efficiently divided between the first charge storage film 70 and the second charge storage film 78.

[0056] The first charge storage film 70 and the second charge storage film 78 are also collectively referred to as a charge storage film 110 (see FIG. 5 described later). The charge storage film 110 is formed around the gate electrode when the gate electrode 63 is viewed in plan from the Z-axis direction.

[0057] As shown in FIG. 4, a first sidewall structure 121 is formed by a first insulating film 74, a first charge storage film 70, and a first insulating spacer 71. Further, a second sidewall structure 122 is formed by a second insulating film 75, a second charge storage film 78, and a second insulating spacer 79. Thus, since sidewalls (the first sidewall structure 121 and the second sidewall structure 122) are formed at the peripheral edge of the gate electrode body 33 in the semiconductor device 1 of the present embodiment, it is also called a sidewall structure.

[0058] The first region 21 is formed self-aligned with respect to the first sidewall structure 121. Further, the first low-concentration impurity region 26 is formed self-aligned with respect to the first side portion 35 of the gate electrode body 33. The second region 22 is formed self-aligned with respect to the second sidewall structure 122. Further, the second low-concentration impurity region 27 is formed self-aligned with respect to the second side portion 34.

[0059] The semiconductor device 1 further includes a coating insulating film 82. The coating insulating film 82 integrally coats a part of the first region 21, the planar gate structure 30, the first sidewall structure 121, the second sidewall structure 122, and a part of the second region 22. The coating insulating film 82 is made of, for example, a silicon oxide film. Since the coating insulating film 82 prevents silicidation of the gate electrode body 33, it may be referred to as a salicide block film.

[0060] First silicide films 83 and second silicide films 84 are formed on the portions exposed from the coating insulating film 82 in the first region 21 and the second region 22, respectively. The first silicide films 83 and the second silicide films 84 may each contain at least one of, for example, TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2. Referring to FIG. 3, the first silicide films 83 and the second silicide films 84 are formed in a rectangular shape in plan view so as to extend from the first long side portion 15A to the second long side portion 15B (see FIG. 3) of the element isolation portion 13.

[0061] Referring to FIG. 4, an interlayer insulating film 85 is formed on the first main surface 10. The interlayer insulating film 85 may include at least one of a silicon oxide film and a silicon nitride film. The interlayer insulating film 85 may have a single-layer structure composed of a silicon oxide film or a silicon nitride film. The interlayer insulating film 85 may have a laminated structure in which one or more silicon oxide films and one or more silicon nitride films are laminated in an arbitrary order.

[0062] A first contact 86 and a second contact 87 are formed in the interlayer insulating film 85. Referring to FIG. 4, the first contact 86 and the second contact 87 penetrate the interlayer insulating film 85 in the Z-axis direction. The first contact 86 is mechanically and electrically connected to the first silicide film 83 in the first region 21 outside the coating insulating film 82. The second contact 87 is mechanically and electrically connected to the second silicide film 84 in the second region 22 outside the coating insulating film 82. The first contact 86 and the second contact 87 may be formed of at least one of copper and tungsten, for example.

[0063] A gate contact 88 is further formed in the interlayer insulating film 85. Although not shown in FIG. 4, the gate contact 88 penetrates the interlayer insulating film 85 in the thickness direction, similar to the first contact 86 and the second contact 87. The gate contact 88 is mechanically and electrically connected to the gate electrode body 33 outside the memory cell region 14. The gate contact 88 may be formed of at least one of copper and tungsten, for example.

[0064] A first wiring 90, a second wiring 91, and a gate wiring 92 are formed on the interlayer insulating film 85. The first wiring 90, the second wiring 91, and the gate wiring 92 may be aluminum wirings, for example.

[0065] The first wiring 90 is electrically connected to the first region 21 via the first contact 86. The second wiring 91 is electrically connected to the second region 22 via the second contact 87. One of the first wiring 90 and the second wiring 91 may be the bit line BL in FIG. 2, and the other may be connected to the ground (GND) potential. The first wiring 90 and the second wiring 91 may be referred to as a source wiring and a drain wiring, respectively, corresponding to the source-drain functions of the transistors of the memory cell 4. The ground side may be the source wiring, and the bit line BL side may be the drain wiring. FIG. 3 shows a case where the first wiring 90 is the source wiring (GND) and the second wiring 91 is the drain wiring (bit line BL). The source wiring may be a common wiring for a plurality of memory cells 4.

[0066] The gate wiring 92 is for applying a gate voltage to the gate electrode body 33 and is electrically connected to the gate electrode body 33 via the gate contact 88.

[0067] Also, as shown in FIG. 3, at least one recess is formed in the gate electrode body 33 in the Y-axis direction. This recess corresponds to the first recess 301 or the third recess 303 described later.

[0068] [Main part of semiconductor device] Next, the main part of the semiconductor device 1 of the present embodiment will be described. FIG. 5 is a diagram showing the main part of the semiconductor device 1 of the present embodiment. FIG. 5 is a diagram showing the main part when the gate electrode 63 is viewed in plan from the Z-axis direction. In FIG. 5, mainly, the semiconductor layer 9, the first contact 86, the second contact 87, the gate contact 88, the gate electrode 63, the first charge storage film 70, and the second charge storage film 78 are shown.

[0069] The first charge storage film 70 and the second charge storage film 78 are formed at the periphery of the gate electrode 63. At least one first recess 301 is formed in the gate electrode 63. In the example of FIG. 5, the at least one first recess 301 is a plurality of first recesses 301. In the example of FIG. 5, the plurality of first recesses 301 are four first recesses 301. More specifically, as described above, the gate electrode 63 extends in the Y-axis direction (third direction). The gate electrode 63 has a first long side 63A along the Y-axis direction when the gate electrode 63 is viewed in plan from the Z-axis direction (first direction). At least one (four in FIG. 5) first recess 301 is formed in the first long side 63A. A part of the second charge storage film 78 is embedded (filled) in the four first recesses 301.

[0070] Further, the first recess 301 has a polygonal shape when viewed in plan from the Z-axis direction. In the example of FIG. 5, this polygonal shape is a rectangular shape.

[0071] FIG. 6 is an enlarged view of the portion (region A in FIG. 5) where the first recess 301 of FIG. 5 is formed. As shown in FIGS. 3 and 6, the gate electrode 63 includes a gate electrode body 33 and insulating films (first insulating film 74 and second insulating film 75) formed on the surface (side) of the gate electrode body 33.

[0072] A third recess 303 is formed in the gate electrode body 33. And a second insulating film 75 is formed on the surface 303A of the third recess 303. Note that the thickness of the second insulating film 75 is 10 nm or more and 50 nm or more. Since the second insulating film 75 is thin, the second insulating film 75 does not fill all of the third recess 303. That is, the third recess 303 with the second insulating film 75 formed on the surface 303A becomes the first recess 301.

[0073] Next, each length of the semiconductor device 1 will be described with reference to FIG. 6. The first length L1 is the shortest length in the Y-axis direction of the portion where the first recess 301 is not formed when the gate electrode body 33 is viewed in plan from the Z-axis direction.

[0074] The second length L2 is the shortest length in the Y-axis direction at the location where the first recess 301 is formed when the gate electrode body 33 is viewed in plan from the Z-axis direction. The first length L1 is longer than the second length L2. Note that the first length L1 may be defined as the length of the channel region 25 facing a location where the first recess 301 is not formed. Also, the second length L2 may be defined as the length of the channel region 25 facing the location where the first recess 301 is formed.

[0075] The third length L3 is the length in the X-axis direction of the second charge storage film 78 at a location where the first recess 301 is not formed when the gate electrode body 33 is viewed in plan from the Z-axis direction. The fourth length L4 is the length in the Y-axis direction of the opening 301B of the first recess 301.

[0076] The fifth length L5 is the length in the X-axis direction of the first recess 301. That is, it is the length obtained by subtracting the second length L2 from the first length L1.

[0077] The first length L1 is, for example, set to any value between 100 nm and 500 nm. The second length L2 is, for example, set to any value between 50 nm and 480 nm. The third length L3 is, for example, set to any value between 50 nm and 300 nm. The fourth length L4 is, for example, set to any value between 100 nm and 400 nm. The fifth length L5 is, for example, set to any value between 20 nm and 50 nm.

[0078] Also, the division value A obtained by dividing the first length L1 by the second length L2 is configured to be any value between 1.11 and 2. The division value B obtained by dividing the fourth length L4 by the third length L3 is configured to be 2 or less.

[0079] FIG. 7 is a cross-sectional view of the XZ plane of the portion where the first recess 301 in FIG. 5 is formed (a cross-sectional view taken along line X2-X2 in FIG. 5). As shown in FIG. 7, the first charge storage film 70 has a first extension portion 70A extending in the X-axis direction and a second extension portion 70B extending in the Z-axis direction. Also, the second charge storage film 78 has a first extension portion 78A extending in the X-axis direction and a second extension portion 78B extending in the Z-axis direction.

[0080] As shown in FIG. 7, the length of the first extension portion 70A in the X-axis direction is the third length L3. On the other hand, the length of the first extension portion 78A in the X-axis direction is the added value of the third length L3 and the fifth length L5. Therefore, the length of the first extension portion 78A of the second charge storage film 78 on the side where the first recess is formed in the X-axis direction can be made longer than the length of the first extension portion 70A of the first charge storage film 70 on the side where the first recess is not formed. Also, as is clear from FIG. 7, the first recess 301 is formed to penetrate in the Z-axis direction.

[0081] [Flowchart of the manufacturing method of the carrier device] FIG. 8 is a flowchart of the manufacturing method of the semiconductor device 1. In step S2, the semiconductor layer 9 is prepared. Next, in step S4, the gate electrode 63, the charge storage films (the first charge storage film 70 and the second charge storage film 78), and the channel region 25 are formed. At least one first recess 301 is formed in the gate electrode 63 as shown in FIG. 5 and the like.

[0082] Next, in step S6, the first region 21 and the second region 22 are formed. Then, in step S8, other components are formed, and thus the semiconductor device 1 is completed.

[0083] [Steps of the manufacturing method of the semiconductor device] Figs. 9 to 21 are diagrams for explaining specific steps of the manufacturing method of the semiconductor device 1. First, referring to Fig. 9, a semiconductor wafer 101 is prepared. The semiconductor wafer 101 serves as the base of the semiconductor layer 9. The semiconductor wafer 101 has a first wafer main surface 102 on one side and a second wafer main surface 103 on the opposite side thereof. The first wafer main surface 102 and the second wafer main surface 103 respectively correspond to the first main surface 10 and the second main surface 11 of the semiconductor layer 9 (see Fig. 4).

[0084] Next, by etching through a mask (not shown) having a predetermined pattern, a part of the semiconductor wafer 101 is selectively removed from the first wafer main surface 102. Thereby, a trench 17 partitioning the memory cell region 14 is formed as shown in Fig. 10. The etching may be, for example, dry etching (e.g., RIE method) or wet etching. In this embodiment, the trench 17 is formed by dry etching.

[0085] Furthermore, referring to Fig. 10, a base insulating film (not shown) serving as the base of the insulator 18 is formed on the first wafer main surface 102 so as to fill the trench 17. The base insulating film is made of silicon oxide in this embodiment. The base insulating film may be formed, for example, by CVD (Chemical Vapor Deposition) method. Next, unnecessary portions of the base insulating film are removed by etching. Thereby, the insulator 18 embedded in the trench 17 is formed.

[0086] Next, referring to Fig. 11, a gate insulating film 104 serving as the base of the gate insulating film 32 (see Fig. 4) is formed on the first wafer main surface 102. The gate insulating film 104 is formed, for example, by thermally oxidizing the surface layer portion of the first wafer main surface 102 in a film shape.

[0087] Next, referring to FIG. 12, a p-type well region 20 is formed in the surface layer portion of the first wafer main surface 102 in the memory cell region 14. Specifically, the well region 20 is formed by introducing p-type impurities into the surface layer portion of the first wafer main surface 102 by an ion implantation method through the gate insulating film 104. By forming the well region 20, a region in the semiconductor wafer 101 where the p-type impurity concentration is lower than that in the well region 20 becomes the back gate region 12. Note that the introduction of p-type impurities into the first wafer main surface 102 may be performed at an arbitrary timing. For example, the introduction of p-type impurities into the first wafer main surface 102 may be performed before the formation of the gate insulating film 104. In that case, a sacrificial oxide film may be formed on the first wafer main surface 102, and p-type impurities may be introduced into the first wafer main surface 102 through the sacrificial oxide film. Then, after the sacrificial oxide film is removed, the gate insulating film 104 is formed.

[0088] Next, referring to FIG. 13, a base electrode 105 serving as a base of the gate electrode body 33 (see FIG. 4) is formed on the first wafer main surface 102 so as to cover the gate insulating film 104 and the insulator 18. In this embodiment, the base electrode 105 is made of conductive polysilicon. The base electrode 105 may be formed by, for example, a CVD method.

[0089] Next, referring to FIG. 14, unnecessary portions of the base electrode 105 are removed by etching through a mask (not shown) having a predetermined pattern. Thereby, the gate electrode body 33 is formed. The etching may be, for example, dry etching (for example, RIE method) or wet etching.

[0090] Here, in the etching for forming the gate electrode body 33, the four third recesses 303 (see FIG. 6) are formed.

[0091] Next, referring to FIG. 15, an n-type first low-concentration impurity region 26 and a second low-concentration impurity region 27 are formed in the surface layer portion of the well region 20. In this embodiment, the first low-concentration impurity region 26 and the second low-concentration impurity region 27 are formed by introducing n-type impurities into the surface layer portion of the well region 20 by an ion implantation method using the gate electrode body 33 as a mask. That is, the first low-concentration impurity region 26 and the second low-concentration impurity region 27 are formed self-aligned with respect to the gate electrode body 33.

[0092] Next, referring to FIG. 16, the gate insulating film 104 is partially removed by etching. Thereby, the gate insulating film 32 is formed from the gate insulating film 104, and the planar gate structure 30 is formed.

[0093] Next, referring to FIG. 17, a lower base insulating film 106 serving as a base for the first insulating film 74 and the second insulating film 75 is formed. The lower base insulating film 106 integrally covers the first wafer main surface 102 and the gate electrode body 33. The lower base insulating film 106 has a certain thickness. In FIG. 17, the lower base insulating film 106 has a film portion 107 on the upper surface 60 of the gate electrode body 33. The lower base insulating film 106 is formed by thermally oxidizing the first wafer main surface 102 and the gate electrode body 33 in a film shape. Further, the lower base insulating film 106 may be formed by a CVD method. Further, when the lower base insulating film 106 is formed, the second insulating film 75 is formed on the surface of the third recess 303 (see FIG. 6).

[0094] Next, referring to FIG. 18, an upper base insulating film 109 that serves as a base for the first charge storage film 70 and the second charge storage film 78 is formed on the lower base insulating film 106. The upper base insulating film 109 integrally covers the first wafer main surface 102 and the gate electrode body 33. The upper base insulating film 109 has a certain thickness. In FIG. 18, the upper base insulating film 109 has a film portion 111 on the upper surface 60 of the gate electrode body 33. The upper base insulating film 109 may be formed, for example, by a CVD method. Note that the lower base insulating film 106 and the upper base insulating film 109 that form the storage structure of the memory may be collectively referred to as a first base insulating film 112.

[0095] Next, referring to FIG. 19, a second base insulating film 113 that serves as a base for the first insulating spacer 71 and the second insulating spacer 79 is formed on the first base insulating film 112. The second base insulating film 113 may be formed, for example, by a CVD method. The second base insulating film 113 integrally covers the first wafer main surface 102 and the gate electrode body 33. In FIG. 19, the second base insulating film 113 has a film portion 114 on the upper surface 60 of the gate electrode body 33.

[0096] Next, referring to FIG. 20, by etch-back, the film portion 114 of the second base insulating film 113, the film portion 107 of the first base insulating film 112, and the portions covering the first wafer main surface 102 of these insulating films are selectively removed. As a result, the upper surface 60 of the gate electrode body 33 is exposed. Also, a first sidewall structure 121 and a second sidewall structure 122 are formed by the first base insulating film 112 and the second base insulating film 113 remaining on the gate electrode body 33.

[0097] Next, referring to FIG. 21, an n-type first region 21 and a second region 22 are formed in the surface layer portion of the well region 20. In this embodiment, the first region 21 and the second region 22 are formed by introducing n-type impurities into the surface layer portion of the well region 20 by an ion implantation method using the first sidewall structure 121 and the second sidewall structure 122 as masks. That is, the first region 21 is formed self-aligned with respect to the first sidewall structure 121, and the second region 22 is formed self-aligned with respect to the second sidewall structure 122.

[0098] Thereafter, other components are formed, and the semiconductor device 1 shown in FIG. 4 is completed. Note that step S2 in FIG. 8 corresponds to FIG. 9. Step S4 corresponds to FIGS. 14 to 18, and step S6 corresponds to FIG. 21.

[0099] [Parentheses] (1) In a conventional semiconductor device, it was necessary to provide a second gate electrode and an integrated sidewall structure in order to increase the charge accumulation amount. Therefore, in the above-described semiconductor device, there may be a problem that the design freedom of the semiconductor device is reduced.

[0100] On the other hand, in the semiconductor device 1 of the present disclosure, as shown in FIG. 5 and the like, at least one first recess 301 is formed on the surface of the gate electrode 63. And a part of a charge storage film (second charge storage film 78) is embedded in the first recess 301. Therefore, compared with a semiconductor device in which the first recess 301 is not formed (hereinafter, also referred to as "the semiconductor device of the first comparative example"), the amount of the charge storage film can be increased. As a result, the semiconductor device 1 of the present disclosure can store more charges compared with the semiconductor device of the first comparative example. Thus, a large amount of charges can be stored without providing the above-described second gate electrode and integrated sidewall structure. Therefore, the writing characteristics to the semiconductor device can be improved without reducing the design freedom of the semiconductor device 1.

[0101] FIG. 22 is a diagram showing a gate electrode 63S and the like of the semiconductor device of the second comparative example. FIG. 22 is a diagram corresponding to FIG. 7. As shown in FIG. 22(A), in the semiconductor device of the second comparative example, a first charge storage film 70S and a second charge storage film 78S are formed on the periphery of the gate electrode 63S.

[0102] Here, as shown in FIG. 22(B), in order to store a large amount of charges in the first charge storage film 70S and the second charge storage film 78S, a configuration in which the length of the first charge storage film 70S and the second charge storage film 78S in the X-axis direction is increased can be considered. However, in such a configuration, a change in element characteristics may occur from a semiconductor device in which the length of the first charge storage film 70S and the second charge storage film 78S in the X-axis direction is not increased. The element characteristics are, for example, at least one of an on-resistance (Ron) and a drain current (Ids). The change in element characteristics is, for example, at least one of an increase in on-resistance and an increase in dark current.

[0103] For example, a circuit different from the memory circuit 2 in FIG. 1 (for example, a logic circuit 3) may be manufactured by the same manufacturing process as the memory circuit 2. In this case, when the above-described change in element characteristics occurs, the circuit characteristics of the other circuit change, and there may occur a problem that the semiconductor device 1 does not function as designed.

[0104] On the other hand, according to the semiconductor device 1 of the present embodiment, since the above-described change in element characteristics can be suppressed, the occurrence of the above problem can be suppressed.

[0105] (2) Also, as shown in FIG. 5, a first recess 301 is formed in the first long side 63A of the gate electrode 63. Therefore, the semiconductor device 1 of the present disclosure can be more easily formed with a recess than a semiconductor device in which a recess is formed on a short side.

[0106] (3) Also, as shown in FIG. 5, the first recess 301 is a plurality of first recesses. Therefore, the semiconductor device 1 of the present disclosure can store more charges than a semiconductor device in which one first recess is formed.

[0107] (4) The division value A obtained by dividing the first length L1 in FIG. 6 by the second length L2 is either a value of 1.11 or more and 2 or less. Therefore, the semiconductor device 1 of the present disclosure can accumulate a large amount of charges while facilitating the formation process of the first recess 301.

[0108] (5) The division value B obtained by dividing the fourth length L4 in FIG. 6 by the third length L3 is configured to be 2 or less. Therefore, the semiconductor device 1 of the present disclosure can accumulate a large amount of charges.

[0109] (6) The shape of the first recess 301 is a polygon when viewed in plan from the Z-axis direction. In the example of FIG. 5, the polygon is a quadrangular shape. Therefore, in the semiconductor device 1 of the present disclosure, the recess is easily formed.

[0110] (7) Further, as shown in FIG. 7, the first recess 301 penetrates in the Z-axis direction. Therefore, in the semiconductor device 1 of the present disclosure, a larger amount of charges can be accumulated compared to a semiconductor device in which a recess that does not penetrate in the Z-axis direction is formed.

[0111] (8) Further, as shown in FIG. 6, the gate electrode 63 has a gate electrode body 33 and a second insulating film 75 formed on the surface 303A of the gate electrode body 33. Further, as shown in FIG. 6, at least one third recess 303 is formed in the gate electrode body. The second insulating film 75 is formed on the surface of this third recess 303. And the third recess 303 having the second insulating film 75 formed on the surface 303A becomes the first recess 301. Therefore, since the second insulating film 75 is formed on the gate electrode body 33 and the third recess 303 of the gate electrode body 33, the semiconductor device 1 of the present disclosure can realize a function as a memory.

[0112] [Second Embodiment] FIG. 23 is a diagram showing the gate electrode 631 and the like of the second embodiment. FIG. 23 is a diagram corresponding to FIG. 5. In the example of FIG. 23, when the gate electrode 631 is viewed in plan from the Z-axis direction, it has a second long side 63B along the Z-axis direction. The second long side 63B is a side opposite to the first long side 63A.

[0113] Furthermore, at least one second recess 302 is formed in the second long side 63B. And a part of the first charge storage film 70 is embedded in at least one second recess 302. Therefore, according to the semiconductor device 1 of the present embodiment, more charges can be stored as compared with a semiconductor device in which the second recess 302 is not formed in the second long side 63B.

[0114] Also, in the example of FIG. 23, the second recess 302 is a plurality of second recesses. Therefore, the semiconductor device 1 of the present disclosure can store more charges as compared with a semiconductor device in which one second recess is formed.

[0115] [Third Embodiment] FIG. 24 is a diagram showing the gate electrode 632 and the like of the third embodiment. FIG. 24 is a diagram corresponding to FIG. 5. In the example of FIG. 24, when the gate electrode 631 is viewed in plan from the Z-axis direction, the shape of the first recess 310 is triangular. And a part of the second charge storage film 78 is embedded in the triangular first recess 310. Even with such a configuration, the first recess 310 can be easily formed.

[0116] [Other Embodiments] In the above-described embodiments, the configuration in which the gate electrode 63 includes the gate electrode body 33 and the insulating films (the first insulating film 74 and the second insulating film 75) has been described. However, the gate electrode 63 may have other configurations. For example, the gate electrode 63 may be composed of only the gate electrode body 33. Also, the gate electrode 63 may include insulating films (the first insulating film 74 and the second insulating film 75) and a component different from the insulating films.

[0117] [Appendix] (Supplementary Note 1) A semiconductor device includes a semiconductor layer having a main surface, a first region of a first conductivity type formed on the main surface, a second region of the first conductivity type formed on the main surface and spaced apart from the first region in a second direction orthogonal to a first direction which is the thickness direction of the semiconductor layer, a channel region of a second conductivity type formed between the first region and the second region on the main surface, a gate electrode disposed to face the channel region, and a charge storage film for storing charges. The charge storage film is formed on the gate electrode when the gate electrode is viewed in plan from the first direction, at least one first recess is formed in the gate electrode, and a part of the charge storage film is embedded in the at least one first recess.

[0118] In a conventional semiconductor device, it has been necessary to provide a second gate electrode and an integrated sidewall structure in order to increase the amount of charge stored. Therefore, in the above-described semiconductor device, there may occur a problem that the design freedom of the semiconductor device is reduced.

[0119] On the other hand, in the semiconductor device of the present disclosure, a part of the charge storage film is embedded in at least one first recess formed on the surface of the gate electrode. Therefore, compared with a semiconductor device in which no first recess is formed (hereinafter, also referred to as "the semiconductor device of the first comparative example"), the amount of the charge storage film can be increased. As a result, the semiconductor device of the present disclosure can store more charges compared with the semiconductor device of the first comparative example. Thus, a large amount of charges can be stored without providing the above-described second gate electrode and integrated sidewall structure. Therefore, the write characteristics of the semiconductor device can be improved without reducing the design freedom of the semiconductor device.

[0120] (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein the gate electrode extends in a third direction orthogonal to the first direction and the second direction, and the at least one first recess is formed in a first long side along the third direction when the gate electrode is viewed in plan from the first direction.

[0121] According to such a configuration, a recess is formed in the extending first long side of the gate electrode. Therefore, the semiconductor device of the present disclosure can be more easily formed with a recess than a semiconductor device having a recess formed in a short side.

[0122] (Appendix 3) The semiconductor device according to Appendix 2, wherein the at least one first recess is a plurality of first recesses.

[0123] According to such a configuration, a plurality of first recesses are formed in the gate electrode. Therefore, the semiconductor device of the present disclosure can accumulate more charges than a semiconductor device having one first recess formed therein.

[0124] (Appendix 4) In the semiconductor device according to any one of Appendices 2 to 3, the value obtained by dividing the length of the opening of the first recess in the third direction when viewed in plan from the first direction by the length of the charge storage film in the second direction at a location where the first recess is not formed is 2 or less.

[0125] According to such a configuration, a large amount of charges can be accumulated. (Appendix 5) In the semiconductor device according to any one of Appendices 2 to 4, the first length is longer than the second length, the first length is the shortest length in the second direction at a location where the first recess is not formed when the gate electrode is viewed in plan from the first direction, and the second length is the shortest length in the second direction at a location where the first recess is formed when the gate electrode is viewed in plan from the first direction.

[0126] (Appendix 6) In the semiconductor device according to Appendix 5, the value obtained by dividing the first length by the second length is 1.11 or more and 2 or less.

[0127] According to such a configuration, while facilitating the formation process of the recess, a large amount of charges can be accumulated. (Supplementary Note 7) The semiconductor device according to any one of Supplementary Notes 2 to 6, wherein at least one second recess is formed along the third direction when the gate electrode is viewed in plan from the first direction and on a second long side facing the first long side, and a part of the charge storage film is embedded in the at least one second recess.

[0128] According to such a configuration, more charges can be stored as compared with a semiconductor device in which no recess is formed on the second long side.

[0129] (Supplementary Note 8) The semiconductor device according to Supplementary Note 7, wherein the at least one second recess is a plurality of second recesses.

[0130] According to such a configuration, more charges can be stored as compared with a semiconductor device in which one recess is formed on the second long side.

[0131] (Supplementary Note 9) The semiconductor device according to any one of Supplementary Notes 1 to 8, wherein the shape of the at least one first recess is a polygon when viewed in plan from the first direction.

[0132] According to such a configuration, the formation process of the recess can be facilitated. (Supplementary Note 10) The semiconductor device according to Supplementary Note 9, wherein the polygon is a triangle.

[0133] According to such a configuration, the formation process of the recess can be facilitated. (Supplementary Note 11) The semiconductor device according to Supplementary Note 9, wherein the polygon is a quadrilateral.

[0134] According to such a configuration, the formation process of the recess can be facilitated. (Supplementary Note 12) The semiconductor device according to any one of Supplementary Notes 1 to 11, wherein the at least one first recess penetrates in the first direction.

[0135] According to such a configuration, more charges can be stored as compared with a semiconductor device in which a recess that does not penetrate in the first direction is formed.

[0136] (Supplementary Note 13) The gate electrode has a gate electrode body and an insulating film formed on the surface of the gate electrode body. At least one third recess is formed in the gate electrode body, the insulating film is formed on the surface of the at least one third recess, and the at least one third recess on which the insulating film is formed on the surface is each of the at least one first recess. The semiconductor device according to any one of Supplementary Notes 1 to 12.

[0137] According to such a configuration, since the insulating film is formed on the gate electrode body and the third recess of the gate electrode body, the semiconductor device of the present disclosure can realize a function as a memory.

[0138] (Supplementary Note 14) A method for manufacturing a semiconductor device, comprising preparing a semiconductor layer having a main surface, forming a gate electrode and a charge storage film for storing charges, forming a first region of a first conductivity type and a second region of the first conductivity type on the main surface, and forming a channel region of a second conductivity type on the main surface. The second region is a region spaced apart from the first region in a second direction orthogonal to a first direction which is a thickness direction of the semiconductor layer. The channel region is a region formed between the first region and the second region on the main surface. The gate electrode is formed to face the channel region, at least one first recess is formed on the surface of the gate electrode, the charge storage film is formed on the gate electrode when the gate electrode is viewed in plan from the first direction, and forming the charge storage film includes embedding a part of the charge storage film in the at least one first recess. A method for manufacturing a semiconductor device.

[0139] The embodiments disclosed this time should be considered as illustrative in all respects and not restrictive. The scope of the present disclosure is shown by the scope of claims rather than the description of the above-described embodiments, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

Explanation of Reference Numerals

[0140] 1 semiconductor device, 2 memory circuit, 3 logic circuit, 4 memory cell, 5 memory array, 6 peripheral circuit, 7 first peripheral circuit, 8 second peripheral circuit, 9 semiconductor layer, 10 first main surface, 11 second main surface, 12 back gate region, 13 element isolation section, 15A first long side section, 15B second long side section, 16A first short side section, 16B second short side section, 17 trench, 18 insulator, 19 protruding section, 20 well region, 21 first region, 22 second region, 23 first boundary section, 24 second boundary section, 25 channel region, 26 first low-concentration impurity region, 27 second low-concentration impurity region, 28 third boundary section, 29 fourth boundary section, 30 planar gate structure, 32,104 gate insulating film, 33 gate electrode body, 34 second side section, 35 first side section, 36 first end section, 37 second end section, 45 memory transistor structure, 60 upper surface, 63 gate electrode, 63A first long side, 63B second long side, 70 first charge storage film, 70A,78A first extension section, 70B,78B second extension section, 71 first insulating spacer, 74 first insulating film, 75 second insulating film, 78 second charge storage film, 79 second insulating spacer, 82 coating insulating film, 83 first silicide film, 84 second silicide film, 85 interlayer insulating film, 86 first contact, 87 second contact, 88 gate contact, 90 first wiring, 91 second wiring, 92 gate wiring, 101 semiconductor wafer, 102 first wafer main surface, 103 second wafer main surface, 105 base electrode, 106 lower base insulating film, 109 upper base insulating film, 110 charge storage film, 112 first base insulating film, 113 second base insulating film, 121 first sidewall structure, 122 second sidewall structure, 301,310 first recess, 301B opening, 302 second recess, 303 third recess.

Claims

1. A semiconductor layer having a main surface, a first region of a first conductivity type formed on the main surface, a second region of the first conductivity type formed on the main surface and spaced apart from the first region in a second direction orthogonal to a first direction which is the thickness direction of the semiconductor layer, a channel region of a second conductivity type formed between the first region and the second region on the main surface, a gate electrode disposed to face the channel region, and a charge storage film for storing charges, wherein the charge storage film is formed on the gate electrode when the gate electrode is viewed in plan from the first direction, at least one first recess is formed in the gate electrode, and a part of the charge storage film is embedded in the at least one first recess. A semiconductor device.

2. The gate electrode extends in a third direction orthogonal to the first direction and the second direction, and the at least one first recess is formed in a first long side along the third direction when the gate electrode is viewed in plan from the first direction. The semiconductor device according to claim 1.

3. The at least one first recess is a plurality of first recesses. The semiconductor device according to claim 2.

4. A value obtained by dividing a length in the third direction of an opening of the first recess when viewed in plan from the first direction by a length in the second direction of the charge storage film at a location where the first recess is not formed is 2 or less. The semiconductor device according to claim 2 or claim 3.

5. A first length is longer than a second length, the first length is the shortest length in the second direction at a location where the first recess is not formed when the gate electrode is viewed in plan from the first direction, and the second length is the shortest length in the second direction at a location where the first recess is formed when the gate electrode is viewed in plan from the first direction. The semiconductor device according to claim 2 or claim 3.

6. A value obtained by dividing the first length by the second length is 1.11 or more and 2 or less. The semiconductor device according to claim 5.

7. At least one second recess is formed in a second long side along the third direction and facing the first long side when the gate electrode is viewed in plan from the first direction, and a part of the charge storage film is embedded in the at least one second recess. The semiconductor device according to claim 2 or claim 3.

8. The at least one second recess is a plurality of second recesses. The semiconductor device according to claim 7.

9. The semiconductor device according to any one of claims 1 to 3, wherein the shape of the at least one first recess is polygonal when viewed in a plan view from the first direction.

10. The semiconductor device according to claim 9, wherein the polygon is a triangle.

11. The semiconductor device according to claim 9, wherein the polygon is a quadrilateral.

12. The semiconductor device according to any one of claims 1 to 3, wherein the at least one first recess penetrates in the first direction.

13. The gate electrode has a gate electrode body and an insulating film formed on the surface of the gate electrode body. At least one third recess is formed in the gate electrode body. The insulating film is formed on the surface of the at least one third recess. The semiconductor device according to any one of claims 1 to 3, wherein each of the at least one third recess having the insulating film formed on its surface is the at least one first recess.

14. A method of manufacturing a semiconductor device, comprising: preparing a semiconductor layer having a main surface; forming a gate electrode and a charge storage film for storing charges; forming a first region of a first conductivity type and a second region of the first conductivity type on the main surface; forming a channel region of a second conductivity type on the main surface, wherein the second region is a region spaced apart from the first region in a second direction orthogonal to a first direction which is a thickness direction of the semiconductor layer, the channel region is a region formed between the first region and the second region on the main surface, the gate electrode is formed to face the channel region, at least one first recess is formed on the surface of the gate electrode, the charge storage film is formed on the gate electrode when the gate electrode is viewed in a plan view from the first direction, and forming the charge storage film includes embedding a part of the charge storage film in the at least one first recess.

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