Memory system and information processing system

Abstract

To provide a memory system that operates with a parameter suitable for startup at startup.SOLUTION: A memory system of an embodiment includes a nonvolatile memory that stores a profile table and a memory controller that is configured to control the nonvolatile memory. The profile table includes a plurality of profile information items. The memory controller is configured to control the nonvolatile memory based on first profile information among the plurality of profile information items in a first process among multiple processes that are included in a startup sequence. The first profile information includes a parameter that is suitable for the first process.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory system and an information processing system.

Background Art

[0002] An information processing system including a memory system and a host connected to the memory system is known. The memory system includes a NAND memory as a semiconductor memory device and a memory controller that controls the semiconductor memory device. The information processing system also boots the BIOS (Basic Input / Output System), boots the bootloader, and then boots the OS (Operating System).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] Provide a memory system that operates with parameters suitable for startup at startup.

Means for Solving the Problems

[0005] To achieve the above object, the memory system of the embodiment includes a non-volatile memory and a memory controller that controls the non-volatile memory. The non-volatile memory includes a plurality of profile information. Each of the plurality of profile information includes parameters. When the host starts the startup sequence, the memory controller controls the non-volatile memory based on the first profile information among the plurality of profile information in the first period of the startup sequence. The first profile information includes parameters to be referred to when controlling the non-volatile memory in the first period.

Brief Description of Drawings

[0006]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Mode for Carrying Out the Invention

[0007] FIG. 1 is a block diagram showing a configuration example of an information processing system 1 including a memory system according to an embodiment of the present invention. The information processing system 1 includes a host device 2 (hereinafter referred to as host 2) and a memory system 3.

[0008] Host 2 is an information processing device external to the memory system 3. Host 2 may be a personal computer, a server, a mobile phone, an imaging device, a mobile terminal such as a tablet or a smartphone, or an in-vehicle terminal such as a car navigation system.

[0009] The memory system 3 is a storage device configured to read data from, for example, a non-volatile memory. The memory system may be realized as, for example, an SSD (Solid State Drive). Alternatively, the memory system may be realized as a hard disk drive (HDD) or a memory card. Here, an example in which the memory system 3 is connected to the host 2 via a cable or a network will be described, but the memory system 3 may be built in the host 2.

[0010] The memory system 3 includes a memory controller 4 and a NAND memory 5. The NAND memory 5 is an example of a semiconductor memory device. The semiconductor memory device is an example of a non-volatile memory that stores data non-volatilely. The NAND memory 5 is, for example, a NAND type flash memory. The NAND type flash memory includes a plurality of blocks. Each of the plurality of blocks includes a plurality of memory cells. A block is a data erasure unit. A block includes a plurality of pages. A page is a data read and write unit.

[0011] The memory controller 4 may be realized by a circuit such as a System-on-a-chip (SoC). The memory controller 4 is electrically connected to the NAND memory 5 via a NAND interface (I / F) 13.

[0012] The memory CPU 12 is a processor configured to control the host interface (I / F) 11 and the NAND I / F 13. The memory CPU 12 loads a control program from the NAND memory 5 or a ROM (not shown) into a DRAM (not shown), and performs various processes by executing the control program. Note that the control program may be loaded onto a SRAM (Static Random Access Memory) (not shown) in the memory controller 4. This memory CPU 12 can execute command processing and the like for processing various commands from the host 2. The operation of the memory CPU 12 is controlled by the above-described control program executed by the memory CPU 12. Note that it may be executed by dedicated hardware in the controller 4.

[0013] The NAND I / F 13 complies with, for example, a Toggle NAND flash interface or an Open NAND Flash Interface (ONFI). The NAND I / F 13 is connected to a plurality of NAND memory chips in the NAND memory 5 via a plurality of channels (Ch), respectively.

[0014] The host I / F 11 is a host interface circuit configured to communicate with the host 2. The host I / F 11 can use, for example, a SATA interface (Serial ATA), a SAS interface (Serial Attached SCSI), PCI Express (PCIe) (registered trademark), Ethernet (registered trademark), or the like.

[0015] The host I / F 11 receives various commands from the host 2. In the SATA interface, ATA commands defined by the ATA standard are used. In the SAS interface, SCSI commands defined by the SCSI standard are used. In PCIe (registered trademark) and Ethernet (registered trademark), NVMe commands defined by the NVM Express (NVMe) (registered trademark) standard are used.

[0016] The NAND memory 5 includes a stored boot area 20 and a user area 21. The boot area 20 includes a boot loader 22.

[0017] In the user area 21, for example, the OS 23 and user data are stored.

[0018] The OS 23 is a program for providing a host 2 with basic functions, such as providing an interface that abstracts various hardware to an application program, or managing resources so that multiple application programs can be efficiently processed independently of each other when used simultaneously.

[0019] The boot loader 22 is a program that is read onto the host RAM 32 by the BIOS 33 and loads a specific program such as the OS 23.

[0020] The host 2 includes a host CPU 30, a host ROM 31, and a host RAM 32. The host ROM 31 and the host RAM 32 may be inside the host CPU 30.

[0021] The host CPU 30 is a processor provided to control the operation of the entire host 2, and starts the BIOS 33, the boot loader 22, and the OS 23.

[0022] The host ROM 31 has data necessary for program startup, etc. The host ROM 31 stores the BIOS 33. The BIOS 33 may be a program recorded at the time of manufacture as part of EFI (Extensible Firmware Interface) / UEFI (Unified Extensible Firmware Interface). The BIOS 33 is read by the host CPU 30 as needed and loaded onto the host RAM 32, and is started by the host CPU.

[0023] The host RAM 32 temporarily stores programs and data and functions as a working memory for the host CPU 30.

[0024] The memory system 3 is configured to hold a profile table 24 in a boot area 20 within the NAND memory 5.

[0025] The profile table 24 has a plurality of pieces of profile information. Each of the plurality of pieces of profile information is information for setting parameters for items related to the processing of the memory system 3. There are a plurality of items related to the processing of the memory system 3, and one parameter is set for each item. The profile table 24 includes a plurality of profile numbers. Profile information corresponds to each of the plurality of profile numbers. The memory controller 4 stores the profile information in the profile table 24 in association with the profile numbers.

[0026] FIG. 2 is a diagram showing an example of the profile table 24 held by the memory system 3.

[0027] Each of the plurality of pieces of profile information included in the profile table 24 has a parameter for setting for an item related to the processing of the memory system 3. In FIG. 2, the case where the items related to the processing of the memory system 3 are the access area, the access type, and the speed of the host I / F 11 is illustrated. In FIG. 2, for example, the profile information of profile number 0 indicates that the parameter of the item of the access area is "boot area only", the parameter of the item of the access type is "read only", and the parameter of the item of the host I / F 11 is "minimum speed". Other items that may be included in the items related to the processing of the memory system 3 include the operating clock of the circuit in the memory system 3, the circuit selected at startup, the number of CPU cores used by the memory controller 4, and the like.

[0028] In the information processing system 1, the processing from when the power of the information processing system 1 is turned on until the application program or the like can be executed is called the startup sequence. The startup sequence can be mainly classified into three types of processing. The three types of processing are boot processing A, boot processing B, and post-boot processing, and they are executed in the order of boot processing A, boot processing B, and post-boot processing. The period during which boot processing A is executed is called the boot stage A. The period during which boot processing B is executed is called the boot stage B. The period during which post-boot processing is executed is called the post-boot stage. Here, the boot stage A is also called the first period. The boot stage B is also called the second period. The post-boot stage is also called the third period.

[0029] In boot processing A, the host CPU 30 starts the BIOS 33, and then the host CPU 30 initializes the memory system 3. Here, when the host CPU 30 initializes the memory system 3, it means that the host CPU 30 sends an initialization command to the memory controller 4. In the startup sequence of the information processing system 1, when the memory controller 4 receives the initialization command, it sets the profile information of the selected profile number for each item related to the processing of the memory system 3. Here, when the profile information of the profile number is set, it means that a plurality of parameters corresponding to the selected profile information are respectively set for each item related to the processing of the memory system 3. Then the host CPU 30 reads out the boot loader 22 and proceeds to boot processing B.

[0030] In boot processing B, after the host CPU 30 starts the boot loader 22, it initializes the memory system 3. Then the memory controller 4 selects the profile number corresponding to boot processing B. The memory controller 4 sets the profile information of the selected profile number for each item related to the processing of the memory system 3. Then the host CPU 30 reads out the OS 23 and proceeds to post-boot processing.

[0031] In the post-boot process, after the host CPU 30 boots the OS 23, it initializes the memory system 3. The memory controller 4 selects a profile number corresponding to the post-boot process. The memory controller 4 sets the profile information of the selected profile number for each item related to the processing of the memory system 3. Then the post-boot process ends. In the post-boot process, parameters necessary for executing the application program are set.

[0032] FIG. 3 is a block diagram for explaining the configuration when executing based on the profile information of each profile number in the information processing system including the memory system 3. Specifically, it is a block diagram for explaining the configuration of the memory system 3 when the memory system 3 executes based on the profile information corresponding to the three profile numbers 0, profile number 1, and profile number N illustrated in FIG. 2. The user area 21 has N areas of user area 21-1 to user area 21-N. FIG. 3 shows the case where the OS 23 is included in the user area 21-1.

[0033] When the memory system 3 is executing based on the profile information of profile number 0, the memory controller 4 can only access the boot area 20 of the memory system 3. When the memory system 3 is executing based on the profile information of profile number 1, the memory controller 4 can access the boot area 20 and the user area 21-1 of the memory system 3. When the memory system 3 is executing based on the profile information of profile number N, the memory controller 4 can access the boot area 20 and all user areas 21 of the memory system 3.

[0034] In the boot process A, the host 2 issues a read request for the boot loader 22 in the boot area 20 to the memory system 3. That is, in the boot process A, it is only necessary for the memory controller 4 to be able to access the boot area 20. Therefore, in the boot stage A, the memory system 3 may execute based on the profile information of profile number 0.

[0035] In boot process B, host 2 makes a read request for OS 23 in user area 21 to memory system 3. That is, in boot process B, it is only necessary for memory controller 4 to be able to access user area 21-1. Therefore, in boot stage B, memory system 3 may be executed based on the profile information with profile number 1.

[0036] When the post-boot process ends and information processing system 1 executes an application program, host 2 may make read and write requests for any area in user area 21. Therefore, in the post-boot stage, memory system 3 may be executed based on the profile information with profile number N.

[0037] An information processing system including a memory system without a profile table sets and operates certain parameters for items related to the processing of the memory system. Here, the certain parameters refer to the parameters set for items related to the processing of the memory system in the post-boot stage of memory system 3. Therefore, for an information processing system including a memory system without a profile table, the memory controller can access any area in the user area even immediately after the BIOS is started. An information processing system including a memory system without a profile table can make read and write requests for any area in the user area. Also, a memory system without a profile table can communicate with the host at the highest speed. That is, an information processing system including a memory system without a profile table operates with performance beyond what is necessary, and it is considered that there is excessive power consumption and an increase in startup time.

[0038] According to the first embodiment, at the time of the startup sequence of the memory system 3, since the memory system 3 has the profile table 24, it can operate with performance suitable for each process of the startup sequence. Therefore, effects such as reduction of the power consumption of the memory system 3 and shortening of the startup time can be expected as compared with an information processing system that does not have a profile table.

[0039] FIG. 4 is a diagram showing an example of a process of setting profile information in the profile table 24 of the information processing system 1 including the memory system 3. In FIG. 4, when the vendor of the information processing system 1 that has purchased the memory system 3 starts the information processing system 1 for the first time, a process of setting the profile information required for each process of the startup sequence in the profile table 24 is described. Also, the series of processes in FIG. 4 is referred to as the profile table setting process.

[0040] The profile table setting process can be performed not only at the first startup of the information processing system 1.

[0041] The memory system 3 has a flag in the NAND memory 5. This flag designates the profile number selected by the memory system 3. Also, the profile table 24 has profile information corresponding to the profile number S. When the vendor of the information processing system 1 that has purchased the memory system 3 purchases the memory system 3, the memory system 3 has a flag designating the profile number S. Therefore, when the information processing system 1 starts up for the first time, the memory system 3 executes based on the profile information of the profile number S.

[0042] Hereinafter, the flowchart in FIG. 4 will be described.

[0043] When the power of the information processing system 1 is turned on, the host CPU 30 reads the BIOS 33 from the host ROM 31 (step S401). The host CPU 30 starts the BIOS 33 (step S402).

[0044] The host CPU 30 sends an initialization command to the memory controller 4 (step S403). When the memory controller 4 receives the initialization command, it initializes the memory system 3 (step S404). The memory controller 4 checks the profile number specified by the flag. The memory controller 4 sets the profile information of the specified profile number (in this case, profile number S) for each item related to the processing of the memory system 3 (step S405). When the setting of the profile information is completed, the memory controller 4 sends a profile information setting completion command to the host 2 (step S406).

[0045] The host CPU 30 sends a profile table setting command to the memory controller 4 (step S407). This command contains the profile information of at least three profile numbers K, profile number M, and profile number N. Let the profile number of the profile information executed in the boot process A be K, the profile number of the profile information executed in the boot process B be M, and the profile number of the profile information executed in the post-boot process be N. S, K, M, and N are different natural numbers from each other.

[0046] The memory controller 4 sets at least three pieces of profile information in the profile table 24 of the memory system 3 (step S408). When the setting is completed, the memory controller 4 sends a profile table setting completion command to the host 2 (step S409).

[0047] The host 2 sends a command to the memory controller 4 to set the profile number specified by the flag to K (step S410). The memory controller 4 changes the profile number specified by the flag to K (step S411). The memory controller 4 sends a profile number setting completion command to the host 2 (step S412), and the profile table setting process of the information processing system 1 ends.

[0048] Describe the transition of the profile number specified by the flag in the profile table setting process of the information processing system 1. At the start of the profile table setting process, the profile number specified by the flag is S. By the process of changing the profile number specified by the flag to K (step S411), the profile number specified by the flag is changed from S to K.

[0049] Describe the transition of the profile number of the profile information referred to in the memory system 3 in the profile table setting process of the information processing system 1. The memory controller 4 sets the profile information of profile number S for each item related to the process of the memory system 3 (step S405). In the subsequent process of the memory system 3, it is executed based on the profile information of profile number S.

[0050] When the profile table setting process of the information processing system 1 ends and then the information processing system 1 is started, the memory system 3 starts the startup sequence from the boot process A. At the start of the boot process A, the profile number specified by the flag is K. Therefore, the memory system 3 executes based on the profile information of profile number K in the boot process A.

[0051] In FIG. 4, the case where the vendor of the information processing system 1 that has purchased the memory system 3 sets the profile information of profile numbers K, M, and N in the profile table 24 and sets the profile number specified by the flag to K is shown. On the other hand, before the vendor of the information processing system 1 purchases the memory system 3, the profile table 24 may have the profile information of profile numbers K, M, and N. In that case, when the vendor of the information processing system 1 purchases the memory system 3, the memory system 3 may be configured to have a flag that specifies the profile number K. If the profile table 24 has the profile information of profile numbers K, M, and N and the memory system 3 has a flag that specifies the profile number K, the information processing system 1 may not perform the profile table setting process.

[0052] FIG. 5 is a diagram showing an example of the boot process A of the information processing system 1. It is assumed that the profile table 24 has the profile information of profile numbers K, M, and N and the memory system 3 has a flag that specifies the profile number K. When the power of the information processing system 1 is turned on, the boot process A of the information processing system 1 starts. FIG. 5 shows an example of the boot process A. When the boot process A is completed, it continues to the boot process B in FIG. 6 described later and the post-boot process in FIG. 7 described later, and the startup sequence is completed.

[0053] Hereinafter, the flowchart in FIG. 5 will be described.

[0054] When the power of the information processing system 1 is turned on, the host CPU 30 reads the BIOS 33 from the host ROM 31 (step S501). The host CPU 30 activates the BIOS 33 (step S502).

[0055] The host CPU 30 sends an initialization command to the memory controller 4 (step S503). When the memory controller 4 receives the initialization command, it initializes the memory system 3 (step S504). The memory controller 4 checks the profile number specified by the flag. The memory controller 4 sets the profile information of the specified profile number (in this case, profile number K) for each item related to the processing of the memory system 3 (step S505). When the setting of the profile information is completed, the memory controller 4 sends a profile information setting completion command to the host 2 (step S506).

[0056] The host 2 sends a command to the memory controller 4 to set the profile number specified by the flag to M (step S507). The memory controller 4 changes the profile number specified by the flag to M (step S508). Then the memory controller 4 sends a profile number setting completion command to the host 2 (step S509).

[0057] The host CPU 30 sends a command to the memory controller 4 to request the reading of the bootloader 22 (step S510). In response to the command, the memory controller 4 reads the bootloader 22 (step S511). The memory controller 4 sends the read bootloader 22 to the host 2 (step S512), and the host 2 receives the bootloader 22 and the boot process A ends.

[0058] Describe the transition of the profile number specified by the flag in the boot process A of the information processing system 1. At the start of the boot process A, the profile number specified by the flag is K. By the process of changing the profile number specified by the flag to M (step S508), the profile number specified by the flag is changed from K to M.

[0059] When the boot process A ends, the information processing system 1 starts the boot process B. At the start of the boot process B, the profile number specified by the flag is M. Therefore, the memory system 3 executes based on the profile information of profile number M in the boot process B.

[0060] In addition, regarding the step (S510) where the host CPU 30 sends a command to request the memory controller 4 to read the boot loader 22, it may be performed at any time after the step (S506) where the memory controller 4 sends a profile information setting completion command to the host 2 and during the boot process A.

[0061] FIG. 6 is a diagram showing an example of the boot process B of the information processing system 1. The boot process B in FIG. 6 is performed following the boot process A in FIG. 5.

[0062] Hereinafter, the flowchart in FIG. 6 will be described.

[0063] The host CPU 30 starts the boot loader 22 (step S601).

[0064] The host CPU 30 sends an initialization command to the memory controller 4 (step S602). When the memory controller 4 receives the initialization command, it initializes the memory system 3 (step S603). The memory controller 4 checks the profile number specified by the flag. The memory controller 4 sets the profile information of the specified profile number (in this case, profile number M) for each item related to the processing of the memory system 3 (step S604). When the setting of the profile information is completed, the memory controller 4 sends a profile information setting completion command to the host 2 (step S605).

[0065] Host 2 sends a command to the memory controller 4 to set the profile number specified by the flag to N (step S606). The memory controller 4 changes the profile number specified by the flag to N (step S607). Then, the memory controller 4 sends a profile number setting completion command to Host 2 (step S608).

[0066] The host CPU 30 sends a command to the memory controller 4 to request a read of the OS 23 (step S609). The memory controller 4 reads the OS 23 upon receiving the command (step S610). The memory controller 4 sends the OS 23 to Host 2 (step S611), and Host 2 receives the OS 23 and the boot process B ends.

[0067] The transition of the profile number specified by the flag in the boot process B of the information processing system 1 will be described. At the start of the boot process B, the profile number specified by the flag is M. Through the process of changing the profile number specified by the flag to N (step S607), the profile number specified by the flag is changed from M to N.

[0068] When the boot process B ends, the information processing system 1 starts the post-boot process. At the start of the post-boot process, the profile number specified by the flag is N. Therefore, in the post-boot process, the memory system 3 executes based on the profile information of profile number N.

[0069] Regarding the step (S609) where the host CPU 30 sends a command to the memory controller 4 to request a read of the OS 23, it may be performed at any time after the step (S605) where the memory controller 4 sends a profile information setting completion command to Host 2 and during the boot process B.

[0070] Figure 7 is a diagram showing an example of the post-boot process of the information processing system 1. The post-boot process of Figure 7 is performed following the boot process B of Figure 6.

[0071] The flowchart of FIG. 7 below will be described.

[0072] The host CPU 30 starts the OS 23 (S701).

[0073] The host CPU 30 sends an initialization command to the memory controller 4 (S702). When receiving the initialization command, the memory controller 4 initializes the memory system 3 (S703). The memory controller 4 checks the profile number specified by the flag. The memory controller 4 sets the profile information of the specified profile number (in this case, profile number N) for each item related to the processing of the memory system 3 (step S704). When the setting of the profile information is completed, the memory controller 4 sends a profile information setting completion command to the host 2 (step S705).

[0074] The host 2 sends a command to define the profile number specified by the flag as K to the memory controller 4 (step S706). The memory controller 4 changes the profile number specified by the flag to K (step S707). Then the memory controller 4 sends a profile number setting completion command to the host 2 (step S708), and the post-boot process ends.

[0075] The transition of the profile number specified by the flag in the post-boot process of the information processing system 1 will be described. At the start of the post-boot process, the profile number specified by the flag is N. By the step of changing the profile number specified by the flag to K (step S707), the profile number specified by the flag is changed from N to K.

[0076] When the post-boot process ends, then for example, the information processing system 1 executes an arbitrary application program. At that time, the memory system 3 executes based on the profile information of the profile number N.

[0077] When the power supply of the information processing system 1 is turned off and then turned on, the memory system 3 starts a startup sequence from the boot process A. When the boot process A starts, the profile number specified by the flag is K. Therefore, the memory system 3 executes based on the profile information with the profile number K in the boot process A.

[0078] In an information processing system including a memory system that does not have a profile table 24, when changing a parameter set for an item related to hardware such as an operation clock during the operation of the memory system, it is necessary to temporarily stop the operating memory system. Therefore, there is a possibility that the operation of the memory system becomes unstable. Furthermore, a circuit for temporarily stopping and restarting the operation of the memory system is required, increasing the circuit scale.

[0079] According to the present embodiment, the memory system 3 sets parameters for each item related to the processing of the memory system 3 and causes the parameters to be changed at the timing of initializing the memory system 3. Therefore, the memory system 3 can stably change even an item related to the hardware setting.

[0080] Note that the present invention is not limited only to the above-described embodiments, and it goes without saying that various changes can be made without departing from the gist of the present invention. Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, as well as in the invention described in the claims and its equivalent scope.

Explanation of Reference Numerals

[0081] 1 ··· Information processing system 2 ··· Host 3 ··· SSD 4... Memory Controller 5... NAND Memory 10... Bus 11... Host I / F 12... Memory CPU 13... NAND I / F 20... Boot Area 21... User Area 22... Boot Loader 23... OS 24... Profile Table 30... Host CPU 31... Host ROM 32... Host RAM 33... BIOS

Claims

1. A memory system connectable to a host, comprising: a non-volatile memory; and a memory controller for controlling the non-volatile memory, wherein the non-volatile memory includes a plurality of profile information, each of the plurality of profile information includes parameters, the memory controller controls the non-volatile memory based on first profile information among the plurality of profile information in a first period of a startup sequence, the first profile information includes parameters to be referred to when controlling the non-volatile memory in the first period, a memory system.

2. The memory system according to claim 1, wherein the first profile information is settable from the host.

3. The memory system according to claim 1, wherein the memory controller receives a first command from the host in the first period, initializes the memory system in response to the first command, and then controls the non-volatile memory based on the first profile information.

4. The memory system according to claim 1, wherein the memory controller controls the non-volatile memory based on second profile information different from the first profile information among the plurality of profile information in a second period following the first period, the second profile information includes parameters to be referred to when controlling the non-volatile memory in the second period. the memory system according to claim 1.

5. The memory system according to claim 4, wherein the memory controller receives a second command from the host in the second period, initializes the memory system in response to the second command, and then controls the non-volatile memory based on the second profile information.

6. The memory system according to claim 4, wherein the memory controller sets a flag for designating the second profile information to be used in the second period in the non-volatile memory in the first period, and checks the flag in the second period and controls the non-volatile memory based on the second profile information.

7. A memory system connectable to a host, comprising: a non-volatile memory; and a memory controller for controlling the non-volatile memory, wherein the non-volatile memory includes first profile information including parameters to be referred to by the memory controller in a first period during a startup sequence, and Second profile information including parameters referenced by the memory controller during a second period different from the first period during the startup sequence, A flag specifying the first profile information, Including, During the first period, when the memory controller receives a first command from the host, it initializes the memory system, checks the flag, controls the non-volatile memory based on the first profile information, and changes the flag to a flag specifying the second profile information. Memory system.

8. The non-volatile memory further includes third profile information including parameters referenced by the memory controller during a third period different from the second period during the startup sequence, The second period starts following the first period, During the second period, when the memory controller receives a second command from the host, it initializes the memory system, checks the flag, controls the non-volatile memory based on the second profile information, and changes the flag to a flag specifying the third profile information. The memory system according to claim 7.

9. The third period starts following the second period, During the third period, when the memory controller receives a third command from the host, it initializes the memory system, checks the flag, controls the non-volatile memory based on the third profile information, and changes the flag to a flag specifying the first profile information. The memory system according to claim 8.

10. A memory system having a non-volatile memory and a memory controller for controlling the non-volatile memory, and a host connected to the memory system, Comprising, The non-volatile memory, First profile information including parameters referenced by the memory controller during a first period during the startup sequence, Second profile information including parameters referenced by the memory controller during a second period different from the first period during the startup sequence, A flag specifying the first profile information, Including, During the first period, the host transmits a first command to the memory controller. When the memory controller receives the first command, it initializes the memory system, checks the flag, controls the non-volatile memory based on the first profile information, and changes the flag to a flag specifying the second profile information. Information processing system.

11. It can be connected to a host, a non-volatile memory, a memory controller for controlling the non-volatile memory, and comprises the non-volatile memory includes a plurality of profile information, each of the plurality of profile information includes parameters, the memory controller, in response to a first command from the host, controls the non-volatile memory based on first profile information among the plurality of profile information, in response to a second command from the host, controls the non-volatile memory based on second profile information different from the first profile information among the plurality of profile information, in response to a third command from the host, controls the non-volatile memory based on third profile information different from the first and second profile information among the plurality of profile information. Memory system.

12. The memory controller, receives the second command after the first command, receives the third command after the second command. The memory system according to claim 11.

13. The host, at startup, executes a startup sequence, during a first period of the period in which the startup sequence is executed, sends the first command to the memory system, during a second period following the first period, sends the second command to the memory system, during a third period following the second period, sends the third command to the memory system. The memory system according to claim 11.

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