Doherty amplifier circuit and semiconductor device

Abstract

To provide a Doherty amplifier circuit capable of being reduced in a size.SOLUTION: A Doherty amplifier circuit includes: a distributor that distributes a received input signal into a first signal and a second signal: a circuit board 55; a first amplifier that is provided on the circuit board, amplifies the first signal, and outputs the amplified first signal as a fourth signal; a second amplifier that is provided on the circuit board, amplifies the second signal, and outputs the amplified first signal as a fifth signal; a combining node that combines the fourth signal and the fifth signal and outputs the combined signal to an output terminal as an output signal; an open stub that is provided on the circuit board and has an end electrically connected to a path between the distributor and the first amplifier; and a first impedance converter that has a first end electrically connected to the second amplifier and a second end electrically connected to the combining node.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a Doherty amplifier circuit and a semiconductor device.

Background Art

[0002] An N (N is 2 or more)-way Doherty amplifier circuit using a main amplifier and two or more peak amplifiers is known (for example, Patent Documents 1 and 2).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in a Doherty amplifier circuit, an impedance converter is provided at the subsequent stage of either the main amplifier or the peak amplifier. In order to adjust the phase delay caused by the impedance converter, a phase adjuster is provided at the preceding stage of either the main amplifier or the peak amplifier. For this reason, the size increases.

[0005] The present disclosure aims to reduce the size.

Means for Solving the Problems

[0006] One embodiment of the present disclosure is a Doherty amplifier circuit including a distributor that distributes an input input signal into a first signal and a second signal, a circuit board, a first amplifier provided on the circuit board that amplifies the first signal and outputs the amplified signal as a fourth signal, a second amplifier provided on the circuit board that amplifies the second signal and outputs the amplified signal as a fifth signal, a combining node that combines the fourth signal and the fifth signal and outputs the combined signal to an output terminal as an output signal, an open stub provided on the circuit board with an end electrically connected to a path between the distributor and the first amplifier, and a first impedance converter provided on the circuit board with a first end electrically connected to the second amplifier and a second end electrically connected to the combining node.

[0007] One embodiment of the present disclosure is a semiconductor device for a Doherty amplifier circuit including a first input terminal into which a first signal into which an input input signal is distributed is input, a second input terminal into which a second signal into which the input signal is distributed is input, a first amplifier that amplifies the first signal and outputs the amplified signal as a fourth signal, a second amplifier that amplifies the second signal and outputs the amplified signal as a fifth signal, a first output terminal from which the fourth signal is output, a second output terminal from which the fifth signal is output, and a terminal connected to a line between the first input terminal and the first amplifier and to which an open stub for adjusting the phase of the first signal can be connected.

Advantages of the Invention

[0008] According to the present disclosure, miniaturization can be achieved.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

MODE FOR CARRYING OUT THE INVENTION

[0010] [Description of Embodiments of the Present Disclosure] First, the content of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure includes a distributor that distributes an input input signal into a first signal and a second signal, a circuit board, a first amplifier provided on the circuit board that amplifies the first signal and outputs the amplified signal as a fourth signal, a second amplifier provided on the circuit board that amplifies the second signal and outputs the amplified signal as a fifth signal, a combining node that combines the fourth signal and the fifth signal and outputs the combined signal to an output terminal as an output signal, an open stub provided on the circuit board with one end electrically connected to a path between the distributor and the first amplifier, and a first impedance converter provided on the circuit board with a first end electrically connected to the second amplifier and a second end electrically connected to the combining node. This makes it possible to shorten the open stub, thus enabling miniaturization. (2) In the above (1), a third amplifier provided on the circuit board that amplifies a third signal and outputs the amplified signal as a sixth signal, and a second impedance converter provided on the circuit board with a first end electrically connected to the third amplifier and a second end electrically connected to the combining node may be provided. The distributor distributes the input signal into the first signal, the second signal, and the third signal, and the combining node combines the fourth signal, the fifth signal, and the sixth signal and outputs the combined signal to the output terminal as the output signal. This makes it possible to miniaturize. (3) In the above (1) or (2), an impedance converter may not be provided between the first amplifier and the synthesis node. Thereby, the phases at the synthesis node can be aligned. (4) In any of the above (1) to (3), the first amplifier may be a main amplifier and the second amplifier may be a peak amplifier. Thereby, broadbanding can be achieved. (5) In any of the above (1) to (4), the first amplifier and the second amplifier are arranged in a first direction, the first impedance converter is provided in a second direction intersecting the first direction of the first amplifier, and the open stub may be provided in the first direction of the first amplifier. Thereby, the width of the circuit board in the second direction can be reduced. (6) In any of the above (1) to (5), a package on which the first amplifier and the second amplifier are mounted and which is mounted on the circuit board is provided, and the open stub and the first impedance converter may not be mounted on the package. Thereby, the first amplifier, the second amplifier, the open stub, and the first impedance converter can be provided on the circuit board. (7) In any of the above (1) to (6), the first impedance converter may be a 1 / 4 wavelength line with respect to the center frequency of the operating band, and the open stub may be a 1 / 8 wavelength line with respect to the center frequency of the operating band. Thereby, the phases of the fourth signal and the fifth signal at the synthesis node can be aligned. (8) One embodiment of the present disclosure includes a first input terminal to which a first signal obtained by distributing an input input signal is input, a second input terminal to which a second signal obtained by distributing the input signal is input, a first amplifier that amplifies the first signal and outputs the amplified signal as a fourth signal, a second amplifier that amplifies the second signal and outputs the amplified signal as a fifth signal, a first output terminal from which the fourth signal is output, a second output terminal from which the fifth signal is output, and a terminal that is connected to a line between the first input terminal and the first amplifier and to which an open stub for adjusting the phase of the first signal can be connected. This enables miniaturization. (9) In the above (8), it may further include a third input terminal to which a third signal obtained by distributing the input signal is input, a third amplifier that amplifies the third signal and outputs the amplified signal as a sixth signal, and a third output terminal from which the sixth signal is output. This enables miniaturization. (10) In the above (8) or (9), it includes a package on which the first amplifier and the second amplifier arranged in a first direction are mounted. The first input terminal and the second input terminal are provided on the first side among the first side and the second side that face each other in a second direction intersecting the first direction of the package. The first output terminal and the second output terminal are provided on the second side of the package. The terminal is provided on a third side connecting the first side and the second side. The first amplifier may be closer to the third side than the second amplifier. This can shorten the electrical length between the path between the first input terminal and the first amplifier and the open stub.

[0011] [Details of Embodiments of the Present Disclosure] Specific examples of the Doherty amplifier circuit and the semiconductor device according to the embodiments of the present disclosure will be described below with reference to the drawings. It should be noted that the present disclosure is not limited to these examples, and is defined by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0012] [Example 1] As a Doherty amplifier circuit, a high-output high-frequency amplifier circuit used in a base station for mobile communication will be described as an example. In this case, the frequency of the high-frequency signal is, for example, 0.5 GHz or higher and 10 GHz or lower. FIG. 1 is a block diagram of the Doherty amplifier circuit according to Embodiment 1.

[0013] As shown in FIG. 1, in the Doherty amplifier circuit 100, a main amplifier 10 (first amplifier), a peak amplifier 12 (second amplifier), and 14 (third amplifier) are connected in parallel between a distributor 16 and a combiner 18. In this way, the Doherty amplifier circuit 100 is a 3-way amplifier circuit. The Doherty amplifier circuit may be an N-way Doherty amplifier circuit having one or three or more peak amplifiers.

[0014] A high-frequency signal is input as an input signal Sin to the input terminal Tin. The distributor 16 distributes the input signal Sin input to the input terminal Tin into a signal S1 (first signal), a signal S2 (second signal), and a signal S3 (third signal). The distributor 16 is, for example, a Wilkinson-type distributor.

[0015] The path through which the signal S1 is input includes an open stub 54, a matching circuit 30, a bias circuit 36, the main amplifier 10, a bias circuit 39, and a matching circuit 33. The path through which the signal S2 is input includes a matching circuit 31, a bias circuit 37, the peak amplifier 12, and a matching circuit 34. The path through which the signal S3 is input includes a matching circuit 32, a bias circuit 38, the peak amplifier 14, and a matching circuit 35.

[0016] The matching circuits 30 to 32 match the impedances seen from the distributor 16 to the matching circuits 30 to 32 to the impedances seen from the matching circuits 30 to 32 to the main amplifier 10, the peak amplifiers 12 and 14, respectively. The bias circuits 36 to 38 supply gate bias voltages VG1 to VG3 to the gates G of the main amplifier 10, the peak amplifiers 12 and 14, respectively.

[0017] The open stub 54 adjusts the phase of the signal S1 in order to adjust the phases of the signals S5 and S6 that are changed by the impedance converters 52 and 53 and the signal S4. The open stub 54 is a transmission line such as, for example, a microstrip line or a coplanar line with an open end, and is, for example, a 1 / 8 wavelength line at the center frequency of the operating band.

[0018] The main amplifier 10, peak amplifiers 12 and 14 amplify the signals S1, S2 and S3 respectively, and output the amplified signals S4 (the fourth signal), S5 (the fifth signal) and S6 (the sixth signal) respectively. The bias circuit 39 supplies a drain bias voltage VD to the drains D of the main amplifier 10, peak amplifiers 12 and 14. The matching circuits 33 to 35 match the impedances seen from the main amplifier 10, peak amplifiers 12 and 14 to the impedances seen from the matching circuits 33 to 35 to the synthesizer 18 respectively.

[0019] The synthesizer 18 includes a synthesis node N1, impedance converters 52 and 53. The impedance converter 52 has its first end electrically connected to the peak amplifier 12 via the matching circuit 34 and its second end electrically connected to the synthesis node N1. The impedance converter 53 has its first end electrically connected to the peak amplifier 14 via the matching circuit 35 and its second end electrically connected to the synthesis node N1. The synthesis node N1 synthesizes the signals S4 to S6 and outputs the synthesized signal as the output signal Sout to the output terminal Tout.

[0020] Impedance converters 52 and 53 convert the impedance on the real axis of the Smith chart as seen from matching circuits 34 and 35 to the impedance at different positions on the real axis of the Smith chart as seen from the combined node N1 from impedance converters 52 and 53. Also, impedance converter 52 makes the impedance seen from the combined node N1 to peak amplifier 12 infinite when peak amplifier 12 is not operating. Impedance converter 53 makes the impedance seen from the combined node N1 to peak amplifier 14 infinite when peak amplifier 14 is not operating.

[0021] Impedance converters 52 and 53 are transmission lines such as microstrip lines or coplanar lines, for example, and are quarter-wavelength lines at the center frequency of the operating band. The electrical length of the quarter-wavelength line does not have to be exactly a quarter wavelength. The quarter-wavelength line only needs to have an electrical length that functions as impedance converters 52 and 53. For example, the electrical length of the quarter-wavelength line may be 3 / 16 wavelength or more and 5 / 16 wavelength or less, or may be 7 / 32 wavelength or more and 9 / 32 wavelength or less. The impedance on the real axis in the Smith chart does not have to be exactly on the real axis (reactance component is 0). The absolute value of the reactance component of the impedance may be 0.2 times or less, or 0.1 times or less, of the resistance component.

[0022] Main amplifier 10, peak amplifiers 12 and 14 each include transistors Q1 to Q3. Transistors Q1 to Q3 are, for example, FETs (Field Effect Transistors), and are, for example, GaN HEMTs (Gallium Nitride High Electron Mobility Transistors) or LDMOSs (Laterally Diffused Metal Oxide Semiconductors). The sources S of transistors Q1 to Q3 are grounded, signals S1 to S3 are input to the gates G respectively, and signals S4 to S6 are output from the drains D respectively.

[0023] Figure 2 is a plan view of the semiconductor device in Example 1. In Figure 2, the lid of the package 50 is not shown. The thickness direction of the base 51 of the package 50 is the Z direction, the direction from the leads 27a to 27c to the leads 28a to 28c is the X direction (the second direction intersecting the first direction), and the direction orthogonal to the X direction and the Z direction is the Y direction (the first direction).

[0024] As shown in Figure 2, in the semiconductor device 102, the package 50 has a base 51 whose at least upper surface is conductive. The base 51 is a conductor substrate such as a laminated substrate of copper and molybdenum, for example. A reference potential such as a ground potential is supplied to the base 51. On the base 51, semiconductor chips 20a to 20c and capacitive components 24a to 24c are mounted.

[0025] Leads 27a to 27c are provided with an insulating layer (not shown) sandwiched on one side of the base 51 in the X direction. Leads 28a to 28c are provided on the + side of the base 51 in the X direction. A lead 29 is provided with an insulating layer (not shown) sandwiched on the + side of the base 51 in the Y direction. The leads 27a to 27c and 28a to 28c are a metal layer or a metal plate such as copper, for example. Signals S1 to S3 are respectively input to the leads 27a to 27c, and signals S4 to S6 are respectively output from the leads 28a to 28c.

[0026] The semiconductor chip 20a includes a substrate 21a, a transistor Q1, pads 22a and 23a provided on the upper surface of the substrate 21a, and electrodes (not shown) provided on the lower surface of the substrate 21a. The pads 22a, 23a and the electrodes on the lower surface are electrically connected to the gate G (input terminal), drain D (output terminal) and source S of the transistor Q1, respectively. The semiconductor chip 20b includes a substrate 21b, a transistor Q2, pads 22b and 23b provided on the upper surface of the substrate 21b, and electrodes provided on the lower surface of the substrate 21b. The pads 22b, 23b and the electrodes on the lower surface are electrically connected to the gate G (input terminal), drain D (output terminal) and source S of the transistor Q2, respectively. The semiconductor chip 20c includes a substrate 21c, a transistor Q3, pads 22c and 23c provided on the upper surface of the substrate 21c, and electrodes provided on the lower surface of the substrate 21c. The pads 22c, 23c and the electrodes on the lower surface are electrically connected to the gate G (input terminal), drain D (output terminal) and source S of the transistor Q3, respectively.

[0027] The substrates 21a to 21c are semiconductor substrates. When the transistors Q1 to Q3 are GaN HEMTs, the substrates 21a to 21c are, for example, silicon carbide (SiC) substrates, sapphire substrates or gallium nitride (GaN) substrates. When the transistors Q1 to Q3 are LDMOSs, the substrates 21a to 21c are, for example, silicon (Si) substrates. The pads 22a to 22c, 23a to 23c and the electrodes on the lower surface are metal layers such as gold layers, for example. The transistor Q1 is shown smaller than the transistors Q2 and Q3 (for example, having a smaller gate width and a smaller saturation power when the gate bias voltage and the drain bias voltage are the same), but the transistor Q1 may be the same as the transistors Q2 and Q3 (for example, having the same gate width and the same saturation power when the gate bias voltage and the drain bias voltage are the same).

[0028] The capacitive components 24a to 24c include a dielectric substrate 25, an electrode 26 provided on the upper surface of the dielectric substrate 25, and an electrode provided on the lower surface of the dielectric substrate 25. The electrode 26 and the lower surface electrode sandwiching the dielectric substrate 25 form a capacitor. The dielectric substrate 25 is, for example, an alumina substrate or a barium titanate substrate. The electrode 26 is a metal layer such as a gold layer, for example.

[0029] The bonding wires 46 connect the leads 27a to 27c and the electrodes 26 of the capacitive components 24a to 24c electrically, respectively. The bonding wires 47 connect the electrodes 26 of the capacitive components 24a to 24c and the pads 22a to 22c electrically, respectively. The bonding wires 48 connect the pads 23a to 23c and the leads 28a to 28c electrically, respectively. The bonding wire 49 connects the lead 27a and 29. The bonding wires 46 to 49 are metal wires such as gold wires or aluminum wires, for example.

[0030] The bonding wires 46 and 47 function as inductors, and the capacitive components 24a to 24c function as capacitors. The bonding wires 46, 47 and the capacitive components 24a to 24c correspond to the matching circuits 30 to 32 of the T-type LCL circuit.

[0031] Figure 3 is a plan view of the circuit board in the first embodiment. As shown in Figure 3, a package 50 is mounted on the circuit board 55. On the upper surface of the circuit board 55, lines 56a to 56b, 57a to 57c, impedance converters 52, 53 and open stubs 54 are provided. The circuit board 55 is a resin board such as a glass epoxy resin, for example. The lines 56a to 56c, 57a to 57c, impedance converters 52, 53 and open stubs 54 are metal layers such as copper layers.

[0032] Lines 56a to 56c are electrically connected to leads 27a to 27c respectively. Lines 57a to 57c are electrically connected to leads 28a to 28c respectively. Lines 56a to 56c and 57a to 57c extend in the X direction. Impedance converters 52 and 53 are provided in the middle of lines 57b and 57c. The impedance converters 52 and 53 have a desired characteristic impedance and are lines with an electrical length of 1 / 4 wavelength. If a 1 / 4 wavelength line is provided linearly, it will be long. Therefore, the 1 / 4 wavelength line is formed by folding like a meander. In FIG. 3, the appearance of the folded 1 / 4 wavelength line is shown in a rectangle.

[0033] The end of the open stub 54 is electrically connected to the lead 29. The open stub 54 extends in the X direction.

[0034] FIG. 4 is a schematic diagram showing the probability with respect to Pout in Example 1, the Pout of each amplifier with respect to Pin, the gain of each amplifier with respect to Pin, and the overall gain with respect to Pin.

[0035] The probability is the probability of the modulated wave signal of the high-frequency signal for mobile communication amplified by the Doherty amplifier circuit 100. That is, it is the probability that the Doherty amplifier circuit 100 outputs a certain output power Pout. Each Pout is the output power Pout of the main amplifier 10, the peak amplifiers 12 and 14. Each gain is the power gain of each of the main amplifier 10, the peak amplifiers 12 and 14. The overall gain is the power gain of the output power Pout of the output signal Sout with respect to the input power Pin of the input signal Sin. Note that Pin and Pout are in dB display. The gain of the main amplifier 10 with an input power Pin below the power P1 is greater than the gain of the peak amplifier 12 with a power above P1 and below P2. That is, the slope of Pout with respect to the input power Pin at an input power Pin of the main amplifier 10 below the power P1 is greater than the slope of Pout with respect to the input power Pin at an input power Pin of the peak amplifier 12 with a power above P1 and below P2. However, FIG. 4 is a schematic diagram, and shows that the slope of Pout with respect to the input power Pin at an input power Pin of the main amplifier 10 below the power P1 is smaller than the slope of Pout with respect to the input power Pin at an input power Pin of the peak amplifier 12 with a power above P1 and below P2.

[0036] As shown in FIG. 4, when the output power Pout is the power P0, the probability of the modulated wave is the highest. That is, when outputting the signal of the modulated wave, the time when the output power Pout is the power P0 is the longest. The main amplifier 10 is a class A or AB amplifier, and the peak amplifiers 12 and 14 are class C amplifiers. The input power Pin at which the peak amplifier 12 turns on is greater than the input power Pin at which the main amplifier 10 turns on, and the input power Pin at which the peak amplifier 14 turns on is greater than the input power Pin at which the peak amplifier 12 turns on. In order to operate in this way, it can be realized by making the gate bias voltage VG2 of the transistor Q2 more negative and larger than the gate bias voltage VG1 of the transistor Q1, and making the gate bias voltage VG3 of the transistor Q3 more negative and larger than the gate bias voltage VG2 of the transistor Q2.

[0037] As the input power Pin of the input signal Sin increases and the input power Pin exceeds the power P0 and reaches up to the power P1, the main amplifier 10 operates, but the peak amplifiers 12 and 14 do not operate. When the input power Pin is below the power P1, as the input power Pin increases, the output power Pout of the main amplifier 10 increases linearly. Therefore, when the input power Pin is below the power P1, each gain and the overall gain are almost constant.

[0038] When the input power Pin is equal to or greater than the power P1 and equal to or less than the power P2, the main amplifier 10 and the peak amplifier 12 operate, but the peak amplifier 14 does not operate. In this range, the main amplifier 10 saturates. Therefore, the gain of the main amplifier 10 decreases. Along with this, the overall gain also decreases. Since the peak amplifier 12 operates in class C, the gain of the peak amplifier 12 between the power P1 and P2 is lower than the gain of the main amplifier 10 below the power P1. Also, the saturation power of the peak amplifier 12 is smaller than the saturation power of the main amplifier 10.

[0039] When the input power Pin is equal to or greater than the power P2 and equal to or less than P3, all of the main amplifier 10, the peak amplifiers 12 and 14 operate. In this range, in addition to the main amplifier 10, the peak amplifier 12 saturates. Therefore, the gain of the peak amplifier 12 decreases. Along with this, the overall gain also decreases. Since the operating point of the peak amplifier 14 is more negative than that of the peak amplifier 12, the gain of the peak amplifier 14 between the power P2 and P3 is lower than the gain of the peak amplifier 12 between the power P1 and P2. Also, the saturation power of the peak amplifier 14 is smaller than the saturation power of the peak amplifier 12.

[0040] When the input power Pin is equal to or greater than the power P3, in addition to the main amplifier 10 and the peak amplifier 12, the peak amplifier 14 saturates. Therefore, the gain of the peak amplifier 14 decreases. Along with this, the overall gain also decreases.

[0041] The product of the probability and the overall gain corresponds to the gain of the modulated wave. In order to improve the gain of the modulated wave, the overall gain at a high probability Pout is improved.

[0042] [Comparative Example 1] FIG. 5 is a block diagram of the Doherty amplifier circuit in Comparative Example 1. As shown in FIG. 5, in the Doherty amplifier circuit 110 of Comparative Example 1, a phase adjuster 58 is provided instead of the open stub 54. The phase adjuster 58 is, for example, a 1 / 4 wavelength line. By the impedance converters 52 and 53, the phases of the signals S5 and S6 are rotated by 90°. For this reason, the phase adjuster 58 is, for example, a 1 / 4 wavelength line.

[0043] FIG. 6 is a plan view of the semiconductor device in Comparative Example 1. As shown in FIG. 6, in Comparative Example 1, instead of the open stub 54, a phase adjuster 58 is provided in the middle of the line 56a.

[0044] In the Doherty amplifier circuit, in the synthesizer 18, in order to appropriately convert the impedance according to the operating states of the main amplifier 10, the peak amplifiers 12 and 14, the impedance converters 52 and 53 are used in any of the paths between the main amplifier 10, the peak amplifiers 12 and 14 and the synthesis node N1. The impedance converters 52 and 53 are, for example, 1 / 4 wavelength lines and the phase rotates by 90°. When the phases of the signals S4 to S6 are not aligned at the synthesis node N1, the overall gain decreases when the input power Pin in FIG. 4 is equal to or higher than the power P1.

[0045] Therefore, a phase adjuster 58 is provided in the path where the impedance converters 52 and 53 are not provided. Thereby, at the synthesis node N1, the phases of the signals S4 to S6 are aligned and the signals S4 to S6 are synthesized. Thereby, the overall gain can be improved.

[0046] However, since the phase adjuster 58 adjusts the phase that rotates by 90° in the impedance converters 52 and 53, the phase is rotated by 90°. For this reason, if a 1 / 4 wavelength line is used as the phase adjuster 58, the Doherty amplifier circuit becomes large-sized.

[0047] [Description of Example 1] In the Doherty amplifier circuit 100, the impedance seen from the main amplifier 10, peak amplifiers 12 and 14 to the combined node N1 is appropriately converted, and when the peak amplifiers 12 and 14 are not operating, the impedance seen from the combined node N1 to the peak amplifiers 12 and 14 is made infinite. For this reason, an impedance converter 52 (first impedance converter) is provided in which the first end of one of the peak amplifiers 12 and 14 (for example, peak amplifier 12) is electrically connected and the second end is electrically connected to the combined node N1. In such a case, as shown in FIG. 1, an open stub 54 whose end is electrically connected to the path between one of the main amplifier 10, peak amplifiers 12 and 14 (for example, main amplifier 10) and the distributor 16 is provided as a phase adjuster. For example, in order to rotate the phase of the signal S1 by 90°, the electrical length of the open stub 54 at the center wavelength of the operating band is 1 / 8 wavelength. Thereby, as shown in FIG. 3, the open stub 54 can be shortened, and thus the circuit board 55 can be miniaturized. The peak amplifier 14 and the impedance converter 53 may not be provided.

[0048] The electrical length of the 1 / 8 wavelength line used as the open stub 54 does not have to be exactly 1 / 8 wavelength with respect to the center frequency of the operating band, as long as the phases of the signals S4 to S6 can be aligned. The electrical length of the 1 / 8 wavelength line may be, for example, 3 / 32 wavelength or more and 5 / 32 wavelength or less, or 7 / 64 wavelength or more and 9 / 64 wavelength or less.

[0049] When two or more peak amplifiers 12 and 14 are provided, an impedance converter 53 (second impedance converter) is provided in which the first end of one of the peak amplifiers 12 and 14 (for example, peak amplifier 14) is electrically connected and the second end is electrically connected to the combined node N1. In this case, the phases of both the signals S5 and S6 are rotated by 90°. Therefore, by providing the open stub 54, the phases of the signals S4 to S6 at the combined node N1 can be aligned.

[0050] An impedance converter is not provided between the main amplifier 10 and the combining node N1. In this case, by providing the open stub 54, the phases of the signals S4 to S6 at the combining node N1 can be aligned.

[0051] When quarter-wave lines are provided as the impedance converters 52 and 53, it is difficult to achieve broadband operation. Therefore, in order to broaden the bandwidth of the main amplifier 10 that operates at all input powers Pin as shown in FIG. 4, there may be a case where no impedance converter is provided between the main amplifier 10 and the combining node N1 as shown in FIG. 1. In such a case, the open stub 54 is connected between the distributor 16 and the main amplifier 10. Thus, the first amplifier is the main amplifier 10, and the second and third amplifiers are the peak amplifiers 12 and 14.

[0052] In Comparative Example 1, as shown in FIG. 6, the main amplifier 10, the peak amplifiers 12 and 14 are arranged in the Y direction (the first direction). The impedance converters 52 and 53 are provided in the + direction in the X direction (the second direction intersecting the first direction) of the peak amplifiers 12 and 14. The phase adjuster 58 is provided in the - direction in the X direction of the main amplifier 10. For this reason, the width of the circuit board 55 in the X direction becomes large.

[0053] In Embodiment 1, the open stub 54 is provided in the Y direction of the main amplifier 10. Thereby, the width of the circuit board 55 in the X direction can be reduced. Thus, the circuit board 55 can be miniaturized. The open stub 54 extends in the X direction. Thereby, the width of the circuit board 55 in the Y direction can be reduced.

[0054] As shown in FIGS. 2 and 3, the main amplifier 10, peak amplifiers 12 and 14 are mounted on the package 50. The open stub 54 and impedance converters 52 and 53 are not mounted on the package 50 but are provided on the circuit board 55. By mounting the package 50 on the circuit board 55, the main amplifier 10, peak amplifiers 12 and 14 can be provided on the circuit board 55, and the impedance converters 52 and 53 can be provided on the circuit board 55.

[0055] The impedance converters 52 and 53 are quarter-wavelength lines with respect to the center frequency of the operating band. Thereby, the impedance converters 52 and 53 can convert the impedance on the real axis in the Smith chart into the impedance on the real axis. The open stub 54 is an eighth-wavelength line with respect to the center frequency of the operating band. Thereby, the phases of the signals S5 and S6 rotated by 90° in the impedance converters 52 and 53 can be aligned with the phase of the signal S4.

[0056] The semiconductor device 102 in FIG. 2 includes leads 27a (first input terminal), 27b (second input terminal), 27c (third input terminal), 28a (first output terminal), 28b (second output terminal), and 28c (third output terminal). The lead 29 (terminal) is connected to the line between the lead 27a and the main amplifier 10, and the open stub 54 for adjusting the phase of the signal S1 can be connected. In this way, by providing the lead 29 for the open stub 54 on the package 50, the circuit board 55 can be miniaturized as shown in FIG. 3.

[0057] The package 50 has opposing sides 59a and 59b in the X direction and opposing sides 59c and 59d in the Y direction. Leads 27a to 27c are provided on side 59a (the first side), and leads 28a to 28c are provided on side 59b (the second side). The main amplifier 10 is the closest to side 59c (the third side) that connects sides 59a and 59b among the main amplifier 10, peak amplifiers 12 and 14. The lead 29 is provided on side 59c. Thereby, the bonding wire 49 connected to the lead 29 can be shortened. Therefore, the electrical length between the path between the lead 27a and the main amplifier 10 and the open stub 54 can be shortened. The accuracy of the substantial electrical length of the open stub 54 can be improved.

[0058] Although the 3-way Doherty amplifier circuit has been described as an example, it may also be a 2-way Doherty amplifier circuit in which the peak amplifier 14 and the impedance converter 53 are not provided. Further, it may be an N-way Doherty amplifier circuit where N is 4 or more. In this case, N-1 peak amplifiers may be provided.

[0059] It should be considered that the embodiments disclosed this time are illustrative in all respects and not restrictive. The scope of the present disclosure is shown not by the above meaning but by the claims, and it is intended that all modifications within the meaning and scope equivalent to the claims are included.

Explanation of reference numerals

[0060] 10 (first amplifier) main amplifier 12 (second amplifier), 14 (third amplifier) peak amplifier 16 splitter 18 combiner 20a, 20b, 20c semiconductor chip 21a, 21b, 21c substrate 22a, 22b, 22c, 23a, 23b, 23c pad 24a, 24b, 24c capacitive component 25 dielectric substrate 26 electrode 27a (First input terminal), 27b (Second input terminal), 27c (Third input terminal), 28a (First output terminal), 28b (Second output terminal), 28c (Third output terminal), 29 (Terminal) Lead 30, 31, 32, 33, 34, 35 Integrated circuit 36, 37, 38, 39 Bias circuit 46, 47, 48, 49 Bonding wire 50 Package 51 Base 52 (First impedance converter), 53 (Second impedance converter) Impedance converter 54 Open stub 55 Circuit board 56a, 56b, 56c, 57a, 57b, 57c Line 58 Phase adjuster 59a (First side), 59b (Second side), 59c (Third side), 59d Side 100, 110 Doherty amplifier circuit 102 Semiconductor device S1 (First signal), S2 (Second signal), S3 (Third signal), S4 (Fourth signal), S5 (Fifth signal), S6 (Sixth signal) Signal N1 Composite node Sin Input signal Sout Output signal Tin Input terminal Tout Output terminal

Claims

1. A distributor that distributes an inputted input signal into a first signal and a second signal, A circuit board, A first amplifier provided on the circuit board that amplifies the first signal and outputs the amplified signal as a fourth signal, A second amplifier provided on the circuit board that amplifies the second signal and outputs the amplified signal as a fifth signal, A combining node that combines the fourth signal and the fifth signal and outputs the combined signal as an output signal to an output terminal, An open stub provided on the circuit board, with an end electrically connected to a path between the distributor and the first amplifier, A first impedance converter provided on the circuit board, with a first end electrically connected to the second amplifier and a second end electrically connected to the combining node, A Doherty amplifier circuit comprising the above.

2. A third amplifier provided on the circuit board that amplifies a third signal and outputs the amplified signal as a sixth signal, A second impedance converter provided on the circuit board, with a first end electrically connected to the third amplifier and a second end electrically connected to the combining node, Comprising, The distributor distributes the input signal into the first signal, the second signal, and the third signal, The Doherty amplifier circuit according to claim 1, wherein the combining node combines the fourth signal, the fifth signal, and the sixth signal and outputs the combined signal as the output signal to the output terminal.

3. The Doherty amplifier circuit according to claim 1 or claim 2, wherein no impedance converter is provided between the first amplifier and the combining node.

4. The Doherty amplifier circuit according to claim 1 or claim 2, wherein the first amplifier is a main amplifier and the second amplifier is a peak amplifier.

5. The first amplifier and the second amplifier are arranged in a first direction, The first impedance converter is provided in a second direction intersecting the first direction of the first amplifier, The Doherty amplifier circuit according to claim 1 or claim 2, wherein the open stub is provided in the first direction of the first amplifier.

6. Comprising a package mounted on the circuit board on which the first amplifier and the second amplifier are mounted, The Doherty amplifier circuit according to claim 1 or claim 2, wherein the open stub and the first impedance converter are not mounted on the package.

7. The first impedance converter is a quarter-wavelength line with respect to the center frequency of the operating band, and the open stub is an eighth-wavelength line with respect to the center frequency of the operating band. The Doherty amplifier circuit according to claim 1 or claim 2.

8. A first input terminal to which a first signal obtained by distributing an input input signal is input; A second input terminal to which a second signal obtained by distributing the input signal is input; A first amplifier that amplifies the first signal and outputs the amplified signal as a fourth signal; A second amplifier that amplifies the second signal and outputs the amplified signal as a fifth signal; A first output terminal from which the fourth signal is output; A second output terminal from which the fifth signal is output; A terminal connected to a line between the first input terminal and the first amplifier and to which an open stub for adjusting the phase of the first signal can be connected; A semiconductor device for a Doherty amplifier circuit comprising:

9. A third input terminal to which a third signal obtained by distributing the input signal is input; A third amplifier that amplifies the third signal and outputs the amplified signal as a sixth signal; A third output terminal from which the sixth signal is output; The semiconductor device according to claim 8, comprising:

10. A package mounting the first amplifier and the second amplifier arranged in a first direction, The first input terminal and the second input terminal are provided on the first side of first and second sides facing each other in a second direction intersecting the first direction of the package, The first output terminal and the second output terminal are provided on the second side of the package, The terminal is provided on a third side connecting the first side and the second side, and the first amplifier is closer to the third side than the second amplifier. The semiconductor device according to claim 8 or claim 9.

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