Wiring board and semiconductor device

Abstract

To improve the dissipation of heat generated by an electronic component in a wiring board having an electronic component built therein.SOLUTION: A wiring board 5 has: a first wiring structure 1 having a first wiring layer 11, a first insulating layer 13, and an electronic component 12 built in the first insulating layer 13; and a second wiring structure 2 having a second wiring layer 21 and a second insulating layer 22 and laminated on one side of the first wiring structure 1. The second wiring layer 21 is higher in wiring density than the first wiring layer 11. The first wiring layer 11 includes a pad having a portion exposed from the first insulating layer 13. The first insulating layer 13 has, in a plan view, a first region in which the pad is arranged and a second region located on the outer periphery of the first region. The electronic component 12 is arranged in the second region and is electrically connected to the second wiring layer 21.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a wiring board and a semiconductor device.

Background Art

[0002] When mounting a semiconductor chip on a wiring board, for example, it is mounted through a wiring structure serving as an interposer having fine wirings. The interposer includes a silicon substrate, a glass substrate, an organic substrate, and the like. A technique for incorporating electronic components in such a wiring board has been proposed (see, for example, Patent Document 1). In such a wiring board, it is preferable to efficiently dissipate heat generated by the electronic components.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the above points, and an object thereof is to improve the heat dissipation of heat generated by electronic components in a wiring board incorporating the electronic components.

Means for Solving the Problems

[0005] This wiring board has a first wiring layer and a first insulating layer, and a first wiring structure having electronic components built in the first insulating layer, and a second wiring layer and a second insulating layer, and a second wiring structure laminated on one side of the first wiring structure, the second wiring layer has a higher wiring density than the first wiring layer, the first wiring layer includes pads having portions exposed from the first insulating layer, the first insulating layer includes a first region where the pads are arranged and a second region located on the outer peripheral side of the first region in a plan view, the electronic components are arranged in the second region and are electrically connected to the second wiring layer.

Advantages of the Invention

[0006] According to the disclosed technology, in a wiring board incorporating electronic components, the heat dissipation of the heat generated by the electronic components can be improved.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Modes for Carrying Out the Invention

[0008] Hereinafter, modes for carrying out the invention will be described with reference to the drawings. In each drawing, the same reference numerals are assigned to the same components, and redundant descriptions may be omitted.

[0009] <First Embodiment> [Structure of Wiring Substrate] FIG. 1 is a plan view illustrating a wiring substrate according to the first embodiment. FIG. 2 is a cross-sectional view illustrating the wiring substrate according to the first embodiment, showing a cross-section along line A-A in FIG. 1. In FIG. 2, for the convenience of drawing preparation, the electronic component 12 is drawn wider than in FIG. 1. The same applies to other cross-sectional views.

[0010] Referring to FIGS. 1 and 2, the wiring substrate 5 has a first wiring structure 1, a second wiring structure 2, and a third wiring structure 3. The second wiring structure 2 is laminated on one side in the thickness direction of the first wiring structure 1. The third wiring structure 3 is laminated on the other side in the thickness direction of the first wiring structure 1. That is, the third wiring structure 3 is disposed on the side opposite to the second wiring structure 2 with the first wiring structure 1 interposed therebetween. Note that the wiring substrate 5 may be composed of the first wiring structure 1 and the second wiring structure 2. That is, the wiring substrate 5 may not have the third wiring structure 3.

[0011] In the present embodiment, for convenience, the side of the wiring layer 27 (described later) of the wiring substrate 5 in FIG. 1 is defined as the upper side or one side, and the side of the wiring layer 331 (described later) is defined as the lower side or the other side. Also, the surface on the wiring layer 27 side of each part is defined as one surface or the upper surface, and the surface on the wiring layer 331 side is defined as the other surface or the lower surface. However, the wiring substrate 5 can be used in an upside-down state or arranged at an arbitrary angle. Also, a plan view refers to viewing an object from the normal direction of one surface of the insulating layer 26 (described later), and a planar shape refers to the shape of an object viewed from the normal direction of one surface of the insulating layer 26.

[0012] The first wiring structure 1 is a wiring structure in which a wiring layer and an insulating layer are laminated, and has electronic components built in the insulating layer. When the wiring layer of the first wiring structure 1 is referred to as the first wiring layer, the insulating layer of the first wiring structure 1 is referred to as the first insulating layer, and the via wiring of the first wiring structure 1 is referred to as the first via wiring. In the example of FIG. 2, the first wiring structure 1 has a wiring layer 11 as the first wiring layer, an insulating layer 13 as the first insulating layer, and a via wiring 14 as the first via wiring. In the first wiring structure 1, the number of layers of the first wiring layer, the first insulating layer, and the first via wiring is not limited to the example of FIG. 2.

[0013] In the first wiring structure 1, the wiring layer 11 is embedded on the lower surface side of the insulating layer 13. The wiring layer 11 has a portion exposed from the insulating layer 13. Specifically, the lower surface of the wiring layer 11 is exposed from the lower surface of the insulating layer 13, and the upper surface and side surfaces of the wiring layer 11 are covered by the insulating layer 13. In the example of FIG. 2, the lower surface of the wiring layer 11 is flush with the lower surface of the insulating layer 13. However, the lower surface of the wiring layer 11 may be recessed on the via wiring 14 side from the lower surface of the insulating layer 13.

[0014] The lower surface of the wiring layer 11 exposed from the lower surface of the insulating layer 13 can be used, for example, as a pad having a circular planar shape and connected to the third wiring structure 3. That is, the wiring layer 11 includes a pad having a portion exposed from the insulating layer 13. The wiring layer 11 may include a wiring pattern in addition to the pad. As the material of the wiring layer 11, for example, copper (Cu) or the like can be used. The wiring layer 11 may have a laminated structure of a plurality of metal layers. The thickness of the wiring layer 11 can be, for example, about 10 to 35 μm. The line / space of the wiring layer 11 can be, for example, about 10 μm / 10 μm to 50 μm / 50 μm.

[0015] Note that in the line / space, the "line" represents the wiring width, and the "space" represents the interval between adjacent wirings (wiring interval). For example, when the line / space is described as 10μm / 10μm to 50μm / 50μm, it means that the wiring width is 10μm or more and 50μm or less, and the wiring interval between adjacent wirings is 10μm or more and 50μm or less. It is not necessarily required that the wiring width and the wiring interval be equal.

[0016] The insulating layer 13 includes, in plan view, a first region where the pads of the wiring layer 11 are disposed and a second region located on the outer peripheral side of the first region. B shown by the two-dot chain line in FIG. 1 indicates an example of the boundary between the first region and the second region. The inside of the boundary B is the first region, and the outside of the boundary B is the second region. Note that the two-dot chain line indicating the boundary B is a virtual line for convenience and does not actually exist.

[0017] In the first wiring structure 1, the electronic component 12 is built in the insulating layer 13. The electronic component 12 is disposed in the second region. That is, the electronic component 12 is disposed at a position on the outer peripheral side of the region where the pads constituting the wiring layer 11 are disposed in plan view and does not interfere with the layout of the pads constituting the wiring layer 11. The electronic component 12 includes an electrode 121 on the side of the second wiring structure 2.

[0018] The electronic component 12 may be a passive component, an active component, or a mixture of both. The electronic component 12 is, for example, an IPD (Intelligent Power Device), a semiconductor chip, a capacitor, an inductor, a resistor, or the like. The thickness of the electronic component 12 excluding the electrode 121 can be, for example, about 50μm to 100μm. The thickness of the electrode 121 can be, for example, about 5μm to 10μm. The thermal expansion coefficient of the electronic component 12 is smaller than that of the insulating layer 13.

[0019] Thus, in the wiring board 5, the insulating layer 13 of the first wiring structure 1 includes, in a plan view, a first region where pads constituting the wiring layer 11 are arranged, and a second region located on the outer peripheral side of the first region. And the electronic component 12 is arranged in the second region. Thereby, since the heat generated by the electronic component 12 easily escapes to the outside of the insulating layer 13, the heat dissipation of the heat generated by the electronic component 12 can be improved.

[0020] The first wiring structure 1 is mounted on the third wiring structure 3 by a joining member 40 (described later) such as solder. During mounting, the first wiring structure 1 is heated and the first wiring structure 1 thermally contracts. However, the thermal contraction of the first wiring structure 1 during mounting is smaller on the first region side (center side) than on the second region side (outer peripheral side) of the insulating layer 13. Therefore, by arranging the pads constituting the wiring layer 11 in the first region with less thermal contraction, the amount of displacement of the pads constituting the wiring layer 11 during mounting is reduced, so that the pads constituting the wiring layer 11 can be made narrower in pitch.

[0021] Also, by incorporating the electronic component 12 in the insulating layer 13 of the first wiring structure 1, the distance in the thickness direction from the semiconductor chip mounted on the second wiring structure 2 can be shortened. Thereby, since the electrical path between the electronic component 12 and the semiconductor chip or the like is also shortened, the resistance loss can be reduced. As a result, improvement in power efficiency and stabilization of the power supply can be realized. Also, the signal characteristics can be improved.

[0022] Also, by arranging the electronic component 12 having a coefficient of thermal expansion smaller than that of the insulating layer 13 on the outer peripheral side of the region where the pads of the insulating layer 13 are arranged, the rigidity of the first wiring structure 1 can be increased. Thereby, warping and expansion / contraction of the first wiring structure 1 due to heating when mounting the first wiring structure 1 on the third wiring structure 3 can be reduced. Also, as a result of reducing the warping and expansion / contraction of the first wiring structure 1, the mounting accuracy when mounting the first wiring structure 1 on the third wiring structure 3 can be improved. Also, as a result of reducing the warping and expansion / contraction of the first wiring structure 1, the amount of displacement of the pads constituting the wiring layer 11 during mounting is further reduced, so that the pads constituting the wiring layer 11 can be made even narrower in pitch.

[0023] The electronic component 12 may be arranged in one or more in the second region. However, from the viewpoint of reducing the warping and expansion / contraction of the first wiring structure 1, it is preferable that a plurality of electronic components 12 are arranged in the second region. In the example of FIG. 1, 14 electronic components 12 are arranged. Further, from the viewpoint of evenly reducing the warping and expansion / contraction of the first wiring structure 1, it is preferable that the plurality of electronic components 12 are arranged point-symmetrically with respect to the center of the insulating layer 13 in a plan view.

[0024] In the example of FIG. 1, in a plan view, the insulating layer 13 is rectangular. The shape of the insulating layer 13 is substantially the same as the shape of the insulating layer 26 shown in FIG. 1. As shown in FIG. 1, when the insulating layer 13 is rectangular in a plan view, it is preferable to arrange the plurality of electronic components 12 so as to be scattered along each side of the rectangle in a frame shape. In this case, since the plurality of electronic components 12 function as stiffeners, the warping and expansion / contraction of the first wiring structure 1 can be further reduced. As a result, it is more advantageous for improving the mounting accuracy when mounting the first wiring structure 1 on the third wiring structure 3 and for making the pitch of the pads constituting the wiring layer 11 narrower.

[0025] The insulating layer 13 is formed so as to cover the upper surface and the side surface of the wiring layer 11. Further, the insulating layer 13 is formed so as to cover the upper surface and the side surface of the electronic component 12. The lower surface of the electronic component 12 and the lower surface of the pad constituting the wiring layer 11 are exposed from the lower surface of the insulating layer 13. The lower surface of the electronic component 12 and the lower surface of the pad constituting the wiring layer 11 can be flush with the lower surface of the insulating layer 13, for example.

[0026] The insulating layer 13 is, for example, an insulating layer mainly composed of a non-photosensitive resin. The insulating layer 13 can be mainly composed of a thermosetting non-photosensitive resin such as an epoxy resin, an imide resin, a phenolic resin, or a cyanate resin. The thickness of the insulating layer 13 is preferably greater than the total thickness of the electronic component 12 and the electrode 121. The insulating layer 13 may contain a filler such as silica (SiO 2 ). Further, the insulating layer 13 may contain a reinforcing member such as glass fiber.

[0027] The insulating layer 13 is provided with via holes 13x that penetrate the insulating layer 13 and expose the upper surface of the wiring layer 11. Further, the insulating layer 13 is provided with via holes 13y that penetrate the insulating layer 13 and expose the upper surface of the electrode 121 of the electronic component 12. The via holes 13x and 13y can be formed as inverted frustoconical recesses in which the diameter of the opening on the second wiring structure 2 side is larger than the diameter of the bottom surface of the opening formed by the upper surface of the wiring layer 11 or the upper surface of the electrode 121.

[0028] The via wiring 14 fills the via holes 13x and 13y. The via wiring 14 does not have a portion extending on the upper surface of the insulating layer 13. The upper surface of the via wiring 14 is exposed from the upper surface of the insulating layer 13. The upper surface of the via wiring 14 is, for example, flush with the upper surface of the insulating layer 13. The upper surface of the via wiring 14 and the upper surface of the insulating layer 13 are polished surfaces. Therefore, the upper surface of the via wiring 14 and the upper surface of the insulating layer 13 are smooth surfaces (low roughness surfaces) with few irregularities. The roughness of the upper surface of the via wiring 14 and the upper surface of the insulating layer 13 can be about 15 to 40 nm in terms of surface roughness Ra.

[0029] The second wiring structure 2 is a wiring structure in which a wiring layer and an insulating layer are laminated. The wiring layer of the second wiring structure 2 may be referred to as a second wiring layer, the insulating layer of the second wiring structure 2 may be referred to as a second insulating layer, and the via wiring of the second wiring structure 2 may be referred to as a second via wiring. In the example of FIG. 2, the second wiring structure 2 has wiring layers 21, 23, 25, and 27 as the second wiring layer and insulating layers 22, 24, and 26 as the second insulating layer. In the second wiring structure 2, the number of layers of the second wiring layer and the second insulating layer is not limited to the example of FIG. 2.

[0030] The wiring width and wiring pitch of the second wiring layer constituting the second wiring structure 2 are smaller than the wiring width and wiring pitch of the first wiring layer constituting the first wiring structure 1. That is, the second wiring layer is a fine wiring layer with a higher wiring density than the first wiring layer. The total thickness of the second wiring structure 2 can be, for example, about 80 to 100 μm. Here, the total thickness of the second wiring structure 2 is the distance in the thickness direction from the lower surface of the insulating layer 22 to the upper surface of the wiring layer 27.

[0031] The wiring layer 21 is pads and / or wiring patterns formed on the upper surface of the insulating layer 13 and the upper surface of the via wiring 14. A part of the lower surface of the wiring layer 21 is in contact with the upper surface of the via wiring 14, and the two are electrically connected. That is, the via wiring 14 is directly connected to the wiring layer 21 which is the lowermost second wiring layer. The wiring layer 21 includes a portion electrically connected to the wiring layer 11 via the via wiring 14. In addition, the wiring layer 21 includes a portion electrically connected to the electrode 121 of the electronic component 12 via the via wiring 14. As the material of the wiring layer 21, for example, mainly copper or the like can be used. The thickness of the wiring layer 21 can be, for example, about 1 to 10 μm. The line / space of the wiring pattern constituting the wiring layer 21 can be, for example, about 1 μm / 1 μm to 8 μm / 8 μm.

[0032] The insulating layer 22 is provided on the upper surface of the insulating layer 13 and covers the upper surface and side surfaces of the wiring layer 21. The insulating layer 22 is, for example, an insulating layer mainly composed of a photosensitive insulating resin. Examples of the photosensitive insulating resin include phenolic resins and polyimide resins. The insulating layer 22 may contain fillers such as silica (SiO 2 ). The insulating layer 22 is thinner than the insulating layer 13. The thickness of the insulating layer 22 can be, for example, about 3 to 20 μm. The insulating layer 22 is provided with via holes 22x that penetrate the insulating layer 22 and reach the upper surface of the wiring layer 21.

[0033] The wiring layer 23 is formed on one side of the insulating layer 22 and is electrically connected to the wiring layer 21. The wiring layer 23 fills the via holes 22x and extends to the upper surface of the insulating layer 22. The portion filling the via holes 22x is via wiring, and the portion extending to the upper surface of the insulating layer 22 is pads and / or wiring patterns. The material of the wiring layer 23, the thickness of the wiring pattern constituting the wiring layer 23, and the line / space of the wiring pattern constituting the wiring layer 23 can be, for example, the same as those of the wiring layer 21.

[0034] The insulating layer 24 is provided on one surface of the insulating layer 22 and covers the upper surface and the side surface of the wiring layer 23. The material and thickness of the insulating layer 24 can be the same as those of the insulating layer 22, for example. The insulating layer 24 may contain fillers such as silica (SiO 2 ). A via hole 24x penetrating the insulating layer 24 and reaching the upper surface of the wiring layer 23 is provided in the insulating layer 24.

[0035] The wiring layer 25 is formed on one side of the insulating layer 24 and is electrically connected to the wiring layer 23. The wiring layer 25 fills the via hole 24x and extends on the upper surface of the insulating layer 24. The portion filling the via hole 24x is a via wiring, and the portion extending on the upper surface of the insulating layer 24 is a pad and / or a wiring pattern. The material of the wiring layer 25, the thickness of the wiring pattern constituting the wiring layer 25, and the line / space of the wiring pattern constituting the wiring layer 25 can be the same as those of the wiring layer 21, for example.

[0036] The insulating layer 26 is provided on one surface of the insulating layer 24 and covers the upper surface and the side surface of the wiring layer 25. The material and thickness of the insulating layer 26 can be the same as those of the insulating layer 24, for example. The insulating layer 26 may contain fillers such as silica (SiO 2 ). A via hole 26x penetrating the insulating layer 26 and reaching the upper surface of the wiring layer 25 is provided in the insulating layer 26.

[0037] The wiring layer 27 is formed on one side of the insulating layer 26 and is electrically connected to the wiring layer 25. The wiring layer 27 fills the via hole 26x and extends on the upper surface of the insulating layer 26. The portion filling the via hole 26x is a via wiring, and the portion extending on the upper surface of the insulating layer 26 is an electrode for external connection. The material of the wiring layer 27 can be the same as that of the wiring layer 21, for example. The thickness of the electrode constituting the wiring layer 27 can be about 50 μm, for example. The electrode constituting the wiring layer 27 can be used for electrical connection with electronic components such as semiconductor chips. The wiring layer 27 can be electrically connected to the electrode 121 of the electronic component 12 via the wiring layer 25, the wiring layer 23, the wiring layer 21, and the via wiring 14.

[0038] The third wiring structure 3 is a wiring structure in which a wiring layer and an insulating layer are laminated. The wiring layer of the third wiring structure 3 may be referred to as the third wiring layer, and the insulating layer of the third wiring structure 3 may be referred to as the third insulating layer. In the third wiring structure 3, the number of layers of the third wiring layer and the third insulating layer is not limited to the example of FIG. 2.

[0039] The wiring width and wiring pitch of the second wiring layer constituting the second wiring structure 2 are smaller than the wiring width and wiring pitch of the third wiring layer constituting the third wiring structure 3. That is, the second wiring layer is a fine wiring layer with a higher wiring density than the third wiring layer. The line / space of the third wiring layer can be, for example, about 10 μm / 10 μm to 20 μm / 20 μm.

[0040] The third wiring structure 3 only needs to have pads or the like connected to the first wiring structure 1, and may have, for example, the same structure as a well-known build-up wiring board. In the example of FIG. 2, the third wiring structure 3 is a multilayer wiring board in which a first laminate 32 is laminated on one side of a core layer 31 and a second laminate 33 is laminated on the other side. In each of the first laminate 32 and the second laminate 33, a wiring layer and an insulating layer are sequentially laminated from the core layer 31 side, and a solder resist layer is formed on the outermost layer.

[0041] The first laminate 32 has a wiring layer 321 including pads as the uppermost wiring layer. The pads constituting the wiring layer 321 are electrically connected to the pads constituting the wiring layer 11 of the first wiring structure 1 via a joining member 40. The joining member 40 is, for example, a solder bump. As the material of the solder bump, for example, SnBi solder or the like can be used.

[0042] An adhesive layer 50 may be formed between the upper surface of the third wiring structure 3 and the lower surface of the first wiring structure 1. As the material of the adhesive layer 50, for example, an epoxy-based insulating resin or the like can be used. The adhesive layer 50 can be formed, for example, by laminating a film of an insulating thermosetting resin called NCF (Non Conductive Film) on the lower surface side of the first wiring structure 1 and performing thermosetting when mounting the first wiring structure 1 on the third wiring structure 3.

[0043] By forming the adhesive layer 50 between the upper surface of the third wiring structure 3 and the lower surface of the first wiring structure 1, the adhesive layer 50 is in direct contact with the insulating layer 13. As a result, the heat generated by the electronic component 12 easily escapes from the insulating layer 13 to the adhesive layer 50 side, so that the heat dissipation performance of the first wiring structure 1 can be further improved.

[0044] The second laminate 33 has, as the lowermost wiring layer, a wiring layer 331 including pads. The pads constituting the wiring layer 331 can be used for electrical connection with a mounting substrate such as a motherboard.

[0045] [Manufacturing Method of Wiring Substrate] Next, a manufacturing method of the wiring substrate according to the first embodiment will be described. FIGS. 3 to 5 are diagrams illustrating the manufacturing process of the wiring substrate according to the first embodiment. Here, an example of the process of forming a layer structure only on one side of the support is shown, but it may also be a process of forming a layer structure on one side and the other side of the support. Note that the broken line C in each figure indicates the position to be cut when the wiring substrate is singulated. The region located between adjacent broken lines C in a cross-sectional view is finally singulated to become one wiring substrate.

[0046] First, in the process shown in FIG. 3(a), a support 300 is prepared. The support 300 has, for example, a structure in which a copper foil 304 with a carrier is laminated on one side of a core substrate 301. The core substrate 301 is, for example, a resin substrate having a thickness of about 0.7 mm and may have a reinforcing member such as glass fiber. The copper foil 304 with a carrier has a structure in which a thin foil 304a made of, for example, copper with a thickness of about 1.5 to 5 μm is adhered in a peelable state via a release layer (not shown) on a thick foil (carrier foil) 304b made of, for example, copper with a thickness of 10 to 50 μm. The thick foil 304b is provided as a support material for facilitating the handling of the thin foil 304a.

[0047] Note that the structure of the above-described support 300 is an example and is not limited thereto. For example, in the support 300, instead of the core substrate 301, a laminate in which a plurality of prepregs are laminated may be used. Further, the support 300 may have a structure in which a copper foil 304 with a carrier is disposed on one side of a glass substrate, a metal substrate, or the like via a release layer.

[0048] Next, in the process shown in FIG. 3(b), a wiring layer 11 is formed on the support 300. Specifically, a resist layer having an opening in a portion where the wiring layer 11 is to be formed is formed on the upper surface (the upper surface of the thin foil 304a) of the copper foil 304 with a carrier using a dry film resist or the like. Then, by an electrolytic plating method using the copper foil 304 with a carrier, which is a metal layer, as a power feeding layer, a wiring layer 11, which is an electrolytic plating layer, is formed on the upper surface of the copper foil 304 with a carrier exposed in the opening. The material and thickness of the wiring layer 11 are as described above. Thereafter, the resist layer is peeled off and removed.

[0049] Thereafter, an electronic component 12 having an electrode 121 is prepared, and the electronic component 12 is disposed face up on the outer peripheral side of the region surrounded by the broken line C on the upper surface of the copper foil 304 with a carrier. The electronic component 12 may be disposed directly on the upper surface of the copper foil 304 with a carrier or may be disposed via an adhesive layer.

[0050] Next, in the process shown in FIG. 3(c), an insulating layer 13 that covers the wiring layer 11 and the electronic component 12 is formed on the upper surface of the copper foil 304 with a carrier of the support 300. Specifically, first, for example, a semi-cured film-like insulating resin mainly composed of a thermosetting resin is prepared. Then, this insulating resin is laminated on the upper surface of the copper foil 304 with a carrier and cured while heating and pressurizing to form the insulating layer 13. Alternatively, instead of laminating the film-like insulating resin, a liquid or paste-like insulating resin may be applied and then cured to form the insulating layer 13. The material and thickness of the insulating layer 13 are as described above.

[0051] Generally, when heating and pressing a semi-cured insulating resin, the softened insulating resin tends to flow outwards, so the outer peripheral side of the insulating layer 13 is likely to lack resin and become thin. However, in the wiring board 5, electronic components 12 are arranged on the outer peripheral side of the insulating layer 13, and since the amount of resin required on the outer peripheral side is small, the variation in the thickness of the insulating layer 13 is reduced from the center side to the outer peripheral side of the insulating layer 13.

[0052] Next, in the process shown in FIG. 3(d), via holes 13x that penetrate the insulating layer 13 and expose the upper surface of the wiring layer 11 are formed in the insulating layer 13. Also, via holes 13y that penetrate the insulating layer 13 and expose the upper surface of the electrode 121 of the electronic component 12 are formed in the insulating layer 13. The via holes 13x and 13y can be formed, for example, by a laser processing method using a CO 2 laser, a YAG laser, an excimer laser, or the like.

[0053] The via holes 13x and 13y can be formed as inverted frustum-shaped recesses in which the diameter of the opening on the upper surface side of the insulating layer 13 is larger than the diameter of the bottom surface of the opening formed by the upper surface of the wiring layer 11 or the upper surface of the electrode 121. After forming the via holes 13x and 13y, it is preferable to perform a desmear treatment to remove the resin residues adhering to the upper surfaces of the wiring layer 11 and the electrode 121 exposed at the bottoms of the via holes 13x and 13y, respectively.

[0054] Next, in the process shown in FIG. 4(a), via wirings 14 that fill each of via holes 13x and 13y are formed. The via wirings 14 can be formed, for example, by a method combining a semi-additive method and polishing. Specifically, for example, a seed layer that continuously covers the upper surface of the insulating layer 13, the inner surfaces of the via holes 13x and 13y, and the upper surfaces of the wiring layer 11 and the electrode 121 exposed at the bottoms of the via holes 13x and 13y is formed by electroless copper plating or copper sputtering. Next, an electrolytic plating layer that fills the inside of the via holes 13x and 13y and extends to the upper surface of the insulating layer 13 is formed by an electrolytic plating method using the seed layer as a power supply layer. Thereafter, the electrolytic plating layer extending to the upper surface of the insulating layer 13 is removed by polishing to planarize the upper surface of the insulating layer 13 and the upper surface of the electrolytic plating layer. The upper surface of the insulating layer 13 may be polished together with the electrolytic plating layer. Thereby, the via wirings 14 that fill the inside of the via holes 13x and 13y are formed. For polishing, for example, the CMP method (chemical mechanical polishing method) can be used. The roughness of the upper surface of the via wiring 14 and the upper surface of the insulating layer 13 after polishing can be about 15 to 40 nm in terms of surface roughness Ra. Note that the roughness of the lower surface of the insulating layer 13 is, for example, about 180 to 280 nm in terms of surface roughness Ra. Through the above steps, the first wiring structure 1 is completed.

[0055] Next, in the process shown in FIG. 4(b), a wiring layer 21 is formed on the upper surface of the via wiring 14 and the upper surface of the insulating layer 13. A part of the lower surface of the wiring layer 21 is in contact with the upper surface of the via wiring 14, and the two are electrically connected. The wiring layer 21 can be formed, for example, by a semi-additive method.

[0056] Next, in the process shown in FIG. 4(c), an insulating layer 22 that covers the upper surface and the side surfaces of the wiring layer 21 is formed on the upper surface of the insulating layer 13. Specifically, for example, an uncured insulating resin film that covers the upper surface and the side surfaces of the wiring layer 21 is laminated on the upper surface of the insulating layer 13. Then, while heating this insulating resin film, pressure is applied to the insulating layer 13 side to cure it, thereby forming the insulating layer 22. At this time, in order to suppress the skin effect, it is preferable to select an insulating resin film with a low roughness of Ra 30 nm or less on the upper surface. It is more preferable to select an insulating resin film with a low roughness of Ra 20 nm or less, and it is even more preferable to select an insulating resin film with a low roughness of Ra 10 nm or less. Note that instead of laminating the insulating resin film, a liquid or paste-like insulating resin may be applied and then cured to form the insulating layer 22. At this time, when the roughness of the upper surface of the insulating layer 22 is high, in order to suppress the skin effect, it is preferable to perform smoothing by chemical mechanical polishing (CMP method: Chemical Mechanical Polishing method) or the like so that the roughness of the upper surface of the insulating layer 22 is as described above. The material and thickness of the insulating layer 22 are as described above.

[0057] Next, in the process shown in FIG. 4(d), a via hole 22x that penetrates the insulating layer 22 and exposes the upper surface of the wiring layer 21 is formed. The via hole 22x can be formed, for example, in the same manner as the via hole 13x. Next, in the process shown in FIG. 5(a), a wiring layer 23 is formed on the insulating layer 22. The wiring layer 23 can be formed, for example, by a semi-additive method. Next, in the process shown in FIG. 5(b), the same processes as those in FIGS. 4(c), 4(d), and 5(a) are repeated to sequentially form the insulating layer 24, the wiring layer 25, the insulating layer 26, and the wiring layer 27. Thereby, the second wiring structure 2 is completed.

[0058] Next, in the process shown in FIG. 5(c), after removing the support 300 shown in FIG. 5(b), it is diced. To remove the support 300, first, the core substrate 301 and the thick foil 304b are mechanically peeled from the thin foil 304a. Then, the thin foil 304a is removed by wet etching using, for example, an aqueous solution of ferric chloride, an aqueous solution of cupric chloride, an aqueous solution of ammonium persulfate, or the like. After that, the portion from which the support 300 has been removed from the structure shown in FIG. 5(b) is cut at the portion of the broken line C using a dicing saw or the like and diced. Thereby, a plurality of laminates of the first wiring structure 1 and the second wiring structure 2 shown in FIG. 5(c) can be obtained. Note that the order of removing the support 300 and dicing may be the reverse of the above.

[0059] After the process shown in FIG. 5(c), a third wiring structure 3 is prepared, and the third wiring structure 3 and the first wiring structure 1 are electrically connected. The third wiring structure 3 can be manufactured, for example, by a well-known build-up method. After preparing the third wiring structure 3, the wiring layer 321 constituting the first laminate 32 of the third wiring structure 3 and the wiring layer 11 of the first wiring structure 1 are joined via a joining member 40 such as a solder bump. If necessary, an adhesive layer 50 is provided between the third wiring structure 3 and the first wiring structure 1. Thereby, the wiring board 5 is completed. Since the first wiring structure 1 incorporating the electronic component 12 in the insulating layer 13 has reduced warping and expansion / contraction during mounting, the mounting accuracy when mounting the first wiring structure 1 on the third wiring structure 3 can be improved.

[0060] <Modification Example 1 of the First Embodiment> In Modification Example 1 of the first embodiment, an example of a method for manufacturing a wiring board different from that of the first embodiment is shown. Note that in Modification Example 1 of the first embodiment, the description of the same components as those in the already described embodiment may be omitted.

[0061] FIG. 6 is a diagram illustrating a manufacturing process of a wiring board according to Modification Example 1 of the first embodiment. The processes shown in FIGS. 4(a) and 4(b) of the first embodiment may be replaced with the processes shown in FIGS. 6(a) and 6(b).

[0062] In the process shown in FIG. 6(a), first, via wirings 14 that fill each of via holes 13x and 13y are formed. Then, the upper surface sides of the insulating layer 13 and the via wirings 14 are polished. The polishing is performed until all of the via wirings 14 that fill the via hole 13y are removed and the upper surface of the electrode 121 of the electronic component 12 is exposed. Thereby, the upper surface of the insulating layer 13, the upper surface of the electrode 121, and the upper surface of the via wiring 14 that fills the via hole 13x can be flush.

[0063] Thereafter, in the process shown in FIG. 6(b), in the same manner as the process shown in FIG. 4(b), a wiring layer 21 is formed on the upper surface of the via wiring 14 and the upper surface of the insulating layer 13. A part of the lower surface of the wiring layer 21 is directly connected to the upper surface of the via wiring 14 that fills the via hole 13x. Also, a part of the lower surface of the wiring layer 21 is directly connected to the upper surface of the electrode 121. The subsequent processes are the same as the processes from FIG. 4(c) onward in the first embodiment.

[0064] Thus, the electrode 121 of the electronic component 12 may be directly connected to the wiring layer 21 which is the second wiring layer. Thereby, the first wiring structure 1 can be made lower by the amount of the via wiring 14 that fills the via hole 13y being removed.

[0065] <Modification Example 2 of the First Embodiment> In modification example 2 of the first embodiment, an example of a method for manufacturing a wiring board different from the first embodiment is shown. Note that in modification example 2 of the first embodiment, the description of the same constituent parts as those in the already described embodiments may be omitted.

[0066] FIG. 7 is a diagram illustrating a manufacturing process of a wiring board according to modification example 2 of the first embodiment. The processes shown in FIGS. 3(a) to 3(c) of the first embodiment may be replaced with the processes shown in FIGS. 7(a) to 7(d).

[0067] In the process shown in FIG. 7(a), first, a wiring layer 11 is formed on a support 300, and then an insulating layer 131 covering the wiring layer 11 is formed. The material and formation method of the insulating layer 131 can be the same as those of the insulating layer 13 in the first embodiment. The thickness of the insulating layer 131 is preferably formed thinner than the insulating layer 13 so that the thickness of the insulating layer 13A described later is comparable to the thickness of the insulating layer 13.

[0068] Next, in the process shown in FIG. 7(b), a through hole 131x that penetrates the insulating layer 131 and exposes the upper surface of the support 300 is formed in the insulating layer 131. The through hole 131x can be formed, for example, by a laser processing method using a CO 2 laser or the like. A cavity for mounting the electronic component 12 is formed by the upper surface of the support 300 and the inner surface of the through hole 131x.

[0069] Next, in the process shown in FIG. 7(c), an electronic component 12 having an electrode 121 is prepared, and the electronic component 12 is placed face-up on the upper surface of the copper foil 304 with a carrier exposed inside the through hole 131x. The electronic component 12 may be placed directly on the upper surface of the copper foil 304 with a carrier, or may be placed via an adhesive layer.

[0070] Next, in the process shown in FIG. 7(d), an embedded resin 132 is formed which fills the through-hole 131x to cover the electronic component 12 and extends upward from within the through-hole 131x to cover the upper surface of the insulating layer 131. Specifically, for example, a semi-cured film-like epoxy resin or the like is laminated so as to cover the electronic component 12 and cured to form the embedded resin 132. Alternatively, instead of laminating a film-like epoxy resin or the like, a liquid or paste-like epoxy resin or the like may be applied and cured to form the embedded resin 132. The insulating layer 13A is formed by the insulating layer 131 and the embedded resin 132. The material of the embedded resin 132 can be the same as that of the insulating layer 13 in the first embodiment. Note that the embedded resin 132 may be formed from a material different from that of the insulating layer 13. The thickness of the embedded resin 132 is preferably formed such that the thickness of the insulating layer 13A is approximately the same as the thickness of the insulating layer 13. The subsequent processes are the same as the processes after FIG. 3(d) in the first embodiment.

[0071] Thus, the insulating layer 13 may be formed after the electronic component 12 is disposed on the support 300, or the insulating layer 131 and the through-hole 131x may be formed on the support 300, the electronic component 12 may be disposed in the through-hole 131x, and the embedded resin 132 may be formed. The wiring board 5 having the same performance can be manufactured by any of these manufacturing methods.

[0072] <Examples of Modifications 3 and 4 of the First Embodiment> In Modifications 3 and 4 of the first embodiment, examples of preferable positions for disposing electronic components are shown when the number of electronic components is relatively small. In Modifications 3 and 4 of the first embodiment, the description of the same components as those in the embodiments already described may be omitted.

[0073] FIG. 8 is a plan view illustrating a wiring board according to Modification Example 3 of the first embodiment. In the example of the wiring board 5A shown in FIG. 8, in a plan view, the insulating layer 13 is rectangular. The shape of the insulating layer 13 is substantially the same as the shape of the insulating layer 26 shown in FIG. 8. As shown in FIG. 8, when the insulating layer 13 is rectangular in a plan view and four electronic components 12 are arranged, it is preferable to arrange them at the four corners of the rectangle. Thereby, the warping and expansion / contraction of the first wiring structure 1 can be reduced evenly and effectively.

[0074] FIG. 9 is a plan view illustrating a wiring board according to Modification Example 4 of the first embodiment. In the example of the wiring board 5B shown in FIG. 9, in a plan view, the insulating layer 13 is rectangular. The shape of the insulating layer 13 is substantially the same as the shape of the insulating layer 26 shown in FIG. 9. As shown in FIG. 9, when the insulating layer 13 is rectangular in a plan view and two electronic components 12 are arranged, it is preferable to arrange them so as to face each other on two sides along the long side of the rectangle. Thereby, the warping and expansion / contraction of the first wiring structure 1 can be reduced evenly and effectively.

[0075] <Modification Example 5 of the First Embodiment> In Modification Example 5 of the first embodiment, an example of a wiring board having a plurality of first wiring structures and second wiring structures is shown. Note that, in Modification Example 5 of the first embodiment, the description of the same components as those in the embodiments already described may be omitted.

[0076] FIG. 10 is a cross-sectional view illustrating a wiring board according to Modification Example 5 of the first embodiment. In the example of the wiring board 5C shown in FIG. 5, two laminates of the first wiring structure 1 and the second wiring structure 2 are arranged on one side of the third wiring structure 3, which is different from the wiring board 5. The number of laminates of the first wiring structure 1 and the second wiring structure 2 may be three or more.

[0077] Thus, by arranging a plurality of laminates of the first wiring structure 1 and the second wiring structure 2, the wiring board 5C can mount more semiconductor chips.

[0078] <Application Example of the First Embodiment> In the application example of the first embodiment, an example of a semiconductor device in which a semiconductor chip is mounted on a wiring substrate is shown. In the application example of the first embodiment, the description of the same components as those in the already described embodiment may be omitted.

[0079] FIG. 11 is a cross-sectional view illustrating a semiconductor device according to an application example of the first embodiment. Referring to FIG. 11, the semiconductor device 8 includes the wiring substrate 5 shown in FIG. 1, a semiconductor chip 80, and an underfill resin 95. The semiconductor chip 80 is mounted on the second wiring structure 2 of the wiring substrate 5.

[0080] The semiconductor chip 80 is, for example, a semiconductor substrate 81 thinned from silicon or the like on which a semiconductor integrated circuit (not shown) or the like is formed. On the circuit formation surface of the semiconductor substrate 81, electrode pads 82 electrically connected to a semiconductor integrated circuit (not shown) are formed.

[0081] The electrode pads 82 of the semiconductor chip 80 are electrically connected to the electrodes constituting the wiring layer 27 of the second wiring structure 2 via bumps 90. The underfill resin 95 is filled between the circuit formation surface of the semiconductor chip 80 and the upper surface of the second wiring structure 2, and covers a part or all of the side surfaces of the semiconductor chip 80. The bumps 90 are, for example, solder bumps. As the material of the solder bumps, for example, SnBi solder or the like can be used.

[0082] In this way, by mounting the semiconductor chip 80 on the wiring substrate 5 according to the first embodiment, the semiconductor device 8 can be realized. The wiring substrate 5 can be suitably used as an interposer substrate for high-speed data communication, for example, between a processor and a memory. Further, since the second wiring structure 2 is thin, the electrical path between the electronic component 12 and the semiconductor chip 80 is shortened. As a result, the resistance loss in the electrical path between the electronic component 12 and the semiconductor chip 80 is reduced, so that improvement in power efficiency and stabilization of the power supply can be realized.

[0083] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope described in the claims.

Explanation of Reference Numerals

[0084] 1 First wiring structure 2 Second wiring structure 3 Third wiring structure 5, 5A, 5B, 5C Wiring board 8 Semiconductor device 11, 21, 23, 25, 27, 321, 331 Wiring layer 12 Electronic component 13, 13A, 22, 24, 26 Insulating layer 13x, 13y, 22x, 24x, 26x Via hole 14 Via wiring 40 Bonding member 50 Adhesive layer 80 Semiconductor chip 81 Semiconductor substrate 82 Electrode pad 90 Bump 95 Underfill resin 121 Electrode 131 Insulating layer 131x Through hole 132 Embedded resin

Claims

1. A first wiring structure having a first wiring layer, a first insulating layer, and electronic components incorporated in the first insulating layer; A second wiring structure having a second wiring layer and a second insulating layer, the second wiring structure being laminated on one side of the first wiring structure; The second wiring layer has a higher wiring density than the first wiring layer; The first wiring layer includes pads having portions exposed from the first insulating layer; The first insulating layer includes, in plan view, a first region where the pads are disposed and a second region located on the outer peripheral side of the first region; The electronic components are disposed in the second region and are electrically connected to the second wiring layer, a wiring substrate.

2. The wiring substrate according to claim 1, wherein a plurality of the electronic components are disposed in the second region.

3. The wiring substrate according to claim 2, wherein the plurality of electronic components are disposed point-symmetrically with respect to the center of the first insulating layer in plan view.

4. In plan view, the first insulating layer is rectangular; The wiring substrate according to claim 2, wherein the plurality of electronic components include electronic components disposed at four corners of the rectangle.

5. The wiring substrate according to claim 4, wherein the plurality of electronic components include electronic components disposed along each side of the rectangle.

6. The lower surfaces of the electronic components and the lower surfaces of the pads are exposed from the lower surface of the first insulating layer; The wiring substrate according to any one of claims 1 to 5, wherein the lower surfaces of the electronic components and the lower surfaces of the pads are flush with the lower surface of the first insulating layer.

7. The electronic components are provided with electrodes on the side of the second wiring structure; The wiring substrate according to any one of claims 1 to 5, wherein the electrodes are directly connected to the second wiring layer.

8. Further having a third wiring structure having a third wiring layer and a third insulating layer, the third wiring structure being laminated on the other side of the first wiring structure; The wiring substrate according to any one of claims 1 to 5, wherein the second wiring layer has a higher wiring density than the third wiring layer.

9. The wiring substrate according to claim 8, wherein a plurality of laminates of the first wiring structure and the second wiring structure are disposed on one side of the third wiring structure.

10. A semiconductor device having the wiring substrate according to claim 8; And a semiconductor chip mounted on the second wiring structure.

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