Semiconductor device, electronic device, and method for manufacturing electronic device

Abstract

To improve the performance of a semiconductor device.SOLUTION: A semiconductor device includes a semiconductor chip, a sealing body MR having an upper surface MRt and a lower surface MRb, a plurality of leads LD1, and a metal plate exposed from the sealing body MR at the upper surface MRt of the sealing body MR. The outer lead portion of each of the plurality of leads LD includes a portion LDZ extending in a direction from the upper surface MRt to the lower surface MRb in the thickness direction of the sealing body MR. The portion LDZ includes a tip end LDE of the outer lead portion. When the lower surface MRb is taken as a reference surface RS1 in a side view, the distance from the tip end LDE to the reference surface RS1 in the thickness direction of the sealing body MR is shorter than the distance from the upper surface MRt to the reference surface RS1.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a semiconductor device, an electronic device, and a method for manufacturing an electronic device.

Background Art

[0002] There is an electronic device in which a lead exposed from a sealing body is inserted into a through hole formed in a substrate, and the lead and the substrate are electrically connected (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When a semiconductor device of a type in which a lead is inserted into a through hole formed in a mounting substrate is mounted on the mounting substrate, in addition to one surface of the mounting substrate (the mounting surface on which the semiconductor device is mounted), the layout of the surface located on the opposite side of the mounting surface is restricted by the through hole. In the case of a mounting substrate having a plurality of wiring layers between the mounting surface and the opposite surface, the wiring layout of each of the plurality of wiring layers is restricted by the through hole.

[0005] As a method of mounting a semiconductor device without forming a through hole in the mounting substrate, there is a method in which terminals are formed on the mounting surface of the mounting substrate, and leads are connected to the terminals via solder. A semiconductor device used in such a mounting method is called a surface-mounted semiconductor device. In the case of a surface-mounted semiconductor device, the tip of the lead is bent, and the lead is shaped so that the end of the lead and the terminal face each other. In this case, an error occurs in the height of the upper surface of the semiconductor device disposed on the terminal according to the forming accuracy of the lead. When terminals for connecting to other members are exposed on the upper surface of the semiconductor device, it is preferable to improve the accuracy of the height of the upper surface of the semiconductor device.

[0006] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0007] A semiconductor device according to one embodiment includes a semiconductor chip, a sealing body that has a first surface and a second surface located opposite to the first surface and seals the semiconductor chip, a plurality of leads electrically connected to the semiconductor chip, and a metal plate having a first exposed surface exposed from the sealing body on the first surface of the sealing body. Each of the plurality of leads includes an inner lead portion sealed in the sealing body and an outer lead portion exposed from the sealing body. The outer lead portion includes a first portion extending in a direction from the first surface toward the second surface in a thickness direction of the sealing body. The first portion includes a tip of the outer lead portion. When the second surface is a first reference plane in a side view, a distance from the tip to the first reference plane in the thickness direction of the sealing body is shorter than a distance from the first surface to the first reference plane.

[0008] An electronic device according to another embodiment includes a mounting substrate having a mounting surface, a first semiconductor device mounted on the mounting surface of the mounting substrate, a second semiconductor device mounted on the mounting surface of the mounting substrate so as to be adjacent to the first semiconductor device, and a heat sink fixed to each of the first semiconductor device and the second semiconductor device and disposed across the first semiconductor device and the second semiconductor device. Each of the first semiconductor device and the second semiconductor device includes a semiconductor chip, a first surface facing the heat sink and a second surface located opposite to the first surface, a sealing body that seals the semiconductor chip, a plurality of leads electrically connected to the semiconductor chip, and a metal plate having a first exposed surface exposed from the sealing body on the first surface of the sealing body. Each of the plurality of leads includes an inner lead portion sealed in the sealing body and an outer lead portion exposed from the sealing body. The outer lead portion includes a first portion extending in a direction from the first surface toward the second surface in the thickness direction of the sealing body. When the second surface is a first reference plane in a side view, a distance from a tip of the outer lead portion to the first reference plane in the thickness direction of the sealing body is shorter than a distance from the first surface to the first reference plane. The second surfaces of each of the first semiconductor device and the second semiconductor device are in contact with the mounting surface of the mounting substrate.

[0009] The manufacturing method of an electronic device according to another embodiment includes: (a) a step of preparing a mounting substrate having a mounting surface, a first insulating film provided on the mounting surface, a plurality of terminals respectively exposed from the first insulating film in a plurality of openings formed in the first insulating film, and a first insulating layer on which the plurality of terminals are formed; (b) a step of mounting the first semiconductor device and the second semiconductor device on the mounting substrate such that the first semiconductor device and the second semiconductor device are adjacent to each other; and (c) a step of fixing a heat sink to each of the first semiconductor device and the second semiconductor device so as to straddle the first semiconductor device and the second semiconductor device after the step (b). Each of the first semiconductor device and the second semiconductor device includes a semiconductor chip, a first surface facing the heat sink and a second surface located opposite to the first surface, a sealing body that seals the semiconductor chip, a plurality of leads electrically connected to the semiconductor chip, and a metal plate having a first exposed surface exposed from the sealing body on the first surface of the sealing body. Each of the plurality of leads includes an inner lead portion sealed in the sealing body and an outer lead portion exposed from the sealing body. The outer lead portion includes a first portion extending in a direction from the first surface toward the second surface in the thickness direction of the sealing body. When the second surface is taken as a first reference plane in a side view, the distance from the tip of the outer lead portion to the first reference plane in the thickness direction of the sealing body is shorter than the distance from the first surface to the first reference plane. In the step (b), the first semiconductor device and the second semiconductor device are arranged such that the second surfaces of the first semiconductor device and the second semiconductor device are in contact with the mounting surface of the mounting substrate.

Advantages of the Invention

[0010] According to the above embodiment, the performance of the semiconductor device or the electronic device can be improved.

Brief Description of the Drawings

[0011]

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Mode for Carrying Out the Invention

[0012] (Explanation of the description format, basic terms, and usage in this application) In this application, the description of the embodiments is divided into a plurality of sections, etc. for convenience as necessary. However, unless otherwise explicitly stated, these are not mutually independent and separate. Regardless of the order of description, each part of a single example, one is a detailed part, a partial or total modification, etc. of the other. Also, in principle, repeated descriptions of similar parts are omitted. Further, each component in the embodiments is not essential unless otherwise explicitly stated, theoretically limited in number, or clearly not so from the context.

[0013] Similarly, in the description of the embodiments, etc., regarding materials, compositions, etc., even if it is said "X consisting of A", etc., unless otherwise explicitly stated or clearly not so from the context, it does not exclude those containing elements other than A. For example, regarding components, it means "X containing A as the main component", etc. For example, even if it is said "silicon member", etc., it is not limited to pure silicon, but also includes members containing SiGe (silicon-germanium) alloy, other multi-element alloys with silicon as the main component, and other additives. Also, regarding gold plating, Cu layer, nickel plating, etc., unless otherwise explicitly stated, it includes not only pure ones but also members with gold, Cu, nickel, etc. as the main components.

[0014] Furthermore, when referring to a specific numerical value or quantity, unless otherwise explicitly stated, or theoretically limited to that number, or clearly not the case from the context, the numerical value may be greater than or less than that specific numerical value.

[0015] Also, in each figure of the embodiments, the same or similar parts are denoted by the same or similar symbols or reference numerals, and the description will not be repeated in principle.

[0016] Also, in the accompanying drawings, conversely, when it becomes complicated or the distinction from voids is clear, hatching or the like may be omitted even for cross-sections. In this regard, even for a planar closed hole, the background contour line may be omitted when it is clear from the description or the like. Furthermore, even if it is not a cross-section, hatching or a dot pattern may be added to clarify that it is not a void or to clarify the boundary of a region.

[0017] In the embodiments described below, as an example of a semiconductor device, a semiconductor device called a power device or a power semiconductor device incorporated in a power control circuit such as a power supply circuit will be taken up and described. The semiconductor device described below is incorporated in a power conversion circuit and functions as a switching element, for example.

[0018] <Semiconductor Device> First, the package structure of the semiconductor device PKG1 shown in FIG. 1 will be described. FIG. 1 is a top view of the semiconductor device of the present embodiment. FIG. 2 is a bottom view of the semiconductor device shown in FIG. 1. FIG. 3 is a perspective plan view showing the internal structure of the semiconductor device with the sealing body shown in FIG. 2 removed. FIG. 4 is a cross-sectional view taken along line A-A of FIG. 3. FIG. 5 is a side view of the semiconductor device shown in FIG. 1 viewed from the Y direction. FIG. 6 is a side view of the semiconductor device shown in FIG. 1 viewed from the X direction.

[0019] In FIGS. 1 to 6, any one of the X direction, Y direction, and Z direction is described. The Y direction is a direction intersecting the X direction, and in the following description, the X direction and the Y direction are orthogonal to each other. The Z direction is a direction orthogonal to each of the X direction and the Y direction. In other words, the Z direction is a normal direction to the X - Y plane including the X direction and the Y direction. In the following description, "thickness" generally means the length in the Z direction. Also, in the following description, "plan view" generally means viewing the X - Y plane. Further, "side view" means viewing a plane including the Z direction, such as the "X - Z plane" or the "Y - Z plane".

[0020] The semiconductor device PKG1 of the present embodiment has a semiconductor chip CP1 (see FIGS. 3 and 4), a sealing body MR that seals the semiconductor chip CP1, a plurality of leads LD1 electrically connected to the semiconductor chip CP1, and a metal plate MP1.

[0021] As shown in FIGS. 1 and 2, the sealing body MR forms a quadrangle in plan view. In other words, the sealing body MR has four sides in plan view. The sealing body MR includes an upper surface MRt (see FIG. 1) and a lower surface MRb (see FIG. 4) located opposite to the upper surface MRt. The sealing body MR is an insulator made of resin. The sealing body MR may contain a pigment, inorganic insulating particles (such as silica), in addition to the thermosetting resin.

[0022] In the case of the present embodiment, the metal plate MP1 shown in FIG. 4 functions as a chip mounting portion (die pad) on which the semiconductor chip CP1 is mounted. The metal plate MP1 includes an exposed surface (surface, upper surface) MP1b and a chip mounting surface (surface, lower surface) MP1t located opposite to the exposed surface MP1b. The exposed surface MP1b is exposed from the sealing body MR on the upper surface MRt of the sealing body MR. The metal plate MP1 is made of a metal material containing, for example, copper, a copper alloy, or iron such as 42 alloy.

[0023] As shown in FIGS. 3 and 4, a semiconductor chip CP1 is mounted on a chip mounting surface MP1t of a metal plate MP1 which is a die pad. As shown in FIG. 4, the semiconductor chip CP1 includes an upper surface (surface, front surface, main surface) CP1t and a lower surface (surface, back surface, main surface) CP1b located opposite to the upper surface CP1t. The semiconductor chip CP1 is mounted on the chip mounting surface MP1t via a die bonding material DB such that the lower surface CP1b faces the chip mounting surface MP1t of the metal plate MP1.

[0024] The die bonding material DB is, for example, solder or a conductive resin. A conductive resin is a resin in which a plurality of conductive particles are mixed in a resin component including a thermosetting resin such as an epoxy resin. Before the thermosetting resin component contained in the conductive resin cures, the conductive resin has a paste-like property, so it is called a conductive resin paste (particularly, a silver paste when the conductive particles are silver particles). Note that, as a modification of this embodiment, there may be a case where the semiconductor chip CP1 and the metal plate MP1 are not electrically connected. In this case, an insulating resin adhesive in which the die bonding material DB does not contain conductive particles can be used.

[0025] As will be described later, the semiconductor chip CP1 of this embodiment has a power transistor composed of a power MOSFET (Metal - Oxide - Semiconductor Field - Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). Hereinafter, as an example, an example of the semiconductor chip CP1 having a power MOSFET will be taken and described. In the following description, the term "power MOSFET" can be replaced with "IGBT". In this case, the term "drain" is replaced with "collector", and the term "source" is replaced with "emitter", respectively.

[0026] As shown in FIGS. 3 and 4, the semiconductor chip CP1 has a plurality of pads PD. As shown in FIG. 3, the semiconductor chip CP1 has a gate electrode pad PDG and a source electrode pad PDS on the upper surface CP1t. Specifically, a plurality of openings are arranged in an insulating film (passivation film) having the upper surface CP1t of the semiconductor chip CP1. Each of the gate electrode pad PDG and the source electrode pad PDS is exposed from the insulating film at the above openings. The area of the source electrode pad PDS is larger than the area of the gate electrode pad PDG. The gate electrode pad PDG is an electrode pad connected to the gate electrode of the power MOSFET. The source electrode pad PDS is an electrode pad connected to the source of the power MOSFET.

[0027] Also, as shown in FIG. 4, the semiconductor chip CP1 has a drain electrode pad PDD formed on the lower surface CP1b. The drain electrode pad PDD is formed, for example, over the entire lower surface CP1b of the semiconductor chip CP1. The drain electrode pad PDD is an electrode pad connected to the drain of the power MOSFET.

[0028] In the case of this embodiment, the metal plate MP1 is electrically connected to the semiconductor chip CP1. Specifically, the metal plate MP1 is electrically connected to the drain electrode pad PDD of the semiconductor chip CP1 via a die bonding material DB which is a conductive member. The metal plate MP1 is integrally formed with a lead LDD which is a drain lead among the plurality of leads LD1 shown in FIG. 3. The metal plate MP1 constitutes a flow path for the drain current.

[0029] As shown in FIGS. 3 and 4, each of the plurality of leads LD1 includes an inner lead portion LDM sealed in the sealing body MR and an outer lead portion LDX exposed from the sealing body MR. As shown in FIG. 1, in a plan view, the plurality of leads LD1 are arranged only on two opposite sides among the four sides of the sealing body MR. The outer lead portion LDX (see FIG. 3) of each of the plurality of leads LD1 protrudes outward from the side surface of the sealing body MR.

[0030] Each of the plurality of leads LD1 is arranged along two of the four sides in this way. A semiconductor device in which the plurality of leads LD1 are arranged along two sides is called an SOP (Small Outline Package) or a DIP (Dual In-line Package). Note that SOP is the name of a surface-mount semiconductor device in which the shape of the lead is formed into a gullwing shape. On the other hand, DIP is the name of a semiconductor device in which a plurality of leads extend linearly in the thickness direction of the sealing body. The DIP is mounted on a mounting substrate provided with through holes. When mounting the DIP on the mounting substrate, a plurality of leads are respectively inserted into the plurality of through holes, and each of the plurality of leads is fixed in the through holes by solder.

[0031] Among the plurality of leads LD1, the gate lead LDG is electrically connected to the gate electrode pad PDG via a wire BW (specifically, the gate wire BWG). Among the plurality of leads LD1, the plurality of source leads LDS are electrically connected to the source electrode pad PDS via a plurality of wires BW (specifically, the source wires BWS). Among the plurality of leads LD1, the lead LDD which is the drain lead is integrally formed with the metal plate MP1 and is electrically connected to the drain electrode pad PDD via the metal plate MP1. In the example shown in FIG. 3, the plurality of source leads LDS are spaced apart from each other. However, as shown in FIG. 11 to be described later, there may be a case where the inner lead portions LDM of adjacent leads LDS are connected to each other via a connecting portion.

[0032] The technology described below can also be applied to surface-mounted semiconductor devices such as SOPs. However, in the case of this embodiment, as shown in FIG. 4, the outer lead portion LDX includes a portion LDZ that extends in the thickness direction of the encapsulation body MR from the upper surface MRt toward the lower surface MRb. The portion LDZ includes the tip LDE of the outer lead portion LDX. In other words, the tip LDE of the outer lead portion LDX coincides with the tip LDZE of the portion LDZ. Therefore, the semiconductor device PKG1 of this embodiment is classified as a semiconductor package closer to DIP than to SOP.

[0033] However, the semiconductor device PKG1 of this embodiment does not plan to insert each of the plurality of leads LD1 into the through holes of the mounting substrate. In this regard, it is different from a general DIP. As shown in FIGS. 5 and 6, in the case of the semiconductor device PKG1, when the lower surface MRb of the encapsulation body MR is used as the reference plane RS1 in a side view, in the thickness direction of the encapsulation body MR, the distance L1 from the tip LDE to the reference plane RS1 is shorter than the distance L2 from the upper surface MRt to the reference plane RS1.

[0034] <Circuit configuration example> Next, a circuit configuration example and an example of the element structure of transistors included in the semiconductor device PKG1 shown in FIG. 3 will be described. FIG. 7 is an explanatory diagram schematically showing an example of a circuit included in the semiconductor device shown in FIG. 1. FIG. 8 is a cross-sectional view of a main part showing an example of the element structure of the field effect transistor shown in FIG. 7.

[0035] Semiconductor devices for power control called power semiconductor devices include, for example, those having semiconductor elements such as diodes, thyristors, or transistors. Transistors are used in various fields. However, like in this embodiment, a transistor incorporated in a power control circuit where a large current of, for example, 1 A (ampere) or more flows and operates as a switching element is called a power transistor. As shown in FIG. 7, the semiconductor device PKG1 of this embodiment has a semiconductor chip CP1 including a transistor Q1 which is a power transistor. In the examples shown in FIGS. 7 and 8, the transistor Q1 included in the semiconductor chip CP1 is a field-effect transistor, specifically, a MOSFET. In a power semiconductor device, a transistor is used, for example, as a switching element. A MOSFET used in a power semiconductor device is called a power MOSFET.

[0036] The above-described MOSFET is described as a general term widely representing a field-effect transistor having a gate electrode made of a conductive material disposed on a gate insulating film. Therefore, even when described as a MOSFET, it does not exclude a gate insulating film other than an oxide film. Also, even when described as a MOSFET, it does not exclude a gate electrode material other than a metal such as polysilicon.

[0037] Also, the transistor Q1 shown in FIG. 7 is formed, for example, by an n-channel type field-effect transistor as shown in FIG. 8. FIG. 8 is a cross-sectional view of a main part showing an example of the element structure of the field-effect transistor shown in FIG. 7.

[0038] In the example shown in FIG. 8, for example, an n-type epitaxial layer EP is formed on the main surface WHt of a semiconductor substrate WH made of n-type single crystal silicon. This semiconductor substrate WH and the epitaxial layer EP constitute the drain region of the MOSFET (the region corresponding to the drain D shown in FIG. 7). This drain region is electrically connected to a drain electrode pad PDD formed on the back surface of the semiconductor chip CP1.

[0039] On the epitaxial layer EP, a channel formation region CH, which is a p+-type semiconductor region, is formed. On this channel formation region CH, a source region SR (a region corresponding to the source S shown in FIG. 7), which is an n+-type semiconductor region, is formed. The source region SR is electrically connected to the source electrode pad PDS of the semiconductor chip CP1 via a lead wiring. Further, in the semiconductor region laminated on the semiconductor substrate WH, a trench (opening, groove) TR1 is formed that penetrates the channel formation region CH from the upper surface of the source region SR and reaches the inside of the epitaxial layer EP.

[0040] Also, a gate insulating film GI is disposed on the inner wall of the trench TR1. Further, a gate G laminated so as to fill the trench TR1 is disposed on the gate insulating film GI. The gate G is electrically connected to the gate electrode pad PDG of the semiconductor chip CP1 via a lead wiring.

[0041] Also, in the transistor Q1, since the drain region and the source region SR are disposed in the thickness direction with the channel formation region CH interposed therebetween, a channel is formed in the thickness direction (hereinafter referred to as a vertical channel structure). In this case, compared with a field effect transistor in which a channel is formed along the main surface WHt, the occupied area of the element in a plan view can be reduced. For this reason, the planar size of the semiconductor chip CP1 can be reduced.

[0042] Also, in the case of the above-described vertical channel structure, in a plan view, the channel width per unit area can be increased, so that the on-resistance can be reduced. Note that FIG. 8 is a diagram showing the element structure of a field effect transistor. In the semiconductor chip CP1 shown in FIG. 7, for example, a plurality (a large number) of transistors Q1 having an element structure as shown in FIG. 8 are connected in parallel. Thereby, for example, a power MOSFET through which a large current exceeding 1 ampere flows can be configured.

[0043] As described above, when a MOSFET is configured by connecting in parallel a plurality of transistors Q1 having a vertical channel structure, the electrical characteristics of the MOSFET (mainly breakdown voltage characteristics, on-resistance characteristics, and capacitance characteristics) vary according to the planar size of the semiconductor chip CP1. For example, if the planar area of the semiconductor chip CP1 is increased, the number of cells (i.e., the number of elements) of the transistors Q1 connected in parallel increases, so the on-resistance decreases and the capacitance increases.

[0044] In FIGS. 7 and 8, a MOSFET is illustrated as an example of the power transistor included in the power semiconductor device, but various modifications can be applied. For example, instead of a MOSFET, an insulated gate bipolar transistor (IGBT) may be provided.

[0045] Also, in the example shown in FIG. 8, the transistor having a vertical channel structure has been exemplarily described, but it can also be replaced with a transistor having a horizontal channel structure. In this case, the drain electrode pad PDD is disposed on the upper surface CP1t (see FIG. 3) of the semiconductor chip CP1. Therefore, the drain lead LDD shown in FIG. 3 and the drain electrode pad PDD (see FIG. 8) connected to the drain of the transistor having a horizontal channel structure are electrically connected via a wire (drain wire) not shown.

[0046] <Modification Examples of Semiconductor Devices> Next, a package structure of a modification of the semiconductor device PKG1 described with reference to FIGS. 1 to 8 will be described. FIG. 9 is a top view of a semiconductor device which is a modification of FIG. 1. FIG. 10 is a bottom view of the semiconductor device shown in FIG. 9. FIG. 11 is a perspective plan view showing the internal structure of the semiconductor device with the sealing body shown in FIG. 10 removed. FIG. 12 is a cross-sectional view taken along line B-B of FIG. 11. Note that the side surfaces of the semiconductor device PKG2 shown in FIGS. 9 to 12 are the same as those in FIGS. 5 and 6. Further, the transistors included in the semiconductor chip CP2 of the semiconductor device PKG2 shown in FIGS. 11 and 12 are the same as the power transistors (MOSFET or IGBT) described with reference to FIGS. 7 and 8. Therefore, hereinafter, the description will focus on the differences between the semiconductor device PKG1 and the semiconductor device PKG2, and the description of the common parts will be omitted.

[0047] The semiconductor device PKG2 of this modification includes a semiconductor chip CP2 (see FIGS. 11 and 12), a sealing body MR that seals the semiconductor chip CP2, a plurality of leads LD2 electrically connected to the semiconductor chip CP2, a metal plate MP1, and a metal plate MP2.

[0048] The metal plate MP1 shown in FIG. 12 functions as a chip mounting portion (die pad) on which the semiconductor chip CP2 is mounted. The exposed surface MP1b of the metal plate MP1 is exposed from the sealing body MR on the lower surface MRb of the sealing body MR.

[0049] As shown in FIGS. 11 and 12, the semiconductor chip CP2 is mounted on the chip mounting surface MP1t of the metal plate MP1 which is a die pad. As shown in FIG. 12, the semiconductor chip CP2 includes an upper surface (surface, main surface) CP2t and a lower surface (surface, back surface, main surface) CP2b located opposite to the upper surface CP2t. The semiconductor chip CP2 is mounted on the chip mounting surface MP1t via a die bonding material DB such that the lower surface CP2b faces the chip mounting surface MP1t of the metal plate MP1. The semiconductor chip CP2 has a power transistor composed of a power MOSFET, similar to the semiconductor chip CP1 shown in FIGS. 3 and 4.

[0050] As shown in FIGS. 11 and 12, the semiconductor chip CP2 has a plurality of pads PD. As shown in FIG. 11, the semiconductor chip CP2 has a gate electrode pad PDG and a source electrode pad PDS on its upper surface CP2t. Specifically, a plurality of openings are arranged in an insulating film (passivation film) having the upper surface CP2t of the semiconductor chip CP2. Each of the gate electrode pad PDG and the source electrode pad PDS is exposed from the insulating film at the above-mentioned opening. The area of the source electrode pad PDS is larger than the area of the gate electrode pad PDG. The gate electrode pad PDG is an electrode pad connected to the gate electrode of the power MOSFET. The source electrode pad PDS is an electrode pad connected to the source of the power MOSFET.

[0051] Also, as shown in FIG. 12, the semiconductor chip CP2 has a drain electrode pad PDD formed on its lower surface CP2b. The drain electrode pad PDD is formed, for example, over the entire lower surface CP2b of the semiconductor chip CP2. The drain electrode pad PDD is an electrode pad connected to the drain of the power MOSFET.

[0052] The metal plate (clip) MP2 shown in FIG. 12 functions as a conductive member for electrically connecting the source electrode pad PDS of the semiconductor chip CP2 and the source lead LDS among the plurality of leads LD2. The metal plate MP2 is electrically connected to the source electrode pad PDS of the semiconductor chip CP2 via the die bonding material DB2. A plate-like member for electrically connecting a semiconductor chip and a lead is called a clip. Compared with the example shown in FIG. 4, in the case of this modification, by replacing the wire BWS shown in FIG. 4 with the metal plate MP2 shown in FIG. 11, the cross-sectional area of the path for electrically connecting the source lead LDS and the source electrode pad PDS is large. Therefore, the resistance of the supply path of the current flowing through the source electrode pad PDS can be reduced.

[0053] The metal plate MP2 includes an exposed surface (surface, upper surface) MP2t and a chip facing surface (surface, lower surface) MP2b that is located opposite to the exposed surface MP2t and faces the semiconductor chip CP2. The exposed surface MP2t is exposed from the sealing body MR on the upper surface MRt of the sealing body MR. The metal plate MP2 is made of a metal material containing iron such as copper, a copper alloy, or 42 alloy, for example.

[0054] Among the plurality of leads, the gate lead LDG is electrically connected to the gate electrode pad PDG via a wire BW (specifically, the gate wire BWG). Among the plurality of leads, the source lead LDS is electrically connected to the source electrode pad PDS via the metal plate MP2. Among the plurality of leads, the drain lead LDD is integrally formed with the metal plate MP1 and is electrically connected to the drain electrode pad PDD via the metal plate MP1.

[0055] As shown in FIGS. 5 and 6, in the case of the semiconductor device PKG2, similar to the semiconductor device PKG1 described above, when the lower surface MRb of the sealing body MR is used as the reference plane RS1 in a side view, in the thickness direction of the sealing body MR, the distance L1 from the tip LDE of the outer lead portion LDX to the reference plane RS1 is shorter than the distance L2 from the upper surface MRt of the sealing body MR to the reference plane RS1.

[0056] In each of the semiconductor devices PKG1 shown in FIGS. 1 to 4 and the semiconductor devices PKG2 shown in FIGS. 9 to 12, a metal plate (the metal plate MP1 shown in FIG. 1 and the metal plate MP2 shown in FIG. 9) is exposed on the upper surface MRt of the sealing body MR. When a part of the metal plate is exposed from the sealing body MR in this way, the heat dissipation efficiency can be improved by thermally connecting a heat sink to the exposed portion of the metal plate.

[0057] The metal plate connected to the heat sink can be the metal plate MP2 that functions as a clip shown in FIG. 12 in addition to the metal plate MP1 that functions as a die pad as shown in FIG. 4.

[0058] <Electronic device> Next, an example of an electronic device including the semiconductor device described with reference to FIGS. 1 to 12 will be described. FIG. 13 is an explanatory diagram showing a circuit configuration example of an electronic device including the semiconductor device described with reference to FIGS. 1 to 12.

[0059] The electronic device ED1 shown in FIG. 13 includes a semiconductor device PKG1 and a semiconductor device PKG2. As already described, each of the semiconductor chip CP1 included in the semiconductor device PKG1 and the semiconductor chip CP2 included in the semiconductor device PKG2 has a power transistor composed of a power MOSFET or an IGBT.

[0060] A lead LDD connected to the drain D of the semiconductor device PKG2 is connected to a terminal (high-side terminal) HT connected to a power supply PW. A lead LDS connected to the source S of the semiconductor device PKG1 is connected to a terminal (low-side terminal) LT connected to the power supply PW. A relatively high potential is supplied to the terminal HT compared to the terminal LT.

[0061] Each of the lead LDS of the semiconductor device PKG2 and the lead LDD of the semiconductor device PKG1 are electrically connected to each other and connected to a load 100. Also, each of the lead LDG connected to the gate G of the semiconductor device PKG1 and the lead LDG connected to the gate G of the semiconductor device PKG2 are connected to a control circuit CTC.

[0062] In the example shown in FIG. 13, the electronic device ED1 includes an inverter circuit including the semiconductor device PKG1 and the semiconductor device PKG2. In the inverter circuit shown in FIG. 13, the semiconductor device PKG2 is used as a high-side switching element, and the semiconductor device PKG1 is used as a low-side switching element.

[0063] Note that although a single-phase inverter is shown in FIG. 13, when there are three sets of the set of the semiconductor device PKG1 and the semiconductor device PKG2 shown in FIG. 13, it can be used as a three-phase inverter circuit.

[0064] FIG. 14 is a top view of the electronic device shown in FIG. 13. FIG. 15 is a cross-sectional view taken along line C-C of FIG. 14. The heat sink HS shown in FIG. 14 covers the semiconductor device PKG1 and the semiconductor device PKG2. However, in FIG. 14, for the sake of clarity of the positional relationship between the heat sink HS, the semiconductor device PKG1, and the semiconductor device PKG2, the heat sink HS is shown by a dotted line and is shown as a transparent plan view through the heat sink. Also, in FIG. 14, the illustration of the conductive members CM1 and CM2 shown in FIG. 15 is omitted.

[0065] As shown in FIGS. 14 and 15, the electronic device ED1 includes a mounting substrate MB1, a semiconductor device PKG1, a semiconductor device PKG2, and a heat sink HS.

[0066] The mounting substrate MB1 has a mounting surface MBt. As shown in FIG. 15, the mounting substrate MB1 includes an insulating film SR1 provided on the mounting surface MBt, a plurality of terminals TM respectively exposed from the insulating film SR1 at a plurality of openings formed in the insulating film SR1, and an insulating layer IL1 in which the plurality of terminals TM are formed. The insulating film SR1 is formed on the insulating layer IL1. The insulating layer IL1 is disposed in the uppermost layer (the layer closest to the terminal arrangement layer TML in which the plurality of terminals TM are arranged) among the plurality of insulating layers IL (insulating layer IL1, insulating layer IL2, and insulating layer IL3) provided in the mounting substrate MB1. The insulating layer IL1 is in contact with the plurality of terminals TM. The plurality of terminals TM and the plurality of leads (lead LD1 and lead LD2) are electrically connected to each other via solder (conductive member) SD.

[0067] The heat sink (heat sink, metal member) HS is a member for dissipating the heat generated in the semiconductor device PKG1 and the semiconductor device PKG2 to the atmosphere. The heat sink HS is made of a metal such as aluminum, for example. The heat sink HS has a lower surface HSb facing the semiconductor device PKG1 and the semiconductor device PKG2 and an upper surface HSt on the opposite side of the lower surface HSb. In FIG. 15, as an example, a heat sink HS composed of a simple plate-like member is illustrated. There are various modifications to the shape of the heat sink HS. For example, there may be a case where a plurality of fins (protrusions) are formed on the upper surface HSt. When a plurality of fins are provided on the upper surface HSt of the heat sink HS, the surface area of the heat sink HS can be increased compared to the case of a mere plate-like member, so the heat dissipation efficiency is improved.

[0068] The detailed structures of the semiconductor device PKG1 and the semiconductor device PKG2 shown in FIG. 15 have already been described with reference to FIGS. 1 to 12, so duplicate explanations are omitted.

[0069] As shown in FIG. 14, in a plan view, the semiconductor device PKG1 and the semiconductor device PKG2 are mounted on the mounting surface MBt of the mounting substrate MB1 so as to be adjacent to each other. As shown in FIG. 15, the heat sink HS is fixed to each of the semiconductor device PKG1 and the semiconductor device PKG2. Further, the heat sink HS is disposed across the semiconductor device PKG1 and the semiconductor device PKG2.

[0070] In the case of the example shown in FIG. 15, the exposed surface MP1b of the metal plate MP1 of the semiconductor device PKG1 is fixed to the heat sink HS via the conductive member CM1. The exposed surface MP2t of the metal plate MP2 of the semiconductor device PKG2 is fixed to the heat sink HS via the conductive member CM2. Each of the conductive member CM1 and the conductive member CM2 is, for example, solder or a conductive resin. As described above, the electrically conductive resin is a resin in which a plurality of conductive particles are mixed in a resin component containing a thermosetting resin such as an epoxy resin.

[0071] In a case where the semiconductor device PKG1 and the semiconductor device PKG2 are arranged adjacent to each other, and one heat sink HS is fixed to each of the semiconductor device PKG1 and the semiconductor device PKG2 as in the present embodiment, the heights of the upper surfaces MRt of the sealing bodies MR (in other words, the heights of the exposed surfaces MP1b of the metal plates MP1 of the semiconductor device PKG1 and the exposed surfaces MP2t of the metal plates MP2 of the semiconductor device PKG2) need to be aligned.

[0072] For example, when the height difference between the position of the upper surface MRt of the semiconductor device PKG1 and the position of the upper surface MRt of the semiconductor device PKG2 is large, the heat sink HS may tilt, and in some cases, either the semiconductor device PKG1 or the semiconductor device PKG2 may not be fixed to the heat sink HS. In this case, the heat dissipation characteristics of the semiconductor device not fixed to the heat sink HS will be significantly reduced.

[0073] In an electronic device on which a surface-mounted semiconductor package is mounted, there are the following two factors that cause the height difference between the position of the upper surface MRt of the sealing body MR of the semiconductor device PKG1 and the position of the upper surface MRt of the sealing body MR of the semiconductor device PKG2 to increase.

[0074] First, when the tip of the lead is bent, individual differences may occur in the position of the upper surface MRt of the sealing body MR due to the tolerance of the lead bending process. Second, in the process of forming the sealing body MR using a mold, individual differences may occur in the position of the upper surface MRt of the sealing body MR due to the forming tolerance. In the case of a semiconductor device in which the sealing body MR is supported by leads on the mounting substrate, variations occur in the position of the upper surface MRt of the sealing body MR due to both factors: the tolerance of the lead bending process and the tolerance of the process of forming the sealing body MR.

[0075] In the case of this embodiment, for each of the semiconductor device PKG1 and the semiconductor device PKG2, as described with reference to FIGS. 5 and 6, when the lower surface MRb of the encapsulation body MR is taken as the reference plane RS1 in a side view, in the thickness direction of the encapsulation body MR, the distance L1 from the tip LDE of the outer lead portion LDX to the reference plane RS1 is shorter than the distance L2 from the upper surface MRt of the encapsulation body MR to the reference plane RS1. Also, the lower surface MRb of each of the semiconductor device PKG1 and the semiconductor device PKG2 is in contact with the mounting surface MBt of the mounting substrate MB1.

[0076] In other words, the length of the lead LD1 (or the lead LD2) in the thickness direction of the encapsulation body MR is short enough for the encapsulation body MR to be in contact with the mounting surface MBt of the mounting substrate MB1. When the length of the lead LD1 (or the lead LD2) in the thickness direction of the encapsulation body MR is short enough for the encapsulation body MR to be in contact with the mounting surface MBt of the mounting substrate MB1, among the above two factors, the factor caused by the tolerance of the lead bending process can be eliminated.

[0077] As shown in FIG. 15, the semiconductor device PKG1 and the semiconductor device PKG2 are mounted on the mounting substrate MB1 such that the entire lower surface MRb is in contact with the insulating film SR1 having the mounting surface MBt of the mounting substrate MB1. In this case, although individual differences within the tolerance range of the process of forming the encapsulation body MR occur in the position of the upper surface MRt of the encapsulation body MR, the factor caused by the tolerance of the lead bending process can be eliminated. Therefore, each of the semiconductor device PKG1 and the semiconductor device PKG2 is a surface-mount type semiconductor device, but the height difference between the position of the upper surface MRt of the semiconductor device PKG1 and the position of the upper surface MRt of the semiconductor device PKG2 can be reduced.

[0078] In the case of the examples shown in FIGS. 14 and 15, each of the plurality of terminals TM is formed around a plurality of holes HL1 formed in the insulating layer IL1. Each of the plurality of holes HL1 is formed so as to penetrate the terminal TM. The tips LDE of the outer lead portions LDX of each of the plurality of leads LD1 and the plurality of leads LD2 are inserted into the plurality of holes. Solder SD is disposed in the plurality of holes HL1. Each of the plurality of leads LD1 and the plurality of LD2 is electrically connected to the terminal TM via the solder SD disposed in the hole HL1.

[0079] Although illustration is omitted, as a modification, there may be a case where the holes HL1 shown in FIGS. 14 and 15 are not formed. In this case, each of the leads LD1 and the leads LD2 is electrically connected to the terminal TM via the solder SD applied on the terminal TM. In the case of the structure of this modification, in order for the lower surface MRb of the sealing body MR to contact the mounting surface MBt of the mounting substrate MB1, the positions of the tips LDE of the leads LD1 and the leads LD2 need to be higher than the position of the lower surface MRb of the sealing body MR.

[0080] Also, if the positions of the tips LDE of the leads LD1 and the leads LD2 become extremely high with respect to the position of the lower surface MRb of the sealing body MR, there is a possibility that the leads LD1 and the leads LD2 do not contact the solder SD. Therefore, it is necessary to improve the positional accuracy of the tips LDE of the leads LD1 and the leads LD2.

[0081] On the other hand, in the case of the present embodiment, since the leads LD1 and the leads LD2 only need to be joined to the solder SD disposed in the hole HL1, by adjusting the depth of the hole HL1, the margin of the positional accuracy of the tips LDE of the leads LD1 and the leads LD2 can be increased. Further, the depth of the hole HL1 is such that the bottom surface of the hole HL1 does not contact the tips LDE of the leads LD1 and the leads LD2. For this reason, as shown in FIG. 15, the semiconductor device PKG1 and the semiconductor device PKG2 can be mounted so that the entire lower surface MRb of the sealing body MR contacts the mounting surface MBt of the mounting substrate MB1.

[0082] As described with reference to FIG. 4, the partial LDZ of the plurality of leads LD1 of the semiconductor device PKG1 includes the tip LDE of the outer lead portion LDX. In other words, the tip LDE of the outer lead portion LDX coincides with the tip LDZE of the partial LDZ. As shown in FIG. 12, the plurality of leads LD2 of the semiconductor device PKG2 are the same as the plurality of leads LD1 shown in FIG. 4. In this case, the contact area between the lead LD1 (or lead LD2) and the solder SD shown in FIG. 15 is smaller than that of a general surface-mount semiconductor device in which the tip portion of the outer lead portion LDX is bent.

[0083] As shown in FIG. 15, when the leads LD1 and LD2 are inserted into the holes HL1, the bonding area between each of the leads LD1 and LD2 and the solder SD becomes wider. As a result, the bonding strength between each of the leads LD1 and LD2 and the solder SD can be improved.

[0084] Incidentally, from the viewpoint of improving the degree of freedom of the wiring layout of the mounting substrate MB1, it is preferable that the depth of the hole HL1 is shallower. For example, in the case of the example shown in FIG. 15, the mounting substrate MB1 has a terminal array layer TML in which a plurality of terminals TM are arranged, and a wiring layer WL below the terminal array layer TML. The wiring layer WL is formed at a position farther from the mounting surface MBt than the terminal array layer TML. In FIG. 15, two wiring layers WL are shown, but the number of wiring layers WL is not limited to two layers, and may be one layer or three or more layers.

[0085] Here, when the depth of the hole HL1 is deeper than the example shown in FIG. 15, for example, when reaching the wiring layer WL, the wiring layer WL cannot be provided around the hole HL1 from the viewpoint of avoiding a short circuit between the wiring layer WL and the terminal TM.

[0086] Therefore, from the viewpoint of improving the degree of freedom of the wiring layout in the wiring layer WL, the following structure is preferable. That is, it is preferable that the plurality of holes HL1 penetrate through the plurality of terminals TM respectively and do not penetrate through the insulating layer IL1.

[0087] As shown in FIGS. 14 and 15, a terminal TM connected to a drain lead LDD of a semiconductor device PKG1 and a terminal TM connected to a source lead LDS of a semiconductor device PKG2 are electrically connected to each other via a wiring WDS.

[0088] Therefore, it is not essential that each of the metal plates MP1 and MP2 is electrically connected to the heat sink HS. However, from the following viewpoints, it is preferable that the metal plate MP1 of the semiconductor device PKG1 and the metal plate MP2 of the semiconductor device PKG2 are electrically connected via the heat sink HS as in the present embodiment.

[0089] For example, a conductive material generally has a high thermal conductivity. For example, the above-mentioned solder and conductive resin (for example, one using silver particles as conductive particles) have a high thermal conductivity. Therefore, when the heat sink HS is fixed to the semiconductor device PKG1 via the conductive member CM1, the thermal conduction efficiency of the heat dissipation path from the semiconductor device PKG1 to the heat sink HS can be improved. Also, when the heat sink HS is fixed to the semiconductor device PKG2 via the conductive member CM2, the thermal conduction efficiency of the heat dissipation path from the semiconductor device PKG2 to the heat sink HS can be improved.

[0090] Also, for example, when the metal plate MP1 of the semiconductor device PKG1 and the metal plate MP2 of the semiconductor device PKG2 are electrically connected via the heat sink HS, the heat sink HS can be utilized as a conductive path connected to the load 100 shown in FIG. 13.

[0091] By the way, the solder SD shown in FIG. 15 can be applied with various modifications as long as it is a conductive member that can ensure the electrical connection reliability between the lead LD1 (or lead LD2) and the terminal TM. For example, there are cases where a conductive resin is used instead of the solder SD. However, when the solder SD is embedded in the hole HL1 as in the electronic device ED1, the solder SD is particularly suitable in that air bubbles are less likely to occur in the hole HL1.

[0092] As described above, each of the conductive members CM1 and CM2 is made of solder or a conductive resin. Although details will be described later, when each of the conductive members CM1 and CM2 is made of solder, in the manufacturing process of the electronic device ED1, each of the conductive members CM1 and CM2 is subjected to a reflow process together with the solder SD. The reflow process is a process of melting the solder by heat treatment and then hardening the solder by cooling.

[0093] On the other hand, when each of the conductive members CM1 and CM2 is made of a conductive resin, in the manufacturing process of the electronic device ED1, each of the conductive members CM1 and CM2 is subjected to a cure bake process after the solder SD is subjected to a reflow process. The cure bake process is a process of curing the conductive resin by heating it to a temperature equal to or higher than the curing temperature of the thermosetting resin contained in the conductive resin.

[0094] Note that there are various modifications for the electronic device ED1 described with reference to FIGS. 13 to 15, including the electronic device ED2 (see FIG. 18), the electronic device ED3 (see FIG. 19), and the electronic device ED4 (see FIG. 21), which will be described later.

[0095] For example, in the case of the electronic device ED1, the semiconductor device PKG1 and the semiconductor device PKG2 having different structures are mounted on the mounting substrate MB1 so as to be adjacent to each other. However, for example, there may be a case where two or more semiconductor devices PKG1 are mounted on the mounting substrate MB1 so as to be adjacent to each other.

[0096] For example, in the case of the electronic device ED1, the metal plate MP1 of the semiconductor device PKG1 and the metal plate MP2 of the semiconductor device PKG2 are electrically connected via the heat sink HS. As a modification, each of the metal plate MP1 of the semiconductor device PKG1 and the metal plate MP2 of the semiconductor device PKG2 may not be connected to the heat sink HS. In this case, instead of the conductive members CM1 and CM2 shown in FIG. 15, it is preferable to arrange an insulating adhesive. In the case of this modification, since an insulating adhesive is interposed between the metal plate MP1 of the semiconductor device PKG1 and the heat sink HS and between the metal plate MP2 of the semiconductor device PKG2 and the heat sink HS, the metal plate MP1 of the semiconductor device PKG1 and the metal plate MP2 of the semiconductor device PKG2 can be electrically separated from each other.

[0097] Examples of the insulating adhesive include resin adhesives containing epoxy-based thermosetting resins. When the conductive members CM1 and CM2 are replaced with an insulating adhesive, the heat dissipation characteristics deteriorate. For this reason, it is particularly preferable that inorganic material particles (such as alumina and aluminum nitride) having electrical insulation and a higher thermal conductivity than the resin are mixed as fillers in the insulating resin.

[0098] <Method for manufacturing an electronic device> Next, a method for manufacturing the electronic device described with reference to FIGS. 13 to 15 will be described. FIG. 16 is an explanatory diagram showing an example of the manufacturing process of the electronic device described with reference to FIGS. 13 to 15. FIG. 17 is an explanatory diagram showing a modification of the manufacturing process shown in FIG. 16. The manufacturing process shown in FIG. 16 corresponds to an embodiment in which solder is used as the conductive members CM1 and CM2 shown in FIG. 15, and the manufacturing process shown in FIG. 17 corresponds to an embodiment in which a conductive resin is used as the conductive members CM1 and CM2 shown in FIG. 15.

[0099] The manufacturing method of the electronic device shown in FIG. 16 includes a mounting substrate preparation step, a semiconductor device mounting step, a heat sink arrangement step, and a reflow step. The manufacturing method of the electronic device shown in FIG. 17 includes a mounting substrate preparation step, a semiconductor device mounting step, a reflow step, a heat sink arrangement step, and a cure bake step.

[0100] <Mounting Substrate Preparation Step> First, in the mounting substrate preparation step shown in FIGS. 16 and 17, the mounting substrate MB1 shown in FIGS. 14 and 15 is prepared. The mounting substrate MB1 has a mounting surface MBt, an insulating film SR1 provided on the mounting surface MBt (see FIG. 15), a plurality of terminals TM respectively exposed from the insulating film SR1 at a plurality of openings formed in the insulating film SR1, and an insulating layer IL1 (see FIG. 15) in which the plurality of terminals TM are formed.

[0101] In the case of this embodiment, a plurality of holes HL1 are provided in advance in the insulating layer IL1 of the mounting substrate MB1. Each of the plurality of holes HL1 is formed so as to penetrate the terminal TM in the thickness direction.

[0102] <Semiconductor Device Mounting Step> Next, in the semiconductor device mounting step shown in FIGS. 16 and 17, as shown in FIGS. 14 and 15, the semiconductor device PKG1 and the semiconductor device PKG2 are mounted on the mounting substrate MB1 so that the semiconductor device PKG1 and the semiconductor device PKG2 are adjacent to each other on the mounting substrate MB1. In the example shown in FIGS. 16 and 17, the semiconductor device mounting step includes a first conductive member application step, an alignment step, and a lead insertion step.

[0103] In the first conductive member application step, solder SD (see FIG. 15) is applied so as to contact each of the plurality of terminals TM. The solder SD applied in this step is strictly different from the solder SD shown in FIG. 15, and is a paste-like solder containing a flux component in addition to the solder components. Such a paste material is called solder paste. In the first conductive member application step, the solder paste, which is the raw material of the solder SD, is applied into each of the plurality of holes HL1.

[0104] Next, in the alignment process, for example, first, alignment between the semiconductor device PKG1 and the mounting substrate MB1 is performed. In the alignment process of the semiconductor device PKG1, alignment is performed such that the tips LDE of the outer lead portions LDX (see FIG. 4) of the plurality of leads LD1 of the semiconductor device PKG1 are positioned above the holes HL1. Note that the alignment process between the semiconductor device PKG2 and the mounting substrate MB1 is performed after the lead insertion process of the semiconductor device PKG1. Since the alignment process of the semiconductor device PKG2 is the same as that of the semiconductor device PKG1, duplicate explanations are omitted.

[0105] Next, in the lead insertion process, for example, first, each of the plurality of leads LD1 of the semiconductor device PKG1 is inserted into the holes HL1. Thereby, the plurality of leads LD1 come into contact with the solder paste in the holes HL1.

[0106] Also, in the lead insertion process, the distance between the semiconductor device PKG1 and the mounting substrate MB1 is decreased until the lower surface MRb of the sealing body MR of the semiconductor device PKG1 contacts the mounting surface MBt of the mounting substrate MB1. Similarly, in the lead insertion process, the distance between the semiconductor device PKG2 and the mounting substrate MB1 is decreased until the lower surface MRb of the sealing body MR of the semiconductor device PKG2 contacts the mounting surface MBt of the mounting substrate MB1. In other words, in this process, the semiconductor devices PKG1 and PKG2 are arranged such that the respective lower surfaces MRb (specifically, the entire lower surfaces MRb) of the semiconductor devices PKG1 and PKG2 are in contact with the mounting surface MBt of the mounting substrate MB1.

[0107] At the stage when this process is completed, the solder paste is in a stage before being cured by the reflow process. Therefore, each of the semiconductor devices PKG1 and PKG2 is in a state of being adhered onto the mounting substrate MB1 via the solder paste.

[0108] In the example shown in FIG. 16, a heat sink placement step is performed following the lead insertion step. On the other hand, in the example shown in FIG. 17, a reflow step is performed after the lead insertion step (in other words, after the semiconductor device mounting step) and before the heat sink placement step. Hereinafter, the description will be made along the example of FIG. 16.

[0109] In the heat sink placement step, after the semiconductor device mounting step, a heat sink HS is placed so as to straddle the semiconductor device PKG1 and the semiconductor device PKG2. The heat sink placement step includes a second conductive member placement step and a heat sink adhesion step.

[0110] In the second conductive member placement step, the conductive member CM1 shown in FIG. 15 is placed on the exposed surface MP1b of the metal plate MP1 of the semiconductor device PKG1, and the conductive member CM2 is placed on the exposed surface MP2t of the metal plate MP2 of the semiconductor device PKG2. In the case of the example shown in FIG. 16, each of the conductive member CM1 and the conductive member CM2 is, for example, solder. In this case, in this step, a solder paste is applied on the exposed surface MP1b of the metal plate MP1 of the semiconductor device PKG1 and on the exposed surface MP2t of the metal plate MP2 of the semiconductor device PKG2 where the conductive member CM2 is located.

[0111] Next, in the heat sink adhesion step, as shown in FIGS. 14 and 15, a heat sink HS is placed so as to straddle the semiconductor device PKG1 and the semiconductor device PKG2. The heat sink HS is adhered to the semiconductor device PKG1 and the semiconductor device PKG2 via the solder paste.

[0112] In the example shown in FIG. 16, a reflow process is performed after the heat sink placement process. In the reflow process, the peripheral temperatures of the solder SD, the conductive member CM1, and the conductive member CM2 shown in FIG. 15 are raised until they reach or exceed the melting point of the solder, which is the raw material for each of them. As the temperature rises, the flux component contained in the solder paste oozes out around the solder paste to activate the bonding interface of the solder. By this activation, the oxide film formed on the metal surface for bonding the solder is removed, and the solder becomes wet. Thereafter, by cooling, the solder hardens, and the solder SD, the conductive member CM1, and the conductive member CM2 shown in FIG. 15 are obtained. The organic components contained in the solder paste as the flux component and the binder material volatilize during the temperature rise of the reflow process. If residues remain, a cleaning process may be performed after reflow.

[0113] When the solder contained in the solder paste hardens, each of the plurality of leads LD1 and the plurality of leads LD2 is fixed to the mounting substrate MB1. Also, the heat sink HS is fixed to the metal plate MP1 of the semiconductor device PKG1 via the conductive member CM1 and to the metal plate MP2 of the semiconductor device PKG2 via the conductive member CM2. In other words, in the case of the example shown in FIG. 16, after the heat sink placement process, it includes a process of fixing the heat sink HS to each of the metal plate MP1 and the metal plate MP2 via the conductive members (the conductive member CM1 and the conductive member CM2).

[0114] In the example shown in FIG. 16, each of the semiconductor device PKG1 and the semiconductor device PKG2 is fixed to the mounting substrate MB1 by the reflow process. Also, the heat sink HS is fixed to each of the semiconductor device PKG1 and the semiconductor device PKG2 by the reflow process.

[0115] In the case of the example shown in FIG. 16, the solder pastes disposed in the plurality of holes HL1, the solder paste disposed on the semiconductor device PKG1, and the solder paste disposed on the semiconductor device PKG2 are all subjected to reflow processing (at the same timing). For this reason, it is possible to prevent the electrical connection interface from being contaminated by the gas generated from the organic material during the heat treatment.

[0116] On the other hand, in the case of the example shown in FIG. 16, since the reflow process is performed with the heat sink HS disposed, there is a problem that it is difficult to raise the temperatures of the conductive member CM1 and the conductive member CM2. In the case of the modified example shown in FIG. 17, it is advantageous in this respect as compared with the example shown in FIG. 16.

[0117] Hereinafter, the manufacturing method of the modified example will be described with reference to FIG. 17. In the case of the modified example shown in FIG. 17, up to the semiconductor device mounting step is the same as the example shown in FIG. 16. Therefore, hereinafter, the description will focus on the differences from the example shown in FIG. 16.

[0118] As described above, in the case of the example shown in FIG. 17, the conductive member shown as the solder SD in FIG. 15 is made of solder, and each of the conductive member CM1 and the conductive member CM2 is made of a conductive resin. In this case, as shown in FIG. 17, after the semiconductor device mounting step and before the heat sink arranging step, there is a reflow step. In the reflow step, as described above, the solder paste disposed in the hole HL1 is heated to a temperature equal to or higher than the melting point of the solder and then cooled, whereby each of the semiconductor device PKG1 and the semiconductor device PKG2 is fixed to the mounting substrate MB1.

[0119] Also, in the second conductive member placement step of the heat sink placement step shown in FIG. 17, on the exposed surface MP1b of the metal plate MP1 of the semiconductor device PKG1 and on the exposed surface MP2t of the metal plate MP2 of the semiconductor device PKG2 where the conductive member CM2 is located, for example, a paste-like (in other words, before thermosetting) conductive resin paste is applied. The conductive resin paste is the raw material of the conductive member CM1 and the conductive member CM2 shown in FIG. 15. The conductive resin paste is a paste material containing, for example, conductive particles made of silver and a resin containing a thermosetting resin. Note that in this step, instead of the paste material, a conductive resin sheet pre-formed into a sheet shape may be used in some cases.

[0120] Next, in the heat sink adhesion step, as shown in FIGS. 14 and 15, the heat sink HS is placed so as to straddle the semiconductor device PKG1 and the semiconductor device PKG2. The heat sink HS is adhered to the semiconductor device PKG1 and the semiconductor device PKG2 via the conductive resin paste.

[0121] Also, the example shown in FIG. 17 includes a cure bake step of performing a cure bake process to cure the thermosetting resin contained in the conductive resin paste after the heat sink placement step. In the cure bake step, by heating to a temperature equal to or higher than the curing temperature of the thermosetting resin contained in the conductive resin paste, the heat sink HS is fixed to each of the semiconductor device PKG1 and the semiconductor device PKG2.

[0122] In the cure bake step, since the thermosetting resin can be cured at a temperature lower than that of the solder SD, even if it is heated with the heat sink HS attached, it is easy to raise the temperature to the required temperature. This is advantageous compared to the example shown in FIG. 16 in this regard.

[0123] On the other hand, in the case of the example shown in FIG. 17, since the semiconductor device PKG1 and the semiconductor device PKG2 are heated to a high temperature in the reflow process, an oxide film may be formed on the exposed surfaces (exposed surface MP1b and exposed surface MP2t) of the metal plates MP1 and MP2 exposed from the sealing body. In addition, a film may be formed due to the gas generated during heating. Depending on the thickness of this film, a process for removing it may be required. In this regard, the manufacturing method of the electronic device shown in FIG. 16 is more advantageous.

[0124] As described above as a modification, when each of the conductive members CM1 and CM2 is replaced with an insulating adhesive, in the flow shown in FIG. 17, in the second conductive member arrangement step, an insulating adhesive is arranged instead of the conductive members CM1 and CM2.

[0125] <Modification Example 1 of Electronic Device> Next, a modification to the electronic device described with reference to FIGS. 13 to 15 will be described. FIG. 18 is an enlarged cross-sectional view of an electronic device that is a modification of FIG. 15. FIG. 19 is an enlarged cross-sectional view of an electronic device that is a modification of FIG. 18. Hereinafter, the differences between the electronic device ED2 shown in FIG. 18 and the electronic device ED1 shown in FIG. 15, and the differences between the ED2 shown in FIG. 18 and the electronic device ED3 shown in FIG. 19 will be described.

[0126] The electronic device ED2 shown in FIG. 18 differs from the electronic device ED1 shown in FIG. 15 in the following points. That is, the metal plate MP1 of the semiconductor device PKG1A of the electronic device ED2 has a screw hole SWH1 formed in the exposed surface MP1b. In addition, the metal plate MP2 of the semiconductor device PKG2A of the electronic device ED2 has a screw hole SWH2 formed in the exposed surface MP2t. The heat sink HS of the electronic device ED2 is fixed to the semiconductor device PKG1A by a screw SW1 fastened to the screw hole SWH1, and is fixed to the semiconductor device PKG2A by a screw SW2 fastened to the screw hole SWH2 of the semiconductor device PKG2A.

[0127] Each of the screws SW1 and SW2 is made of metal. Spiral grooves are formed on the side surfaces of each of the screw holes SWH1 and SWH2. The spiral grooves provided on each of the screws SW1 and SW2 and the spiral grooves provided on each of the screw holes SWH1 and SWH2 are combined with each other and fixed.

[0128] When the heat sink HS is fixed using the screws SW1 and SW2 as in this modification example, high strength can be obtained. Also, in the example shown in FIG. 18, the exposed surface MP1b of the metal plate MP1 of the semiconductor device PKG1A is in contact with the lower surface HSb of the heat sink HS. Further, the exposed surface MP2t of the metal plate MP2 of the semiconductor device PKG2A is in contact with the lower surface HSb of the heat sink HS. In this way, when the metal plates MP1 and MP2 are in direct contact with the heat sink HS, the heat dissipation efficiency is improved.

[0129] However, in order to increase the contact area between each of the metal plates MP1 and MP2 and the heat sink HS, the surfaces facing each other need to be flattened. If there are irregularities on either one or both of the lower surface HSb of the heat sink HS and the exposed surface MP1b (or the exposed surface MP2t) of the metal plate MP1, a gap will occur between them, which will cause a decrease in heat dissipation performance.

[0130] Therefore, there is a modification example in which a heat dissipation sheet HDS is disposed between the semiconductor device PKG1A and the heat sink HS and between the semiconductor device PKG2A and the heat sink HS as in the electronic device ED3 shown in FIG. 19. The heat dissipation sheet (resin sheet) HDS shown in FIG. 19 is, for example, a resin sheet (a resin body molded into a sheet shape), and inorganic material particles (for example, alumina, aluminum nitride, or metal particles) having a higher thermal conductivity than the resin are mixed as fillers in the resin.

[0131] In the case of this modification example, since the fixing of the heat sink HS is realized by the screws SW1 and SW2, adhesiveness is not required for the heat dissipation sheet HDS. Also, in the case of this modification example, the screw SW1 is electrically connected to the metal plate MP1, and the screw SW2 is electrically connected to the metal plate MP2. Therefore, conductivity is not required for the heat dissipation sheet HDS. Thus, the heat dissipation sheet HDS can be selected from the viewpoints that a gap is less likely to occur between the heat sink HS and the metal plate MP1 (or the metal plate MP2), and that the heat dissipation property of the heat dissipation sheet HDS itself is high. For this reason, the degree of freedom in the selection of the heat dissipation sheet HDS is high.

[0132] In the case of the electronic device ED1 shown in FIG. 18 and the electronic device ED2 shown in FIG. 19, the metal plate MP1 of the semiconductor device PKG1A is electrically connected to the semiconductor chip CP1. Therefore, the semiconductor chip CP1 is electrically connected to the heat sink HS via the metal plate MP1 and the screw (conductive member) SW1. Also, the metal plate MP2 of the semiconductor device PKG2A is electrically connected to the semiconductor chip CP2. Accordingly, the semiconductor chip CP2 is electrically connected to the heat sink HS via the metal plate MP2 and the screw (conductive member) SW2.

[0133] However, as a modification example, when the semiconductor chip CP1 and the metal plate MP1 of the semiconductor device PKG1A are not electrically connected, the semiconductor chip CP1 and the heat sink HS are electrically separated. Similarly, when the semiconductor chip CP2 and the metal plate MP2 of the semiconductor device PKG2A are not electrically connected, the semiconductor chip CP2 and the heat sink HS are electrically separated.

[0134] The structures of the electronic device ED2 shown in FIG. 18 and the electronic device ED3 shown in FIG. 19 are the same as those of the electronic device ED1 shown in FIG. 15 except for the above points. Also, the semiconductor device PKG1A shown in FIGS. 18 and 19 is the same as the semiconductor device PKG1 shown in FIG. 15 except that it has a screw hole SWH1. The semiconductor device PKG2A shown in FIGS. 18 and 19 is the same as the semiconductor device PKG2 shown in FIG. 15 except that it has a screw hole SWH2. Therefore, overlapping explanations are omitted.

[0135] Next, a method for manufacturing the electronic device ED2 shown in FIG. 18 and the electronic device ED3 shown in FIG. 19 will be described. FIG. 20 is an explanatory diagram showing an example of the manufacturing process of the electronic device shown in FIG. 18 or the electronic device shown in FIG. 19. The manufacturing process shown in FIG. 20 is the same as the manufacturing process and the reflow process described with reference to FIG. 17, except that screw holes SWH1 and SWH2 shown in FIGS. 18 and 19 are formed in advance in the semiconductor device mounted in the semiconductor device mounting process. Therefore, in the following description, the differences from FIG. 17 will be described.

[0136] The manufacturing method of the electronic device shown in FIG. 20 includes a heat sink fixing process in addition to the mounting substrate preparation process, the semiconductor device mounting process, and the reflow process described with reference to FIG. 17. In the heat sink fixing process, as shown in FIGS. 18 and 19, the heat sink HS is fixed to each of the metal plates MP1 and MP2. Note that the heat sink arrangement process to the reflow process shown in FIG. 16, and the heat sink arrangement process to the cure bake process shown in FIG. 17 can be considered as the heat sink fixing process shown in FIG. 20.

[0137] The heat sink fixing process of this modification includes a screwing process. In the screwing process, as shown in FIG. 18, the heat sink HS is fixed to the semiconductor device PKG1A by a screw SW1 fastened to the screw hole SWH1, and is fixed to the semiconductor device PKG2A by a screw SW2 fastened to the screw hole SWH2 of the semiconductor device PKG2A.

[0138] In addition, in the case of the manufacturing method of the electronic device ED3 shown in FIG. 19, the heat sink fixing process includes a heat sink sheet arrangement process before the screwing process. In the heat sink sheet arrangement process, the heat sink sheet HDS shown in FIG. 19 is arranged on the metal plate MP1 of the semiconductor device PKG1A and on the metal plate MP2 of the semiconductor device PKG2A, respectively. Through holes for inserting the screw SW1 or the screw SW2 are formed in advance in the heat sink sheet HDS. In the heat sink sheet arrangement process, alignment is performed so that the through holes formed in the heat sink sheet HDS are located above the screw holes SWH1 of the metal plate MP1 or above the screw holes SWH2 of the metal plate MP2.

[0139] The manufacturing method of the electronic device shown in FIG. 20 is the same as the manufacturing method of the electronic device described with reference to FIG. 17, except for the above points. Therefore, duplicate explanations are omitted.

[0140] <Second Modification Example of Electronic Device> Next, another modification example of the electronic device described with reference to FIGS. 13 to 15 will be described. Hereinafter, a modification example of the electronic device ED1 shown in FIG. 15 will be taken as a representative and described. However, the structures of the semiconductor devices PKG1B and PKG2B shown in FIG. 21 are the same as those of the semiconductor devices PKG1 and PKG2 shown in FIG. 15, except for the shape of the tip of the outer lead portion LDX. The technology described below can be applied as a modification example of the semiconductor devices PKG1A and PKG2A described with reference to FIGS. 18 and 19. That is, the technology described in this modification example can be applied in combination with the technology described in the section of <First Modification Example of Electronic Device>.

[0141] FIG. 21 is an enlarged cross-sectional view showing another modification example of FIG. 15. FIG. 22 is an enlarged cross-sectional view showing an enlargement of one of the plurality of leads shown in FIG. 21. In the electronic device ED4 shown in FIG. 21, the lead shapes of the semiconductor devices PKG1B and PKG2B are different from those of the electronic device ED1 shown in FIG. 15.

[0142] As shown in FIG. 22, the lead LD1 (or lead LD2) of the semiconductor device PKG1B (or semiconductor device PKG2B) of this modification example has an outer lead portion LDX with a shape different from that of the semiconductor device PKG1 shown in FIG. 4 and the semiconductor device PKG2 shown in FIG. 12.

[0143] In the case of this modification example, as shown in FIG. 22, the outer lead portion LDX is connected to a portion LDZ that extends in the direction from the upper surface MRt to the lower surface MRb in the thickness direction (Z direction) of the sealing body MR, and further has a portion LDY that extends in a direction intersecting the Z direction (in other words, extends along the Y direction). Therefore, the tip LDE of the outer lead portion LDX is included in the portion LDY, not in the portion LDZ. In other words, in the case of this modification example, the tip LDE of the outer lead portion LDX coincides with the tip LDYE of the portion LDY. In the case of this modification example, since the portion LDZ is connected to the portion LDY, there is no tip of the portion LDZ. That is, the tip LDE of the outer lead portion LDX does not coincide with the tip LDZE of the portion LDZ shown in FIG. 4. Therefore, each of the semiconductor devices PKG1B and PKG2B shown in FIG. 21 is classified as a semiconductor package closer to SOP than DIP.

[0144] As shown in FIG. 21, even in the case of the semiconductor device PKG1B (or the semiconductor device PKG2B) having the portion LDY (see FIG. 22), a hole HL1 is formed in the mounting substrate MB1, and the tip of the lead LD1 (or the lead LD2) is inserted into the hole HL1, so that the lower surface MRb of the sealing body MR and the mounting surface MBt of the mounting substrate MB1 can be brought into contact.

[0145] In the case of this modification example, as shown in FIG. 22, by accommodating the entire portion LDY in the hole HL1 (see FIG. 21), the contact area between the solder SD and the lead LD1 (or the lead LD2) can be increased. As a result, the mounting strength of the semiconductor devices PKG1B and PKG2B on the mounting substrate MB1 is higher than the mounting strength of the semiconductor devices PKG1 and PKG2 on the mounting substrate MB1 shown in FIG. 15.

[0146] On the other hand, as can be seen by comparing FIG. 15 and FIG. 21, in order to accommodate the entire portion LDY (see FIG. 22) in the hole HL1, it is necessary to increase the opening diameter of the hole HL1. Therefore, from the viewpoint of reducing the mounting area by reducing the opening area of the hole HL1, the electronic device ED1 shown in FIG. 15 is more preferable.

[0147] Also, as can be seen by comparing FIG. 15 and FIG. 21, in order to accommodate the entire portion LDY (see FIG. 22) within the hole HL1, it is necessary to increase the depth of the hole HL1. Therefore, from the perspective of preventing interference with the wiring layer WL of the mounting substrate MB1 by reducing the depth of the hole HL1, the electronic device ED1 shown in FIG. 15 is preferred.

[0148] As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof.

Explanation of Reference Numerals

[0149] 100 Load BW, BWG, BWS Wire CH Channel Formation Region CM1, CM2 Conductive Member CP1, CP2 Semiconductor Chip CP1b, CP2b Lower Surface (Surface, Back Surface, Main Surface) CP1t, CP2t Upper Surface (Surface, Front Surface, Main Surface) CTC Control Circuit D Drain DB, DB2 Die Bonding Material ED1, ED2, ED3, ED4 Electronic Device EP Epitaxial Layer G Gate GI Gate Insulating Film HDS Heat Dissipation Sheet (Resin Sheet) HL1 Hole HS Heat Sink (Heat Sink, Metal Member) HSb Lower Surface HSt Upper Surface HT Terminal (High-Side Terminal) IL, IL1 Insulating Layer L1, L2 Distance LD1, LD2, LDD, LDG, LDS Lead LDE, LDYE, LDZE Tip LDM Inner Lead Part LDX Outer Lead Part LDY, LDZ Parts LT Terminal (Low Side Terminal) MB1 Mounting Substrate MBt Mounting Surface MP1, MP2 Metal Plates MP1b, MP2t Exposed Surfaces (Surfaces, Upper Surfaces) MP1t Chip Mounting Surface (Surface, Lower Surface) MP2b Chip Opposing Surface (Surface, Lower Surface) MR Sealing Body MRb Lower Surface MRt Upper Surface PD Pad PDD Drain Electrode Pad PDG Gate Electrode Pad PDS Source Electrode Pad PKG1, PKG1A, PKG1B, PKG2, PKG2A, PKG2B Semiconductor Devices PW Power Supply Q1 Transistor RS1 Reference Plane S Source SD Solder (Conductive Member) SR Source Region SR1 Insulating Film SW1, SW2 Screws SWH1, SWH2 Screw Holes TM Terminal TML Terminal Array Layer TR1 Trench (Opening, Groove) WDS Wiring WH Semiconductor Substrate WHt Main Surface WL Wiring Layer

Claims

1. A semiconductor chip, A sealing body having a first surface and a second surface located opposite to the first surface, for sealing the semiconductor chip, A plurality of leads electrically connected to the semiconductor chip, A metal plate having a first exposed surface exposed from the sealing body on the first surface of the sealing body, And having, Each of the plurality of leads, An inner lead portion sealed in the sealing body, An outer lead portion exposed from the sealing body, And comprising, The outer lead portion includes a first portion extending in a direction from the first surface toward the second surface in the thickness direction of the sealing body, The first portion includes the tip of the outer lead portion, When the second surface is taken as a first reference plane in a side view, in the thickness direction of the sealing body, the distance from the tip to the first reference plane is shorter than the distance from the first surface to the first reference plane, a semiconductor device.

2. In Claim 1, The semiconductor chip has a power transistor composed of a power MOSFET or an IGBT, The metal plate is electrically connected to the drain or source of the power MOSFET, or the collector or emitter of the IGBT, a semiconductor device.

3. In Claim 1, The metal plate has a screw hole formed in the first exposed surface, a semiconductor device.

4. A mounting substrate having a mounting surface, A first semiconductor device mounted on the mounting surface of the mounting substrate, A second semiconductor device mounted on the mounting surface of the mounting substrate so as to be adjacent to the first semiconductor device, A heat sink fixed to each of the first semiconductor device and the second semiconductor device and disposed across the first semiconductor device and the second semiconductor device, And having, Each of the first semiconductor device and the second semiconductor device, A semiconductor chip, A sealing body having a first surface facing the heat sink and a second surface located opposite to the first surface, for sealing the semiconductor chip, A plurality of leads electrically connected to the semiconductor chip, A metal plate having a first exposed surface exposed from the sealing body on the first surface of the sealing body, And having, Each of the plurality of leads, An inner lead portion sealed in the sealing body, An outer lead portion exposed from the sealing body, And comprising, The outer lead portion includes a first portion extending in a direction from the first surface toward the second surface in the thickness direction of the sealing body, When the second surface is taken as the first reference plane in a side view, in the thickness direction of the sealing body, the distance from the tip of the outer lead portion to the first reference plane is shorter than the distance from the first surface to the first reference plane. An electronic device in which the respective second surfaces of the first semiconductor device and the second semiconductor device are in contact with the mounting surface of the mounting substrate. **Claim 5** In claim 4, the mounting substrate has a first insulating film provided on the mounting surface, a plurality of terminals respectively exposed from the first insulating film in a plurality of openings formed in the first insulating film, a first insulating layer on which the plurality of terminals are formed, and the first insulating film is formed on the first insulating layer, each of the plurality of terminals is formed around a plurality of holes formed in the first insulating layer, the tip of the outer lead portion is inserted into the plurality of holes, An electronic device in which the plurality of terminals and the plurality of leads are electrically connected to each other via a first conductive member disposed inside the plurality of holes. **Claim 6** In claim 5, An electronic device in which the plurality of holes penetrate the plurality of terminals respectively and do not penetrate the first insulating layer. **Claim 7** In claim 5, the metal plate of the first semiconductor device is a first metal plate, the metal plate of the second semiconductor device is a second metal plate, An electronic device in which the heat sink is fixed to each of the first metal plate and the second metal plate via a second conductive member. **Claim 8** In claim 7, the semiconductor chip of the first semiconductor device is a first semiconductor chip, the semiconductor chip of the second semiconductor device is a second semiconductor chip, the first semiconductor chip is electrically connected to the heat sink via the first metal plate and the second conductive member, An electronic device in which the second semiconductor chip is electrically connected to the heat sink via the second metal plate and the second conductive member. **Claim 9** In claim 8, An electronic device in which the first conductive member and the second conductive member are each made of solder. **Claim 10** In claim 8, An electronic device in which the first conductive member is made of solder and the second conductive member is made of conductive resin. **Claim 11** In claim 8, each of the first semiconductor chip and the second semiconductor chip has a power transistor composed of a power MOSFET or an IGBT. The first metal plate is electrically connected to the source of the power MOSFET of the first semiconductor chip or the emitter of the IGBT. An electronic device in which the second metal plate is electrically connected to the drain of the power MOSFET of the second semiconductor chip or the collector of the IGBT.

12. In claim 6, The metal plate of the first semiconductor device is a first metal plate, and the metal plate of the second semiconductor device is a second metal plate. The first metal plate is provided with a first screw hole formed in the first exposed surface. The second metal plate is provided with a second screw hole formed in the first exposed surface. The heat sink is fixed to the first semiconductor device by a first screw fastened to the first screw hole and is fixed to the second semiconductor device by a second screw fastened to the second screw hole of the second semiconductor device. An electronic device.

13. In claim 12, The semiconductor chip of the first semiconductor device is a first semiconductor chip, and the semiconductor chip of the second semiconductor device is a second semiconductor chip. The first semiconductor chip is electrically connected to the heat sink via the first metal plate and the first screw. An electronic device in which the second semiconductor chip is electrically connected to the heat sink via the second metal plate and the second screw.

14. (a) A step of preparing a mounting substrate having a mounting surface, a first insulating film provided on the mounting surface, a plurality of terminals each exposed from the first insulating film in a plurality of openings formed in the first insulating film, and a first insulating layer on which the plurality of terminals are formed. (b) A step of mounting the first semiconductor device and the second semiconductor device on the mounting substrate so that the first semiconductor device and the second semiconductor device are adjacent to each other. (c) After the step (b), a step of fixing a heat sink to each of the first semiconductor device and the second semiconductor device so as to straddle the first semiconductor device and the second semiconductor device. including Each of the first semiconductor device and the second semiconductor device a semiconductor chip; A sealing body that includes a first surface facing the heat sink and a second surface located opposite to the first surface and seals the semiconductor chip. A plurality of leads electrically connected to the semiconductor chip. A metal plate provided with a first exposed surface exposed from the sealing body on the first surface of the sealing body. having Each of the plurality of leads An inner lead portion sealed in the sealing body. The outer lead portion exposed from the sealing body, comprising, The outer lead portion includes a first portion extending in a direction from the first surface toward the second surface in the thickness direction of the sealing body, When the second surface is taken as a first reference plane in a side view, in the thickness direction of the sealing body, the distance from the tip of the outer lead portion to the first reference plane is shorter than the distance from the first surface to the first reference plane, In the step (b), a method of manufacturing an electronic device, in which the first semiconductor device and the second semiconductor device are arranged such that the respective second surfaces of the first semiconductor device and the second semiconductor device are in contact with the mounting surface of the mounting substrate.

15. In claim 14, Each of the plurality of terminals is formed around a plurality of holes formed in the first insulating layer, In the step (b), a method of manufacturing an electronic device, in which the tip of the outer lead portion is inserted into the plurality of holes coated with the first conductive member.

16. In claim 15, The metal plate of the first semiconductor device is a first metal plate, and the metal plate of the second semiconductor device is a second metal plate, (d) After the step (c), a step of fixing the heat sink to each of the first metal plate and the second metal plate via a second conductive member, the method of manufacturing an electronic device further including.

17. In claim 16, The first conductive member and the second conductive member are each made of solder, In the step (d), a reflow process is performed in which each of the first conductive member and the second conductive member is heated to a temperature equal to or higher than the melting point of the solder and then cooled, Each of the first semiconductor device and the second semiconductor device is fixed to the mounting substrate by the reflow process, The heat sink is fixed to each of the first semiconductor device and the second semiconductor device by the reflow process, the method of manufacturing an electronic device.

18. In claim 16, The first conductive member is made of solder, and the second conductive member is made of a conductive resin, (e) After the step (b) and before the step (c), a step of heating the first conductive member to a temperature equal to or higher than the melting point of the solder and then cooling to fix each of the first semiconductor device and the second semiconductor device to the mounting substrate, the method further including. In the step (d), the heat dissipation plate is fixed to each of the first semiconductor device and the second semiconductor device by heating the thermosetting resin contained in the conductive resin to a temperature equal to or higher than the curing temperature thereof, a method for manufacturing an electronic device.

19. In claim 15, the metal plate of the first semiconductor device is a first metal plate, and the metal plate of the second semiconductor device is a second metal plate, the first metal plate includes a first screw hole formed in the first exposed surface, the second metal plate includes a second screw hole formed in the first exposed surface, (d) after the step (c), further including a step of fixing the heat dissipation plate to each of the first metal plate and the second metal plate, In the step (d), the heat dissipation plate is fixed to the first semiconductor device by a first screw fastened to the first screw hole, and is fixed to the second semiconductor device by a second screw fastened to the second screw hole of the second semiconductor device, a method for manufacturing an electronic device.

20. In claim 19, the semiconductor chip of the first semiconductor device is a first semiconductor chip, and the semiconductor chip of the second semiconductor device is a second semiconductor chip, the first semiconductor chip is electrically connected to the heat dissipation plate through the first metal plate and the first screw, the second semiconductor chip is electrically connected to the heat dissipation plate through the second metal plate and the second screw, a method for manufacturing an electronic device.

Images