Display device

Abstract

To provide a semiconductor device with high reliability, in which a back plate is formed of an oxide semiconductor film.SOLUTION: A semiconductor device includes a first conductive film, a first insulating film on the first conductive film, an oxide semiconductor film overlapping with the first conductive film on the first insulating film, a second insulating film on the oxide semiconductor film, and a pair of second conductive films electrically connected to the oxide semiconductor film in an opening of the second insulating film. The second insulating film overlaps with a region of the oxide semiconductor film where carriers flow between the pair of second conductive films, and an end part of the oxide semiconductor film.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an article, a method, or a manufacturing method. , manufacture, or composition of matter. One embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a memory device, and a driving method thereof. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, The present invention relates to a light-emitting device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof. . [Background technology]

[0002] Metal oxides that exhibit semiconductor properties, known as oxide semiconductors, are attracting attention. These materials are used in a variety of applications, for example indium oxide, a well-known metal oxide. Semiconductors are used in transparent pixel electrodes in liquid crystal displays and light-emitting devices. Examples of metal oxides that exhibit this characteristic include tungsten oxide, tin oxide, indium oxide, Metal oxides that exhibit such semiconducting properties are used in the channel formation region. Transistors having this structure are already known (Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0004] A transistor having a channel formation region in an oxide semiconductor film is used on a backplane for mass production of a semiconductor device. One of the major issues is to improve reliability. One aspect of the present invention is to provide a semiconductor device having high reliability with a backplane made of an oxide semiconductor film as one of the issues. As one of the major issues in mass production of a semiconductor device using a transistor having a channel formation region in an oxide semiconductor film on a backplane, there is an improvement in reliability. One aspect of the present invention is to provide a semiconductor device having high reliability with a backplane made of an oxide semiconductor film as one of the issues. As one of the major issues in mass production of a semiconductor device using a transistor having a channel formation region in an oxide semiconductor film on a backplane, there is an improvement in reliability. One aspect of the present invention is to provide a semiconductor device having high reliability with a backplane made of an oxide semiconductor film as one of the issues. As one of the major issues in mass production of a semiconductor device using a transistor having a channel formation region in an oxide semiconductor film on a backplane, there is an improvement in reliability. One aspect of the present invention is to provide a semiconductor device having high reliability with a backplane made of an oxide semiconductor film as one of the issues.

[0005] One aspect of the present invention is to provide a novel semiconductor device or the like as one of the issues. Note that the description of these issues does not prevent the existence of other issues. One aspect of the present invention does not necessarily need to solve all of these issues. Other issues will be apparent from the description of the specification, drawings, claims, etc., and it is possible to extract these other issues from the description of the specification, drawings, claims, etc. One aspect of the present invention is to provide a novel semiconductor device or the like as one of the issues. Note that the description of these issues does not prevent the existence of other issues. One aspect of the present invention does not necessarily need to solve all of these issues. Other issues will be apparent from the description of the specification, drawings, claims, etc., and it is possible to extract these other issues from the description of the specification, drawings, claims, etc. One aspect of the present invention is to provide a novel semiconductor device or the like as one of the issues. Note that the description of these issues does not prevent the existence of other issues. One aspect of the present invention does not necessarily need to solve all of these issues. Other issues will be apparent from the description of the specification, drawings, claims, etc., and it is possible to extract these other issues from the description of the specification, drawings, claims, etc. One aspect of the present invention is to provide a novel semiconductor device or the like as one of the issues. Note that the description of these issues does not prevent the existence of other issues. One aspect of the present invention does not necessarily need to solve all of these issues. Other issues will be apparent from the description of the specification, drawings, claims, etc., and it is possible to extract these other issues from the description of the specification, drawings, claims, etc. One aspect of the present invention is to provide a novel semiconductor device or the like as one of the issues. Note that the description of these issues does not prevent the existence of other issues. One aspect of the present invention does not necessarily need to solve all of these issues. Other issues will be apparent from the description of the specification, drawings, claims, etc., and it is possible to extract these other issues from the description of the specification, drawings, claims, etc.

Means for Solving the Issues

[0006] A semiconductor device according to one aspect of the present invention includes a first conductive film, a first insulating film on the first conductive film, an oxide semiconductor film overlapping the first conductive film on the first insulating film, a second insulating film on the oxide semiconductor film, and a pair of second conductive films electrically connected to the oxide semiconductor film at an opening of the second insulating film. The second insulating film overlaps a region where carriers flow between the pair of second conductive films and an end portion of the oxide semiconductor film. A semiconductor device according to one aspect of the present invention includes a first conductive film, a first insulating film on the first conductive film, an oxide semiconductor film overlapping the first conductive film on the first insulating film, a second insulating film on the oxide semiconductor film, and a pair of second conductive films electrically connected to the oxide semiconductor film at an opening of the second insulating film. The second insulating film overlaps a region where carriers flow between the pair of second conductive films and an end portion of the oxide semiconductor film. A semiconductor device according to one aspect of the present invention includes a first conductive film, a first insulating film on the first conductive film, an oxide semiconductor film overlapping the first conductive film on the first insulating film, a second insulating film on the oxide semiconductor film, and a pair of second conductive films electrically connected to the oxide semiconductor film at an opening of the second insulating film. The second insulating film overlaps a region where carriers flow between the pair of second conductive films and an end portion of the oxide semiconductor film. A semiconductor device according to one aspect of the present invention includes a first conductive film, a first insulating film on the first conductive film, an oxide semiconductor film overlapping the first conductive film on the first insulating film, a second insulating film on the oxide semiconductor film, and a pair of second conductive films electrically connected to the oxide semiconductor film at an opening of the second insulating film. The second insulating film overlaps a region where carriers flow between the pair of second conductive films and an end portion of the oxide semiconductor film. A semiconductor device according to one aspect of the present invention includes a first conductive film, a first insulating film on the first conductive film, an oxide semiconductor film overlapping the first conductive film on the first insulating film, a second insulating film on the oxide semiconductor film, and a pair of second conductive films electrically connected to the oxide semiconductor film at an opening of the second insulating film. The second insulating film overlaps a region where carriers flow between the pair of second conductive films and an end portion of the oxide semiconductor film. A semiconductor device according to one aspect of the present invention includes a first conductive film, a first insulating film on the first conductive film, an oxide semiconductor film overlapping the first conductive film on the first insulating film, a second insulating film on the oxide semiconductor film, and a pair of second conductive films electrically connected to the oxide semiconductor film at an opening of the second insulating film. The second insulating film overlaps a region where carriers flow between the pair of second conductive films and an end portion of the oxide semiconductor film.

[0007] Alternatively, a semiconductor device according to one aspect of the present invention includes a first conductive film, a first insulating film on the first conductive film, and an oxide semiconductor film overlapping the first conductive film on the first insulating film. Alternatively, a semiconductor device according to one aspect of the present invention includes a first conductive film, a first insulating film on the first conductive film, and an oxide semiconductor film overlapping the first conductive film on the first insulating film. and a second insulating film on the oxide semiconductor film, and at an opening of the second insulating film a pair of second conductive films electrically connected to the oxide semiconductor film, and the second insulating film and a third insulating film containing an oxide on the pair of second conductive films, and a nitride on the third insulating film a fourth insulating film containing a substance, wherein the second insulating film overlaps with a region where carriers flow between the pair of second conductive films in the oxide semiconductor film and an end portion of the oxide semiconductor film and overlaps with an end portion of the oxide semiconductor film.

[0008] Alternatively, a semiconductor device according to an aspect of the present invention includes a first conductive film, a first insulating film on the first conductive film, and an oxide semiconductor film overlapping the first conductive film on the first insulating film a second insulating film on the oxide semiconductor film, a pair of second conductive films electrically connected to the oxide semiconductor film at a first opening of the second insulating film, and the second insulating film and a third insulating film containing an oxide on the pair of second conductive films, a fourth insulating film containing a nitride on the third insulating film, and a third conductive film overlapping the oxide semiconductor film on the fourth insulating film wherein the second insulating film overlaps with a region where carriers flow between the pair of second conductive films in the oxide semiconductor film and an end portion of the oxide semiconductor film, and the third conductive film is electrically connected to the first conductive film at a second opening of the first insulating film to the fourth insulating film and the end portion of the oxide semiconductor film overlaps with the third conductive film through the first insulating film to the fourth insulating film in a region different from a region where the pair of second conductive films are located.

[0009] Furthermore, in a semiconductor device according to an aspect of the present invention, the oxide semiconductor film contains In, Ga, and It may contain Zn.

[0010] Furthermore, in the semiconductor device according to one aspect of the present invention, the oxide semiconductor film may be a CAAC-OS film. It may be.

Advantages of the Invention

[0011] According to one aspect of the present invention, a semiconductor device having high reliability in which a backplane is formed of an oxide semiconductor film can be provided. It can be provided.

[0012] Note that, according to one aspect of the present invention, a novel semiconductor device or the like can be provided. Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc. These descriptions of effects do not prevent the existence of other effects. One aspect of the present invention does not necessarily have all of these effects. Other effects will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc. from the description in the specification, drawings, claims, etc. from the description in the specification, drawings, claims, etc. It is possible to extract other effects from the description in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0013]

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Mode for Carrying Out the Invention

[0014] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below.

[0015] Note that the source of the transistor means a source region that is a part of the semiconductor film functioning as an active layer, or a source electrode connected to the semiconductor film. Similarly, the drain of the transistor means a drain region that is a part of the semiconductor film, or a drain electrode connected to the semiconductor film. Also, the gate means a gate electrode.

[0016] 〈Configuration Example 1 of Transistor〉 FIG. 1 shows a specific configuration example of the transistor 10 included in the semiconductor device according to one aspect of the present invention. FIG. 1(A) shows a top view of the transistor 10. In FIG. 1(A), To clarify the layout of the transistor 10, various insulating films such as the gate insulating film are omitted. Further, the cross-sectional view taken along the dashed line Y1 - Y2 in the top view shown in FIG. 1(A) is shown in FIG. 1(B), and the cross-sectional view taken along the dashed line X1 - X2 is shown in FIG. 1(C).

[0017] As shown in FIG. 1, the transistor 10 includes a gate electrode and a conductive film 12 having the function as such, an insulating film 13 having the function as a gate insulating film and located on the conductive film 1 2, an oxide semiconductor film 14 overlapping the conductive film 12 on the insulating film 13, an insulating film 15 on the oxide semiconductor film 14, and a conductive film 16 and a conductive film 17 having the function as a source electrode or a drain electrode and electrically connected to the oxide semiconductor film 14 at the openings 23 and 24 of the insulating film 15, respectively. In FIG. 1, a case where the insulating film 15 is composed of an insulating film 15a and an insulating film 15b laminated in sequence is illustrated. And, the insulating film 15 overlaps the region 18 where carriers flow between the conductive film 16 and the conductive film 17 and the end portion 19 of the oxide semiconductor film 14 in the oxide semiconductor film 14. In FIG. 1, a case where all of the end portion 19 of the oxide semiconductor film 14 overlaps the insulating film 15 is illustrated, but a part of the end portion 19 of the oxide semiconductor film 14 may overlap the insulating film 15.

[0018] By the region 18 and the end portion 19 overlapping the insulating film 15, it is possible to prevent the metal contained in the conductive film 16 and the conductive film 17 from mixing into the oxide semiconductor film 14 due to etching or the like for forming the conductive film 16 and the conductive film 17. Thus, the transistor 10 caused by impurities

[0019] ​​​​​​It becomes possible to suppress the degradation of the electrical characteristics and provide a highly reliable semiconductor device.

[0020] Furthermore, in FIG. 1, an insulating film 20 and an insulating film 21 are provided so as to be sequentially laminated on the insulating film 15, the conductive film 16, and the conductive film 17. The transistor 10 may include the insulating film 20 and the insulating film 21 as its components. In FIG. 1, a multilayer insulating film 20 and a single-layer insulating film 21 are illustrated, but the insulating film 20 may be composed of a single-layer insulating film or a laminated insulating film of three or more layers layers. Also, the insulating film 21 may be composed of two or more laminated insulating films.

[0021] As the insulating film 15 and the insulating film 20, an insulating film having a higher ability to supply oxygen to the oxide semiconductor film 14 than the insulating film 21, for example, an insulating oxide film such as a silicon oxide film or a silicon oxynitride film (hereinafter referred to as an oxide insulating film) can be used. Also, as the insulating film 21, an insulating film having a higher ability to block oxygen, hydrogen, water, etc. than the insulating film 20 can be used. By sandwiching the insulating film 15 and the insulating film 20 and overlapping the insulating film 21 with the oxide semiconductor film 14, oxygen released from the insulating film 15 or the insulating film 20 can be efficiently supplied to the oxide semiconductor film 14. Also, by overlapping the insulating film 21 with the oxide semiconductor film 14, it is possible to prevent the intrusion of hydrogen, water, etc. from the outside into the oxide semiconductor film 14.

[0022] As the insulating film 21, for example, a nitride insulating film can be used. The nitride insulating film has the ability to block oxygen, hydrogen, water, etc., and in addition, has the ability to block alkali metals and alkaline earth metals. The above nitride insulating film includes a silicon nitride film, a silicon oxynitride film, a nitride ​​​​​​​Aluminum oxide films, aluminum oxynitride films, etc. can be used. The nitride insulating film can be used as the insulating film 21 to prevent not only hydrogen, water, etc. but also alkali metals and alkaline earth

[0023] metalloids from mixing into the oxide semiconductor film 14 from the outside. Also, an oxide insulating film having the ability to block oxygen, hydrogen, water, etc. may be used as the insulating film 21. Examples of the oxide insulating film having the ability to block oxygen, hydrogen, water, etc. include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc.

[0024] Therefore, by using the insulating film 15, insulating film 20, and insulating film 21 having the above configuration, the deterioration of the electrical characteristics of the transistor 10 can be further suppressed, and a more reliable semiconductor device can be provided.

[0025] Note that an oxide semiconductor (purified Oxide Semiconductor) that is purified by reducing impurities such as moisture or hydrogen that act as electron donors (donors) and further reducing oxygen vacancies has few carrier generation sources, so it can be of type i (intrinsic semiconductor) or can be made as close as possible to type i. Therefore, a transistor having a channel formation region in a highly purified oxide semiconductor film has an extremely small off-current and high reliability. And a transistor in which a channel formation region is formed in the oxide semiconductor film tends to have electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive.

[0026] Specifically, the off-current of a transistor having a channel formation region in a highly purified oxide semiconductor film is small, which can be proven by various experiments. For example, even in an element with a channel width of 1 × 1 0 6 μm and a channel length of 10 μm, when the voltage (drain voltage) between the source electrode and the drain electrode is in the range of 1 V to 10 V, the off-current is below the measurement limit of a semiconductor parameter analyzer , that is, a characteristic of 1 × 10 -13 A or less can be obtained. In this case, it can be seen that the off-current normalized by the channel width of the transistor is 100 zA / μm or less. Also, a circuit is used in which a capacitor element and a transistor are connected and the charge flowing into or flowing out of the capacitor element is controlled by the transistor to measure the off-current. In this measurement, a highly purified oxide semiconductor film is used for the channel formation region of the transistor, and the off-current of the transistor is measured from the change in the charge amount per unit time of the capacitor element. As a result, it was found that when the voltage between the source electrode and the drain electrode of the transistor is 3 V, an even smaller off-current of several tens of yA / μm can be obtained. Therefore, a transistor using a highly purified oxide semiconductor film for the channel formation region has a significantly smaller off-current than a transistor using crystalline silicon.

[0027] <Example Configuration 2 of Transistor> Next, another configuration example of the transistor 10 included in the semiconductor device according to one aspect of the present invention is shown in FIG. 2. FIG. 2(A) shows a top view of the transistor 10. Note that in FIG. 2(A), , in order to clarify the layout of the transistor 10, various insulating films such as a gate insulating film is omitted. Also, a cross-sectional view taken along the dashed line Y1 - Y2 in the top view shown in Fig. 2(A) is shown in Fig. 2(B), and a cross-sectional view taken along the dashed line X1 - X2 is shown in Fig. 2(C).

[0028] The transistor 10 shown in Fig. 2, similar to the transistor 10 shown in Fig. 1, has an insulating surface on a substrate 11, a conductive film 12 having a function as a gate electrode, and an insulating film having a function as a gate insulating film and located on the conductive film 12, an oxide semiconductor film 14 overlapping the conductive film 12 on the insulating film 13, an insulating film 15 on the oxide semiconductor film 14, a conductive film 16 having a function as a source electrode or a drain electrode and electrically connected to the oxide semiconductor film 14 at the opening 23 and the opening 24 of the insulating film 15 respectively, and a conductive film 17, and has and a conductive film 17 electrically connected to the oxide semiconductor film 14 at the opening 23 and the opening 24 of the insulating film 15 respectively.

[0029] And the transistor 10 shown in Fig. 2, similar to the transistor 10 shown in Fig. 1, has an insulating film 15 overlapping a region 18 where carriers flow between the conductive film 16 and the conductive film 17 and an end portion 19 of the oxide semiconductor film 14 in the oxide semiconductor film 14. In Fig. 2, although the case where all of the end portion 19 of the oxide semiconductor film 14 overlaps the insulating film 15 is illustrated, a part of the end portion 19 of the oxide semiconductor film 14 may overlap the insulating film 15. Note that in Fig. 2, a part of the end portion 19 of the oxide semiconductor film 14 may overlap the insulating film 15.

[0030] By the region 18 and the end portion 19 overlapping the insulating film 15, it is possible to prevent the metal contained in the conductive film 16 and the conductive film 17 from mixing into the oxide semiconductor film 14 due to etching or the like for forming the conductive film 16 and the conductive film 17. Also, by the region 18 and the end portion 19 overlapping the insulating film 15, in the etching for forming the conductive film 16 and the conductive film 17, the region 18 and the end portion 19 can be protected from being damaged. In addition, by the region 18 and the end portion 19 overlapping the insulating film 15, during the etching for forming the conductive film 16 and the conductive film 17, the region 18 and the end portion 19 The portion 19 can be prevented from being exposed to plasma. Thereby, it is possible to prevent oxygen from desorbing from the region 18 and the end portion 19 to form oxygen vacancies. Alternatively, it is possible to prevent the state in which oxygen easily desorbs from the region 18 and the end portion 19 and oxygen vacancies are easily formed. Therefore, it is possible to suppress the deterioration of the electrical characteristics of the transistor 10 caused by impurities and provide a highly reliable semiconductor device. From this, it is possible to prevent oxygen from desorbing and oxygen vacancies from being formed. Or, it is possible to prevent the state in which oxygen easily desorbs and oxygen vacancies are easily formed from the region 18 and the end portion 19. Thus, it is possible to suppress the deterioration of the electrical characteristics of the transistor 10 due to impurities and provide a highly reliable semiconductor device. Furthermore, in FIG. 2, an insulating film 20 and an insulating film 21 are provided so as to be sequentially stacked on the insulating film 15, the conductive film 16, and the conductive film 17. As the insulating film 15 and the insulating film 20, an insulating film having a higher ability to supply oxygen to the oxide semiconductor film 14 than the insulating film 21 can be used. Also, as the insulating film 21, an insulating film having a higher ability to block oxygen, hydrogen, water, etc. than the insulating film 20 can be used. With the above configuration, it is possible to further suppress the deterioration of the electrical characteristics of the transistor 10 and provide a more highly reliable semiconductor device.

[0031]

[0032] And the transistor 10 shown in FIG. 2 is different in configuration from the transistor 10 shown in FIG. 1 in that it has a conductive film 22 on the insulating film 21. The conductive film 22 is provided at a position overlapping the oxide semiconductor film 14 on the insulating film 21. Also, the conductive film 22 is electrically connected to the conductive film 12. Specifically, in FIG. 2, the conductive film 22 and the conductive film 12 are electrically connected at the opening 25 provided in the insulating film 13, the insulating film 15, the insulating film 20, and the insulating film 21.

[0033] The transistor 10 shown in FIG. 2, among the end portions of the oxide semiconductor film 14, ​​​​​​​​​​​​​An end portion that does not overlap with the film 17, in other words, an end portion located in a region different from the regions where the conductive films 16 and 17 are located, and the conductive films 12 and 22 have an overlapping configuration. The end portions of the oxide semiconductor film 14 are exposed to plasma during etching for forming the end portions, and when this occurs, chlorine radicals, fluorine radicals, etc. generated from the etching gas are likely to bond with the metal elements constituting the oxide semiconductor. Therefore, at the end portions of the oxide semiconductor film 14, oxygen that was bonded to the metal elements is likely to desorb, resulting in the formation of oxygen vacancies and making it likely to become n-type. However, in the transistor 10 shown in FIG. 2, the end portions of the oxide semiconductor film 14 that do not overlap with the conductive films 16 and 17 overlap with the conductive films 12 and 22. Therefore, by controlling the potentials of the conductive films 12 and 22, the electric field applied to the end portions can be controlled. Thus, the current flowing between the conductive films 16 and 17 through the end portions of the oxide semiconductor film 14 can be controlled by the potentials applied to the conductive films 12 and 22. Such a structure of the transistor 10 is called a Surrounded Channel (S-Channel) structure. Specifically, when potentials are applied to the conductive films 12 and 22 such that the transistor 10 is in a non-conducting state, the off-current flowing between the conductive films 16 and 17 through the end portions can be reduced. Therefore, in the transistor 10, in order to obtain a large on-current, the channel length is shortened. As a result, even if the length between the conductive films 16 and 17 at the end portions of the oxide semiconductor film 14 becomes short, the off-current of the transistor 10 can be reduced. Thus, the transistor 10 can obtain a large on-current when in the conducting state by shortening the channel length.

[0034] When potentials are applied to the conductive films 12 and 22 such that the transistor 10 is in a non-conducting state, the off-current flowing between the conductive films 16 and 17 through the end portions can be reduced. Therefore, in the transistor 10, in order to obtain a large on-current, the channel length is shortened. As a result, even if the length between the conductive films 16 and 17 at the end portions of the oxide semiconductor film 14 becomes short, the off-current of the transistor 10 can be reduced. Thus, the transistor 10 can obtain a large on-current when in the conducting state by shortening the channel length. By shortening the channel length, the transistor 10 can obtain a large on-current when in the conducting state. A drain current can be obtained, and the off-current can be suppressed to a low level when in the non-conducting state. When a potential is applied to the conductive film 12 and the conductive film 22 such that the transistor 10 is in the conducting state, the end portion 19 of the oxide semiconductor film 14 overlaps with the conductive film 12 and the conductive film 22, so that the region 18 where carriers flow in the oxide semiconductor film 14 extends not only near the interface of the oxide semiconductor film 14 close to the insulating film 15 but also over a wide range of the oxide semiconductor film 14. Therefore, the amount of carrier movement in the transistor 10 increases. As a result, the on-current of the transistor 10 can be increased and the field-effect mobility can be increased.

[0035] Note that the channel length means the distance between the conductive films 16 and 17 in the direction in which carriers move at the shortest distance within the region where the oxide semiconductor film 14 overlaps with the conductive film 12. .

[0036] <Example Configuration 3 of Transistor> Next, another configuration example of the transistor 10 included in the semiconductor device according to one aspect of the present invention is shown in FIG. 3. FIG. 3(A) shows a top view of the transistor 10. In FIG. 3(A), for clarity of the layout of the transistor 10, various insulating films such as the gate insulating film are omitted. Also, a cross-sectional view taken along the broken line Y1 - Y2 of the top view shown in FIG. 3(A) is shown in FIG. 3(B), and a cross-sectional view taken along the broken line X1 - X2 is shown in FIG. 3(C).

[0037] The transistor 10 shown in FIG. 3 does not have the insulating film 15, and an insulating film 20 is located on the oxide semiconductor film 14. At the openings 23 and 24 of the insulating film 20, the conductive film 16 In that the conductive films 17 are electrically connected to the oxide semiconductor film 14 respectively, it is different in configuration from the transistor 10 shown in FIG. 1.

[0038] Specifically, the transistor 10 shown in FIG. 3 includes, on a substrate 11 having an insulating surface, a conductive film 12 having a function as a gate electrode, an insulating film 13 having a function as a gate insulating film and located on the conductive film 12, an oxide semiconductor film 14 overlapping the conductive film 12 on the insulating film 13, an insulating film 20 on the oxide semiconductor film 14, and conductive films 16 and 17 having a function as a source or a drain and electrically connected to the oxide semiconductor film 14 at openings 23 and 24 of the insulating film 20 respectively.

[0039] And in the transistor 10 shown in FIG. 3, the insulating film 20 overlaps a region 18 where carriers flow between the conductive film 16 and the conductive film 17 and an end portion 19 of the oxide semiconductor film 14. In FIG. 3, an example is illustrated in which all of the end portion 19 of the oxide semiconductor film 14 overlaps the insulating film 20, but a part of the end portion 19 of the oxide semiconductor film 14 may overlap the insulating film 20. 0.

[0040] By the region 18 and the end portion 19 overlapping the insulating film 20, it is possible to prevent metal contained in the conductive films 16 and 17 from mixing into the oxide semiconductor film 14 due to etching or the like for forming the conductive films 16 and 17. Further, by the region 18 and the end portion 19 overlapping the insulating film 20, it is possible to prevent the region 18 and the end portion 19 from being exposed to plasma in the etching for forming the conductive films 16 and 17. Thereby, the region 18 and the end portion 19 It is possible to prevent oxygen from desorbing and forming oxygen vacancies. Alternatively, the region 18 and the end portion 19 can be prevented from being in a state where oxygen easily desorbs and oxygen vacancies are easily formed. Therefore, it is possible to suppress a decrease in the electrical characteristics of the transistor 10 due to impurities and provide a highly reliable semiconductor device.

[0041] Furthermore, in FIG. 3, an insulating film 21 is provided on the insulating film 20, the conductive film 16, and the conductive film 17. As the insulating film 20, an insulating film having a higher ability to supply oxygen to the oxide semiconductor film 14 than the insulating film 21 can be used. Also, as the insulating film 21, an insulating film having a higher ability to block oxygen, hydrogen, water, etc. than the insulating film 20 can be used. With the above configuration, it is possible to further suppress a decrease in the electrical characteristics of the transistor 10 and provide a more reliable semiconductor device.

[0042] In the transistor 10 shown in FIG. 3, by not having the insulating film 15, the number of manufacturing steps can be reduced as compared with the transistor 10 shown in FIG. 1.

[0043] Note that in the transistors 10 shown in FIGS. 1 and 2, a metal oxide film may be provided between the oxide semiconductor film 14 and the insulating film 15, the conductive film 16, and the conductive film 17. Also, in the transistors 10 shown in FIGS. 3 and 4, a metal oxide film may be provided between the oxide semiconductor film 14 and the insulating film 20, the conductive film 16, and the conductive film 17.

[0044] When the metal oxide film is an In-M-Zn oxide film, by having an element M such as Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf in an atomic ratio higher than that of In, the metal ​​​​​​​The energy gap of the oxide film can be increased and the electron affinity can be decreased. Therefore, when the difference in electron affinity from the oxide semiconductor film 14 can be controlled by the composition of the element M, there is a case. Also, since Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf is a metal element with a strong binding force with oxygen, by having these elements at an atomic ratio higher than that of In, the occurrence of oxygen deficiency is less likely.

[0045] When the metal oxide film is an In-M-Zn oxide, the atomic ratio of In and M excluding Zn and O is preferably less than 50 atomic% for In and 50 atom ic% or more, more preferably less than 25 atomic% for In and 75 atomic % or more.

[0046] When the oxide semiconductor film 14 and the metal oxide film are an In-M-Zn oxide film (M is Ti, G a, Y, Zr, La, Ce, Nd, Sn, or Hf), compared with the oxide semiconductor film 14, the atomic ratio of M (Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf) contained in the metal oxide film is large. Typically, compared with the above atoms contained in the oxide semiconductor film 14, it is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more higher in atomic ratio.

[0047] When the oxide semiconductor film 14 and the metal oxide film are an In-M-Zn oxide film (M is Ti, G a, Y, Zr, La, Ce, Nd, Sn, or Hf), for the oxide semiconductor film 14, In :M:Zn = x 1 :y 1 :z 1 [atomic ratio], for the metal oxide film, In:M:Zn = x 2 :y 2 :z2 When the atomic ratio is y 2 / x 2 it is larger than y 1 / x 1 and preferably, y 2 / x 2 is at least 1.5 times larger than y 1 / x 1 . More preferably, y 2 / x 2 is at least 2 times larger than y 1 / x 1 and even more preferably, y 2 / x 2 is at least 3 times or 4 times larger than y 1 / x 1 . At this time, in the oxide semiconductor film 14, y is x 1 or more 1 which is preferable because stable electrical characteristics can be imparted to the transistor 10 using the oxide semiconductor film 14 . However, when y exceeds 3 times x 1 the field-effect mobility of the transistor using the oxide semiconductor film 14 decreases. Therefore, it is preferable that y 1 is less than 3 times x . 1 y 1 is preferably less than 3 times x .

[0048] When the oxide semiconductor film 14 is an In-M-Zn oxide film (M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), in the target used for forming the oxide semiconductor film 14, if the atomic ratio of the metal elements is In:M:Zn = x :y :z 1 :y 1 :z 1 then 、 x 1 / y 1 is from 1 / 3 to 6, more preferably from 1 to 6, and z 1 / y 1 is from 1 / 3 It is preferably 6 or less, more preferably 1 or more and 6 or less. Note that z 1 / y 1 is 1 or more and 6 or less, so that the CAAC-OS film described later is easily formed as the oxide semiconductor film 14. Representative examples of the atomic ratio of the metal elements in the target include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, etc.

[0049] Further, when the metal oxide film is an In-M-Zn oxide film (M is Ti, Ga, Y, Zr, La, C e, Nd, Sn or Hf), in the target used to form the metal oxide film, assuming the atomic ratio of the metal elements is In:M:Zn = x 2 :y 2 :z 2 then 、 x 2 / y 2 <x 1 / y 1 and z 2 / y 2 is preferably 1 / 3 or more and 6 or less, more preferably 1 or more and 6 or less. Also, by increasing the atomic ratio of M to indium, it is possible to increase the energy gap of the metal oxide film and decrease the electron affinity. Therefore, it is preferable that y / x is 3 or more, or 4 or more. Representative examples of the atomic ratio of the metal elements in the target include In:M:Zn = 1:3:2, In:M:Zn = 1:3:4, I 2 / x 2 n:M:Zn = 1:3:5, In:M:Zn = 1:3:6, In:M:Zn = 1:4:2 n:M:Zn = 1:4:4, In:M:Zn = 1:4:5, etc.

[0050] Further, when the metal oxide film is an In-M oxide film (M is Ti, Ga, Y, Zr, La, Ce, N ​​​d, in the case of Sn or Hf), does not contain a divalent metal atom (e.g., zinc, etc.) as M By configuring it in this way, a metal oxide film that does not contain a spinel-type crystal structure can be formed Further, as the metal oxide film, for example, an In-Ga oxide film can be used As the In-Ga oxide, for example, an In-Ga metal oxide target (In:Ga =7:93) can be used to form it by a sputtering method. Further, in order to form the metal oxide film by a sputtering method using DC discharge, when In:M = x:y [atomic number ratio], y / (x + y) should be 0.96 or less, preferably 0.95 or less, for example it is good to set it to 0.93.

[0051] Note that the atomic number ratios of the oxide semiconductor film 14 and the metal oxide film each include a variation of plus or minus 40% of the above atomic number ratio as an error.

[0052] <Example Configuration 4 of Transistor> Next, another configuration example of the transistor 10 included in the semiconductor device according to one aspect of the present invention is shown in FIG. 4. FIG. 4(A) shows a top view of the transistor 10. In FIG. 4(A), for the sake of clarifying the layout of the transistor 10, various insulating films such as the gate insulating film are omitted. Also, the cross-sectional view taken along the broken line Y1 - Y2 of the top view shown in FIG. 4(A) is shown in FIG. 4(B), and the cross-sectional view taken along the broken line X1 - X2 is shown in FIG. 4(C). The transistor 10 shown in FIG. 4 is different in configuration from the transistor 10 shown in FIG. 3 in that it has a conductive film 22 on the insulating film 21. The conductive film 22 is provided at a position overlapping the oxide semiconductor film 14 on the insulating film 21. Also, the conductive film 22 is electrically connected to the conductive film 12

[0053] The transistor 10 shown in FIG. 4 is different in configuration from the transistor 10 shown in FIG. 3 in that it has a conductive film 22 on the insulating film 21. The conductive film 22 is provided at a position overlapping the oxide semiconductor film 14 on the insulating film 21. Also, the conductive film 22 is electrically connected to the conductive film 12 body film 14. This continues. Specifically, in FIG. 4, in the openings 25 provided in the insulating film 13, the insulating film 20, and the insulating film 21, the conductive film 22 and the conductive film 12 are electrically connected.

[0054] The transistor 10 shown in FIG. 4 has an S-Channel structure due to the above configuration. Therefore, even if the channel length is shortened and, as a result, the length between the conductive film 16 and the conductive film 17 at the end of the oxide semiconductor film 14 becomes shorter, the off-current of the transistor 10 can be suppressed to a small value. In addition, since the amount of carrier movement in the oxide semiconductor film 14 increases, the on-current of the transistor 10 can be increased and the field-effect mobility can be increased.

[0055] <Example Configuration of Display Device> Next, a configuration example of a display device according to an example of a semiconductor device according to one aspect of the present invention will be described.

[0056] In the display device 70 shown in FIG. 7(A), the pixel portion 71 includes a plurality of pixels 30, wirings GL represented by wirings GL1 to GLy (y is a natural number) for selecting the pixels 30 row by row, and wirings SL represented by wirings SL1 to SLx (x is a natural number) for supplying an image signal to the selected pixels 30. The input of a signal to the wiring GL is controlled by the driving circuit 72. The input of an image signal to the wiring SL is controlled by the driving circuit 73. The plurality of pixels 30 are each electrically connected to at least one of the wirings GL and at least one of the wirings SL.

[0057] Note that the types and numbers of the wirings provided in the pixel portion 71 depend on the configuration, number, and arrangement of the pixels 30. ​​​​​​​Therefore, it can be determined. Specifically, in the case of the pixel portion 71 shown in FIG. 7(A), x columns × y rows of pixels 30 are arranged in a matrix, and wirings SL1 to SLx and wirings GL1 to GLy are arranged within the pixel portion 71, which is illustrated as an example.

[0058] Note that in FIG. 7(A), the case where the drive circuits 72 and 73 are formed on the same substrate as the pixel portion 71 is illustrated, but the drive circuits 72 and 73 may be formed on a substrate different from the pixel portion 7 1.

[0059] Also, FIG. 7(B) shows, as an example, the configuration of a pixel 30 of a liquid crystal display device, which is one of the display devices. Each pixel 30 includes a liquid crystal element 74, a transistor 10P that controls the supply of an image signal to the liquid crystal element 74, and a capacitor element 31 for holding the voltage between the pixel electrode and the common electrode of the liquid crystal element 74. The liquid crystal element 74 has a pixel electrode, a common electrode, and a liquid crystal layer containing a liquid crystal material to which a voltage between the pixel electrode and the common electrode is applied.

[0060] The transistor 10P controls whether to apply the potential of the wiring SL to the pixel electrode of the liquid crystal element 74. A predetermined potential is applied to the common electrode of the liquid crystal element 74.

[0061] Hereinafter, the specific connection configuration of the transistor 10P and the liquid crystal element 74 will be described. In FIG. 7( B), the gate of the transistor 10P is electrically connected to any one of the wirings GL1 to GLy. One of the source and drain of the transistor 10P is electrically connected to any one of the wirings SL 1 to SLx, and the other of the source and drain of the transistor 10P is electrically connected to the pixel electrode of the liquid crystal element 74. ​​​​​​​

[0062] In the liquid crystal element 74, according to the value of the voltage applied between the pixel electrode and the common electrode, the alignment of the liquid crystal molecules contained in the liquid crystal layer changes, and the transmittance changes. Therefore, the liquid crystal element 74 can display gradations by controlling its transmittance according to the potential of the image signal applied to the pixel electrode. And in each of the plurality of pixels 30 included in the pixel portion 71, the gradation of the liquid crystal element 74 is adjusted according to the image signal having the image information, so that an image is displayed on the pixel portion 71. is included, and the transmittance changes. Therefore, the liquid crystal element 74 can display gradations by controlling its transmittance according to the potential of the image signal applied to the pixel electrode. And in each of the plurality of pixels 30 included in the pixel portion 71, the gradation of the liquid crystal element 74 is adjusted according to the image signal having the image information, so that an image is displayed on the pixel portion 71. is controlled, and gradations can be displayed. And in each of the plurality of pixels 30 included in the pixel portion 71, the gradation of the liquid crystal element 74 is adjusted according to the image signal having the image information, so that an image is displayed on the pixel portion 71. And in each of the plurality of pixels 30 included in the pixel portion 71, the gradation of the liquid crystal element 74 is adjusted according to the image signal having the image information, so that an image is displayed on the pixel portion 71. is adjusted according to the image signal having the image information, so that an image is displayed on the pixel portion 71. is displayed.

[0063] In FIG. 7(B), the case where one transistor 10P is used as a switch for controlling the input of the image signal to the pixel 30 in the pixel 30 is illustrated. However, a plurality of transistors functioning as one switch may be used for the pixel 30. However, a plurality of transistors functioning as one switch may be used for the pixel 30. functioning as one switch may be used for the pixel 30.

[0064] In one aspect of the present invention, it is preferable to use the transistor 10P having an extremely small off-current as a switch for controlling the input of the image signal to the pixel 30. When the off-current of the transistor 10P is small, it is possible to prevent charge from leaking through the transistor 10P. Therefore, the potential of the image signal applied to the liquid crystal element 74 and the capacitor element 31 can be more reliably held, so that a change in the transmittance of the liquid crystal element 74 due to charge leakage within one frame period can be prevented, thereby improving the quality of the displayed image. Further, when the off-current of the transistor 10P is small, charge leakage through the transistor 10P can be prevented, so that during the period of displaying a still image, the supply of the power supply potential or the signal to the drive circuit 72 and the drive circuit 73 may be stopped. With the above configuration, the pixel portion 71 is preferably used as a switch for controlling the input of the image signal to the pixel 30. When the off-current of the transistor 10P is small, charge leakage through the transistor 10P can be prevented. Therefore, the potential of the image signal applied to the liquid crystal element 74 and the capacitor element 31 can be more reliably held, so that a change in the transmittance of the liquid crystal element 74 due to charge leakage within one frame period can be prevented, thereby improving the quality of the displayed image. Further, when the off-current of the transistor 10P is small, charge leakage through the transistor 10P can be prevented, so that during the period of displaying a still image, the supply of the power supply potential or the signal to the drive circuit 72 and the drive circuit 73 may be stopped. With the above configuration, the pixel portion 71 is small, charge leakage through the transistor 10P can be prevented. Therefore, the potential of the image signal applied to the liquid crystal element 74 and the capacitor element 31 can be more reliably held, so that a change in the transmittance of the liquid crystal element 74 due to charge leakage within one frame period can be prevented, thereby improving the quality of the displayed image. Further, when the off-current of the transistor 10P is small, charge leakage through the transistor 10P can be prevented, so that during the period of displaying a still image, the supply of the power supply potential or the signal to the drive circuit 72 and the drive circuit 73 may be stopped. With the above configuration, the pixel portion 71 can be more reliably held, so that a change in the transmittance of the liquid crystal element 74 due to charge leakage within one frame period can be prevented, thereby improving the quality of the displayed image. Further, when the off-current of the transistor 10P is small, charge leakage through the transistor 10P can be prevented, so that during the period of displaying a still image, the supply of the power supply potential or the signal to the drive circuit 72 and the drive circuit 73 may be stopped. With the above configuration, the pixel portion 71 can be prevented, and thereby the quality of the displayed image can be improved. Also, when the off-current of the transistor 10P is small, charge leakage through the transistor 10P can be prevented, so that during the period of displaying a still image, the supply of the power supply potential or the signal to the drive circuit 72 and the drive circuit 73 may be stopped. With the above configuration, the pixel portion 71 When the off-current of the transistor 10P is small, charge leakage through the transistor 10P can be prevented. Therefore, during the period of displaying a still image, the supply of the power supply potential or the signal to the drive circuit 72 and the drive circuit 73 may be stopped. With the above configuration, the pixel portion 71 can be stopped. With the above configuration, the pixel portion 71 The number of times of writing the image signal can be reduced, and the power consumption of the display device can be reduced. .

[0065] For example, since a transistor including an oxide semiconductor in a semiconductor film has an extremely small off-current, it is suitable to be used as the transistor 10P.

[0066] Next, FIG. 7(C) shows another example of a pixel 30 of a light-emitting device which is one of the display devices. The pixel 30 includes a transistor 76 that controls the input of an image signal to the pixel 30, a light-emitting element 79, a transistor 77 that controls the current value supplied to the light-emitting element 79 according to the image signal, and a capacitor element 78 for holding the potential of the image signal.

[0067] The light-emitting element 79 includes elements whose luminance is controlled by current or voltage, such as an LED (Light Emitting Diode) or an OLED (Organic Light Emitting Diode). rganic Light Emitting Diode). For example, an OLED includes at least an EL layer, an anode, and a cathode. The EL layer is composed of a single layer or a plurality of layers provided between the anode and the cathode, and at least includes a light-emitting layer containing a light-emitting substance among these layers.

[0068] Note that the EL layer obtains electroluminescence by the current supplied when the potential difference between the cathode and the anode becomes equal to or higher than the threshold voltage of the light-emitting element 79. Electroluminescence includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state.

[0069] Either the anode or the cathode of the light-emitting element 79 has its potential controlled according to the image signal input to the pixel 30. Therefore, the potential thereof is controlled. Among the anode and the cathode, the electrode whose potential is controlled according to the image signal is defined as the pixel electrode, and the other electrode is defined as the common electrode. A predetermined potential is applied to the common electrode of the light-emitting element 79, and the luminance of the light-emitting element 79 is determined by the potential difference between the pixel electrode and the common electrode. Therefore, the light-emitting element 79 can display gradations by controlling its luminance according to the potential of the image signal. And in each of the plurality of pixels 30 included in the pixel portion, the gradation of the light-emitting element 79 is adjusted according to the image signal having the image information, whereby an image is displayed on the pixel portion 71. Then, the connection configuration of the transistor 76, the transistor 77, the capacitor element 78, and the light-emitting element 79 included in the pixel 30 will be described. One of the source or the drain of the transistor 76 is electrically connected to the wiring SL, and the other of the source or the drain is electrically connected to the gate of the transistor 77. The gate of the transistor 76 is electrically connected to the wiring GL. One of the source or the drain of the transistor 77 is electrically connected to the power supply line VL, and the other of the source or the drain is electrically connected to the light-emitting element 79. Specifically, the other of the source or the drain of the transistor 77 is electrically connected to either the anode or the cathode of the light-emitting element 79. A predetermined potential is applied to the other of the anode and the cathode of the light-emitting element 79. The transistor 10 shown in FIGS. 1 to 4 is used as the transistor 10P in FIG. 7(B).

[0070] Next, the connection configuration of the transistor 76, the transistor 77, the capacitor element 78, and the light-emitting element 79 included in the pixel 30 will be described.

[0071] One of the source or the drain of the transistor 76 is electrically connected to the wiring SL, and the other of the source or the drain is electrically connected to the gate of the transistor 77. The gate of the transistor 76 is electrically connected to the wiring GL. One of the source or the drain of the transistor 77 is electrically connected to the power supply line VL, and the other of the source or the drain is electrically connected to the light-emitting element 79. Specifically, the other of the source or the drain of the transistor 77 is electrically connected to either the anode or the cathode of the light-emitting element 79. A predetermined potential is applied to the other of the anode and the cathode of the light-emitting element 79. One of the source or the drain of the transistor 77 is electrically connected to the power supply line VL, and the other of the source or the drain is electrically connected to the light-emitting element 79. Specifically, the other of the source or the drain of the transistor 77 is electrically connected to either the anode or the cathode of the light-emitting element 79. A predetermined potential is applied to the other of the anode and the cathode of the light-emitting element 79. One of the source or the drain of the transistor 77 is electrically connected to the power supply line VL, and the other of the source or the drain is electrically connected to the light-emitting element 79. Specifically, the other of the source or the drain of the transistor 77 is electrically connected to either the anode or the cathode of the light-emitting element 79. A predetermined potential is applied to the other of the anode and the cathode of the light-emitting element 79.

[0072] The transistor 10 shown in FIGS. 1 to 4 is used as the transistor 10P in FIG. 7(B).​​ It can be. Further, the transistor 10 shown in FIGS. 1 to 4 can be used as the transistor 76 or the transistor 77 in FIG. 7(C).

[0073] Here, an example in the case where the light-emitting element 79 and the liquid crystal element 74 are used as the display element is shown, but one aspect of the present invention is not limited thereto.

[0074] For example, in this specification and the like, the display element, the display device which is a device having the display element, the light-emitting element, and the light-emitting device which is a device having the light-emitting element can use various forms or have various elements. As an example of the display element, the display device, the light-emitting element, or the light-emitting device, there are an EL (electroluminescence) element (EL element including organic and inorganic substances, organic EL element, inorganic EL element), an LED (white LED, red LED, green LED, blue LED, etc.), a transistor (a transistor that emits light according to current), an electron-emitting element, a liquid crystal element, an electronic ink, an electrophoretic element, a grating light valve (GLV), a plasma display panel (PDP), a display element using MEMS (micro-electro-mechanical system), a digital micromirror device (DMD), a DMS (digital micro shutter), a MIRASOL (registered trademark), an IMOD (interference modulation) element, a shutter-type MEMS display element, an optical interference-type MEMS display element, an electro-wetting element, a piezoelectric ceramic display, a carbon nanotube, etc., and those having a display medium in which contrast, luminance, reflectance, transmittance, etc. change due to electromagnetic action. As an example of a display device using an EL element, there is an EL display. ​​​​​​​​​​​​​​​There is a stomach. As an example of a display device using an electron-emitting element, there is a field emission display (FED) or a surface-conduction electron-emitter display (SED) flat panel display, etc. spray (FED) or SED type flat panel display (SED: Surface-conduction Electron-emitter Display), etc. nduction Electron-emitter Display), etc. As an example of a display device using a liquid crystal element, there are liquid crystal displays (transmissive liquid crystal displays, transflective liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays, projection liquid crystal displays), etc. As an example of a display device using an electron ink or an electrophoretic element, there is an electronic paper, etc. When realizing a transflective liquid crystal display or a reflective liquid crystal display, a part or all of the pixel electrodes may have the function of a reflective electrode. For example, a part or all of the pixel electrodes may have aluminum, silver, etc. Further, in that case, it is also possible to provide a memory circuit such as an SRAM under the reflective electrode. This can further reduce power consumption.

[0075] 〈Configuration Example 1 of Pixel〉 Next, taking a liquid crystal display device, which is one of the semiconductor devices according to an aspect of the present invention, as an example, the configuration example of the pixel 30 will be described. In FIG. 5, a top view of the pixel 30 formed on the substrate 11 together with the transistor 10 shown in FIG. 1 is shown as an example. In FIG. 5, various insulating films are omitted for clarity of the pixel layout. Also, a cross-sectional view of the liquid crystal display device formed using the element substrate having the pixel 30 shown in FIG. 5 is shown in FIG. 6. FIG. 6 corresponds to the cross-sectional view taken along the dashed line A1 - A2 in FIG. 5.

[0076] ​​​​​​​​​​The pixel 30 shown in FIGS. 5 and 6 has a transistor 10P and a capacitive element 31. Further the pixel 30 shown in FIG. 6 has a liquid crystal element 74. In FIGS. 5 and 6, the case where the transistor 10 shown in FIG. 1 is used as the transistor 10P is illustrated, but the transistor 10 shown in any of FIGS. 2 to 4 may be used as the transistor 10P.

[0077] In addition to functioning as the gate of the transistor 10P, the conductive film 12 has a function as the wiring GL shown in FIG. 7(B). Further, in addition to functioning as the source or drain of the transistor 10P, the conductive film 17 has a function as the wiring SL shown in FIG. 7(B).

[0078] Also, the pixel 30 has a metal oxide film 32 on the insulating film 13. The metal oxide film 32 is a conductive film having translucency to visible light. And on the metal oxide film 32, a conductive film 33 electrically connected to the metal oxide film 32 is provided. The conductive film 33 has a function as a wiring for supplying a predetermined potential to the metal oxide film 32.

[0079] Also, the insulating film 15 and the insulating film 20 have openings on the metal oxide film 32. Specifically, the insulating film 15 has an opening 34, and the insulating film 20 has an opening 35. And in the region where the opening 34 and the opening 35 overlap, the insulating film 21 is in contact with the metal oxide film 32.

[0080] Note that by forming an oxide semiconductor film on the insulating film 13 and forming an insulating film 21, which is a nitride insulating film, in contact with the oxide semiconductor film, the conductivity of the oxide semiconductor film can be increased. And the oxide semiconductor film with increased conductivity is used as the metal oxide film 32. ​​​​​​​​​​​This is possible. The conductivity of the oxide semiconductor film increases when the opening 35 is formed or when the insulating film 21 is formed, oxygen vacancies are formed in the oxide semiconductor film, and hydrogen diffusing from the insulating film 21 binds to the oxygen vacancies to generate donors. Specifically, the resistivity of the metal oxide film 32 is typically 1×10 Ωcm or more and less than 1×10 Ωcm, more preferably, the resistivity is 1×10 Ωcm or more and less than 1×10 -3 Ωcm. 4 Furthermore, it is preferably that the resistivity is 1×10 Ωcm or more and less than 1×10 -3 Ωcm. -1 It is preferable that the hydrogen concentration in the metal oxide film 32 is higher than that in the oxide semiconductor film 14. In the metal oxide film 32, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is 8×10 .

[0081] The metal oxide film 32 preferably has a higher hydrogen concentration than the oxide semiconductor film 14. In the metal oxide film 32, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is 8×10 atoms / cm or more, preferably 1×10 19 atoms / cm or more, more preferably 5× 3 10 20 atoms / cm 3 or more. In the oxide semiconductor film 14, the hydrogen concentration obtained by secondary ion mass spectrometry is less than 5×10 atoms / cm 20 , preferably less than 5× 3 10 atoms / cm 19 , preferably less than 1×10 3 atoms / cm ×10 18 atoms / cm 3 , preferably less than 1×10 18 atoms / cm 3 , more preferably less than 5×10 atoms / cm 17 , even more preferably less than 1×10 3 atoms / cm 16 a toms / cm 3 .

[0082] As the insulating film 21 which is a nitride insulating film, for example, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, an aluminum oxynitride film, etc. can be used.

[0083] Further, an opening 36 is provided in the insulating films 20 and 21 at a position overlapping with the conductive film 17. And on the insulating films 20 and 21, a conductive film 37 having translucency to visible light and functioning as a pixel electrode is provided. The conductive film 37 is electrically connected to the conductive film 17 at the opening 36. Also, the conductive film 37 overlaps with the metal oxide film 32 in the overlapping region of the opening 34 and the opening 35. The portion where the conductive film 37 and the metal oxide film 32 overlap with the insulating film 21 interposed therebetween functions as a capacitor element 31.

[0084] The capacitor element 31 has translucency to visible light with the metal oxide film 32 and the conductive film 37 functioning as a pair of electrodes and the insulating film 21 functioning as a dielectric film. Therefore, the capacitor element 31 has translucency to visible light, and the aperture ratio of the pixel 30 can be increased compared to a pixel with low translucency of the capacitor element to visible light. Thus, while securing the capacitance value necessary for obtaining high image quality, the light loss in the panel can be reduced, and the power consumption of the display device can be reduced.

[0085] An alignment film 38 is provided on the conductive film 37.

[0086] Also, a substrate 40 is provided so as to face the substrate 11. On the substrate 40, a shielding film 41 having a function of blocking visible light and a coloring layer 42 transmitting visible light in a specific wavelength range are provided. is provided. A resin film 43 is provided on the shielding film 41 and the coloring layer 42, and the resin film 43 is provided with a conductive film 44 having a function as a common electrode. Further, an alignment film 45 is provided on the conductive film 44.

[0087] And, a liquid crystal layer 46 containing a liquid crystal material is provided between the substrate 11 and the substrate 40 so as to be sandwiched between the alignment film 38 and the alignment film 45. The liquid crystal element 74 has a conductive film 37, a conductive film 44, and a

[0088] liquid crystal layer 46.

[0088] Note that in FIGS. 5 and 6, the case where the TN (Twisted Nematic ) mode is used as the liquid crystal driving method is illustrated, but as the liquid crystal driving method, there are the FFS (Fringe Field Switching) mode, the STN (Super Twisted Ne matic) mode, the VA (Vertical Alignment) mode, the MVA ( Multi-domain Vertical Alignment) mode, the IPS ( In-Plane Switching) mode, the OCB (Optically Com pensated Birefringence) mode, the blue phase mode, the TBA (T ransverse Bend Alignment) mode, the VA-IPS mode, the E CB (Electrically Controlled Birefringence l) mode, the PNLC (Polymer Network Liquid Crysta l) mode, guest-host mode, ASV (Advanced Super View) It is also possible to apply modes such as this one.

[0089] Also, in a liquid crystal display device, a liquid crystal material classified as, for example, a thermotropic liquid crystal or a lyotropic liquid crystal can be used for the liquid crystal layer. Alternatively, a liquid crystal material classified as, for example, a nematic liquid crystal, a smectic liquid crystal, a cholesteric liquid crystal, or a discotic liquid crystal can be used for the liquid crystal layer. Alternatively, a liquid crystal material classified as, for example, a ferroelectric liquid crystal or an antiferroelectric liquid crystal can be used for the liquid crystal layer. Alternatively, a liquid crystal material classified as, for example, a main-chain polymer liquid crystal, a side-chain polymer liquid crystal, or a composite polymer liquid crystal, or a low-molecular liquid crystal can be used for the liquid crystal layer. Alternatively, a liquid crystal material classified as, for example, a polymer-dispersed liquid crystal (PDLC) can be used for the liquid crystal layer. Also, a liquid crystal showing a blue phase without using an alignment film may be used for the liquid crystal layer. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated up. Since the blue phase appears only in a narrow temperature range, a chiral agent or an ultraviolet-curable resin is added to improve the temperature range. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response speed of 1 msec or less and is optically isotropic, so alignment treatment is unnecessary and the viewing angle dependence is small, which is preferable. can be done.

[0090] Also, a liquid crystal showing a blue phase without using an alignment film may be used for the liquid crystal layer. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated up. Since the blue phase appears only in a narrow temperature range, a chiral agent or an ultraviolet-curable resin is added to improve the temperature range. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response speed of 1 msec or less and is optically isotropic, so alignment treatment is unnecessary and the viewing angle dependence is small, which is preferable. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated up. Since the blue phase appears only in a narrow temperature range, a chiral agent or an ultraviolet-curable resin is added to improve the temperature range. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response speed of 1 msec or less and is optically isotropic, so alignment treatment is unnecessary and the viewing angle dependence is small, which is preferable. for which alignment treatment is unnecessary and the viewing angle dependence is small, which is preferable.

[0091] Also, in FIG. 6, a liquid crystal display device that displays a color image by using a color filter is Although it is illustrated, the liquid crystal display device according to one aspect of the present invention may have a configuration in which a plurality of light sources that emit light of different hues are sequentially lit to display a color image.

[0092] <Example 1 of the connection configuration between conductive films> Next, an example of the connection configuration between a conductive film 50 located in the same layer as the conductive film 12 that functions as the gate of the transistor 10 shown in FIG. 1 and a conductive film 51 located in the same layer as the source electrode or drain electrode of the transistor 10 shown in FIG. 1 will be described.

[0093] FIG. 8 shows an example of the cross-sectional structure of the transistor 10D, the conductive film 50, and the conductive film 51. In FIG. 8, the case where the transistor 10 shown in FIG. 1 is used as the transistor 10D is illustrated.

[0094] In FIG. 8, the conductive film 50 is located on the substrate 11. On the conductive film 50, an insulating film 13 and an insulating film 15 are provided so as to be laminated in sequence. And on the insulating film 15, a conductive film 51 is provided. On the insulating film 15 and the conductive film 51, an insulating film 20 and an insulating film 21 are provided so as to be laminated in sequence.

[0095] And on the conductive film 50, an opening 52 is provided in the insulating film 13, the insulating film 15, the insulating film 20, and the insulating film 21. Also, on the conductive film 51, an opening 53 is provided in the insulating film 20 and the insulating film 21. And in the opening 52 and the opening 53, a conductive film 54 is provided on the insulating film 21 so as to be electrically connected to the conductive film 50 and the conductive film 51, respectively. Therefore, the conductive film 54 is the conductive film included in the pixel 30 shown in FIGS. 5 and 6. 37 is provided in the same layer. The conductive film 37 and the conductive film 54 can be formed by etching one conductive film.

[0096] In FIG. 8, after forming openings in the insulating film 15 and the insulating film 20, the insulating film 21 is formed, and in the region overlapping with the above openings, openings are formed in the insulating film 13 and the insulating film 21, and the case of forming the opening 52 is illustrated. In one aspect of the present invention, the opening 52 may be formed in the insulating film 13, the insulating film 15, the insulating film 20, and the insulating film 21 by etching using one mask. However, when the transistor 10D shown in FIG. 8 and the conductive films 50 and 51 electrically connected thereto are formed on the same substrate 11 as the pixel 30 shown in FIGS. 5 and 6, the opening 36 shown in FIGS. 5 and 6 and the opening 52 shown in FIG. 8 will have a large difference in the total film thickness of the insulating film removed by etching. Therefore, when forming both the opening 36 and the opening 52 with one mask, there is a risk of problems such as the conductive film 17 being partially over-etched at the opening 36 or the conductive film 50 not being exposed at the opening 52 due to insufficient etching. However, as shown in the cross-sectional view of FIG. 8, after forming openings in the insulating film 15 and the insulating film 20, the insulating film 21 is formed, and in the region overlapping with the above openings, openings are formed in the insulating film 13 and the insulating film 21 to form the opening 52. When forming both the opening 36 and the opening 52 with one mask, the difference in the film thickness of the insulating film removed by etching between the opening 36 and the opening 52 is less likely to occur. Therefore, problems as described above are less likely to occur, and the yield can be increased.

[0097] ​​​​​​​​​​​​​​​​​In addition, when using the transistor 10 shown in FIG. 2 as the transistor 10D, as shown in FIG. 2 the conductive film 22 can be formed in the same layer as the conductive film 54. Therefore, the conductive film 22 and the conductive film 54 can be formed by etching a single conductive film.

[0098] <Example Configuration 2 of Pixel and Connection Configuration 2 between Conductive Films> Next, taking a liquid crystal display device, which is one of the semiconductor devices according to an aspect of the present invention, as an example, another configuration example of a pixel will be described. FIG. 9 shows a cross-sectional view of an element substrate in a pixel as an example. FIG. 9(A) shows a pixel having a transistor 10P and a capacitor element 31. FIG. 9(A) illustrates a case where the transistor 10 shown in FIG. 3 is used as the transistor 10P.

[0099] The pixel shown in FIG. 9(A) has a metal oxide film 32 on the insulating film 13. The metal oxide film 32 is a conductive film having translucency to visible light. Also, the insulating film 20 has an opening 55 on the metal oxide film 3 . And at the opening 55, the insulating film 21 is in contact with the metal oxide film 32.

[0100] The pixel shown in FIG. 9(A) has a metal oxide film 32 on the insulating film 13. The metal oxide film 32 is a conductive film having translucency to visible light. Also, the insulating film 20 has an opening 55 on the metal oxide film 3 2. And at the opening 55, the insulating film 21 is in contact with the metal oxide film 32. is in contact with the metal oxide film 32.

[0101] In addition, an opening 36 is provided in the insulating film 21 at a position overlapping the conductive film 17. And on the insulating film 21, a conductive film 37 having translucency to visible light and functioning as a pixel electrode is provided. The conductive film 37 is electrically connected to the conductive film 17 at the opening 36 . Also, the conductive film 37 overlaps the metal oxide film 32 at the opening 55 . The portion where the conductive film 37 and the metal oxide film 32 overlap with the insulating film 21 interposed therebetween functions as the capacitor element 31. functions as 31.

[0102] The capacitance element 31 includes a metal oxide film 32 and a conductive film 37 that function as a pair of electrodes, and a dielectric film, an insulating film 21, which is transparent to visible light. Therefore, the capacitance element 31 is transparent to visible light, and the aperture ratio of the pixel can be increased compared to a pixel with low transparency to visible light. Therefore, while securing the capacitance value necessary for obtaining high image quality, the light loss in the panel can be suppressed to a small level, and the power consumption of the display device can be reduced.

[0103] Note that an alignment film 38 may be provided on the conductive film 37, similar to FIG. 6.

[0104] Next, an example of the connection configuration between a conductive film 50 located in the same layer as the conductive film 12 that functions as the gate of the transistor 10 shown in FIG. 3, and a conductive film 51 located in the same layer as the conductive films 16 and 17 that function as the source electrode or drain electrode of the transistor 10 shown in FIG. 3 will be described.

[0105] FIG. 9(B) shows an example of the cross-sectional structure of the transistor 10D, the conductive film 50, and the conductive film 51. In FIG. 9(B), the case where the transistor 10 shown in FIG. 3 is used as the transistor 10D is illustrated as an example.

[0106] In FIG. 9(B), the conductive film 50 is located on the substrate 11. On the conductive film 50, an insulating film 13 and an insulating film 20 are provided so as to be laminated in this order. And on the insulating film 20, the conductive film 51 is provided. On the insulating film 20 and the conductive film 51, an insulating film 21 is provided.

[0107] Then, on the conductive film 50, openings 52 are provided in the insulating film 13, the insulating film 20, and the insulating film 21. Also, on the conductive film 51, an opening 53 is provided in the insulating film 21. Then, in the openings 52 and 53, a conductive film 54 is provided on the insulating film 21 so as to be electrically connected to the conductive film 50 and the conductive film 51, respectively. Therefore, the conductive film 54 is provided in the same layer as the conductive film 37 in FIG. 9(A). The conductive film 37 and the conductive film 54 can be formed by etching a single conductive film.

[0108] In addition, in FIG. 9(B), after forming the openings in the insulating film 13 and the insulating film 20, the insulating film 21 is formed, and in the region overlapping with the above openings, an opening is formed in the insulating film 21 to form the opening 52. This illustrates a case of forming the opening 52. In one aspect of the present invention, the opening 52 may be formed in the insulating film 13, the insulating film 20, and the insulating film 21 by etching using a single mask. However, when the conductive film 50 and the conductive film 51 electrically connected to the transistor 10D shown in FIG. 9(B) are formed on the same substrate 11 as the pixel shown in FIG. 9(A), the opening 36 shown in FIG. 9(A) and the opening 52 shown in FIG. 9(B) will have a large difference in the total film thickness of the insulating film to be removed by etching. Therefore, when forming both the opening 36 and the opening 52 with a single mask, there is a risk of problems such as the conductive film 17 being over-etched in the opening 36 or the conductive film 50 not being exposed in the opening 52 due to insufficient etching. However, as shown in the cross-sectional view of FIG. 9(B), after forming the openings in the insulating film 13 and the insulating film 20, the insulating film 21 is formed, ​​​​​In the region overlapping with the above opening, by forming an opening in the insulating film 21, the opening 52 is formed. When forming the above opening 36 and the opening 52 together with one mask, even if the thickness of the insulating film removed by etching with the opening 3 6 and the opening 52 is likely to have a difference. Therefore, the above-described problems are less likely to occur, and the yield can be increased.

[0109] When using the transistor 10 shown in FIG. 4 as the transistor 10D, as shown in FIG. 4 the conductive film 22 can be formed in the same layer as the conductive film 54. Therefore, the conductive film 22 and the conductive film 54 can be formed by etching one conductive film.

[0110] <Example of manufacturing method 1> Next, an example of a method for manufacturing a semiconductor device according to an aspect of the present invention will be described with reference to FIGS. 10 to 1 4.

[0111] As shown in FIG. 10(A), after forming a conductive film on the substrate 11, the conductive film is etched and processed (patterned) in shape by etching or the like to form the conductive film 12A and the conductive film 12B .

[0112] As the substrate 11, a substrate having heat resistance sufficient to withstand subsequent manufacturing processes is desirable , and for example, a glass substrate, a quartz substrate, a ceramic substrate, a sapphire substrate, etc. are used.

[0113] As the conductive film 12A and the conductive film 12B, a film made of a conductive material containing one or more of aluminum, titanium, chromium, cobalt, nickel , copper, yttrium, zirconium, molybdenum, ruthenium, silver, tantalum, and tungsten is laminated in one layer or two or more layers and used For example, a copper film may be formed on a tungsten nitride film as the conductive film 12A and the conductive film 12B. A laminated conductive film or a single layer tungsten film can be used. The film 12A and the conductive film 12B are a titanium film having a thickness of 10 nm and a copper film having a thickness of 200 nm. The conductive film used is obtained by stacking the above layers in order from the bottom up.

[0114] Next, as shown in FIG. 10B, an insulating film is formed so as to cover the conductive film 12A and the conductive film 12B. After forming the insulating film 13, the oxide semiconductor film 14A, the oxide semiconductor film 14B, and the The oxide semiconductor film 14A and the conductive film 12A are overlapped with each other. The oxide semiconductor film 14B is formed at a position overlapping the conductive film 12B.

[0115] The insulating film 13 may be made of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, Silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, dioxide One or more of: lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide The insulating film containing the insulating film may be used as a single layer or a stacked layer.

[0116] In this specification, an oxynitride is a material having a composition in which the oxygen content is higher than that of nitrogen. Nitrogen oxide refers to a material that contains more nitrogen than oxygen in its composition. Point.

[0117] For example, when the insulating film 13 has a two-layer structure, the first layer is a silicon nitride film and the second layer is a silicon oxide film. The second silicon oxide film can be a silicon oxynitride film. In addition, the first silicon nitride film can be a silicon oxynitride film. A silicon nitride film with a thickness of 400 nm and a silicon oxynitride film with a thickness of 50 nm are sequentially laminated and used as the insulating film 13.

[0118] It is preferable to use a silicon oxide film with a low defect density. Specifically, the spin density of spins derived from a signal with a g value of 2.0 in electron spin resonance (ESR) is 3×10 17 spins / cm 3 or less, preferably or 5×10 16 spins / cm 3 or less. It is preferable to use a silicon oxide film that has an excessive amount of oxygen. For the silicon nitride film, a silicon nitride film with a low emission amount of hydrogen and ammonia is used. The emission amounts of hydrogen and ammonia can be measured by TDS (Thermal Desorption Spectroscopy: temperature-programmed desorption gas spectrometry) analysis.

[0119] As the oxide semiconductor film 14A, the oxide semiconductor film 14B, and the oxide semiconductor film 32a, an oxide semiconductor film can be used. If the oxide semiconductor films used as the oxide semiconductor film 14A and the oxide semiconductor film 14B contain a large amount of hydrogen, a part of the hydrogen becomes a donor by combining with the oxide semiconductor and generates electrons as carriers. As a result, the threshold voltages of the transistors 10A and 10B shift in the negative direction. Therefore, after forming the oxide semiconductor film, it is preferable to perform a dehydration treatment (dehydrogenation treatment) to remove hydrogen or moisture from the oxide semiconductor film so that impurities are not contained as much as possible.

[0120] The oxide semiconductor films 14A, 14B, and 32a typically include In-Ga oxides, In-Zn oxides, and In-M-Zn oxides (where M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf). In particular, for the oxide semiconductor films 14 A and 14B, it is preferable to use In-M-Zn oxides (where M is Ti, Ga, Y, Z r, La, Ce, Nd, Sn, or Hf).

[0121] When the oxide semiconductor films 14A, 14B, and 32a are In-M- Zn oxides (where M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide preferably satisfies In≥M and Zn≥M. As such atomic ratios of the metal elements of the sputtering target, In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, and In:M:Zn = 3:1:2 are preferable. Note that the atomic ratios of the formed oxide semiconductor films 14A, 14B, and 32a each include a plus or minus 40% variation of the atomic ratio of the metal elements contained in the above sputtering target as an error. -M-Zn oxide When the oxide semiconductor films 14A, 14B, and 32a are In-M-Zn oxides, the atomic ratio of In to M excluding Zn and O is preferably such that In is 25 atomic% or more and M is less than 75 atomic%, more preferably In is 34 atomic% or more and M is less than 66 atomic%. -M-Zn oxide

[0122]

[0123] ​​​​​In addition, the oxide semiconductor films 14A and 14B have an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. Thus, by using an oxide semiconductor with a wide energy gap, the off-current of the transistors 10A and 10B can be reduced.

[0124] In addition, the thicknesses of the oxide semiconductor films 14A, 14B, and the oxide semiconductor film 32a are 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0125] In addition, as the oxide semiconductor films 14A, 14B, and the oxide semiconductor film 32a, oxide semiconductor films with a low carrier density are used. For example, the oxide semiconductor film 14 has a carrier density of 1×10 17 per cm 3 or less, preferably 1×10 15 per cm 3 or less, and more preferably 1×10 13 per cm 3 or less, more preferably 1×10 11 per cm 3 or less , particularly preferably 1×10 10 / cm 3 or less, and 1×10 -9 / cm 3 or more.

[0126] In this manufacturing method, an In-Ga-Zn oxide semiconductor film with a film thickness of 35 nm, which is formed using a target composed of a metal oxide with an atomic ratio of metal elements of In:Ga:Zn = 1:1:1, is used as the oxide semiconductor films 14A, 14B, and the oxide semiconductor film 32a.

[0127] Note that the dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film causes the oxide semiconductor film to lose its oxygen. Therefore, the oxide semiconductor film is preferably subjected to a dehydration treatment (dehydrogenation treatment) In order to compensate for oxygen vacancies increased by the above-mentioned treatment, oxygen is added to the oxide semiconductor film. In this manner, the oxide semiconductor film is preferably dehydrated by dehydration treatment (dehydrogenation treatment). The oxygen deficiency is compensated for by oxygen addition treatment, resulting in i-type ( An oxide semiconductor film that is almost intrinsic or i-type can be formed.

[0128] Next, as shown in FIG. 11(A), the oxide semiconductor film 14A, the oxide semiconductor film 14B, and The insulating film 15a and the insulating film 15b are formed on the insulating film 13 so as to cover the oxide semiconductor film 32a and the oxide semiconductor film 32b. The layers are formed in order by laminating them.

[0129] The insulating film 15b is formed continuously after the insulating film 15a is formed without exposing it to the air. After the insulating film 15a is formed, the flow rate, pressure, and high frequency of the source gas are controlled without exposing the insulating film 15a to the atmosphere. By adjusting one or more of the power and the substrate temperature, the insulating film 15b is continuously formed. The impurity concentration at the interface between the insulating film 15a and the insulating film 15b can be reduced. The oxygen contained in the insulating film 15b is transferred to the oxide semiconductor film 14A and the oxide semiconductor film 14B. It is possible to reduce the amount of oxygen vacancies in the oxide semiconductor film 14A and the oxide semiconductor film 14B. It can be reduced.

[0130] The substrate placed in the evacuated processing chamber of the plasma CVD device is heated to 180°C or higher (up to 400°C). The temperature is preferably kept at 200° C. or higher and 370° C. or lower, and the raw material gas is introduced into the processing chamber. The pressure in the processing chamber is set to be 30 Pa or more and 250 Pa or less, more preferably 40 Pa or more and 200 Pa or less, and a silicon oxide film or a silicon oxynitride film is formed as the insulating film 15a under the condition of supplying high-frequency power to the electrode provided in the processing chamber.

[0131] As the raw material gas for the insulating film 15a, it is preferable to use a depositable gas containing silicon and an oxidizing gas. Typical examples of the depositable gas containing silicon include silane, disilane, trisilane, silane fluoride, and the like. Examples of the oxidizing gas include oxygen, ozone, dinitrogen monoxide, nitrogen dioxide, and the like.

[0132] By using the above conditions, an oxide insulating film that permeates oxygen can be formed as the insulating film 15a. In addition, by providing the insulating film 15a, damage to the oxide semiconductor film 14A, the oxide semiconductor film 14B, and the oxide semiconductor film 32a can be reduced in the formation process of the insulating film 15b formed later.

[0133] Note that by setting the amount of the oxidizing gas to 100 times or more the amount of the depositable gas containing silicon, it is possible to reduce the hydrogen content in the insulating film 15a and reduce the dangling bonds contained in the insulating film 15a. Since oxygen migrating from the insulating film 15b may be trapped by the dangling bonds contained in the insulating film 15a, the oxygen contained in the insulating film 15b can be efficiently transferred to the oxide semiconductor film 14A and the oxide semiconductor film 14B, filling the oxygen vacancies contained in the oxide semiconductor film 14A and the oxide semiconductor film 14B. As a result, impurities mixed into the oxide semiconductor film 14A and the oxide semiconductor film 14B can be reduced. It is possible to reduce the hydrogen content and reduce oxygen vacancies contained in the oxide semiconductor film 14A and the oxide semiconductor film 14B. Therefore, it is possible to suppress a negative shift in the threshold voltage of the transistor 10A and the transistor 10B, and to reduce the off-current of the transistor 10A and the transistor 10B. In this manufacturing method, as the insulating film 15a, silane with a flow rate of 20 sccm and dinitrogen monoxide with a flow rate of 3000 sccm are used as source gases, the pressure in the processing chamber is 200 Pa, the substrate temperature is 350 °C, and 100 W of high-frequency power is supplied to the parallel plate electrode using a 27.12 MHz high-frequency power source. A silicon oxynitride film with a thickness of 50 nm is formed by plasma CVD. The plasma CVD apparatus is a parallel plate type plasma CVD apparatus with an electrode area of 6000 cm

[0134] When the supplied power is converted to power per unit area (power density), it is 1.6×10 W / cm Under these conditions, a silicon oxynitride film that permeates oxygen can be formed. 2 -2 2 -2 W / cm 2

[0135] As the insulating film 15b, the substrate placed in the evacuated processing chamber of the plasma CVD apparatus is maintained at 180 °C or higher and 260 °C or lower, more preferably 180 °C or higher and 230 °C or lower. / cm 2 2 2 2 2 2Under the conditions of supplying the following high-frequency power, a silicon oxide film or a silicon oxynitride film is formed.

[0136] As the film formation conditions of the insulating film 15b, by supplying the high-frequency power of the above power density in the processing chamber of the above pressure, the decomposition efficiency of the source gas in the plasma increases, the oxygen radicals increase, and the oxidation of the source gas proceeds. Therefore, the oxygen content in the insulating film 15b becomes more than the stoichiometric composition. However, when the substrate temperature is the above temperature, the bonding force between silicon and oxygen is weak so that a part of oxygen desorbs by heating. As a result, an oxide insulating film containing more oxygen than the stoichiometric composition and from which a part of oxygen desorbs by heating can be formed. Also, since the insulating film 15a is provided on the oxide semiconductor film 14A, the oxide semiconductor film 14B, and the oxide semiconductor film 32a, in the formation process of the insulating film 15b, the insulating film 15a has a function of protecting the oxide semi conductor film 14A, the oxide semiconductor film 14B, and the oxide semiconductor film 32a. As a result, while reducing the damage to the oxide semiconductor film 14A, the oxide semiconductor film 14B, and the oxide semiconductor film 3 2a, the insulating film 15b can be formed using high-frequency power with a high power density. In this manufacturing method, as the insulating film 15b, silane with a flow rate of 160 sccm and dinitrogen monoxide with a flow rate of 3000 s ccm are used as source gases, the pressure in the reaction chamber is 200 Pa, the substrate temperature is 220 °C and a silicon oxynitride film with a thickness of 200 nm is formed by plasma CVD using a 27.12 MHz high-frequency power supply to supply 1500 W of high-frequency power to the parallel plate electrodes. Note that the plasma CVD apparatus is a parallel plate type plasma CVD apparatus with an electrode area of 6000 cm 2 is

[0137] In this manufacturing method, as the insulating film 15b, silane with a flow rate of 160 sccm and dinitrogen monoxide with a flow rate of 3000 s ccm are used as source gases, the pressure in the reaction chamber is 200 Pa, the substrate temperature is 220 °C and a silicon oxynitride film with a thickness of 200 nm is formed by plasma CVD using a 27.12 MHz high-frequency power supply to supply 1500 W of high-frequency power to the parallel plate electrodes. Note that the plasma CVD apparatus is a parallel plate type plasma CVD apparatus with an electrode area of 6000 cm 2 is ​The power supplied can be converted to power per unit area (power density) of 2.5×10 - 1 W / cm 2 It is.

[0138] Next, as shown in FIG. 11B, an insulating film is formed at a position overlapping the oxide semiconductor film 14A. The openings 23A and 24A are formed in the film 15a and the insulating film 15b, respectively, and the oxide semiconductor film 14B At positions where the insulating film 15a and the insulating film 15b overlap with each other, an opening 23B and an opening 24B are formed in the insulating film 15a and the insulating film 15b. are formed, respectively.

[0139] In addition, when the openings 23A and 24A and the openings 23B and 24B are formed, As a result, a part of the oxide semiconductor film 14A and the oxide semiconductor film 14B are removed by over-etching. When etching is performed to form recesses in the oxide semiconductor film 14A and the oxide semiconductor film 14B, In addition, the openings 23A and 24A, and the openings 23B and 24B , wet etching, dry etching, or wet etching and dry etching The insulating layer 11 can be formed by a combination of etching methods.

[0140] Next, the openings 23A and 24A, and the openings 23B and 24B are covered with Then, a conductive film is formed on the insulating film 15b, and the shape of the conductive film is processed by etching or the like. As a result, the conductive film 16A and the conductive film 17A in contact with the oxide semiconductor film 14A and the oxide A conductive film 16B and a conductive film 17B are formed in contact with the semiconductor film 14B (see FIG. 12(A)). The conductive film 16A and the conductive film 17A, and the conductive film 16B and the conductive film 17B are the conductive film 1 The same conductive material as that of 2A and conductive film 12B can be used.

[0141] In the manufacturing method of this product, a titanium film with a thickness of 35 nm and a copper film with a thickness of 200 nm are laminated in order from the bottom The conductive film obtained by laminating is used as conductive films 16A and 17A, and conductive films 16B and conductive film 17B.

[0142] Next, as shown in Fig. 12(B), an insulating film 20a and an insulating layer 20b are formed on the insulating film 15b so as to cover the conductive films 16A and 17A, and the conductive films 16B and and conductive film 17B. Form.

[0143] The insulating film 20a can be formed using the same material and manufacturing method as the insulating layer 15a Yes. In addition, the insulating layer 20b can be formed using the same material and the same manufacturing method as the insulating film 15b Yes.

[0144] In the manufacturing method of this product, as the insulating film 20a, silane with a flow rate of 20 sccm and dinitrogen monoxide with a flow rate of 3000 sc cm are used as raw material gases, the pressure in the processing chamber is 200 Pa, the substrate temperature is 350 °C, and Using a 27.12 MHz high-frequency power supply, 100 W of high-frequency power is supplied to the parallel plate electrode A silicon oxynitride film with a thickness of 50 nm is formed by the plasma CVD method. The plasma The CVD apparatus is a parallel plate type plasma CVD apparatus with an electrode area of 6000 cm 2 Yes When the supplied power is converted to the power per unit area (power density), it is 1.6×10 -2 W / cm 2 Yes. Under these conditions, a silicon oxynitride film that permeates oxygen can be formed . In addition, as the insulating film 20b, silane with a flow rate of 160 sccm and dinitrogen monoxide with a flow rate of 4000 sccm are used as raw material gases, the pressure in the reaction chamber is 200 Pa, the substrate temperature is 220 °C, and 2 Using a high-frequency power supply of 7.12 MHz, 1500 W of high-frequency power was supplied to the parallel plate electrodes. By the plasma CVD method, a silicon oxynitride film with a thickness of 200 nm is formed. Note that the plasma CVD apparatus is a parallel plate type plasma CVD apparatus with an electrode area of 6000 cm 2 and, When the supplied power is converted to the power per unit area (power density), it is 2.5×10 -1 W / c m 2 .

[0145] Next, after forming the insulating film 20b, a heat treatment is performed to move the oxygen contained in the insulating film 15a or the insulating film 15b to the oxide semiconductor film 14A and the oxide semiconductor film 14B, and it is preferable to compensate for the oxygen deficiency of the oxide semiconductor film 14A and the oxide semiconductor film 14B. Note that the heat treatment may be performed as a heat treatment for dehydrogenation or dehydration of the oxide semiconductor film 14A and the oxide semiconductor film 14B. Specifically, in this manufacturing method, a heat treatment at 350 °C for 1 hour is performed in a nitrogen and oxygen atmosphere.

[0146] Through the above series of steps, the transistor 10A and the transistor 10B are formed.

[0147] Next, as shown in FIG. 13(A), the insulating film 15a, the insulating film 15b, the insulating film 20a, and the insulating film b are partially etched to form the opening 60. In the opening 60, part or all of the oxide semiconductor film 32a is exposed.

[0148] Next, the insulating film 21 and the insulating film 61 are sequentially formed on the insulating film 20b so as to cover the opening 60. The insulating film 21 is in contact with the oxide semiconductor film 32a at the opening 60.

[0149] ​​​​​​ As the insulating film 21, for example, a nitride insulating film such as a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film formed by using a CVD method or the like can be used. By forming the insulating film 21, which is a nitride insulating film, so as to be in contact with the oxide semiconductor film 32a at the opening 60, the conductivity of the oxide semiconductor film 32a can be increased. The oxide semiconductor film 32a with increased conductivity is shown as the metal oxide film 32 in FIG. 13(B).

[0150] In this manufacturing method, as the insulating film 21, silane with a flow rate of 50 sccm, nitrogen with a flow rate of 5000 sccm, and ammonia with a flow rate of 100 sccm are used as source gases, the pressure in the processing chamber is set to 100 Pa, the substrate temperature is set to 350°C, and a high-frequency power of 1000 W (power density: 1.6×10 W / cm) is supplied to the parallel plate electrode by using a 27.12 MHz high-frequency power source, and a silicon nitride film with a thickness of 100 nm is formed by plasma CVD method. -1 W / cm 2 )

[0151] It is desirable to use an insulating film for the insulating film 61 that has a lower relative permittivity and a smaller internal stress than the insulating film 21. Specifically, as the insulating film 61, for example, a silicon oxide film, a silicon oxynitride film, aluminum oxide, or the like can be used.

[0152] Note that the insulating film 61 is not necessarily provided. However, the insulating film 61 functions as a dielectric film of the pixel capacitor element together with the insulating film 21. The insulating film 21 has a tendency to have a higher relative permittivity and a larger internal stress than an oxide insulating film such as silicon oxide. Therefore, when only the insulating film 21 is used without using the insulating film 61 as the dielectric film of the capacitor element, the film of the insulating film 21 ​​​​​​​​​​​​​​If the thickness is small, the capacitance value of the capacitive element becomes too large, and it becomes difficult to write image signals to pixels. On the other hand, if the thickness of the insulating film 21 is large, When the internal stress becomes too large, it can cause problems such as a shift in the threshold voltage of a transistor. In addition, the internal stress of the insulating film 21 may deteriorate the characteristics of the semiconductor device formed by the insulating film 21. If the thickness becomes too large, the insulating film 21 becomes easily peeled off from the substrate 11, which hinders the improvement of the yield. On the other hand, the insulating film 61 using an insulating material such as silicon oxide having a lower relative dielectric constant than the insulating film 21 is When the insulating film 21 is used as a dielectric film of a capacitance element of a pixel, the dielectric constant of the dielectric film is can be adjusted to a desired value without increasing the thickness of the insulating film 21.

[0153] For example, the insulating film 61 is a silicon oxide film formed by a CVD method using an organic silane gas. As the organic silane gas, ethyl silicate (TEOS: chemical formula Si( O.C. 2 H 5 ) 4 ), tetramethylsilane (TMS: chemical formula Si(CH 3 ) 4 ), Tetramer Tylcyclotetrasiloxane (TMCTS), Octamethylcyclotetrasiloxane (O MCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC 2 H 5 ) 3 ), trisdimethylaminosilane (SiH(N(CH 3 ) 2 ) 3 ) etc. It is possible.

[0154] In this manufacturing method, the insulating film 61 is formed by a CVD method using ethyl silicate. A silicon oxide film with a thickness of 20 nm is used.

[0155] Next, as shown in FIG. 14(A), the insulating film 21 and the insulating film 61 are partially etched to form an opening 36. In the opening 36, at least a part of the conductive film 17B is exposed.

[0156] Next, as shown in FIG. 14(B), a transparent conductive film is formed on the insulating film 61, and the shape of the transparent conductive film is processed by etching or the like to form a conductive film 22A and a conductive film 37. The conductive film 22A is provided at a position overlapping the conductive film 12A with the oxide semiconductor film 14A interposed therebetween. The conductive film 37 is connected to the conductive film 17B at the opening 36.

[0157] Note that as the transparent conductive film used to form the conductive film 12A and the conductive film 37, a conductive film containing indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, zinc oxide, zinc oxide added with gallium, indium tin oxide added with silicon oxide, or the like can be used.

[0158] In this manufacturing method, a conductive film containing indium tin oxide added with silicon oxide or the like with a film thickness of 110 nm is used to form the conductive film 12A and the conductive film 37.

[0159] After forming the conductive film 12A and the conductive film 37, a heat treatment may be performed. The heat treatment may be performed, for example, at 250° C. for 1 hour in a nitrogen atmosphere.

[0160] Note that various films such as the conductive film, insulating film, oxide semiconductor film, and metal oxide film described above are sputtered.​​​​​​​​​​​ It can be formed by a patterning method or a PECVD method, but other methods, such as thermal C VD (Chemical Vapor Deposition) method may also be used for formation. . As an example of the thermal CVD method, MOCVD (Metal Organic Chemical Vapor Deposition) method or ALD (Atomic Layer Depo sition) method may be used.

[0161] Since the thermal CVD method is a film formation method that does not use plasma, it has the advantage that defects are not generated due to plasma damage.

[0162] In the thermal CVD method, a source gas and an oxidizing agent are simultaneously fed into the chamber, and the inside of the chamber is set to atmospheric pressure or under reduced pressure, and the reaction is carried out near or on the substrate to deposit a film on the substrate.

[0163] Also, in the ALD method, the inside of the chamber is set to atmospheric pressure or under reduced pressure, and source gases for the reaction are sequentially introduced into the chamber, and film formation may be carried out by repeating the order of the gas introduction. For example, by switching each switching valve (also called a high-speed valve), two or more types of source gases are sequentially supplied to the chamber, and an inert gas (such as argon or nitrogen) is introduced simultaneously with or after the first source gas so that the plurality of types of source gases do not mix, and the second source gas is introduced. When an inert gas is introduced simultaneously, the inert gas serves as a carrier gas, and an inert gas may also be introduced simultaneously when the second source gas is introduced. Also, instead of introducing an inert gas, after exhausting the first source gas by vacuum evacuation, It is also possible to introduce a second source gas. The first source gas adsorbs on the surface of the substrate to form a first layer and reacts with the subsequently introduced second source gas, so that a second layer is laminated on the first layer to form a thin film. By repeating this process a plurality of times until a desired thickness is reached while controlling the gas introduction order, a thin film with excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas introduction order is repeated, precise film thickness adjustment is possible, which is suitable for fabricating fine FETs.

[0164] Thermal CVD methods such as MOCVD and ALD can form various films such as the conductive films, insulating films, oxide semiconductor films, and metal oxide films described in this specification. For example, when forming an In-Ga-Z nO film, trimethylindium, trimethylgallium, and dimethyl zinc are used. The chemical formula of trimethylindium is In(CH 3 ) 3 . Also , the chemical formula of trimethylgallium is Ga(CH 3 ) 3 . Also, the chemical formula of dimethylzinc is Zn(CH 3 ) 2 . Also, not limited to these combinations, triethylgallium (chemical formula Ga(C H 2 H 5 ) 3 ) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C 2 H 5 ) 2 ) can be used instead of dimethylzinc .

[0165] For example, when forming a hafnium oxide film using a film forming apparatus that utilizes ALD, a solvent and A liquid containing a hafnium precursor compound (hafnium alkoxide solution, typically tetrakis dimethylamide hafnium (TDMAH)) is vaporized to obtain a source gas, and two types of gases, ozone (O 3 ), are used as the oxidant. The chemical formula of tetrakis dimethylamide hafnium is Hf[N(CH 3 ) 2 4 . Also, as other material liquids, there are tetrakis(ethyl methylamide) hafnium and the like.

[0166] For example, when forming an aluminum oxide film using a film-forming apparatus that utilizes ALD, a liquid containing a solvent and an aluminum precursor compound (such as trimethylaluminum (TMA)) is vaporized to obtain a source gas, and two types of gases, H O, are used as the oxidant. The chemical formula of trimethylaluminum is Al(CH 2 ) 3 3 . Also, as other material liquids, there are tris(di methylamide) aluminum, triisobutylaluminum, aluminum tris(2, 2,6,6-tetramethyl-3,5-heptanedionate), and the like.

[0167] For example, when forming a silicon oxide film using a film-forming apparatus that utilizes ALD, hexachlorodisilane is adsorbed on the film-forming surface, chlorine contained in the adsorbed material is removed, and radicals of an oxidizing gas (O 2 , nitrous oxide) are supplied to react with the adsorbed material.

[0168] For example, when forming a tungsten film using a film-forming apparatus that utilizes ALD, WF 6 gas and B 2 H 6 ​​​​​​​The gas is sequentially introduced repeatedly to form an initial tungsten film, and then WF 6 gas and H 2 gas are introduced simultaneously to form a tungsten film. Note that B 2 H 6 gas can be replaced with SiH 4 gas.

[0169] For example, in the case of forming an oxide semiconductor film, such as an In-Ga-ZnO film, by a film forming apparatus using ALD In(CH 3 ) 3 gas and O 3 gas are sequentially introduced repeatedly to form an In-O layer, and then Ga(CH 3 ) 3 gas and O 3 gas are introduced simultaneously to form a GaO layer formed, and then further Zn(CH 3 ) 2 and O 3 gas are introduced simultaneously to form a ZnO layer. Note that the order of these layers is not limited to this example. Also, these gases can be mixed to form a mixed compound layer such as an In-Ga-O layer or an In-Zn-O layer, a Ga-Zn-O layer. Note that O 3 gas can be replaced with H 2 O gas obtained by bubbling with an inert gas such as Ar. However, it is preferable to use O 3 gas that does not contain H. Also, instead of In(CH 3 ) 3 gas, In(C 2 H 5 ) 3 gas can be used. Also, instead of Ga(CH 3 ) 3 gas, Ga (C 2 H 5 ) 3 gas can be used. Also, instead of In(CH 3 )3 Instead of the gas, In(C 2 H 5 ) 3 gas may be used. Also, Zn(CH 3 ) 2 gas may be used.

[0170] Next, an element substrate can be formed by forming an alignment film on the conductive film 37.

[0171] The alignment film can be formed using an organic resin such as polyimide or polyvinyl alcohol, and on its surface, an alignment treatment for aligning liquid crystal molecules in a certain direction, such as rubbing, is performed. Rubbing can be carried out by rotating a roller wrapped with a cloth such as nylon so as to be in contact with the alignment film and rubbing the surface of the alignment film in a certain direction. Note that an alignment film having alignment characteristics can also be directly formed by vapor deposition using an inorganic material such as silicon oxide without performing an alignment treatment.

[0172] After forming the element substrate and the counter substrate, as shown in FIG. 6, a liquid crystal layer 46 is enclosed between the substrate 11 and the substrate 40, and a panel of the liquid crystal display device can be formed. The injection of the liquid crystal performed to form the liquid crystal layer 46 may use a dispenser type (dropping type) or a dip type (suction type).

[0173]

[0174] <Production Method Example 2> Next, another example of a method for manufacturing a semiconductor device according to an aspect of the present invention will be described with reference to FIGS. 10 and FIGS. 15 to 17.

[0174] First, after performing up to the step shown in FIG. 10(B) in the same manner as the above-described manufacturing method, in FIG. 15(A) As shown, an insulating film 20a and an insulating film 20b are sequentially laminated on the insulating film 13 so as to cover the oxide semiconductor film 14A, the oxide semiconductor film 14B, and the oxide semiconductor film 32a. It is formed in such a manner.

[0175] It is preferable that the insulating film 20b is continuously formed without exposing it to the atmosphere after the insulating film 20a is formed. After the insulating film 20a is formed, without opening to the atmosphere, by adjusting one or more of the flow rate, pressure, high-frequency power, and substrate temperature of the source gas, and continuously forming the insulating film 20b, the impurity concentration at the interface between the insulating film 20a and the insulating film 20b can be reduced, and the oxygen contained in the insulating film 20b can be moved to the oxide semiconductor film 14A and the oxide semiconductor film 14B, and the oxygen deficiency amount of the oxide semiconductor film 14A and the oxide semiconductor film 14B can be reduced.

[0176] The substrate placed in the vacuum-exhausted processing chamber of the plasma CVD apparatus is held at 180°C or higher and 400°C or lower, more preferably 200°C or higher and 370°C or lower. The source gas is introduced into the processing chamber, and the pressure in the processing chamber is set to 30 Pa or higher and 250 Pa or lower, more preferably 40 Pa or higher and 200 Pa or lower. Under the condition of supplying high-frequency power to the electrode provided in the processing chamber, a silicon oxide film or a silicon oxynitride film is formed as the insulating film 20a.

[0177] As the source gas for the insulating film 20a, it is preferable to use a depositable gas containing silicon and an oxidizing gas. Representative examples of the depositable gas containing silicon include silane, disilane, trisilane, silane fluoride, etc. Examples of the oxidizing gas include oxygen, ozone, dinitrogen monoxide, nitrogen dioxide, etc.

[0178] ​​​​​​​​​​​​​​By using the above conditions, an oxide insulating film that permeates oxygen can be formed as the insulating film 20a. Also, by providing the insulating film 20a, in the forming process of the insulating film 20b to be formed later, damage to the oxide semiconductor film 14A, the oxide semiconductor film 14B, and the oxide semiconductor film 32a can be reduced.

[0179] Note that by setting the amount of oxidizing gas with respect to the deposition gas containing silicon to 100 times or more, it is possible to reduce the hydrogen content in the insulating film 20a and reduce the dangling bonds contained in the insulating film 20a. Oxygen moving from the insulating film 20b may be captured by the dangling bonds contained in the insulating film 20a. Therefore, oxygen contained in the insulating film 20b can be efficiently moved to the oxide semiconductor film 14A and the oxide semiconductor film 14B, and the oxygen deficiencies contained in the oxide semiconductor film 14A and the oxide semiconductor film 14B can be filled. As a result, the amount of hydrogen mixed into the oxide semiconductor film 14A and the oxide semiconductor film 14B can be reduced, and the oxygen deficiencies contained in the oxide semiconductor film 14A and the oxide semiconductor film 14B can be reduced. Therefore, it is possible to suppress the negative shift of the threshold voltages of the transistor 10A and the transistor 10B, and reduce the off-current of the transistor 10A and the transistor 10B.

[0180] In this manufacturing method, as the insulating film 20a, silane with a flow rate of 20 sccm and dinitrogen monoxide with a flow rate of 3000 sccm are used as source gases, the pressure in the processing chamber is 200 Pa, the substrate temperature is 350 °C, and 100 W of high-frequency power is supplied to the parallel plate electrode using a 27.12 MHz high-frequency power supply. A silicon oxynitride film with a thickness of 50 nm is formed by the following plasma CVD method. Note that the plasma CVD apparatus is a parallel plate type plasma CVD apparatus with an electrode area of 6000 cm 2 and when the supplied power is converted to the power per unit area (power density), it is 1.6×10 W / -2 W / cm 2 . Under these conditions, a silicon oxynitride film that permeates oxygen can be formed. .

[0181] Also, as the insulating film 20b, the substrate placed in the evacuated processing chamber of the plasma CVD apparatus is held at 180°C or higher and 260°C or lower, more preferably 180°C or higher and 230°C or lower. The raw material gas is introduced into the processing chamber, and the pressure in the processing chamber is set to 100 Pa or higher and 250 Pa or lower, more preferably 100 Pa or higher and 200 Pa or lower. High-frequency power of 0. 17 W / cm or higher and 0.5 W / cm 2 or lower, more preferably 0.25 W / cm 2 or higher and 0 2 .35 W / cm or lower is supplied to the electrode provided in the processing chamber to form a silicon oxide film or a silicon oxynitride film. 2

[0182] As the film formation conditions of the insulating film 20b, by supplying the high-frequency power of the above power density in the processing chamber of the above pressure, the decomposition efficiency of the raw material gas in the plasma increases, the oxygen radicals increase, and the oxidation of the raw material gas proceeds. Therefore, the oxygen content in the insulating film 20b becomes higher than the stoichiometric composition. However, when the substrate temperature is the above temperature, the binding force between silicon and oxygen is weak. Therefore, part of the oxygen is desorbed by heating. As a result, more oxygen than the stoichiometric composition is obtained. Since the binding force between silicon and oxygen is weak, part of the oxygen is desorbed by heating. As a result, more oxygen than the stoichiometric composition is obtained. It contains a large amount of oxygen, and a part of the oxygen is desorbed by heating to form an oxide insulating film. In addition, since the insulating film 20a is provided on the oxide semiconductor film 14A, the oxide semiconductor film 14B, and the oxide semiconductor film 32a, in the step of forming the insulating film 20b, the insulating film 20 a has a function of protecting the oxide semiconductor film 14A, the oxide semiconductor film 14B, and the oxide semiconductor film 32a. As a result, while reducing the damage to the oxide semiconductor film 14A, the oxide semiconductor film 14B, and the oxide semiconductor film 32a, the insulating film 20b can be formed using high-frequency power with a high power density.

[0183] In this manufacturing method, as the insulating film 20, silane with a flow rate of 160 sccm and dinitrogen monoxide with a flow rate of 3000 sccm are used as source gases, the pressure in the processing chamber is 200 Pa, the substrate temperature is 220 °C, and a 1500 W high-frequency power is supplied to the parallel plate electrode using a 27.12 MHz high-frequency power source, and a silicon oxynitride film with a thickness of 400 nm is formed by plasma CVD. The plasma CVD apparatus is a parallel plate type plasma CVD apparatus with an electrode area of 6000 cm 2 and when the supplied power is converted to power per unit area (power density), it is 2.5×10 W / cm -1 2

[0184] Next, after forming the insulating film 20b, a heat treatment is performed to move the oxygen contained in the insulating film 20a or the insulating film 20b to the oxide semiconductor film 14A and the oxide semiconductor film 14B to compensate for the oxygen deficiency of the oxide semiconductor film 14A and the oxide semiconductor film 14B. It is preferable that the heat treatment dehydrogenates or dehydrates the oxide semiconductor film 14A and the oxide semiconductor film 14B. ​​​​The heat treatment may be performed as follows. Specifically, in this manufacturing method, a heat treatment is performed at 350°C for 1 hour in an atmosphere of nitrogen and oxygen.

[0185] Next, as shown in FIG. 15(B), openings 23A and 24A are formed in the insulating films 20a and 20b at positions overlapping the oxide semiconductor film 14A, openings 23B and 24B are formed in the insulating films 20a and 20b at positions overlapping the oxide semiconductor film 14B, and an opening 60 is formed in the insulating films 20a and 20b at a position overlapping the oxide semiconductor film 32a.

[0186] When forming the openings 23A and 24A, the openings 23B and 24B, and the opening 60, a part of the oxide semiconductor film 14A, the oxide semiconductor film 14B, and the oxide semiconductor film 32a may be etched by over-etching, and recesses may be formed in the oxide semiconductor film 14A, the oxide semiconductor film 14B, and the oxide semiconductor film 32a. The openings 23A and 24A, the openings 23B and 24B, and the opening 60 can be formed by an etching method such as a wet etching method, a dry etching method, or a combination of a wet etching method and a dry etching method.

[0187] Next, after forming a conductive film on the insulating films 20a and 20b so as to cover the openings 23A and 24A, the openings 23B and 24B, and the opening 60, the shape of the conductive film is processed by etching or the like, so that the conductive films 16A and 17A in contact with the oxide semiconductor film 14A, and the conductive films 16B and 17B in contact with the oxide semiconductor film 14B are formed. ​​​​​​​​​​​​​​to form (see Fig. 16(A)). The conductive films 16A and 17A, and the conductive films 16B and 17B can be made of the same conductive material as the conductive films 12A and 12B.

[0188] Through the above series of steps, the transistors 10A and 10B are formed.

[0189] Next, as shown in Fig. 16(B), on the insulating films 20a and 20b, the insulating films 21 and 61 are formed so as to cover the conductive films 16A and 17A, the conductive films 16B and 17B, and the opening 60 in this order. The insulating film 21 is in contact with the oxide semiconductor film 32a at the opening 60. Note that for the types, film thicknesses, and manufacturing methods of the insulating films used for the insulating films 21 and 61, reference can be made to the above-described manufacturing method described with reference to Figs. 10 to 14. By forming the insulating film 21, which is a nitride insulating film, so as to be in contact with the oxide semiconductor film 32a at the opening 60, the conductivity of the oxide semiconductor film 32a can be increased. The oxide semiconductor film 32a with increased conductivity is shown as a metal oxide film 32 in Fig. 16(B).

[0190] By forming the insulating film 21, which is a nitride insulating film, so as to be in contact with the oxide semiconductor film 32a at the opening 60, the conductivity of the oxide semiconductor film 32a can be increased. The oxide semiconductor film 32a with increased conductivity is shown as a metal oxide film 32 in Fig. 16(B). By forming the insulating film 21, which is a nitride insulating film, so as to be in contact with the oxide semiconductor film 32a at the opening 60, the conductivity of the oxide semiconductor film 32a can be increased. The oxide semiconductor film 32a with increased conductivity is shown as a metal oxide film 32 in Fig. 16(B). The oxide semiconductor film 32a with increased conductivity is shown as a metal oxide film 32 in Fig. 16(B).

[0191] Next, as shown in Fig. 17(A), by partially etching the insulating film 21 and the insulating film 61, an opening 36 is formed. At the opening 36, at least a part of the conductive film 17B is exposed.

[0192] Next, as shown in Fig. 17(B), a transparent conductive film is formed on the insulating film 61, and by processing the shape of the transparent conductive film by etching or the like, the conductive films 22A and 37 are formed. ​​​​​The conductive film 22A is provided at a position overlapping the conductive film 12A with the oxide semiconductor film 14A interposed therebetween. The conductive film 37 is connected to the conductive film 17B at the opening 36.

[0193] Note that, regarding the type, film thickness, and fabrication method of the transparent conductive film used to form the conductive films 22 and 37, reference may be made to the above-described fabrication method explained with reference to FIGS. 10 to 14. This is possible.

[0194] After forming the conductive films 22 and 37, a heat treatment may be performed. The heat treatment may be performed, for example, at 250° C. for 1 hour in a nitrogen atmosphere.

[0195] Next, an element substrate can be formed by forming an alignment film on the conductive film 37.

[0196] <Example configuration of sequential circuit> Next, an example configuration of a sequential circuit included in a semiconductor device according to one aspect of the present invention is shown in FIG. 18. .

[0197] The sequential circuit SR shown in FIG. 18 includes transistors M1 to M15 and capacitor elements C 1 and C2. In FIG. 18, among the transistors M1 to M15, all transistors other than the transistors M5 to M7 are illustrated as having an S -Channel structure. However, in one aspect of the present invention, all of the transistors M1 to M15 may have an S-Channel structure. Alternatively, any one or more of the transistors M1 to M15 may have an S-Channel structure. This is possible.

[0198] Specifically, the gates of transistor M3, transistor M12, and transistor M13 are , electrically connected to the wiring to which signal LIN is supplied. One of the source or drain of transistor M3, transistor M5, and transistor M7 is , electrically connected to the wiring to which the high-level potential VDD is supplied. The other of the source or drain of transistor M3 is , electrically connected to one of the source or drain of transistor M15. One of the source or drain of transistor M10 is electrically connected to one of the source or drain of transistor M15, and the other is electrically connected to one of the source or drain of transistor M11.

[0199] One of the source or drain of transistor M11, transistor M13, transistor M14, and transistor M2 is , electrically connected to the wiring to which potential VSS is supplied. The gates of transistor M10, transistor M11, transistor M14, and transistor M2 are , electrically connected to one of the source or drain of transistor M6, transistor M7, transistor M8 and one of the source or drain of transistor M12.

[0200] The gate of transistor M5 is electrically connected to the wiring to which signal CLK3 is supplied. The gate of transistor M6 is electrically connected to the wiring to which signal CLK2 is supplied. The other of the source or drain of transistor M5 is electrically connected to the other of the source or drain of transistor M6. The gate of transistor M7 is , electrically connected to the wiring to which signal RIN is supplied.

[0201] The gate of transistor M8 is electrically connected to the wiring to which signal INI_RES is supplied. The other of the source or drain of transistor M8 is electrically connected to the wiring to which potential VDD is supplied. The gate of transistor M4 is electrically connected to the wiring to which potential VDD is supplied. One of the source or drain of transistor M4 is electrically connected to the other of the source or drain of transistor M3. The other of the source or drain of transistor M4 is electrically connected to the gate of transistor M9. One of the source or drain of transistor M9 is electrically connected to the wiring to which signal CLK1 is supplied. The other of the source or drain of transistor M9 and one of the source or drain of transistor M14 are electrically connected to the wiring to which signal SROUT is supplied.

[0202] One of the source or drain of transistor M15 is electrically connected to the gate of transistor M1. The gate of transistor M15 is electrically connected to the wiring to which potential VDD is supplied. One of the source or drain of transistor M1 is electrically connected to the wiring to which signal PWC1 is supplied. The other of the source or drain of transistor M1 and the other of the source or drain of transistor M2 are electrically connected to the wiring to which signal OUT is supplied.

[0203] One of the pair of electrodes of capacitor C1 is electrically connected to the wiring to which potential VSS is supplied, and the other is electrically connected to the gate of transistor M2. One of the pair of electrodes of capacitor C2 One of the pair of electrodes it has is electrically connected to the source or drain of transistor M15, and the other is electrically connected to the wiring to which signal OUT is supplied. The transistor 10 shown in FIG. 2 or FIG. 4 can be used as transistor M1 to transistor M4 or transistor M8 to transistor M15. Also, the transistor 10 shown in FIG. 1 or FIG. 3 can be used as transistor M5 to transistor M7.

[0204] The transistor 10 shown in FIG. 2 or FIG. 4 can be used as transistor M1 to transistor M4 or transistor M8 to transistor M15. Also, the transistor 10 shown in FIG. 1 or FIG. 3 can be used as transistor M5 to transistor M7. The transistor 10 shown in FIG. 1 or FIG. 3 can be used as transistor M5 to transistor M7. The transistor 10 shown in FIG. 1 or FIG. 3 can be used as transistor M5 to transistor M7. The transistor 10 shown in FIG. 1 or FIG. 3 can be used as transistor M5 to transistor M7.

[0205] Next, a shift register configured by connecting a plurality of sequential circuits SR shown in FIG. 18 in multiple stages is shown as an example in FIG. 19. The shift register shown in FIG. 19 has y sequential circuits SR (y is a natural number of 2 or more). The y sequential circuits SR each have the same configuration as the sequential circuit SR shown in FIG. 18. Next, a shift register configured by connecting a plurality of sequential circuits SR shown in FIG. 18 in multiple stages is shown as an example in FIG. 19. The shift register shown in FIG. 19 has y sequential circuits SR (y is a natural number of 2 or more). The y sequential circuits SR each have the same configuration as the sequential circuit SR shown in FIG. 18. Next, a shift register configured by connecting a plurality of sequential circuits SR shown in FIG. 18 in multiple stages is shown as an example in FIG. 19. The shift register shown in FIG. 19 has y sequential circuits SR (y is a natural number of 2 or more). The y sequential circuits SR each have the same configuration as the sequential circuit SR shown in FIG. 18. Next, a shift register configured by connecting a plurality of sequential circuits SR shown in FIG. 18 in multiple stages is shown as an example in FIG. 19. The shift register shown in FIG. 19 has y sequential circuits SR (y is a natural number of 2 or more). The y sequential circuits SR each have the same configuration as the sequential circuit SR shown in FIG. 18.

[0206] Also, the shift register shown in FIG. 19 further has a sequential circuit SR of the (y + 1) - th stage and a sequential circuit SR of the (y + 2) - th stage after the y sequential circuits SR. The sequential circuit SR of the (y + 1) - th stage and the sequential circuit SR of the (y + 2) - th stage are different in configuration from the sequential circuit SR shown in FIG. 18 in that they do not have transistor M7. That is, the sequential circuit SR of the (y + 1) - th stage and the sequential circuit SR of the (y + 2) - th stage are different in configuration from the sequential circuit SR shown in FIG. 18 in that they do not have a function of controlling the supply of the potential VDD to the gate of transistor M2 according to signal RIN. Also, the shift register shown in FIG. 19 further has a sequential circuit SR of the (y + 1) - th stage and a sequential circuit SR of the (y + 2) - th stage after the y sequential circuits SR. The sequential circuit SR of the (y + 1) - th stage and the sequential circuit SR of the (y + 2) - th stage are different in configuration from the sequential circuit SR shown in FIG. 18 in that they do not have transistor M7. Also, the shift register shown in FIG. 19 further has a sequential circuit SR of the (y + 1) - th stage and a sequential circuit SR of the (y + 2) - th stage after the y sequential circuits SR. The sequential circuit SR of the (y + 1) - th stage and the sequential circuit SR of the (y + 2) - th stage are different in configuration from the sequential circuit SR shown in FIG. 18 in that they do not have transistor M7. Also, the shift register shown in FIG. 19 further has a sequential circuit SR of the (y + 1) - th stage and a sequential circuit SR of the (y + 2) - th stage after the y sequential circuits SR. The sequential circuit SR of the (y + 1) - th stage and the sequential circuit SR of the (y + 2) - th stage are different in configuration from the sequential circuit SR shown in FIG. 18 in that they do not have transistor M7. Also, the shift register shown in FIG. 19 further has a sequential circuit SR of the (y + 1) - th stage and a sequential circuit SR of the (y + 2) - th stage after the y sequential circuits SR. The sequential circuit SR of the (y + 1) - th stage and the sequential circuit SR of the (y + 2) - th stage are different in configuration from the sequential circuit SR shown in FIG. 18 in that they do not have a function of controlling the supply of the potential VDD to the gate of transistor M2 according to signal RIN. Also, the shift register shown in FIG. 19 further has a sequential circuit SR of the (y + 1) - th stage and a sequential circuit SR of the (y + 2) - th stage after the y sequential circuits SR. The sequential circuit SR of the (y + 1) - th stage and the sequential circuit SR of the (y + 2) - th stage are different in configuration from the sequential circuit SR shown in FIG. 18 in that they do not have a function of controlling the supply of the potential VDD to the gate of transistor M2 according to signal RIN. Also, the shift register shown in FIG. 19 further has a sequential circuit SR of the (y + 1) - th stage and a sequential circuit SR of the (y + 2) - th stage after the y sequential circuits SR. The sequential circuit SR of the (y + 1) - th stage and the sequential circuit SR of the (y + 2) - th stage are different in configuration from the sequential circuit SR shown in FIG. 18 in that they do not have a function of controlling the supply of the potential VDD to the gate of transistor M2 according to signal RIN.

[0207] Also, in the shift register shown in FIG. 19, the positions of the respective wirings connected to the sequential circuit SR of the j - th stage (j is a natural number less than or equal to y) are schematically shown in FIG. 20. The sequential circuit S shown in FIG. 18 Also, in the shift register shown in FIG. 19, the positions of the respective wirings connected to the sequential circuit SR of the j - th stage (j is a natural number less than or equal to y) are schematically shown in FIG. 20. The sequential circuit S shown in FIG. 18 In the case of R, the wiring T1 corresponds to the signal LIN, the wiring T2 corresponds to the signal PWC1, and the wiring T3 corresponds to the signal CLK1, the wiring T4 corresponds to the signal CLK2, and the wiring T5 corresponds to the signal CLK3, the wiring T6 corresponds to the signal INI_RES, the wiring T7 corresponds to the signal SROUT, the wiring T8 corresponds to the signal OUT, and the wiring T9 corresponds to the signal RIN.

[0208] As can be seen from FIGS. 19 and 20, in the sequential circuit SR of the j-th stage, the signal SROUT output from the wiring T7 of the sequential circuit SR of the (j - 1)-th stage is given as the signal LIN to the wiring T1. However, the level of the start pulse signal SP is given to the wiring T1 of the sequential circuit SR of the first stage. Let it be configured as such.

[0209] Also, in the sequential circuit SR shown in FIG. 18, the case where the signals CLK1 to CLK3 are given to the wirings T3 to T5 respectively is illustrated. However, in FIG. 19, necessarily, the signals CLK1 to CLK3 are not always given to the wirings T3 to T5 in the same manner as in the case of the sequential circuit SR shown in FIG. 18. That is not always the case.

[0210] Specifically, in the sequential circuit SR of the (4m + 1)-th stage, the signals CLK1 to CLK3 are given to the wirings T3 to T5 respectively. In the sequential circuit SR of the (4m + 2)-th stage, the signals CLK2 to CLK4 are given to the wirings T3 to T5 respectively. In the sequential circuit SR of the (4m + 3)-th stage, the signals CLK3, CLK4, and CLK1 are given to the wirings T3 to T5 respectively. In the sequential circuit SR of the (4m + 4)-th stage, the signals CLK4, CLK1, and CLK2 are given to the wirings T3 to T5 respectively. However, let m be any integer that satisfies the condition that the total number of sequential circuits SR is y.

[0211] Also, in the j-th sequential circuit SR, the wiring T9 receives the signal SROUT output from the wiring T 7 of the sequential circuit SR two stages later as the signal RIN. However, for the sequential circuit SR at the (y + 1)-th stage and the sequential circuit SR at the (y + 2)-th stage corresponding to the last two stages, the signal RIN is not given.

[0212] <Method for manufacturing a display device> Next, a method for manufacturing the display device 400 according to an aspect of the present invention will be described with reference to FIGS. 21 and 22.

[0213] First, an insulating film 420 is formed on a substrate 462, and a first element layer 410 is formed on the insulating film 420 (see FIG. 21(A)). The first element layer 410 is provided with semiconductor elements. Alternatively, in addition to semiconductor elements, the first element layer 410 may be provided with a display element or a part of a display element such as a pixel electrode.

[0214] The substrate 462 needs to have at least heat resistance enough to withstand subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. may be used as the substrate 4 62.

[0215] When a glass substrate is used as the substrate 462, it is preferable to form an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a silicon nitride oxide film between the substrate 462 and the insulating film 420 to prevent contamination from the glass substrate.

[0216] The insulating film 420 includes, for example, an epoxy resin, an aramid resin, an acrylic resin, a polyimide resin, Organic resin films such as fats, polyamide resins, and polyamideimide resins can be used. Among them it is also preferable to use a polyimide resin because of its high heat resistance. As the insulating film 420, for example, when using a polyimide resin, the film thickness of the polyimide resin is 3 nm or more and 20 μm or less, preferably 500 nm or more and 2 μm or less. When using a polyimide resin as the insulating film 420 it can be formed by a spin coating method, a dip coating method, a doctor blade method, or the like. For example, when using a polyimide resin as the insulating film 420, by the doctor blade method, by removing a part of the film using the polyimide resin, an insulating film 420 having a desired thickness can be obtained.

[0217] Note that the temperature in the manufacturing process of the first element layer 410 is preferably room temperature or higher and 300 °C or lower. For example, the insulating film or conductive film using an inorganic material included in the first element layer 410 is preferably formed at a film formation temperature of 150 °C or higher and 300 °C or lower, and further preferably 200 °C or higher and 270 °C or lower. Also, the insulating film or the like using an organic resin material included in the first element layer 410 is preferably formed at a film formation temperature of room temperature or higher and 100 °C or lower.

[0218] In addition, for the oxide semiconductor film of the transistor included in the first element layer 410, it is preferable to use CAAC-OS described later. When using CAAC-OS for the oxide semiconductor film of the transistor, for example, when folding the display device 400, it is difficult for cracks or the like to enter the channel formation region, and it is possible to improve the resistance to bending.

[0219] In addition, as the conductive film included in the first element layer 410, indium added with silicon oxide ​​When using a tin oxide, when the display device 400 is bent, cracks or the like are likely to occur in the conductive film, which is preferable.

[0220] Next, the first element layer 410 and the temporary support substrate 466 are adhered using the release adhesive 464. Then, the insulating film 420 and the first element layer 410 are peeled off from the substrate 462. As a result, the insulating film 420 and the first element layer 410 are provided on the side of the temporary support substrate 466 (see FIG. 21(B)).

[0221] As the temporary support substrate 466, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate, or the like can be used. Also, a plastic substrate having heat resistance that can withstand the processing temperature of the present embodiment may be used, or a flexible substrate such as a film may be used.

[0222] As the release adhesive 464, an adhesive that can be chemically or physically separated from the temporary support substrate 466 and the first element layer 410 when necessary, such as one that is soluble in water or a solvent or can be plasticized by irradiation with ultraviolet light or the like, is used.

[0223] Note that various methods can be appropriately used for the step of transferring to the temporary support substrate 466. For example, by irradiating the insulating film 420 with a laser beam 468 from the side of the substrate 462 where the insulating film 420 is not formed, that is, the lower side shown in FIG. 21(B), the insulating film 420 can be made fragile, and the substrate 462 and the insulating film 420 can be peeled off. Also, by adjusting the energy density of the irradiation of the laser beam 468, after creating separate regions with high adhesion between the substrate 462 and the insulating film 420 and low adhesion between the substrate 462 and the insulating film 420, they may be peeled off. ​​​​​

[0224] In addition, in this embodiment, although the method of peeling at the interface between the substrate 462 and the insulating film 420 has been exemplified, it is not limited thereto. For example, peeling may be performed at the interface between the insulating film 420 and the first element layer 410. In addition, a liquid may be infiltrated into the interface between the substrate 462 and the insulating film 420 to peel the insulating film 420 from the substrate 462. Alternatively, a liquid may be infiltrated into the interface between the insulating film 420 and the first element layer 410 to peel the first element layer 410 from the insulating film 420. As the above liquid, for example, water, a polar solvent, or the like can be used. By infiltrating a liquid into the interface for peeling the insulating film 420, specifically, the interface between the substrate 462 and the insulating film 420 or the interface between the insulating film 420 and the first element layer 410, it is possible to suppress the influence of static electricity or the like generated due to the peeling applied to the first element layer 410.

[0225] Next, using the adhesive layer 418, the first substrate 401 is adhered to the insulating film 420 (see FIG. 21(C)).

[0226] Next, the peeling adhesive 464 is dissolved or plasticized to remove the peeling adhesive 464 and the temporary support substrate 466 from the first element layer 410 (see FIG. 21(D)).

[0227]

[0228] It is preferable to remove the peeling adhesive 464 with water, a solvent, or the like so that the surface of the first element layer 410 is exposed.

[0229] As described above, the first element layer 410 can be formed on the first substrate 401.

[0230] Next, by a forming method similar to the steps shown in FIGS. 21(A) to 21(D), a second substrate 4 05, an adhesive layer 412 on the second substrate 405, an insulating film 440 on the adhesive layer 412, and a second element layer 411 are formed (see FIG. 22(A)).

[0231] As the insulating film 440 included in the second element layer 411, a material similar to the insulating film 420, here it can be formed using an organic resin.

[0232] Next, a sealing layer 432 is filled between the first element layer 410 and the second element layer 411, and the first element layer 410 and the second element layer 411 are bonded together (see FIG. 22(B)).

[0233] With the sealing layer 432, for example, solid sealing can be achieved. However, as the sealing layer 432 a configuration having flexibility is preferable. As the sealing layer 432, for example, glass materials such as glass frit or curable resins that cure at room temperature such as two-component mixed resins, photo-curable resins and thermosetting resins can be used as resin materials.

[0234] Thus, the display device 400 can be manufactured.

[0235] <Method for manufacturing a display device 2> Next, another manufacturing method of the display device 400 according to an aspect of the present invention will be described with reference to FIG. 23. In FIG. 23, a configuration using an inorganic insulating film as the insulating film 420 and the insulating film 440 will be described. First, a release layer 463 is formed on the substrate 462. Next, an insulating film 420 is formed on the release layer 463, and a first element layer 410 is formed on the insulating film 420 (see FIG. 23(A)).

[0236] First, a release layer 463 is formed on the substrate 462. Next, an insulating film 420 is formed on the release layer 463, and a first element layer 410 is formed on the insulating film 420 (see FIG. 23(A)).

[0237] ​​As the release layer 463, for example, tungsten, molybdenum, titanium, tantalum, niobium , nickel, cobalt, zirconium, zinc, ruthenium, rhodium, palladium, osm ium, iridium, an element selected from silicon, an alloy material containing the element, or a compound material containing the element can be included, and a single-layer or laminated structure can be used. Further, in the case of a layer containing silicon, the crystal structure of the layer containing silicon may be any of amorphous, microcrystalline, polycrystalline, and single crystal.

[0238] The release layer 463 can be formed by a sputtering method, a PECVD method, a coating method, a printing method, or the like. Note that the coating method includes a spin coating method, a droplet discharge method, and a dispensing method.

[0239] When the release layer 463 has a single-layer structure, it is preferable to form a layer containing tungsten, molybdenum, or a mixture of tungsten and molybdenum. Further, a layer containing an oxide or oxynitride of tungsten, a layer containing an oxide or oxynitride of molybdenum, or a layer containing an oxide or oxynitride of a mixture of tungsten and molybdenum may be formed. Note that the mixture of tungsten and molybdenum corresponds to, for example, an alloy of tungsten and molybdenum.

[0240] Also, when forming a laminated structure of a layer containing tungsten and a layer containing an oxide of tungsten as the release layer 463, a layer containing tungsten is formed, and an insulating layer formed of an oxide is formed on the upper layer thereof, and an oxide of tungsten is formed at the interface between the tungsten layer and the insulating layer. The layer containing may be utilized. Further, the surface of the layer containing tungsten is subjected to thermal oxidation treatment, oxygen plasma treatment, dinitrogen monoxide (N ​2 (O) Plasma treatment, treatment with a solution having a strong oxidizing power such as ozone water, etc. may be performed to form a layer containing tungsten oxide. Further, the plasma treatment and the heat treatment may be performed in an atmosphere of oxygen, nitrogen, dinitrogen monoxide alone, or a mixed gas of the gas and other gases. By the above plasma treatment and heat treatment, the surface state of the release layer 463 is changed, so that the adhesion between the release layer 463 and the insulating film 420 formed later can be controlled. It is also possible to form a layer containing tungsten oxide by performing treatment with a solution having a strong oxidizing power such as ozone water, etc. Also, the plasma treatment and the heat treatment may be performed in an atmosphere of oxygen, nitrogen, dinitrogen monoxide alone, or a mixed gas of the gas and other gases. By the above plasma treatment and heat treatment, the surface state of the release layer 463 is changed, so that the adhesion between the release layer 463 and the insulating film 420 formed later can be controlled. The plasma treatment and the heat treatment may be performed in an atmosphere of oxygen, nitrogen, dinitrogen monoxide alone, or a mixed gas of the gas and other gases. By the above plasma treatment and heat treatment, the surface state of the release layer 463 is changed, so that the adhesion between the release layer 463 and the insulating film 420 formed later can be controlled. The plasma treatment and the heat treatment may be performed in an atmosphere of oxygen, nitrogen, dinitrogen monoxide alone, or a mixed gas of the gas and other gases. By the above plasma treatment and heat treatment, the surface state of the release layer 463 is changed, so that the adhesion between the release layer 463 and the insulating film 420 formed later can be controlled. The plasma treatment and the heat treatment may be performed in an atmosphere of oxygen, nitrogen, dinitrogen monoxide alone, or a mixed gas of the gas and other gases. By the above plasma treatment and heat treatment, the surface state of the release layer 463 is changed, so that the adhesion between the release layer 463 and the insulating film 420 formed later can be controlled. The plasma treatment and the heat treatment may be performed in an atmosphere of oxygen, nitrogen, dinitrogen monoxide alone, or a mixed gas of the gas and other gases. By the above plasma treatment and heat treatment, the surface state of the release layer 463 is changed, so that the adhesion between the release layer 463 and the insulating film 420 formed later can be controlled.

[0241] For the insulating film 420, for example, an inorganic insulating film with low moisture permeability such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, etc. can be used. The above inorganic insulating film can be formed, for example, using a sputtering method, a PECVD method, etc. For the insulating film 420, for example, an inorganic insulating film with low moisture permeability such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, etc. can be used. The above inorganic insulating film can be formed, for example, using a sputtering method, a PECVD method, etc. For the insulating film 420, for example, an inorganic insulating film with low moisture permeability such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, etc. can be used. The above inorganic insulating film can be formed, for example, using a sputtering method, a PECVD method, etc.

[0242] Next, the first element layer 410 and the temporary support substrate 466 are adhered using the release adhesive 464, and the insulating film 420 and the first element layer 410 are peeled from the release layer 463. Thereby, the insulating film 420 and the first element layer 410 are provided on the side of the temporary support substrate 466 (see Fig. 23(B)). Next, the first element layer 410 and the temporary support substrate 466 are adhered using the release adhesive 464, and the insulating film 420 and the first element layer 410 are peeled from the release layer 463. Thereby, the insulating film 420 and the first element layer 410 are provided on the side of the temporary support substrate 466 (see Fig. 23(B)). Next, the first element layer 410 and the temporary support substrate 466 are adhered using the release adhesive 464, and the insulating film 420 and the first element layer 410 are peeled from the release layer 463. Thereby, the insulating film 420 and the first element layer 410 are provided on the side of the temporary support substrate 466 (see Fig. 23(B)). )

[0243] In addition, various methods can be appropriately used for the process of transferring to the temporary support substrate 466. For example, when a layer containing a metal oxide film is formed at the interface between the release layer 463 and the insulating film 420, the metal oxide film can be made fragile by crystallization, and the insulating film 420 can be peeled from the release layer 463. Also, when the release layer 463 is formed of a tungsten film, peeling may be performed while etching the tungsten film with a mixed solution of aqueous ammonia and hydrogen peroxide water. In addition, various methods can be appropriately used for the process of transferring to the temporary support substrate 466. For example, when a layer containing a metal oxide film is formed at the interface between the release layer 463 and the insulating film 420, the metal oxide film can be made fragile by crystallization, and the insulating film 420 can be peeled from the release layer 463. Also, when the release layer 463 is formed of a tungsten film, peeling may be performed while etching the tungsten film with a mixed solution of aqueous ammonia and hydrogen peroxide water. In addition, various methods can be appropriately used for the process of transferring to the temporary support substrate 466. For example, when a layer containing a metal oxide film is formed at the interface between the release layer 463 and the insulating film 420, the metal oxide film can be made fragile by crystallization, and the insulating film 420 can be peeled from the release layer 463. Also, when the release layer 463 is formed of a tungsten film, peeling may be performed while etching the tungsten film with a mixed solution of aqueous ammonia and hydrogen peroxide water. In addition, various methods can be appropriately used for the process of transferring to the temporary support substrate 466. For example, when a layer containing a metal oxide film is formed at the interface between the release layer 463 and the insulating film 420, the metal oxide film can be made fragile by crystallization, and the insulating film 420 can be peeled from the release layer 463. Also, when the release layer 463 is formed of a tungsten film, peeling may be performed while etching the tungsten film with a mixed solution of aqueous ammonia and hydrogen peroxide water. In addition, various methods can be appropriately used for the process of transferring to the temporary support substrate 466. For example, when a layer containing a metal oxide film is formed at the interface between the release layer 463 and the insulating film 420, the metal oxide film can be made fragile by crystallization, and the insulating film 420 can be peeled from the release layer 463. Also, when the release layer 463 is formed of a tungsten film, peeling may be performed while etching the tungsten film with a mixed solution of aqueous ammonia and hydrogen peroxide water.

[0244] Further, a liquid may be infiltrated into the interface between the release layer 463 and the insulating film 420 to release the insulating film 420 from the release layer 420. As the above liquid, for example, water, a polar solvent, etc. can be used. By infiltrating a liquid into the interface for releasing the insulating film 420, specifically, the interface between the release layer 463 and the insulating film 420, the influence of static electricity generated and the like due to the release applied to the first element layer 410 can be suppressed.

[0245] Next, the first substrate 401 is adhered to the insulating film 420 using the adhesive layer 418 (see Fig. 23(C) for reference).

[0246] Next, the release adhesive 464 is dissolved or plasticized, and the release adhesive 464 and the temporary support substrate 466 are removed from the first element layer 410 (see Fig. 23(D)).

[0247] Note that it is preferable to remove the release adhesive 464 with water, a solvent, etc. so that the surface of the first element layer 410 is exposed.

[0248] Thus, the first element layer 410 can be fabricated on the first substrate 401.

[0249] Next, by a forming method similar to the steps shown in Figs. 23(A) to 23(D), the second substrate 4 05, the adhesive layer 412 on the second substrate 405, the insulating film 440 on the adhesive layer 412, and the second element layer 411 are formed. Then, the sealing layer 432 is filled between the first element layer 410 and the second element layer 411, and the first element layer 410 and the second element layer 411 are bonded together.

[0250] Finally, an anisotropic conductive film and an FPC (Flexible printed cir ​​​​​​Attach the [[circuit]]. If necessary, an IC chip or the like may be mounted.

[0251] As described above, the display device 400 can be manufactured.

[0252] <Regarding the structure of the oxide semiconductor> Hereinafter, the structure of the oxide semiconductor will be described.

[0253] The oxide semiconductor can be divided into a single crystal oxide semiconductor and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor), polycrystalline oxide semiconductor, microcrystalline oxide semiconductor, amorphous oxide semiconductor, and the like.

[0254] From another perspective, the oxide semiconductor can be divided into an amorphous oxide semiconductor and other crystalline oxide semiconductors. Examples of the crystalline oxide semiconductor include a single crystal oxide semiconductor, CAAC-O S, polycrystalline oxide semiconductor, microcrystalline oxide semiconductor, and the like.

[0255] <caac-os> First, CAAC-OS will be described. Note that CAAC-OS can also be called an oxide semiconductor having CANC (C-Axis Aligned nanocrystals).

[0256] CAAC-OS is one of the oxide semiconductors having a plurality of c-axis oriented crystal parts (also referred to as pellets).

[0257] By a transmission electron microscope (TEM: Transmission Electron Microscope), when observing a composite analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of CAAC-OS, a plurality of pellets can be confirmed. On the other hand, in the high-resolution TEM image, the boundaries between the pellets, that is, the grain boundaries (also referred to as grain boundaries), cannot be clearly confirmed. Therefore, it can be said that CAAC-OS is less likely to cause a decrease in electron mobility due to grain boundaries.

[0258] Hereinafter, CAAC-OS observed by TEM will be described. FIG. 24(A) shows a high-resolution TEM image of a cross-section of CAAC-OS observed from a direction substantially parallel to the sample surface. For the observation of the high-resolution TEM image, a spherical aberration corrector function was used. The high-resolution TEM image using the spherical aberration corrector function is particularly referred to as a Cs-corrected high-resolution TEM image. The acquisition of the Cs-corrected high-resolution TEM image can be performed, for example, by using a JEOL atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

[0259] An enlarged Cs-corrected high-resolution TEM image of the region (1) in FIG. 24(A) is shown in FIG. 24(B).​​​​​​​​​​​​​​ As shown in FIG. 24(B), it can be confirmed that in the pellet, metal atoms are arranged in layers. . The arrangement of each layer of metal atoms reflects the unevenness of the surface (also referred to as the surface to be formed.) or the upper surface of the CAAC-OS film, and is parallel to the surface to be formed or the upper surface of the CAAC-OS.

[0260] As shown in FIG. 24(B), CAAC-OS has a characteristic atomic arrangement. FIG. 24(C) shows the characteristic atomic arrangement indicated by auxiliary lines. From FIGS. 24(B) and 24(C), it can be seen that the size of one pellet is about 1 nm or more and 3 nm or less, and the size of the gap generated by the inclination between pellets is about 0.8 nm. Therefore, the pellet can also be called a nanocrystal (nc).

[0261] Here, based on the Cs-corrected high-resolution TEM image, when the arrangement of the CAAC-OS pellets 6100 on the substrate 6120 is schematically shown, it has a structure like bricks or blocks stacked (see FIG. 24(D)). The location where the inclination occurs between the pellets observed in FIG. 24(C) corresponds to the region 6161 shown in FIG. 24(D).

[0262] Also, FIG. 25(A) shows the Cs-corrected high-resolution TEM image of the plane of CAAC-OS observed from a direction substantially perpendicular to the sample surface. The Cs-corrected high-resolution TEM images of the regions (1), (2), and (3) in FIG. 25(A) are shown in FIGS. 25(B), 25(C), and 25(D), respectively. From FIGS. 25(B), 25(C), and 25(D), it can be confirmed that in the pellet, metal atoms are arranged in a triangular, square, or hexagonal shape. However However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0263] Next, CA analyzed by X-ray diffraction (XRD) AC-OS will be described. For example, InGaZnO 4 CAAC-OS having the crystal of When performing a structural analysis by the out-of-plane method on, as shown in Fig. 26(A) a peak may appear at around a diffraction angle (2θ) of 31°. This peak is due to InGaZ nO 4 being attributed to the (009) plane of the crystal of, it can be confirmed that the crystal of CAAC-OS has c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface.

[0264] In the structural analysis of CAAC-OS by the out-of-plane method, in addition to the peak around 2θ of 31° a peak may also appear at around 2θ of 36°. The peak around 2θ of 36° indicates that a part of CAAC-OS contains crystals without c-axis orientation. A more preferable CAAC-OS shows a peak at around 2θ of 31° and no peak at around 2θ of 36° in the structural analysis by the out-of-plane method.

[0265] On the other hand, when performing a structural analysis by the in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis on CAAC-OS a peak appears at around 2θ of 56°. This peak is attributed to the (110) plane of the crystal of In GaZnO 4 In the case of CAAC-OS, even when the analysis ( φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed at around 56° as shown in Fig. 26(B), no distinct peak appears. In contrast and, InGaZnO 4 In the case of a single-crystalline oxide semiconductor, when 2θ is fixed near 56° and φ is scanned, six peaks attributed to a crystal plane equivalent to the (110) plane are observed as shown in Fig. 26(C). Therefore, from the structural analysis using XRD, it can be confirmed that in CAAC-OS, the orientations of the a-axis and b-axis are irregular.

[0266] Next, CAAC-OS analyzed by electron diffraction will be described. For example, for CAAC-OS having a crystal of InGaZ 4 nO, when an electron beam with a probe diameter of 300 nm is incident parallel to the sample surface, a diffraction pattern (also referred to as a limited-field transmission electron diffraction pattern) as shown in Fig. 27(A) may appear. This diffraction pattern includes spots due to the (009) plane of the InGaZnO 4 crystal. Therefore, also by electron diffraction, it can be seen that the pellets included in CAAC-OS have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. On the other hand, for the same sample, the diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicular to the sample surface is shown in Fig. 27(B). From Fig. 27 (B), a ring-shaped diffraction pattern is confirmed. Therefore, also by electron diffraction, it can be seen that the a-axis and b-axis of the pellets included in CAAC-OS do not have orientation. Note that the first ring in Fig. 27(B) is considered to be due to the (010) plane and 4 the (100) plane, etc. of the InGaZnO crystal. Also, the second ring in Fig. 27(B) is considered to be due to the (110) plane, etc.

[0267] In addition, CAAC-OS is an oxide semiconductor with a low density of defect levels. Defects in the oxide semiconductor include, for example, defects caused by impurities and oxygen deficiencies. Therefore, CAA C-OS can also be said to be an oxide semiconductor with a low impurity concentration. Also, CAAC-OS can be said to be an oxide semiconductor with few oxygen deficiencies.

[0268] Impurities contained in the oxide semiconductor may act as carrier traps or carrier generation sources. Also, oxygen deficiencies in the oxide semiconductor may act as carrier traps or become carrier generation sources by capturing hydrogen.

[0269] Note that impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metal elements. For example, elements with a stronger binding force to oxygen than the metal elements constituting the oxide semiconductor, such as silicon, deprive the oxide semiconductor of oxygen, disrupt the atomic arrangement of the oxide semiconductor, and become a factor in reducing crystallinity. Also, heavy metals such as iron and nickel, argon, carbon dioxide, etc., due to their large atomic (or molecular) radii, disrupt the atomic arrangement of the oxide semiconductor and become a factor in reducing crystallinity.

[0270] In addition, an oxide semiconductor with a low density of defect levels (few oxygen deficiencies) can lower the carrier density. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and a low density of defect levels. That is, it is likely to become a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Therefore, a transistor using CAA C-OS has electrical characteristics such that the threshold voltage becomes negative (normally It is less likely to be turned on. Also, high-purity genuine or substantially high-purity genuine acid Oxide semiconductors have few carrier traps. The charges trapped in the carrier traps of the oxide semiconductor take a long time to be released and behave like fixed charges. Therefore, transistors using oxide semiconductors with high impurity concentration and high defect level density may have unstable electrical characteristics. On the other hand, transistors using CAAC-OS have small fluctuations in electrical characteristics and are highly reliable transistors.

[0271] In addition, since CAAC-OS has a low defect level density, carriers generated by light irradiation or the like are less likely to be trapped in defect levels. Therefore, transistors using CAAC-OS have small fluctuations in electrical characteristics due to visible light or ultraviolet light irradiation.

[0272] <Microcrystalline Oxide Semiconductor> Next, the microcrystalline oxide semiconductor will be described.

[0273] The microcrystalline oxide semiconductor has a region where crystal parts can be confirmed in a high-resolution TEM image and a region where clear crystal parts cannot be confirmed. The crystal parts contained in the microcrystalline oxide semiconductor are often 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less in size. In particular, an oxide semiconductor having nanocrystals that are 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less is called nc-OS (nanocrystalline Oxide Semiconductor). For example, nc-OS may not clearly show grain boundaries in a high-resolution TEM image. Note that the nanocrystals are CAAC ​-OS may have the same origin as the pellets. Therefore, hereinafter, the crystalline part of nc-O S may be referred to as a pellet.

[0274] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Further, nc-OS has no regularity in the crystal orientation between different pellets . Therefore, no orientation is observed in the entire film. Thus, depending on the analysis method, nc-OS may not be distinguishable from an amorphous oxide semiconductor . For example, when performing structural analysis on nc-OS using an XRD apparatus that uses X-rays with a diameter larger than that of the pellets , in the analysis by the out-of-plane method, no peak indicating a crystal plane is detected . Further, when performing electron diffraction (also referred to as limited-field electron diffraction) on nc-OS using an electron beam with a probe diameter larger than that of the pellets (for example 50 nm or more), a diffraction pattern such as a halo pattern is observed . On the other hand, when performing nano-beam electron diffraction on nc-OS using an electron beam with a probe diameter close to the size of the pellets or smaller than the pellets , spots are observed . Further, when performing nano-beam electron diffraction on nc-OS , there may be cases where regions with high luminance are observed in a circular (ring-like) shape . Furthermore, there may be cases where a plurality of spots are observed within the ring-like region .

[0275] As described above, since there is no regularity in the crystal orientation between the pellets (nanocrystals), nc- OS can also be referred to as an oxide semiconductor having RANC (Random Aligned nanocrystals) , or an oxide semiconductor having NANC (Non-Aligned nanocrystals ).

[0276] nc-OS is an oxide semiconductor with higher regularity than the amorphous oxide semiconductor. Therefore, nc-OS has a lower density of defect levels than the amorphous oxide semiconductor. However, nc-OS shows no regularity in crystal orientation between different pellets. Therefore, nc-OS has a higher density of defect levels than CA-AC-OS.

[0277] <Amorphous oxide semiconductor> Next, the amorphous oxide semiconductor will be described.

[0278] An amorphous oxide semiconductor is an oxide semiconductor in which the atomic arrangement in the film is irregular and has no crystal part. An oxide semiconductor having an amorphous state such as quartz is an example.

[0279] In a high-resolution TEM image, no crystal part can be confirmed in the amorphous oxide semiconductor.

[0280] When performing structural analysis on an amorphous oxide semiconductor using an XRD apparatus, no peak indicating a crystal plane is detected in the out-of-pl ane method analysis. Also, when performing electron diffraction on an amorphous oxide semiconductor, a halo pattern is observed. Also, when performing nano-beam electron diffraction on an amorphous oxide semiconductor, no spot is observed and only a halo pattern is observed. For an amorphous oxide semiconductor, when performing nano-beam electron diffraction, no spot is observed and only a halo pattern is observed.

[0281] Regarding the amorphous structure, various views have been presented. For example, a structure having no order at all in the atomic arrangement may be called a completely amorphous structure. Sometimes, a structure having order up to the nearest-neighbor atomic distance or the second-nearest-neighbor atomic distance and having no long-range order may also be called an amorphous structure. Therefore, sometimes, a structure having order up to the nearest-neighbor atomic distance or the second-nearest-neighbor atomic distance and having no long-range order may also be called an amorphous structure. Sometimes, a structure having no order at all in the atomic arrangement may be called a completely amorphous structure (completely amorphous stru cture). Also, sometimes, a structure having order up to the nearest-neighbor atomic distance or the second-nearest-neighbor atomic distance and having no long-range order may also be called an amorphous structure. According to the strictest definition, an oxide semiconductor with even a slight degree of order in its atomic arrangement cannot be called an amorphous oxide semiconductor. Moreover, at least an oxide semiconductor with long-range order cannot be called an amorphous oxide semiconductor. Therefore, since it has a crystalline part, for example, CAAC-OS and nc-OS cannot be called amorphous oxide semiconductors or completely amorphous oxide semiconductors.

[0282] <Amorphous-like Oxide Semiconductor> In addition, an oxide semiconductor may have a structure between nc-OS and an amorphous oxide semiconductor. An oxide semiconductor having such a structure is particularly called an amorphous-like oxide semiconductor (a-li ke OS: amorphous-like Oxide Semiconductor ) .

[0283] Voids may be observed in the high-resolution TEM image of a-like OS. Also, in the high-resolution TEM image, there are regions where a crystalline part can be clearly confirmed and regions where a crystalline part cannot be confirmed.

[0284] Because it has voids, a-like OS has an unstable structure. Below, in order to show that a-like OS has a more unstable structure compared to CAAC-OS and nc-OS, structural changes due to electron irradiation are shown.

[0285] As samples for electron irradiation, a-like OS, nc-OS, and CAAC-OS are prepared. All samples are In-Ga-Zn oxides.

[0286] First, high-resolution cross-sectional TEM images of each sample are obtained. From the high-resolution cross-sectional TEM images, each sample​​​​ It can be seen that they all have crystal parts.

[0287] Note that the determination of which part is regarded as one crystal part may be performed as follows. For example, InGaZnO 4 The unit cell of the crystal has three In-O layers and six Ga-Zn-O layers, and it is known that a total of nine layers are stacked in a layered structure in the c-axis direction. The distance between these adjacent layers is about the same as the lattice plane spacing of the (009) plane (also referred to as the d value). From crystal structure analysis, the value is determined to be 0.29 nm. Therefore, a portion where the lattice fringe spacing is between 0.28 nm and 0.30 nm can be regarded as the crystal part of 4 InGaZnO. Note that the lattice fringes correspond to the a-b plane of the InGaZnO 4 crystal.

[0288] Figure 28 shows an example in which the average size of the crystal parts (from 22 to 45 locations) of each sample was investigated. . However, the length of the lattice fringes described above is regarded as the size of the crystal part. From Figure 28, it can be seen that the crystal part of a-like OS grows larger as the cumulative electron irradiation dose increases. Specifically, as shown by (1) in Figure 28, at the initial stage of observation by TEM, the crystal part (also referred to as the initial nucleus) with a size of about 1.2 nm grows to a size of about 2.6 nm when the cumulative irradiation dose is 4.2×10 8 e - / nm 2 . On the other hand, it can be seen that for nc-OS and CAAC-OS, there is no change in the size of the crystal part in the range up to a cumulative electron irradiation dose of 4.2×10 8 e - / nm 2 . Specifically, as shown in Figure As shown in (2) and (3) of 28, regardless of the cumulative irradiation dose of electrons, nc-OS and the size of the crystalline parts of CAAC-OS is about 1.4 nm and about 2.1 nm, respectively, as can be seen.

[0289] Thus, crystal growth of a-like OS may be observed by electron irradiation. On the other hand, it can be seen that nc-OS and CAAC-OS hardly show crystal growth by electron irradiation. That is, it can be seen that a-like OS has a less stable structure compared to nc-OS and CAAC-OS.

[0290] Also, because of having looseness, a-like OS has a lower density structure compared to nc-OS and CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal of the same composition. Also, the density of nc-OS and the density of CAAC-OS are 92.3% or more and less than 100% of the density of a single crystal of the same composition. An oxide semiconductor with a density less than 78% of that of a single crystal is difficult to form a film itself.

[0291] For example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of a single crystal InGaZnO having a rhombohedral crystal structure is 6.357 g / cm 4 3 Thus, for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of a-like OS is 5.0 g / cm or more and less than 5.9 g / cm 3 3 Also, for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], ​​​​​The density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 or more and less than 6.3 g / cm 3 It becomes less than.

[0292] In addition, there may be no single crystal of the same composition. In that case, by combining single crystals with different compositions in any ratio, the density corresponding to the single crystal in any composition can be estimated. The density corresponding to the single crystal of any composition may be estimated using a weighted average with respect to the ratio of combining single crystals with different compositions. However, it is preferable to estimate the density by combining as few types of single crystals as possible. As described above, the oxide semiconductor has various structures, each having various characteristics. In addition, the oxide semiconductor may be a laminated film having two or more of, for example, an amorphous oxide semiconductor, an a-like OS, a microcrystalline oxide semiconductor, and a CAAC-OS.

[0293] <Film formation model> Hereinafter, an example of the film formation model of CAAC-OS and nc-OS will be described.

[0294]

[0295]

[0296] FIG. 29(A) is a schematic diagram of a film formation chamber showing how CAAC-OS is formed by a sputtering method.

[0296] The target 6130 is adhered to the backing plate. A plurality of magnets are arranged at a position facing the target 6130 through the backing plate. A magnetic field is generated by the plurality of magnets. The sputtering method that uses the magnetic field of the magnets to increase the film formation speed is called a magnetron sputtering method.

[0297] ​ The substrate 6120 is arranged to face the target 6130, and the distance d (also referred to as the target-substrate distance (T-S distance)) is 0.01 m or more and 1 m or less, preferably 0.02 m or more and 0.5 m or less. Most of the film deposition chamber is filled with a film deposition gas (for example, a mixed gas containing oxygen, argon, or oxygen at a ratio of 5% by volume or more), and is controlled to be 0.01 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. Here, by applying a voltage equal to or higher than a certain level to the target 6130, discharge starts and plasma is confirmed. In the vicinity of the target 6130, a high-density plasma region is formed by a magnetic field. In the high-density plasma region, the film deposition gas is ionized to generate ions 6101. The ions 6101 are, for example, positive ions of oxygen (O ) or positive ions of argon (A r ). Here, the target 6130 has a polycrystalline structure having a plurality of crystal grains, and any one of the crystal grains contains a cleavage plane. FIG. 30(A) shows, as an example, the crystal structure of InGaZnO contained in the target 6130. Note that FIG. 30(A) is a structure when observing the crystal of InGaZnO + parallel to the b-axis. From FIG. 30(A), it can be seen that in two adjacent Ga-Zn-O layers, oxygen atoms in each layer are arranged at a short distance from each other. And since oxygen atoms have a negative charge, a repulsive force is generated between two adjacent G a-Zn-O layers. As a result, the crystal of InGaZnO + has a cleavage plane between two adjacent Ga-Zn-O layers.

[0298] Here, the target 6130 has a polycrystalline structure having a plurality of crystal grains, and any one of the crystal grains contains a cleavage plane. FIG. 30(A) shows, as an example, the crystal structure of InGaZnO contained in the target 6130. Note that FIG. 30(A) is a structure when observing the crystal of InGaZnO parallel to the b-axis. From FIG. 30(A), it can be seen that in two adjacent Ga-Zn-O layers, oxygen atoms in each layer are arranged at a short distance from each other. And since oxygen atoms have a negative charge, a repulsive force is generated between two adjacent G 4 a-Zn-O layers. As a result, the crystal of InGaZnO parallel to the b-axis. From FIG. 30(A), it can be seen that in two adjacent Ga-Zn-O layers, oxygen atoms in each layer are arranged at a short distance from each other. And since oxygen atoms have a negative charge, a repulsive force is generated between two adjacent G 4 a-Zn-O layers. As a result, the crystal of InGaZnO has a cleavage plane between two adjacent Ga-Zn-O layers. And since oxygen atoms have a negative charge, a repulsive force is generated between two adjacent G a-Zn-O layers. As a result, the crystal of InGaZnO has a cleavage plane between two adjacent Ga-Zn-O layers. As a result, the crystal of InGaZnO 4 has a cleavage plane between two adjacent Ga-Zn-O layers. has a cleavage plane between two adjacent Ga-Zn-O layers.

[0299] Ions 6101 generated in the high-density plasma region are accelerated toward the target 6130 by an electric field and eventually collide with the target 6130. At this time, pellets 6100a and 6100b, which are sputtered particles in the form of flat plates or pellets from the cleavage plane, are peeled off and ejected. Note that the structures of pellets 6100a and 6100b may be distorted by the impact of the collision with ions 6101. Pellet 6100a is a sputtered particle in the form of a flat plate or pellet having a triangular, for example, equilateral triangle plane. Also, pellet 6100b is a sputtered particle in the form of a flat plate or pellet having a hexagonal, for example, regular hexagonal plane. Note that flat plate or pellet-shaped sputtered particles such as pellets 6100a and 6100b are collectively referred to as pellet 6100. The planar shape of pellet 6100 is not limited to a triangle or a hexagon. For example, it may be a shape formed by combining a plurality of triangles. For example, it may be a quadrilateral (for example, a rhombus) formed by combining two triangles (for example, equilateral triangles). Pellet 6100 is determined in thickness according to the type of film-forming gas and the like. The reason will be described later, but the thickness of pellet 6100 is preferably uniform. Also, the sputtered particles are preferably in the form of non-thick pellets rather than thick dice-shaped ones. For example, pellet 6100 has a thickness of 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. Also, for example, pellet 6100 has a width of 1 nm or more and 3 nm or less, preferably 1.2 nm or more and 2.5 nm or less. Pellet 6100 is as shown in (1) in FIG. 28 above. Note that the structures of pellets 6100a and 6100b may be distorted by the impact of the collision with ions 6101. Note that the structures of pellets 6100a and 6100b may be distorted by the impact of the collision with ions 6101.

[0300] Pellet 6100a is a sputtered particle in the form of a flat plate or pellet having a triangular, for example, equilateral triangle plane. Also, pellet 6100b is a sputtered particle in the form of a flat plate or pellet having a hexagonal, for example, regular hexagonal plane. Note that flat plate or pellet-shaped sputtered particles such as pellets 6100a and 6100b are collectively referred to as pellet 6100. The planar shape of pellet 6100 is not limited to a triangle or a hexagon. For example, it may be a shape formed by combining a plurality of triangles. For example, it may be a quadrilateral (for example, a rhombus) formed by combining two triangles (for example, equilateral triangles). For example, it may be a quadrilateral (for example, a rhombus) formed by combining two triangles (for example, equilateral triangles). For example, it may be a quadrilateral (for example, a rhombus) formed by combining two triangles (for example, equilateral triangles).

[0301] Pellet 6100 is determined in thickness according to the type of film-forming gas and the like. The reason will be described later, but the thickness of pellet 6100 is preferably uniform. Also, the sputtered particles are preferably in the form of non-thick pellets rather than thick dice-shaped ones. For example, pellet 6100 has a thickness of 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. Also, for example, pellet 6100 has a width of 1 nm or more and 3 nm or less, preferably 1.2 nm or more and 2.5 nm or less. Pellet 6100 is as shown in (1) in FIG. 28 above. This corresponds to the initial nucleus described above. For example, when ions 6101 are collided with a target 61 having an In-Ga-Zn oxide 30, as shown in FIG. 30(B), a pellet 6100 having three layers of a Ga-Zn-O layer, an In-O layer, and a Ga-Zn-O layer is peeled off. FIG. 30 (C) shows the structure of the peeled pellet 6100 observed from a direction parallel to the c-axis. The pellet 6100 can also be called a sandwich structure having two Ga-Zn-O layers (bread) and an In-O layer (filling).

[0302] When the pellet 6100 passes through the plasma, its side surface may be charged negatively or positively . For example, oxygen atoms located on the side surface of the pellet 6100 may be negatively charged. When the side surfaces have the same-polarity charges, repulsion between the charges occurs, making it possible to maintain a flat-plate or pellet -like shape. When the CAAC-OS is an In-Ga-Zn oxide, oxygen atoms bonded to indium atoms may be negatively charged. Also, oxygen atoms bonded to indium atoms, gallium atoms, or zinc atoms may be negatively charged . Further, when the pellet 6100 passes through the plasma, it may grow by bonding with indium atoms, gallium atoms, zinc atoms, oxygen atoms, etc. in the plasma . The difference in size between (2) and (1) in FIG. 28 described above corresponds to the growth component in the plasma . Here, when the substrate 6120 is at about room temperature, growth of the pellet 6100 on the substrate 6120 is unlikely to occur, resulting in nc-OS (see FIG. 29(B)). Since film formation can be performed at about room temperature, even when the substrate 6120 has a large area, nc-OS film formation is possible . Yes. In order to grow the pellets 6100 in plasma, it is effective to increase the film-forming power in the sputtering method. By increasing the film-forming power, the structure of the pellets 61 00 can be stabilized. 00.

[0303] As shown in FIGS. 29(A) and 29(B), for example, the pellets 6100 fly in the plasma like a kite and flutter up onto the substrate 6120. Since the pellets 61 00 are charged, a repulsive force is generated when approaching the area where other pellets 6100 have already been deposited. Here, on the upper surface of the substrate 6120, a magnetic field (also referred to as a horizontal magnetic field) parallel to the upper surface of the substrate 6120 is generated. Also, a potential difference is applied between the substrate 6120 and the target 61 30, so a current flows from the substrate 6120 toward the target 6130. Therefore, the pellets 6100 receive a force (Lorentz force) on the upper surface of the substrate 6120 due to the action of the magnetic field and the current. This can be understood by Fleming's left-hand rule. 30. field and the current. This can be understood by Fleming's left-hand rule. left-hand rule.

[0304] The pellets 6100 are large in mass compared to a single atom. Therefore, it is important to apply some force externally to move on the upper surface of the substrate 6120. One of the forces may be the force generated by the action of the magnetic field and the current. In order to apply sufficient force to the pellets 6100 to move on the upper surface of the substrate 6120, on the upper surface of the substrate 6120, a magnetic field parallel to the upper surface of the substrate 6120 should be set in a region where the magnetic field is 10 G or more, preferably 20 G or more, more preferably 30 G or more, and even more preferably 50 G or more. Alternatively, on the upper surface of the substrate 6120, the magnetic field parallel to the upper surface of the substrate 6120 is such that on the upper surface of the substrate 6120, the magnetic field parallel to the upper surface of the substrate 6120 is 10 G or more, preferably 20 G or more, more preferably 30 G or more, and even more preferably 50 G or more. Alternatively, on the upper surface of the substrate 6120, the magnetic field parallel to the upper surface of the substrate 6120 is such that on the upper surface of the substrate 6120, a magnetic field perpendicular to the surface that is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more, and even more preferably 5 times or more, may be provided.

[0305] At this time, the magnet and the substrate 6120 move relative to each other or rotate, so that the direction of the horizontal magnetic field on the upper surface of the substrate 6120 continues to change. Therefore, on the upper surface of the substrate 6120, the pellet 6100 can receive forces from various directions and move in various directions.

[0306] Also, when the substrate 6120 is heated as shown in Fig. 29(A), the resistance due to friction or the like between the pellet 6100 and the substrate 6120 is in a low state. As a result, the pellet 6100 moves as if skimming on the upper surface of the substrate 6120. The movement of the pellet 6100 occurs with the flat plate surface facing the substrate 6120. Then, when it reaches the side surface of another pellet 6100 that has already been deposited, the side surfaces are joined. At this time, the oxygen atoms on the side surface of the pellet 6100 desorb. Since the oxygen vacancies in the CAAC-OS may be filled by the desorbed oxygen atoms, a CAAC-OS with a low defect level density is obtained. The temperature of the upper surface of the substrate 6120 may be, for example, 100°C or higher and less than 500°C, 150°C or higher and less than 450°C, or 170°C or higher and less than 400°C. Therefore, even when the substrate 6120 has a large area, film formation of CAAC-OS is possible.

[0307] In addition, when the pellet 6100 is heated on the substrate 6120, the atoms are rearranged, and the strain in the structure generated by the collision of the ions 6101 is relaxed. The strain-relaxed pellet 61 ​​​​00 becomes almost a single crystal. Since the pellet 6100 becomes almost a single crystal, even if the pellets 6100 are heated after being joined together, the expansion and contraction of the pellet 6100 itself hardly occurs. Therefore, the gap between the pellets 6100 does not widen to form defects such as grain boundaries and does not crack.

[0308] In addition, CAAC-OS is not a single crystal oxide semiconductor in the form of a single plate, but is an arrangement in which aggregates of pellets 6100 (nanocrystals) are stacked like bricks or blocks. Also, there are no grain boundaries between the pellets 6100. Therefore, even when CAAC-OS undergoes deformation such as shrinkage due to heating during film formation, heating after film formation, or bending, it is possible to relieve local stress or release strain. Therefore, it is a structure suitable for use in a flexible semiconductor device. Note that nc-OS has an arrangement in which the pellets 6100 (nanocrystals) are stacked disorderly.

[0309] When the target 6130 is sputtered with ions 6101, not only the pellets 6100 but also zinc oxide may be peeled off. Since zinc oxide is lighter than the pellet 6100, it reaches the upper surface of the substrate 6120 first. Then, a zinc oxide layer 6102 with a thickness of 0.1 nm or more and 10 nm or less, 0.2 nm or more and 5 nm or less, or 0.5 nm or more and 2 nm or less is formed. A cross-sectional schematic view is shown in FIG. 31.

[0310] As shown in FIG. 31(A), pellets 6105a and pellets 6105b are deposited on the zinc oxide layer 6102. Here, the pellet 6105a and the pellet 6105b are mutually It is arranged so that the side surfaces are in contact. Also, pellet 6105c moves so as to slide on pellet 6105 b after being deposited on it. Also, on another side surface of pellet 610 5a, a plurality of particles 6103 peeled off from the target together with zinc oxide are crystallized by heating from substrate 6120 to form region 6105a1. Note that the plurality of particles 6103 may contain oxygen, zinc, indium, gallium, and the like.

[0311] Then, as shown in Fig. 31(B), region 6105a1 is integrated with pellet 6105a to become pellet 6105a2. Also, pellet 6105c is arranged so that its side surface is in contact with another side surface of pellet 6 105b.

[0312] Next, as shown in Fig. 31(C), after pellet 6105d is further deposited on pellet 6105a2 and pellet 6105b, it moves so as to slide on pellet 6105a2 and pellet 61 05b. Also, towards another side surface of pellet 6105c, pellet 6105e further moves so as to slide on zinc oxide layer 6102.

[0313] Then, as shown in Fig. 31(D), pellet 6105d is arranged so that its side surface is in contact with the side surface of pellet 610 5a2. Also, pellet 6105e is arranged so that its side surface is in contact with another side surface of pellet 610 5c. Also, on another side surface of pellet 6105d, a plurality of particles 6103 peeled off from target 6130 together with zinc oxide are crystallized by heating from substrate 6120 to form region 6105d1.

[0314] ​As described above, the deposited pellets are arranged so as to be in contact with each other, and growth occurs on the side surfaces of the pellets, whereby CAAC-OS is formed on the substrate 6120. Therefore, the CAAC-OS has larger individual pellets than the nc-OS. The difference in size between (3) and (2) in FIG. 28 described above corresponds to the growth after deposition. In addition, when the gaps between the pellets become extremely small, one large pellet may be formed. One large pellet has a single crystal structure. For example, the size of the pellet may be 10 nm or more and 200 nm or less, 15 nm or more and 100 nm or less, or 20 nm or more and 50 nm or less as viewed from the upper surface. At this time, in the oxide semiconductor used for a fine transistor, the channel formation region may be included in one large pellet. That is, a region having a single crystal structure can be used as the channel formation region. Further, as the pellets become larger, a region having a single crystal structure may be used as the channel formation region, the source region, and the drain region of the transistor. As described above, the deposited pellets are arranged so as to be in contact with each other, and growth occurs on the side surfaces of the pellets, whereby CAAC-OS is formed on the substrate 6120. Therefore, the CAAC-OS has larger individual pellets than the nc-OS. The difference in size between (3) and (2) in FIG. 28 described above corresponds to the growth after deposition. As described above, the deposited pellets are arranged so as to be in contact with each other, and growth occurs on the side surfaces of the pellets, whereby CAAC-OS is formed on the substrate 6120. Therefore, the CAAC-OS has larger individual pellets than the nc-OS. The difference in size between (3) and (2) in FIG. 28 described above corresponds to the growth after deposition.

[0315] In addition, when the gaps between the pellets become extremely small, one large pellet may be formed. One large pellet has a single crystal structure. For example, the size of the pellet may be 10 nm or more and 200 nm or less, 15 nm or more and 100 nm or less, or 20 nm or more and 50 nm or less as viewed from the upper surface. At this time, in the oxide semiconductor used for a fine transistor, the channel formation region may be included in one large pellet. That is, a region having a single crystal structure can be used as the channel formation region. Further, as the pellets become larger, a region having a single crystal structure may be used as the channel formation region, the source region, and the drain region of the transistor. In addition, when the gaps between the pellets become extremely small, one large pellet may be formed. One large pellet has a single crystal structure. For example, the size of the pellet may be 10 nm or more and 200 nm or less, 15 nm or more and 100 nm or less, or 20 nm or more and 50 nm or less as viewed from the upper surface. At this time, in the oxide semiconductor used for a fine transistor, the channel formation region may be included in one large pellet. That is, a region having a single crystal structure can be used as the channel formation region. Further, as the pellets become larger, a region having a single crystal structure may be used as the channel formation region, the source region, and the drain region of the transistor. In addition, when the gaps between the pellets become extremely small, one large pellet may be formed. One large pellet has a single crystal structure. For example, the size of the pellet may be 10 nm or more and 200 nm or less, 15 nm or more and 100 nm or less, or 20 nm or more and 50 nm or less as viewed from the upper surface. At this time, in the oxide semiconductor used for a fine transistor, the channel formation region may be included in one large pellet. That is, a region having a single crystal structure can be used as the channel formation region. Further, as the pellets become larger, a region having a single crystal structure may be used as the channel formation region, the source region, and the drain region of the transistor. In addition, when the gaps between the pellets become extremely small, one large pellet may be formed. One large pellet has a single crystal structure. For example, the size of the pellet may be 10 nm or more and 200 nm or less, 15 nm or more and 100 nm or less, or 20 nm or more and 50 nm or less as viewed from the upper surface. At this time, in the oxide semiconductor used for a fine transistor, the channel formation region may be included in one large pellet. That is, a region having a single crystal structure can be used as the channel formation region. Further, as the pellets become larger, a region having a single crystal structure may be used as the channel formation region, the source region, and the drain region of the transistor. In addition, when the gaps between the pellets become extremely small, one large pellet may be formed. One large pellet has a single crystal structure. For example, the size of the pellet may be 10 nm or more and 200 nm or less, 15 nm or more and 100 nm or less, or 20 nm or more and 50 nm or less as viewed from the upper surface. At this time, in the oxide semiconductor used for a fine transistor, the channel formation region may be included in one large pellet. That is, a region having a single crystal structure can be used as the channel formation region. Further, as the pellets become larger, a region having a single crystal structure may be used as the channel formation region, the source region, and the drain region of the transistor. In addition, when the gaps between the pellets become extremely small, one large pellet may be formed. One large pellet has a single crystal structure. For example, the size of the pellet may be 10 nm or more and 200 nm or less, 15 nm or more and 100 nm or less, or 20 nm or more and 50 nm or less as viewed from the upper surface. At this time, in the oxide semiconductor used for a fine transistor, the channel formation region may be included in one large pellet. That is, a region having a single crystal structure can be used as the channel formation region. Further, as the pellets become larger, a region having a single crystal structure may be used as the channel formation region, the source region, and the drain region of the transistor. In addition, when the gaps between the pellets become extremely small, one large pellet may be formed. One large pellet has a single crystal structure. For example, the size of the pellet may be 10 nm or more and 200 nm or less, 15 nm or more and 100 nm or less, or 20 nm or more and 50 nm or less as viewed from the upper surface. At this time, in the oxide semiconductor used for a fine transistor, the channel formation region may be included in one large pellet. That is, a region having a single crystal structure can be used as the channel formation region. Further, as the pellets become larger, a region having a single crystal structure may be used as the channel formation region, the source region, and the drain region of the transistor. In addition, when the gaps between the pellets become extremely small, one large pellet may be formed. One large pellet has a single crystal structure. For example, the size of the pellet may be 10 nm or more and 200 nm or less, 15 nm or more and 100 nm or less, or 20 nm or more and 50 nm or less as viewed from the upper surface. At this time, in the oxide semiconductor used for a fine transistor, the channel formation region may be included in one large pellet. That is, a region having a single crystal structure can be used as the channel formation region. Further, as the pellets become larger, a region having a single crystal structure may be used as the channel formation region, the source region, and the drain region of the transistor.

[0316] As described above, when the channel formation region of the transistor and the like are formed in a region having a single crystal structure, the frequency characteristics of the transistor may be improved. As described above, when the channel formation region of the transistor and the like are formed in a region having a single crystal structure, the frequency characteristics of the transistor may be improved.

[0317] According to the above model, it is considered that the pellets 6100 are deposited on the substrate 6120. Since the film formation of CAAC-OS is possible even when the surface to be formed does not have a crystal structure, it can be seen that the growth mechanism is different from epitaxial growth. In addition, CAAC-OS does not require laser crystallization, and uniform film formation is possible even on a large-area glass substrate or the like. According to the above model, it is considered that the pellets 6100 are deposited on the substrate 6120. Since the film formation of CAAC-OS is possible even when the surface to be formed does not have a crystal structure, it can be seen that the growth mechanism is different from epitaxial growth. In addition, CAAC-OS does not require laser crystallization, and uniform film formation is possible even on a large-area glass substrate or the like. According to the above model, it is considered that the pellets 6100 are deposited on the substrate 6120. Since the film formation of CAAC-OS is possible even when the surface to be formed does not have a crystal structure, it can be seen that the growth mechanism is different from epitaxial growth. In addition, CAAC-OS does not require laser crystallization, and uniform film formation is possible even on a large-area glass substrate or the like. According to the above model, it is considered that the pellets 6100 are deposited on the substrate 6120. Since the film formation of CAAC-OS is possible even when the surface to be formed does not have a crystal structure, it can be seen that the growth mechanism is different from epitaxial growth. In addition, CAAC-OS does not require laser crystallization, and uniform film formation is possible even on a large-area glass substrate or the like. is possible. For example, even if the structure of the upper surface (surface to be formed) of the substrate 6120 is an amorphous structure (e.g., amorphous silicon oxide), it is possible to form CAAC-OS.

[0318] Also, even when there are irregularities on the upper surface of the substrate 6120 which is the surface to be formed, it can be seen that the pellets 6100 are arranged along the shape thereof. For example, when the upper surface of the substrate 6120 is flat at the atomic level, the pellets 6100 are juxtaposed with the flat plate surface which is a plane parallel to the a-b plane facing downward. When the thickness of the pellets 6100 is uniform, a layer having a uniform thickness, being flat, and having high crystallinity is formed. And by stacking such layers in n layers (n is a natural number), CAAC-OS can be obtained.

[0319] On the other hand, even when the upper surface of the substrate 6120 has irregularities, CAAC-OS has a structure in which layers in which the pellets 6100 are juxtaposed along the irregularities are stacked in n layers (n is a natural number). Since the substrate 6120 has irregularities, there are cases where gaps are likely to occur between the pellets 6100 in CAAC-OS. However, even in this case, intermolecular forces act between the pellets 6100, and they are arranged so that the gaps between the pellets become as small as possible. Therefore, even when there are irregularities, CAAC-OS having high crystallinity can be obtained. 0

[0320] Since CAAC-OS is formed by such a model, it is preferable that the sputtering particles are in the form of pellets having no thickness. When the sputtering particles are in the form of thick dice, the surface facing the substrate 6120 may not be constant, and it may not be possible to make the thickness and crystal orientation uniform.

[0321] ​​​​​​​​​​​​According to the film formation model described above, even on a surface to be formed having an amorphous structure, CAAC-OS having high crystallinity can be obtained.

[0322] <Top view and cross-sectional view of semiconductor device> Next, taking a liquid crystal display device as an example, the appearance of a semiconductor device according to one aspect of the present invention will be described with reference to FIG. 32. FIG. 32 is a top view of a liquid crystal display device in which a substrate 4001 and a substrate 4006 are adhered by a sealing material 4005 . Further, FIG. 33 corresponds to a cross-sectional view taken along the broken line C1- C2 in FIG. 32.

[0323] A sealing material 4005 is provided so as to surround a pixel portion 4002 provided on the substrate 4001 and a pair of drive circuits 4004. Further, a substrate 4006 is provided on the pixel portion 4002 and the drive circuit 4004. Therefore, the pixel portion 4002 and the drive circuit 4004 are sealed by the substrate 4001, the sealing material 4005, and the substrate 4006.

[0324] In addition, a drive circuit 4003 is mounted in a region different from the region surrounded by the sealing material 4005 on the substrate 4001.

[0325] The pixel portion 4002 and the drive circuit 4004 provided on the substrate 4001 have a plurality of transistors . In FIG. 33, a transistor 4010 included in the pixel portion 4002 is exemplified . An insulating film 4020 and an insulating film 4021 are provided on the transistor 4010 so as to be laminated in sequence, and the transistor 4010 is connected to a pixel electrode 4022 on the insulating film 4021 at an opening provided in the insulating film 4020 and the insulating film 40 21.

[0326] ​​​​Also, a resin film 4059 is provided on the substrate 4006, and a common electrode 4060 is provided on the resin film 4059. And between the substrate 4001 and the substrate 4006, a liquid crystal layer 4028 is provided so as to be sandwiched between the pixel electrode 4022 and the common electrode 4060. The liquid crystal element 4023 has the pixel electrode 4022, the common electrode 4060, and the liquid crystal layer 4028.

[0327] In the liquid crystal element 4023, according to the value of the voltage applied between the pixel electrode 4022 and the common electrode 4060, the alignment of the liquid crystal molecules contained in the liquid crystal layer 4028 changes, and the transmittance changes. Thus, the liquid crystal element 4023 can display gradation by controlling its transmittance according to the potential of the image signal applied to the pixel electrode 4022.

[0328] Also, as shown in FIG. 33, in one aspect of the present invention, the insulating film 4020 is removed at the end of the panel. And in the region where the insulating film 4020 is removed, a conductive film 4 050 is formed. The conductive film 4050 and the conductive film that functions as the source or drain of the transistor 4010 can be formed by etching one conductive film.

[0329] And between the substrate 4001 and the substrate 4006, a resin film 4062 in which conductive particles 4061 having conductivity are dispersed is provided. The conductive film 4050 is electrically connected to the common electrode 4060 via the conductive particles 4061. That is, the common electrode 4060 and the conductive film 4050 are electrically connected via the conductive particles 4061 at the end of the panel. The resin film 4062 uses a thermosetting resin or an ultraviolet curable resin. ​​​​​​​​​It is possible. Further, as the conductive particles 4061, for example, particles coated with a thin film of a metal such as Au, Ni, or C o can be used.

[0330] Although the alignment film is not shown in FIG. 33, when the alignment film is provided on the pixel electrode 4022 and the common electrode 4 060, in order to electrically connect the common electrode 4060, the conductive particles 4061, and the conductive film 4050 a part of the alignment film may be removed at the portion overlapping the common electrode 4060 and a part of the alignment film may be removed at the portion overlapping the conductive film 4050.

[0331] Note that the liquid crystal display device may display a color image by using a color filter or may display a color image by sequentially lighting a plurality of light sources that emit light of different hues.

[0332] Further, the image signal from the driving circuit 4003, various control signals and potentials from the FPC 4018 are supplied to the driving circuit 4004 or the pixel portion 400 2 via the routing wirings 4030 and 4031.

[0333] <Example of Configuration of Electronic Device> A semiconductor device according to an aspect of the present invention can be used in a display device, a notebook personal computer, a recording image reproducing device having a medium (typically a device having a display capable of reproducing a recording medium such as a DVD: Digital Versatile Disc and displaying the image thereof). In addition, as electronic devices that can use a semiconductor device according to an aspect of the present invention, mobile phones, portable game machines, portable information terminals, electronic books, video cameras, cameras such as digital still cameras, and goggle-type displays (head-mounted displays ). Other electronic devices that can use the semiconductor device according to an aspect of the present invention include mobile phones, portable game machines, portable information terminals, electronic books, video cameras, cameras such as digital still cameras, and goggle-type displays (head-mounted displays ). (i) Navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, fax machines, printers, printer multifunction devices, automated teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIG. 34. Layers, etc.), copiers, fax machines, printers, printer multifunction devices, automated teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIG. 34. Shown.

[0334] FIG. 34(A) is a display device, having a housing 5001, a display unit 5002, a support base 5003, and the like. The semiconductor device according to one aspect of the present invention can be used for the display unit 5002 or other circuits. Note that the display device includes all information display devices such as those for personal computers, TV broadcast reception, and advertising display. The semiconductor device according to one aspect of the present invention can be used for the display unit 5002 or other circuits. Note that the display device includes all information display devices such as those for personal computers, TV broadcast reception, and advertising display. The semiconductor device according to one aspect of the present invention can be used for the display unit 5002 or other circuits. Note that the display device includes all information display devices such as those for personal computers, TV broadcast reception, and advertising display. The semiconductor device according to one aspect of the present invention can be used for the display unit 5002 or other circuits. Note that the display device includes all information display devices such as those for personal computers, TV broadcast reception, and advertising display.

[0335] FIG. 34(B) is a portable information terminal, having a housing 5101, a display unit 5102, operation keys 5103, and the like. The semiconductor device according to one aspect of the present invention can be used for the display unit 5102 or other circuits. The semiconductor device according to one aspect of the present invention can be used for the display unit 5102 or other circuits. The semiconductor device according to one aspect of the present invention can be used for the display unit 5102 or other circuits.

[0336] FIG. 34(C) is a display device, having a housing 5701 with a curved surface, a display unit 5702, and the like. By using a flexible substrate for the semiconductor device according to one aspect of the present invention, the semiconductor device can be used for the display unit 5702 supported by the housing 5701 having a curved surface. By using a flexible substrate for the semiconductor device according to one aspect of the present invention, the semiconductor device can be used for the display unit 5702 supported by the housing 5701 having a curved surface. By using a flexible substrate for the semiconductor device according to one aspect of the present invention, the semiconductor device can be used for the display unit 5702 supported by the housing 5701 having a curved surface.

[0337] FIG. 34(D) is a portable game machine, having a housing 5301, a housing 5302, display units 5303, Display units 5304, a microphone 5305, a speaker 5306, operation keys 5307, a Sticker 5308, and the like. The semiconductor device according to one aspect of the present invention can be used for the display unit 5303, the display Unit 5304, or other circuits. Note that the portable The belt-shaped game machine has two display units 5303 and 5304, but the number of display units of the portable game machine is not limited to this. The number of display units of the portable game machine is not limited to this.

[0338] FIG. 34(E) is an e-book and has a housing 5601, a display unit 5602, etc. The semiconductor device according to one aspect of the present invention can be used for the display unit 5602 or other circuits. Thus, by using a flexible substrate, the semiconductor device can be made flexible. Thus, by using a flexible substrate, the semiconductor device can be made flexible. .

[0339] FIG. 34(F) is a mobile phone, and a display unit 5902, a microphone 5907, a speaker 5904, a camera 5903, an external connection unit 5906, and operation buttons 5905 are provided on a housing 5901. The semiconductor device according to one aspect of the present invention can be used for the display unit 5902 or other circuits. Also, when the semiconductor device according to one aspect of the present invention is formed on a flexible substrate, the semiconductor device can be applied to the display unit 5902 having a curved surface as shown in FIG. 34(F). The semiconductor device according to one aspect of the present invention can be used for the display unit 5902 or other circuits. Also, when the semiconductor device according to one aspect of the present invention is formed on a flexible substrate, the semiconductor device can be applied to the display unit 5902 having a curved surface as shown in FIG. 34(F). The semiconductor device according to one aspect of the present invention can be used for the display unit 5902 having a curved surface as shown in FIG. 34(F). is applicable.

Example

[0340] Next, a transistor using a CAAC-OS film was fabricated, and the results of measuring the value of the drain current ID (A) with respect to the gate voltage VG (V) will be described. The fabricated transistor had the same laminated structure as the transistor 10 shown in FIG. 3.

[0341] The fabricated transistor had the same laminated structure as the transistor 10 shown in FIG. 3. The fabricated transistor had a channel length L of 6 μm, a channel width W of 3 μm, or 10 cm, and a Lov length of 2 μm. Also, the distance ΔW between the end of the opening 23 or the opening 24 and the end of the oxide semiconductor film 14 in the channel width direction was set to 1.5 μm. The fabricated transistor had a channel length L of 6 μm, a channel width W of 3 μm, or 10 cm, and a Lov length of 2 μm. The distance ΔW between the end of the opening 23 or the opening 24 and the end of the oxide semiconductor film 14 in the channel width direction was set to 1.5 μm. The channel width W is the width of the opening 23 or It corresponds to the width of the opening 24. Also, the Lov length is the length of the The distance in the channel length direction in a region where the conductive film and the conductive film functioning as a gate overlap each other. It means separation.

[0342] The conductive film 12 is a laminate of a titanium film having a thickness of 35 nm and a copper film having a thickness of 200 nm. The insulating film 13 was a silicon nitride film having a thickness of 400 nm and a conductive film obtained by The insulating film used was a 50 nm thick silicon oxynitride film. The semiconductor film 14 is a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1. A 35 nm thick In-Ga-Zn oxide film was formed using a target consisting of The conductive film 16 and the conductive film 17 were made of a titanium film having a thickness of 35 nm and a A conductive film obtained by sequentially laminating a 200 nm thick copper film and a 200 nm thick copper film was used. A silicon oxynitride film having a thickness of 50 nm was used as the insulating film 20b. As the insulating film 21, a silicon nitride film having a thickness of 100 nm was used.

[0343] The drain current ID (A) of the fabricated transistor is calculated based on the gate voltage VG (V). The measurement results are shown in FIG.

[0344] In addition, by forming a nitride insulating film in contact with the oxide semiconductor film, The resistivity of the metal oxide film obtained by reducing the resistance of the film was investigated. The target used was made of metal oxide with a ratio of In:Ga:Zn=1:1:1. Using the formed In-Ga-Zn oxide semiconductor film, a silicon nitride film was used as the nitride insulating film. When used, the resistivity of the metal oxide film obtained by reducing the resistance of the In-Ga-Zn oxide semiconductor film was estimated to be approximately 7.0×10 -3 [Ω·cm].

[0345] Also, the transmittance of the above metal oxide film was investigated. Fig. 36 shows the wavelength dependence of the transmittance of a sample obtained by sequentially laminating an In-G a-Zn oxide semiconductor film and a silicon nitride film on a glass substrate. The In-Ga-Zn oxide semiconductor film was formed using a target composed of a metal oxide with In:Ga:Zn = 1: 1:1, and its film thickness was 35n m. The silicon nitride film had a substrate temperature of 350°C during film formation, and its film thickness was 100 nm . As shown in Fig. 36, it was found that the transmittance of the above sample in the visible light region of 380 nm to 770 nm was 70% or more.

[0346] Also, a liquid crystal display device having the pixel 30 shown in Fig. 5 was prototyped. However, the pixel 30 of the prototyped liquid crystal display device had the same structure as the cross-sectional view shown in Fig. 9(A). Table 1 below shows the specifications of the prototyped liquid crystal display device.

[0347]

Table 1

[0348] Fig. 37 shows a photograph of the prototyped liquid crystal display device displaying an image.

Explanation of Signs

[0349] C1 Capacitor element C2 Capacitor element CLK1 Signal CLK2 Signal​ CLK3 signal CLK4 signal GL1 wiring M1 transistor M2 transistor M3 transistor M4 transistor M5 transistor M6 transistor M7 transistor M8 transistor M9 transistor M10 transistor M11 transistor M12 transistor M13 transistor M14 transistor M15 transistor PWC1 signal SL1 wiring T1 wiring T2 wiring T3 wiring T4 wiring T5 wiring T6 wiring T7 wiring T8 wiring T9 wiring 10 transistors 10A transistor 10B transistor 10D transistor 10P transistor 11 substrate 12 conductive film 12A conductive film 12B conductive film 13 insulating film 14 oxide semiconductor film 14A oxide semiconductor film 14B oxide semiconductor film 15 insulating film 15a insulating film 15b insulating film 16 conductive film 16A conductive film 16B conductive film 17 Conductive film 17A Conductive film 17B Conductive film 18 Region 19 End 20 Insulating film 20a Insulating film 20b Insulating film 21 Insulating film 22 Conductive film 22A Conductive film 23 Opening 23A Opening 23B Opening 24 Opening 24A Opening 24B Opening 25 Opening 30 Pixel 31 Capacitive element 32 Metal oxide film 32a Oxide semiconductor film 33 Conductive film 34 Opening 35 Opening 36 Opening 37 Conductive film 38 Alignment film 40 Substrate 41 Masking film 42 Coloring layer 43 Resin film 44 Conductive film 45 Alignment film 46 Liquid crystal layer 50 Conductive film 51 Conductive film 52 Opening 53 Opening 54 Conductive film 55 Opening 60 Opening 61 Insulating film 70 Display device 71 Pixel section 72 Driving circuit 73 Driving circuit 74 Liquid crystal element 76 Transistor 77 Transistor 78 Capacitive element 79 Light-emitting element 360 Connection electrode 380 Anisotropic conductive film 400 Display device 401 Substrate 405 Substrate 410 Element layer 411 Element layer 412 Adhesive layer 418 Adhesive layer 420 Insulating film 432 Sealing layer 440 Insulating film 462 Substrate 463 Release layer 464 Release adhesive 466 Temporary support substrate 468 Laser beam 4001 Substrate 4002 Pixel portion 4003 Driving circuit 4004 Driving circuit 4005 Sealing material 4006 Substrate 4010 Transistor 4018 FPC 4020 Insulating film 4021 Insulating film 4022 Pixel electrode 4023 Liquid crystal element 4028 Liquid crystal layer 4030 Wiring 4050 Conductive film 4059 Resin film 4060 Common electrode 4061 Conductive particles 4062 Resin film 5001 Housing 5002 Display unit 5003 Support stand 5101 Housing 5102 Display unit 5103 Operation key 5301 Housing 5302 Housing 5303 Display unit 5304 Display unit 5305 Microphone 5306 Speaker 5307 Operation Key 5308 Stylus 5601 Housing 5602 Display Unit 5701 Housing 5702 Display Unit 5901 Housing 5902 Display Unit 5903 Camera 5904 Speaker 5905 Button 5906 External Connection Port 5907 Microphone 6100 Pellet 6100a Pellet 6100b Pellet 6101 Ion 6102 Zinc Oxide Layer 6103 Particle 6105a Pellet 6105a1 Region 6105a2 Pellet 6105b Pellet 6105c Pellet 6105d Pellet 6105d1 Region 6105e Pellet 6120 Substrate 6130 Target 6161 Region

Claims

1. A pixel includes a transistor, a capacitor, and a display element. one of a source and a drain of the transistor is electrically connected to a first electrode of the display element; a display device in which one of a source and a drain of the transistor is electrically connected to one electrode of the capacitor element, a first conductive film having a region disposed above an insulating surface and functioning as a gate electrode of the transistor; a first insulating film having a region disposed above the first conductive film and functioning as a gate insulating film of the transistor; an oxide semiconductor film having a region disposed above the first insulating film and having a channel region of the transistor; a second conductive film having a region located above the first insulating film, functioning as the other electrode of the capacitor, and having a light-transmitting property; a second insulating film having a region located above the oxide semiconductor film and the second conductive film, the second insulating film including silicon oxide; a third conductive film electrically connected to the oxide semiconductor film and to the first electrode; a fourth conductive film that is electrically connected to the oxide semiconductor film, has a function as a first wiring electrically connected to the other of the source and the drain of the transistor, and has a region extending in a first direction across the pixel and an adjacent pixel; a fifth conductive film electrically connected to the second conductive film, having a function as a second wiring for supplying a potential to the second conductive film, and having a region extending in the first direction across the pixel and an adjacent pixel; a third insulating film having a region disposed above the second conductive film, a region disposed above the third conductive film, a region disposed above the fourth conductive film, and a region disposed above the fifth conductive film; a second electrode of the display element having a region disposed above the first electrode; the first electrode has a region disposed above the third insulating film, the second conductive film has a first region that is a region that does not overlap the fifth conductive film and does not overlap the second insulating film; an upper surface of the first region has a region in contact with the third insulating film; the fifth conductive film does not overlap with the fourth conductive film; Display device.

2. A pixel includes a transistor, a capacitor, and a display element. one of a source and a drain of the transistor is electrically connected to a first electrode of the display element; a display device in which one of a source and a drain of the transistor is electrically connected to one electrode of the capacitor element, a first conductive film having a region disposed above an insulating surface and functioning as a gate electrode of the transistor; a first insulating film having a region disposed above the first conductive film and functioning as a gate insulating film of the transistor; an oxide semiconductor film having a region disposed above the first insulating film and having a channel region of the transistor; a second conductive film having a region located above the first insulating film, functioning as the other electrode of the capacitor, and having a light-transmitting property; a second insulating film having a region located above the oxide semiconductor film and the second conductive film, the second insulating film including silicon oxide; a third conductive film electrically connected to the oxide semiconductor film and to the first electrode; a fourth conductive film that is electrically connected to the oxide semiconductor film, has a function as a first wiring electrically connected to the other of the source and the drain of the transistor, and has a region extending in a first direction across the pixel and an adjacent pixel; a fifth conductive film electrically connected to the second conductive film, having a function as a second wiring for supplying a potential to the second conductive film, and having a region extending in the first direction across the pixel and an adjacent pixel; a third insulating film having a region disposed above the second conductive film, a region disposed above the third conductive film, a region disposed above the fourth conductive film, and a region disposed above the fifth conductive film; a second electrode of the display element having a region disposed above the first electrode; the first electrode has a region disposed above the third insulating film, the second conductive film has a first region that is a region that does not overlap the fifth conductive film and does not overlap the second insulating film; an upper surface of the first region has a region in contact with the third insulating film; the fifth conductive film does not overlap with the fourth conductive film, the second conductive film does not overlap with the third conductive film; Display device.

3. A pixel includes a transistor, a capacitor, and a display element. one of a source and a drain of the transistor is electrically connected to a first electrode of the display element; a display device in which one of a source and a drain of the transistor is electrically connected to one electrode of the capacitor element, a first conductive film having a region disposed above an insulating surface and functioning as a gate electrode of the transistor; a first insulating film having a region disposed above the first conductive film and functioning as a gate insulating film of the transistor; an oxide semiconductor film having a region disposed above the first insulating film and having a channel region of the transistor; a second conductive film having a region located above the first insulating film, functioning as the other electrode of the capacitor, and having a light-transmitting property; a second insulating film having a region located above the oxide semiconductor film and the second conductive film, the second insulating film including silicon oxide; a third conductive film electrically connected to the oxide semiconductor film and to the first electrode; a fourth conductive film that is electrically connected to the oxide semiconductor film, has a function as a first wiring electrically connected to the other of the source and the drain of the transistor, and has a region extending in a first direction across the pixel and an adjacent pixel; a fifth conductive film electrically connected to the second conductive film, having a function as a second wiring for supplying a potential to the second conductive film, and having a region extending in the first direction across the pixel and an adjacent pixel; a third insulating film having a region disposed above the second conductive film, a region disposed above the third conductive film, a region disposed above the fourth conductive film, and a region disposed above the fifth conductive film; a second electrode of the display element having a region disposed above the first electrode; the first electrode has a region disposed above the third insulating film, the second conductive film has a first region that is a region that does not overlap the fifth conductive film and does not overlap the second insulating film; an upper surface of the first region has a region in contact with the third insulating film; the fifth conductive film does not overlap with the fourth conductive film, the second conductive film does not overlap with the fourth conductive film; Display device.

4. A pixel includes a transistor, a capacitor, and a display element. one of a source and a drain of the transistor is electrically connected to a first electrode of the display element; a display device in which one of a source and a drain of the transistor is electrically connected to one electrode of the capacitor element, a first conductive film having a region disposed above an insulating surface and functioning as a gate electrode of the transistor; a first insulating film having a region disposed above the first conductive film and functioning as a gate insulating film of the transistor; an oxide semiconductor film having a region disposed above the first insulating film and having a channel region of the transistor; a second conductive film having a region located above the first insulating film, functioning as the other electrode of the capacitor, and having a light-transmitting property; a second insulating film having a region located above the oxide semiconductor film and the second conductive film, the second insulating film including silicon oxide; a third conductive film electrically connected to the oxide semiconductor film and to the first electrode; a fourth conductive film that is electrically connected to the oxide semiconductor film, has a function as a first wiring electrically connected to the other of the source and the drain of the transistor, and has a region extending in a first direction across the pixel and an adjacent pixel; a fifth conductive film electrically connected to the second conductive film, having a function as a second wiring for supplying a potential to the second conductive film, and having a region extending in the first direction across the pixel and an adjacent pixel; a third insulating film having a region disposed above the second conductive film, a region disposed above the third conductive film, a region disposed above the fourth conductive film, and a region disposed above the fifth conductive film; a second electrode of the display element having a region disposed above the first electrode; the first electrode has a region disposed above the third insulating film, the second conductive film has a first region that is a region that does not overlap the fifth conductive film and does not overlap the second insulating film; an upper surface of the first region has a region in contact with the third insulating film; the fifth conductive film does not overlap with the fourth conductive film, the second conductive film does not overlap with the third conductive film, the second conductive film does not overlap with the fourth conductive film; Display device.

5. In any one of claims 1 to 4, the oxide semiconductor film contains In, Ga, and Zn; Display device.

Images