High-density low voltage nv differential memory bit-cell with shared plate-line

Abstract

To describe a low power, high-density non-volatile differential memory bit-cell.SOLUTION: Transistors of a differential memory bit-cell can be planar or non-planer and can be fabricated in the frontend or backend of a die. A bit-cell of the non-volatile differential memory bit-cell includes a first transistor and a first non-volatile structure that are controlled to store data of a first value, and another bit-cell of the non-volatile differential memory bit-cell includes a second transistor and a second non-volatile structure that are controlled to store data of a second value, the first value being an inverse of the second value. First and second volatile structures include ferroelectric material (e.g., perovskite, hexagonal ferroelectric, or improper ferroelectric).SELECTED DRAWING: Figure 1A

Description

Background Art

[0001] [Priority Claim] This application claims priority to U.S. Patent Application No. 16 / 287,876, entitled "High-Density Low Voltage Non-Volatile Differential Memory Bit-Cell with Shared Plate-line", filed on February 27, 2019, the entire contents of which are incorporated herein by reference.

[0002] [Background Art] Standard memories used in processors are static random access memory (SRAM) or dynamic random access memory (DRAM) and their derivatives. These memories are volatile memories. For example, when the power to the memory is turned off, the memory loses the stored data. Currently, non-volatile memories are commonly used in computing platforms to replace magnetic hard disks. Non-volatile memories retain their stored data for a long time (e.g., months, years, or permanently) even when the power to these memories is turned off. Examples of non-volatile memories are magnetic random access memory (MRAM), NAND or NOR flash memory. Since these memories have high write energy, low density, and high power consumption, they may not be suitable for low-power and compact computing devices.

[0003] The description of the background art provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise specified herein, the materials described in this section are not prior art to the claims of this application and are not admitted to be prior art by inclusion in this section.

Brief Description of the Drawings

[0004] Embodiments of the present disclosure will be more fully understood from the following detailed description given below and the accompanying drawings of various embodiments of the present disclosure, which should not be construed as limiting the present disclosure to the specific embodiments, but are for illustration and understanding only.

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DETAILED DESCRIPTION OF THE INVENTION

[0005] In a typical ferroelectric (FE) capacitor, the switching voltages of the positive and negative polarities are asymmetric. This is due to the spatial movement of atoms with respect to the electrodes from the ferroelectric when the total numbers of 1s and 0s are unbalanced. This makes it difficult to use a typical FE capacitor for a memory bit cell because writing a 0 or 1 to the FE capacitor may require different energies, which generates an overhead for circuit design.

[0006] Some embodiments describe a low-power, high-density non-volatile differential memory bit cell that compensates for the asymmetry of a typical ferroelectric capacitor. The transistors of the differential memory bit cell can be planar or non-planar and can be fabricated at the front-end or back-end of the die. The bit cells of the non-volatile differential memory bit cell include a first transistor and a first non-volatile structure that are controlled to store data of a first value. The other bit cells of the non-volatile differential memory bit cell include a second transistor and a second non-volatile structure that are controlled to store data of a second value, where the first value is the inverse of the second value. The first volatile structure and the second volatile structure include a low-voltage ferroelectric material (e.g., perovskite material, hexagonal ferroelectric, or irregular ferroelectric) that can switch its state with a small voltage change (e.g., 100 mV).

[0007] In some embodiments, each of the first non-volatile structure and the second non-volatile structure includes a first layer that includes a first refractive intermetallic compound, and the first layer is adjacent to the drain or source of the first transistor or the second transistor. Examples of the first refractive intermetallic compound include Ti—Al (Ti3Al, TiAl, TiAl3, etc.), Ni—Al (Ni3Al, NiAl3, NiAl, etc.), Ni—Ti, Ni—Ga, Ni2MnGa, FeGa, Fe3Ga, borides, carbides, or nitrides. In some embodiments, the refractive intermetallic compound is part of a barrier layer that is a superlattice of a first material and a second material, the first material includes Ti and Al (e.g., TiAl), and the second material includes Ta, W, and Co (e.g., layers of Ta, W, and Co). In various embodiments, the lattice parameter of the barrier layer matches the lattice parameter of the conductive oxide and / or the FE material. In some embodiments, the first non-volatile structure and the second non-volatile structure include a second layer that includes a first conductive oxide, and the second layer is adjacent to the first layer. The first non-volatile structure and the second non-volatile structure include a third layer that includes an FE material, and the third layer is adjacent to the second layer.

[0008] The FE material can be any suitable low-voltage FE material that enables the FE material to switch its state by a low voltage (e.g., 100 mV). In some embodiments, the FE material includes an ABO 3 type perovskite material, where "A" and "B" are two cations of different sizes, and "O" is oxygen, an anion that binds to both cations. Generally, the size of the A atoms is larger than that of the B atoms. In some embodiments, the perovskite material can be doped (e.g., with La or a lanthanide). In various embodiments, when the FE material is a perovskite material, the conductive oxide is of the AA'BB'O 3 type. A' is a dopant at the atomic position A and can be an element of the lanthanide series. B' is a dopant at the atomic position B and can be an element from transition metal elements, particularly Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn. A' may have the same valence as position A with a different ferroelectric polarization rate.

[0009] In some embodiments, the FE material includes a hexagonal ferroelectric of the h-RMnO3 type, where R is a rare earth element, i.e., cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), and yttrium (Y). The ferroelectric phase is characterized by the buckling of the layered MnO5 polyhedra accompanied by the transfer of Y ions, which results in a net electric polarization. In various embodiments, when the FE material includes a hexagonal ferroelectric, the conductive oxide is of the A2O3 (e.g., In2O3, Fe2O3) and ABO3 type, where A is a rare element.

[0010] In some embodiments, the FE material includes a ferroelectric material having irregularity. The ferroelectric material having irregularity is a ferroelectric material in which a primary order parameter is an ordering mechanism such as distortion or buckling of atomic order. Examples of the ferroelectric material having irregularity are materials of the LuFeO3 class or superlattices of ferroelectric materials and paraelectric materials (PbTiO3 (PTO) and SnTiO3 (STO), respectively, and LaAlO3 (LAO) and STO, respectively). For example, a superlattice of [PTO / STO]n or [LAO / STO]n, where "n" ranges from 1 to 100. Although various embodiments are described herein with reference to ferroelectric materials for storing a charge state, the embodiments are also applicable to paraelectric materials. For example, the pillar capacitors of various embodiments can be formed using a paraelectric material instead of a ferroelectric material.

[0011] In some embodiments, the first non-volatile structure and the second non-volatile structure include a fourth layer including a second conductive oxide, and the fourth layer is adjacent to the third layer. The first non-volatile structure and the second non-volatile structure include a fifth layer including a second refractive intermetallic compound, and the fifth layer is adjacent to the PL and adjacent to the fourth layer. In some embodiments, the first non-volatile structure and the second non-volatile structure include a sixth layer adjacent to a first side surface of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer. The first non-volatile structure and the second non-volatile structure also include a seventh layer adjacent to a second side surface of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer, and the sixth layer and the seventh layer include a sidewall barrier material (e.g., Ti—Al—O, Al2O3, or MgO). The sidewall barrier material is an insulating material.

[0012] There are many technical effects in various embodiments. For example, the differential FE memory bit cell compensates for the asymmetry inherent in the FE material. Over time, the FE memory cell experiences an asymmetry in the switching voltages of the positive and negative polarities. This is due to the spatial movement of atoms with respect to the electrodes from the FE when the total number of 1s and 0s is unbalanced. By operating the first FE capacitor structure and the second FE capacitor structure such that the data stored in the first FE capacitor structure is the complement of the data stored in the second FE capacitor structure, the asymmetry within the FE cell is compensated. The differential FE memory bit cell results in a compact layout for the realization of high-density memory. The differential FE memory bit cell with compensated FE asymmetry enables high-integrity artificial intelligence (AI) processing at low power. Other technical effects will become apparent from the various embodiments and the drawings.

[0013] In the following description, numerous details are discussed in order to provide a more complete explanation of embodiments of the present disclosure. However, it will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the present disclosure.

[0014] Note that in the corresponding drawings of the embodiments, signals are represented by lines. Some lines may be made thicker to indicate the signal paths of more components and / or may have arrows at one or more ends to indicate the direction of the main information flow. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate the understanding of the circuit or logic unit. Any represented signal, defined by design requirements or preferences, may actually include one or more signals that can travel in any direction and may be implemented in any suitable type of signaling scheme.

[0015] The term "device" may generally refer to an apparatus in accordance with the context of the usage of that term. For example, a device may refer to a stack of layers or structures, a single structure or layer, the connection of various structures having active and / or passive elements, etc. Generally, a device is a three-dimensional structure having a plane along the x-y direction and a height along the z direction of an x-y-z Cartesian coordinate system. The plane of the device may also be the plane of the apparatus containing the device.

[0016] In the specification and claims, the term "connected" means a direct connection such as an electrical, mechanical or magnetic connection between the connected objects without an intermediate device.

[0017] The term "coupled" means a direct or indirect connection such as a direct electrical, mechanical or magnetic connection or an indirect connection between the connected objects through one or more passive or active intermediate devices.

[0018] In this specification, the term "adjacent" generally indicates a position where an object is next (e.g., immediately next to or in proximity to one or more objects between them), or a position adjacent to (e.g., in contact with) another object.

[0019] The term "circuit" or "module" may refer to one or more passive and / or active components configured to cooperate with each other to provide a desired function.

[0020] The term "signal" may refer to at least one current signal, voltage signal, magnetic signal or data / clock signal. The meaning of "one" includes multiple references. The meaning of "within" includes "within" and "on".

[0021] The term "scaling" generally refers to converting a design (schematic and layout) from one process technology to another and then shrinking in the layout area. Also, the term "scaling" generally refers to shrinking the layout and devices within the same technology node. Also, the term "scaling" may refer to adjusting the signal frequency to other parameters (e.g., power level) (e.g., slowing down or speeding up, i.e., shrinking or expanding respectively).

[0022] "Substantially", "close", "approximately", "nearly" and "about" generally indicate within + / - 10% of the target value. For example, unless otherwise specified in the explicit context of their use, the terms "substantially equal", "nearly equal" and "approximately equal" mean that there are only incidental variations between the things so described. In the art, such variations are typically within + / - 10% of a given target value.

[0023] Unless otherwise specified, the use of ordinal adjectives such as "first", "second" and "third" to describe a common object simply indicates that different instances of the same object are being referred to, and is not intended to imply that the objects so described must be in a given order, whether temporally, spatially, in ranking, or otherwise.

[0024] For the purposes of this disclosure, the terms "A and / or B" and "A or B" mean (A), (B) or (A and B). For the purposes of this disclosure, the term "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C).

[0025] In the specification and claims, terms such as "left", "right", "front", "back", "top", "bottom", "above", "below", etc., if present, are used for purposes of explanation and are not necessarily used to describe permanent relative positions. For example, the terms "above", "below", "front side", "back side", "top", "bottom", "above", "below", and "on" as used in this specification indicate the relative position of one component, structure, or material with respect to another referenced component, structure, or material within the device, and attention is paid to such physical relationships. These terms are used in this specification mainly only within the context of the device's z-axis and may be related to the orientation of the device. Thus, the first material "above" the second material in the context of the drawings provided in this specification may also be "below" the second material if the device is oriented upside down with respect to the context of the drawings provided. In the context of materials, one material disposed above or below another material may be in direct contact or may have one or more intervening materials. Further, one material disposed between two materials may be in direct contact with both layers or may have one or more intervening layers. In contrast, the first material "on" the second material is in direct contact with the second material. A similar distinction is also made in the context of assemblies of components.

[0026] The term "between" may be used in the context of the device's z-axis, x-axis, or y-axis. A material between two other materials may be in contact with one or both of these materials or may be separated from both of the other two materials by one or more intervening materials. Thus, a material "between" two other materials may be in contact with either of the two other materials or may be coupled to the two other materials through an intervening material. A device between two other devices may be directly connected to one or both of these devices or may be separated from both of the other two devices by one or more intervening devices.

[0027] Here, a plurality of non-silicon semiconductor material layers may be stacked within a single fin structure. The plurality of non-silicon semiconductor material layers may include one or more "P-type" layers suitable for P-type transistors (e.g., providing higher hole mobility than silicon). The plurality of non-silicon semiconductor material layers may further include one or more "N-type" layers suitable for N-type transistors (e.g., providing higher electron mobility than silicon). The plurality of non-silicon semiconductor material layers may further include one or more intervening layers separating the N-type layers from the P-type layers. The intervening layers may be at least partially sacrificial, e.g., enabling one or more of the gates, sources, or drains to completely wrap around the channel regions of one or more of the N-type and P-type transistors. The plurality of non-silicon semiconductor material layers may be manufactured, at least in part, by self-alignment techniques such that a stacked CMOS device can include both high-mobility N-type and P-type transistors having the footprint of a single FET (field effect transistor).

[0028] Here, the term "backend" generally refers to the part of the die opposite the "front-end" and indicates the portion of the die where the IC (integrated circuit) package attaches to the IC die bump. For example, high-level metal layers close to the package of the die (e.g., metal layers 6 and above in a 10-metal stacked die) and corresponding vias are considered part of the backend of the die. Conversely, the term "front-end" generally refers to the active region (e.g., where transistors are fabricated) and the portion of the die that includes low-level metal layers and corresponding vias close to the active region (e.g., metal layers 5 and below in the example of a 10-metal stacked die).

[0029] It is noted that elements of the drawings having the same reference numerals (or names) as elements of other drawings may operate or function in a similar manner as those described, but are not limited thereto.

[0030] Figure 1A shows an apparatus 100 including a memory 101 and corresponding logic 102 and 103 according to some embodiments, where the memory includes differential FE memory bit cells. Logic 102 includes an address decoder for selecting rows and / or specific bit cells of bit cells from an M×N array, where M and N are integers of the same value or different values. Logic 103 includes a sense amplifier for reading values from the selected bit cells, and a write driver is used to write a specific value to the selected differential bit cells. Here, differential bit cell 101 0,0 is shown in a schematic diagram. The same embodiment also applies to other bit cells of the M×N array.

[0031] In some embodiments, differential bit cell 101 0,0 includes a word line (WL), a plate line (PL), a bit line (BL), a complementary bit line (BLB), and two half bit cells 101 0,0_A and 101 0,0_B . In some embodiments, the first half bit cell 101 0,0_A includes an n-type transistor MN 1 and an FE capacitor structure Cfe 1 . In some embodiments, the second half bit cell 101 0,0_B includes an n-type transistor MN 2 and an FE capacitor structure Cfe 2 . The gates of transistors MN 1 and MN 2 share a common WL. In various embodiments, one terminal of the first FE capacitor structure and the second FE capacitor structure (Cfe 1 and Cf 2 ) is coupled to a common PL. The second terminals of the first FE capacitor structure and the second FE capacitor structure (Cfe 1 and Cf 2 ) are coupled to the source terminal or drain terminal of their respective transistors.

[0032] For example, the second terminal of Cfe 1 is coupled to the drain or source terminal of transistor MN 1 , and the second terminal of Cfe 2 is coupled to the drain or source terminal of transistor MN 2 . In various embodiments, BL is coupled to the source or drain terminal of the first transistor MN 0,0_A of the first half cell 101, and BLB is coupled to the source or drain terminal of the second transistor MN 1 of the first half cell 101. In some embodiments, the first BL capacitor CBl 0,0_B is coupled to the source or drain terminal of the first transistor MN 2 and a reference node (e.g., ground), and the second BL capacitor CBl 1 is coupled to the source or drain terminal of the second transistor MN 1 and a reference node such that the FE capacitor is not coupled to the same source or drain terminal. 2 2

[0033] In various embodiments, the half bit cells 101 0,0_A and 101 0,0_B are self - reference cells because they are in close proximity to each other. For example, static spatial process variations are in a common mode for the Cfe 0,0_A and Cfe 0,0_B of each of the half bit cells 101 1 and 101 2 . Here, BL and BLB generate differential polarity detection signals. In the first use of the differential memory bit cell, the FE capacitors Cfe 1 and Cfe 2Assume that the upper critical voltage is the critical switching voltage of the following series, i.e., +VFe1, +VFe2, -VFe1, -VFe2, and in the initial operation of the memory, +VFe1 = +VFe2 and -Vfe1 = -vfe2. When the operation of the memory results in symmetric switching voltages, i.e., +VFe1 + DF1, -VFe1 + DF1, +VFe2 + DF1, -VFe2 + DF1, the half-bit cell 101 0,0_A and 101 0,0_B all switching voltages of remain as (+VFe1 + DF1) - (-VFe2 + DF1) = VFe1 + VFe2, enabling self-compensation for asymmetry. Here, DF1 is the offset due to asymmetry. This offset is added to the hysteresis of the behavior of the FE material.

[0034] FIG. 1B shows a timing diagram 200 for writing logic 1 and logic 0 to a differential bit cell according to some embodiments. To write data to the differential bit cell, BL, PL, and BLB generate a signal series for writing to the half-bit cell 101 0,0_A and 101 0,0_B with opposite polarities. For example, as shown in the timing diagram 200, when logic 1 is written to the half-bit cell 101 0,0_A logic 0 is written to the half-bit cell 101 0,0_B . The signal scheme for detecting data in the differential bit cell is similar to the detection scheme for SRAM (Static Random Access Memory). Although various embodiments are shown using n-type transistors, the differential bit cell may be implemented using p-type transistors.

[0035] FIG. 2A shows a 3D diagram 200 of a half-bit cell of a differential FE memory bit cell including a planar transistor according to some embodiments. The memory bit cell includes a planar transistor MN having a substrate 201, a source 202, a drain 203, a channel region 204, a gate dielectric 205, gate spacers 206a and 206b, a gate metal 207, a source contact 208a, and a drain contact 208b.

[0036] The substrate 201 includes a suitable semiconductor material such as single-crystalline silicon, polycrystalline silicon, and silicon on insulator (SOI). In one embodiment, the substrate 201 includes other semiconductor materials such as Si, Ge, SiGe, or suitable group III-V or group III-N compounds. The substrate 201 may also include semiconductor materials, metals, dopants, and other materials commonly found in semiconductor substrates.

[0037] In some embodiments, the source region 202 and the drain region 203 are formed in the substrate 201 adjacent to the gate stack of the transistor. The source region 202 and the drain region 203 are generally formed using either an etching / film deposition process or an implantation / diffusion process.

[0038] In the etching / film deposition process, first, the substrate 201 may be etched to form recesses at the positions of the source 202 and drain 203 regions. Then, an epitaxial growth process may be performed to fill the recesses with the material used to fabricate the source region 202 and the drain region 203. In the implantation / diffusion process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the substrate to form the source region 202 and the drain region 203. Typically, an annealing process to activate the dopants and further diffuse them into the substrate 201 follows the ion implantation process.

[0039] In some embodiments, one or more layers of metal and / or metal alloy are used to form source region 202 and drain region 203. In some embodiments, source region 202 and drain region 203 are formed using one or more alternative semiconductor materials such as germanium or a suitable III-V compound. In some embodiments, source region 202 and drain region 203 are fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, an epitaxially grown silicon alloy is doped in-situ with a dopant such as boron, arsenic, or phosphorus.

[0040] According to some embodiments, the semiconductor material for channel region 204 may have the same material as substrate 201. In some embodiments, channel region 204 comprises one of Si, SiGe, Ge, and GaAs.

[0041] The gate dielectric layer 205 may include one layer or a stack of layers. The one or more layers may include a high-k dielectric material, silicon oxide, and / or silicon dioxide (SiO 2 )). The high-k dielectric material may include elements such as zinc, niobium, scandium, dilute yttrium, hafnium, silicon, strontium, oxygen, barium, titanium, zirconium, tantalum, aluminum, and lanthanum. Examples of high-k materials that may be used for the gate dielectric layer include lead niobate, hafnium oxide, strontium scandium tantalum oxide, hafnium silicon oxide, yttrium oxide, aluminum oxide, lanthanum oxide, barium strontium tantalum oxide, lanthanum aluminum oxide, titanium oxide, zirconium oxide, tantalum oxide, and zirconium silicon oxide. In some embodiments, when a high-k material is used, an annealing process is used to improve the quality of the gate dielectric layer 205.

[0042] In some embodiments, a pair of spacer layers (sidewall spacers) 206a / b are formed on the opposite side of the gate stack that brackets the gate stack. The pair of spacer layers 206a / b are formed from materials such as silicon oxynitride, silicon nitride, silicon nitride doped with carbon, or silicon carbide. The process for forming the sidewall spacers is well known in the art and generally includes film deposition and etching process operations. In some embodiments, multiple spacer pairs may be used. For example, two pairs, three pairs, or four pairs of sidewall spacers may be formed on the opposite side of the gate stack.

[0043] The gate metal layer 207 may include at least one P-type work function metal or N-type work function metal depending on whether the transistor is a p-type transistor or an n-type transistor. The gate metal layer 207 may include a stack of two or more metal layers, where one or more of the metal layers are work function metal layers and at least one of the metal layers is a conductive fill layer.

[0044] For an n-type transistor, the metals that can be used for the gate metal layer 207 include aluminum carbide, tantalum carbide, zirconium carbide, and hafnium carbide. In some embodiments, the metal of the gate metal layer 207 for an n-type transistor includes aluminum, hafnium, zirconium, titanium, tantalum, and their alloys. The n-type metal layer enables the formation of an n-type gate metal layer 207 having a work function of about 3.9 eV to about 4.2 eV. In some embodiments, the metal of layer 207 includes one of TiN, TiSiN, TaN, Cu, Al, Au, W, TiSiN, or Co. In some embodiments, the metal of layer 107 includes one or more of Ti, N, Si, Ta, Cu, Al, Au, W, or Co.

[0045] Regarding the p-type transistor, the metal used for the gate metal layer 207 includes, but is not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides. Examples of the conductive oxide include ruthenium oxide. The p-type metal layer enables the formation of a p-type gate metal layer 207 having a work function of about 4.9 eV to about 5.2 eV.

[0046] The drain contact 208b is coupled to a via 209a that is coupled to the metal layer 210. The metal layer 210 is a bit line extending along the x-axis. The source contact 208a is coupled to the via 209b. Any suitable material can be used for the drain and source contacts 208a / n and the vias 209a / b. For example, one or more of Ti, N, Si, Ta, Cu, Al, Au, W, or Co can be used for the drain and source contacts 208a / n and the vias 209a / b. The via 209b includes a refractive intermetallic compound 211a / b as a barrier material, a conductive oxide 212a / bb, and an FE material 213, and is coupled to the FE capacitor Cfe 1 thereof.

[0047] The refractive intermetallic compound 211a / b maintains the FE characteristics of the FE capacitor Cfe 1 thereof. In the absence of the refractive intermetallic compound 211a / b, the ferroelectric material or paraelectric material 213 of the capacitor may lose its effectiveness. In some embodiments, the refractive intermetallic compound 211a / b includes Ti and Al (e.g., a TiAl compound). In some embodiments, the refractive intermetallic compound 211a / b includes one or more of Ta, W, and / or Co.

[0048] For example, the refractory intermetallic compounds 211a / b include the lattices of Ta, W, and Co. In some embodiments, the refractory intermetallic compounds 211a / b include one of Ti—Al (Ti3Al, TiAl, TiAl3, etc.), Ni—Al (Ni3Al, NiAl3, NiAl, etc.), Ni—Ti, Ni—Ga, Ni2MnGa, FeGa, Fe3Ga, borides, carbides, or nitrides. In some embodiments, the TiAl material includes Ti-(45-48)Al-(1-10)M (trace % of X), where M is at least one element from V, Cr, Mn, Nb, Ta, W, and Mo, and includes trace amounts of 0.1-5% of Si, B, and / or Mg. In some embodiments, TiAl is a single-phase alloy γ (TiAl). In some embodiments, TiAl is a two-phase alloy γ (TiAl)+α2 (Ti3Al). The single-phase γ alloy includes a third alloy element such as Nb or Ta that promotes strengthening and further enhances oxidation resistance. The role of the third alloy element in the two-phase alloy is to enhance ductility (V, Cr, Mn), oxidation resistance (Nb, Ta), or composite properties. Additives such as Si, B, and Mg can significantly enhance other properties. The barrier layer 211a is coupled to the plate line or power line (PL) 215.

[0049] In various embodiments, the PL 215 extends parallel to the BL 110 along the x direction. By making the BL and PL parallel to each other, the footprint of the memory bit cell is reduced compared to when the BL and PL are orthogonal to each other, thus further improving the density of the memory. The gate metal 207 is coupled to the gate contact 216 coupled to the metal line 217. The metal line 217 is used as a word line (WL). In some embodiments, the WL 217 extends orthogonally to the BL 210 and the PL 115. In some embodiments, the WL 217 is also parallel to the BL 210 and the PL 215. Any suitable metal can be used for the BL 210, PL 215, and WL 217. For example, Al, Cu, Co, Au, or Ag can be used for the BL 210, PL 215, and WL 217.

[0050] In some embodiments, the FE material 213 is a perovskite material containing one or more of La, Sr, Co, Sr, Ru, Y, Ba, Cu, Bi, Ca, and Ni. For example, (La,Sr)CoO 3 , SrRuO 3 , (La,Sr)MnO 3 , YBa 2 Cu 3 O 7 , Bi 2 Sr 2 CaCu 2 O 8 , LaNiO 3 and other metal perovskites such as these may be used for the FE material 213. The perovskite can be suitably doped to achieve a spontaneous strain in the range of 0.3 - 2%. For example, for lead titanate chemically substituted with Zr in the Ti site, La in the Ti site, Nb, the concentration of these substitutions is such that it achieves a spontaneous strain in the range of 0.3 - 2%. In chemically substituted BiFeO3, BrCrO3, BuCoO3 class of materials, La or rare earth substitutions to the Bi site can adjust the spontaneous strain.

[0051] In various embodiments, when a metal perovskite material is used for the FE material 213, the conductive oxide 112a / b can contain one or more of IrO 2 , RuO 2 , PdO 2 , OsO 2 or ReO 3 . In some embodiments, the perovskite material is doped with La or a lanthanide. In some embodiments, a thin layer (e.g., about 10 nm) perovskite material template conductor such as SrRuO3 coated on top of IrO2, RuO2, PdO2, PtO2, which is a non - perovskite structure but has higher conductivity, is used as the conductive oxide 212a / b to provide a seed or template for the growth of a pure perovskite ferroelectric at low temperature.

[0052] In some embodiments, the FE material 213 includes an AMnO3-type hexagonal ferroelectric. In various embodiments, when the FE material 213 includes a hexagonal ferroelectric, the conductive oxide is of the ABO 3 type, and A is a rare earth metal. Examples of hexagonal metals used as the conductive oxides 212a / b include one or more of other delafossite-structured hexagonal metal oxides such as PtCoO2, PdCoO2, and Al-doped ZnO.

[0053] In some embodiments, the FE material 213 includes a disordered FE material. Examples of disordered FE materials are materials of the LuFeO3 class or superlattices of ferroelectric and paraelectric materials (PbTiO3 (PTO) and SnTiO3 (STO), respectively, and LaAlO3 (LAO) and STO, respectively). For example, a superlattice of [PTO / STO]n or [LAO / STO]n, where "n" ranges from 1 to 100. Other examples of conductive oxides include spinels such as Fe3O4, LiV2O4, and cubic metal oxides such as ITO (indium tin oxide), Sn-doped In2O3. In some embodiments, the BL210 is wide and tall enough to provide a parasitic capacitance comparable to Cbl1. In various embodiments, the sidewall barrier materials 221a / b shown in FIG. 2C (e.g., Ti-Al-O, Al2O3, or MgO) are formed along the sides of the FE capacitor structure. The sidewall barrier material is an insulating material (e.g., a non-conductive material).

[0054] In this specification, various embodiments are described with reference to ferroelectric materials for storing charge states, but the embodiments are also applicable to paraelectric materials. For example, the material 213 of various embodiments can be formed using a paraelectric material instead of a ferroelectric material.

[0055] FIG. 2B shows a cross-sectional view 2200 of a half-bit cell of the differential FE memory bit cell of FIG. 2B, according to some embodiments.

[0056] Figure 2C shows a cross-sectional view 2300 of the differential FE memory bit cell of FIG. 1 according to some embodiments, where the FE capacitor structure is disposed above the bit line. This embodiment enables the use of the space between the BL and the PL to form the FE capacitor structure.

[0057] Figure 2D shows a cross-sectional view 2400 of the differential FE memory bit cell of FIG. 1 according to some embodiments. In some embodiments, the two half-bit cells 101 0,0_A and 101 0,0_B are mirror images of each other to achieve matching of device characteristics and to achieve differential behavior in the bit cell to compensate for the asymmetry of the FE material. PL215 and WL217 are shared by the two bit cells. Here, BLB is labeled 218.

[0058] Figure 2E shows a layout 2500 of the differential FE memory bit cell of FIG. 2C according to some embodiments. The pitch of the layout 2400 of the bit cell is approximately the pitch of two transistor regions. Here, the pitch represents the x and y dimensions of the bit cell. Since the pitch is small, many bit cells can be packed in an array fashion, resulting in a high-density memory array that compensates for the FE asymmetry.

[0059] The capacitor structures of various embodiments are shown as rectangular structures, but can also have other shapes. For example, the capacitor structures of various embodiments can have a cylindrical shape with dimensions similar to those described for the rectangular capacitor structure.

[0060] Figure 3 shows a 3D view 300 of the FE capacitor structure according to some embodiments. The materials for the various layers are discussed with reference to FIG. 2A. In some embodiments, the thickness t 111 of the refractive intermetallic compound layer 211a / b is in the range of 1 nm to 20 nm. In some embodiments, the thickness t 112is in the range of 1 nm to 20 nm. In some embodiments, the thickness t of the FE material (e.g., perovskite material, hexagonal ferroelectric or rhombohedral ferroelectric) 213a / b 113 is within the range of 1 nm to 20 nm. In some embodiments, the lateral thickness t of the sidewall barrier seal 221a / b (insulating material) 121 is in the range of 0.1 nm to 20 nm. In some embodiments, the lateral thickness L of the capacitor structure Cfe (without sidewall barriers) is in the range of 5 nm to 200 nm. In some embodiments, the height H of the capacitor structure Cfe is in the range of 10 nm to 200 nm. In some embodiments, the FE capacitor structure does not include the refractive intermetallic compound layer 211a / b. In that case, the conductive oxide layer 212a / b is in direct contact with a contact, via or metal (e.g., PL, source / drain region contact of the transistor MN). In some embodiments, the sidewall barrier seal 221a / b does not exist. In such an embodiment, the sidewalls of the layers 211a / b, 212a / n and 213 are in direct contact with an ILD (interlayer dielectric) such as SiO2.

[0061] Figure 4A shows a 3D view 400 of a half-bit cell of a differential FE memory bit cell including a non-planar transistor according to some embodiments. Figure 4B shows a cross-sectional view of the half-bit cell of the differential FE memory bit cell of Figure 4A according to some embodiments. The memory bit cells of Figures 4A-4B are similar to the memory bit cells of Figures 2A-2B, but are non-planar transistors. A FinFET is an example of a non-planar transistor. A FinFET includes fins including a source region 402 and a drain 403 region. A channel exists between the source region 402 and the drain region 403. The transistor MN can have a plurality of fins parallel to each other coupled to the same gate stack. The fins pass through the gate stack forming the source region 402 and the drain region 403. Figure 4C shows a cross-sectional view 430 of the half-bit cell of the differential FE memory bit cell of Figure 4A according to some embodiments, where the FE capacitor structure is disposed above the bit line. This embodiment enables the formation of the FE capacitor structure Cfe1 using the region above BL210.

[0062] Figure 5 shows a 3D view 500 of a half-bit cell of a differential FE memory bit cell including a non-planar transistor at the back end of a die according to some embodiments. Although a FinFet is shown, any back-end transistor that can be coupled to the FE capacitor structure can be used.

[0063] Figure 6 shows a flowchart 600 for forming a differential non-volatile memory bit cell according to some embodiments. The blocks of flowchart 600 are shown in a particular order, but that order is not critical. For example, some blocks or processes can be executed before others, and some can be executed in parallel or simultaneously.

[0064] In block 601, the method includes manufacturing a first transistor MN1 having a gate terminal coupled to a word line (WL) and one of a source terminal or a drain terminal coupled to a first bit line (BL). The transistor MN1 can be planar or non-planar.

[0065] In block 602, the method includes manufacturing a second transistor MN2 having a gate terminal coupled to the WL and one of a source terminal or a drain terminal coupled to a second bit line (BLB), where BLB provides a signal that is the inverse of the signal on the BL. In block 603, the method includes forming a first ferroelectric structure Cfe1 coupled to one of the drain or source of the first transistor and further coupled to a plate line (PL) 215. In block 604, the method includes forming a second ferroelectric structure Cfe2 coupled to one of the drain or source of the second transistor and further coupled to the PL. Various materials for the FE capacitor structure, the BL capacitor, and other layers are described with reference to FIGS. 2A-2B.

[0066] FIG. 7 shows a flowchart 700 for a method of forming a first ferroelectric structure or a second ferroelectric structure for a differential bit cell according to some embodiments. Although shown in a particular order, that order is not determinative. For example, some blocks or processes can be executed before others, and some can be executed in parallel or simultaneously.

[0067] In block 701, the method includes forming a first layer 211b that includes a first refractive intermetallic compound, the first layer being adjacent to a drain or source of the first transistor or the second transistor. In block 702, the method includes forming a second layer 212b that includes a first conductive oxide, the second layer being adjacent to the first layer 211b. In block 703, the method includes forming a third layer 213 that includes a perovskite material, the third layer 213 being adjacent to the second layer. In some embodiments, the perovskite material is doped with La or a lanthanide.

[0068] In block 704, the method includes forming a fourth layer 212a that includes a second conductive oxide, the fourth layer being adjacent to the third layer. The first conductive oxide or the second conductive oxide includes an oxide of one or more of Ir, Ru, Pd, Os, or Re. In block 705, the method includes forming a fifth layer 211a that includes a second refractive intermetallic compound, the fifth layer being adjacent to PL215 and adjacent to the fourth layer. The first refractive intermetallic compound and the second refractive intermetallic compound include one or more of Ti, Al, Ta, W, or Co.

[0069] In block 706, the method includes forming a sixth layer 221a that is adjacent to a first side surface of the first, second, third, fourth, and fifth layers. In block 707, the method includes forming a seventh layer 221b that is adjacent to a second side surface of the first, second, third, fourth, and fifth layers, the sixth and seventh layers including a barrier material. The barrier material includes an oxide of one or more of Ti, Al, or Mg. Various materials for the FE capacitor structure are described with reference to FIGS. 2A-2B.

[0070] FIG. 8 shows a smart memory chip 800 having an array of differential non-volatile ferroelectric bit cells and logic circuits according to some embodiments. Chip 800 includes a memory module 801 having a non-volatile differential ferroelectric DRAM (FE-DRAM) array 802, which includes the differential bit cells described with reference to various embodiments herein. Memory module 801 further includes CMOS logic 803 such as a decoder, multiplexer, and drivers for driving BL, WL, and PL. Memory module 801 further includes an input / output (IO) interface 804 used to communicate with other devices such as an artificial intelligence (AI) processor 805 (e.g., a dedicated AI processor, a graphics processor configured as an AI processor) via link 805.

[0071] References in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The appearances of "an embodiment," "one embodiment," or "some embodiments" in various places in the specification are not necessarily all referring to the same embodiment. When the specification refers to a component, feature, structure, or characteristic as being "may be included," "may be included," or "may be included," that particular component, feature, structure, or characteristic need not be included. When the specification or claims refer to an element, it does not mean only one of the elements. When the specification or claims refer to a "further" element, it does not prevent there being more than one of the further elements.

[0072] Furthermore, particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment if the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0073] Although the present disclosure has been described in connection with its particular embodiments, many alternatives, modifications, and variations of these embodiments will be apparent to those skilled in the art in light of the above description. Embodiments of the present disclosure are intended to embrace all such alternatives, modifications, and variations that fall within the broad scope of the appended claims.

[0074] Furthermore, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the presented drawings for the sake of brevity of illustration and discussion and to avoid obscuring the disclosure. Further, the configurations may be shown in block diagram form in order to avoid obscuring the present disclosure and in view of the fact that details regarding the implementation of such block diagram configurations may depend significantly on the platform on which the present disclosure is implemented (i.e., such details should be within the scope of those skilled in the art). When specific details (e.g., circuits) are described for purposes of illustrating exemplary embodiments of the present disclosure, it should be apparent to those skilled in the art that the present disclosure can be practiced without or with variations of these specific details. Accordingly, the description should be regarded as illustrative rather than limiting.

[0075] The following examples illustrate various embodiments. Any one example can be combined with other examples described herein.

[0076] Example 1: A differential bit cell, a first transistor having a gate terminal coupled to a word line (WL) and one of a source terminal or a drain terminal coupled to a first bit line (BL), a second transistor having a gate terminal coupled to the WL and one of a source terminal or a drain terminal coupled to a second bit line (BLB), where the BLB provides a signal that is the inverse of the signal on the BL, a first non-volatile structure coupled to one of the drain or source of the first transistor and further coupled to a plate line (PL), A second non-volatile structure coupled to one of the drain or source of the second transistor and further coupled to the PL, and comprising wherein each of the first non-volatile structure and the second non-volatile structure is a first layer comprising a first refractive intermetallic compound, a first layer adjacent to the drain or source of the first transistor or the second transistor, is a second layer comprising a first conductive oxide, a second layer adjacent to the first layer, is a third layer comprising a perovskite material, a third layer adjacent to the second layer, is a fourth layer comprising a second conductive oxide, a fourth layer adjacent to the third layer, is a fifth layer comprising a second refractive intermetallic compound, a fifth layer adjacent to the PL and adjacent to the fourth layer and comprising a differential bit cell.

[0077] Example 2: wherein each of the first non-volatile structure and the second non-volatile structure is a sixth layer adjacent to a first side of the first layer, the second layer, the third layer, the fourth layer and the fifth layer, and is a seventh layer adjacent to a second side of the first layer, the second layer, the third layer, the fourth layer and the fifth layer, and the sixth layer and the seventh layer comprise a barrier material, a seventh layer and comprising the differential bit cell according to Example 1.

[0078] Example 3: The differential bit cell according to Example 1, wherein the first transistor and the second transistor are of the same conductivity type.

[0079] Example 4: The differential bit cell according to Example 1, wherein the first transistor and the second transistor are one of a planar transistor or a non-planar transistor.

[0080] Example 5: The barrier material contains one or more of the oxides of Ti, Al, or Mg, or the perovskite material is doped with La or a lanthanide, or the refractive intermetallic compound contains one or more of Ti, Al, Ta, W, or Co, the differential bit cell according to Example 2.

[0081] Example 6: The first transistor and the second transistor are disposed at the back end of the die, or the transistor is disposed at the front end of the die, the differential bit cell according to Example 1.

[0082] Example 7: The first conductive oxide or the second conductive oxide contains one or more oxides of Ir, Ru, Pd, Os, or Re, the differential bit cell according to Example 1.

[0083] Example 8: The perovskite material contains one of LaCoO3, SrCoO3, SrRuO3, LaMnO3, SrMnO3, YBa2Cu3O7, Bi2Sr2CaCu2O8, or LaNiO3, the differential bit cell according to Example 1.

[0084] Example 9: The perovskite material contains one of La, Sr, Co, Ru, Mn, Y, Na, Cu, or Ni, the differential bit cell according to Example 1.

[0085] Example 10: The capacitor structure is in a cylindrical shape, the differential bit cell according to Example 1.

[0086] Example 11: The perovskite material is doped with Sc or Mn to control leakage through the third layer, the differential bit cell according to Example 1.

[0087] Example 12: The reference power line is grounded, the differential bit cell according to Example 1.

[0088] Example 13: The first transistor and the first non-volatile structure are controlled to store data of a first value, the second transistor and the second non-volatile structure are controlled to store data of a second value, and the first value is the inverse of the second value. The differential bit cell according to Example 1.

[0089] Example 14: An artificial intelligence (AI) processor, A non-volatile memory coupled to the AI processor and including differential bit cells A system comprising: One of the differential bit cells is A first transistor having a gate terminal coupled to a word line (WL) and one of a source terminal or a drain terminal coupled to a first bit line (BL), A second transistor having a gate terminal coupled to the WL and one of a source terminal or a drain terminal coupled to a second bit line (BLB), where the BLB provides a signal that is the inverse of the signal on the BL. A first non-volatile structure coupled to one of the drain or source of the first transistor and further coupled to a plate line (PL), A second non-volatile structure coupled to one of the drain or source of the second transistor and further coupled to the PL Including, Each of the first non-volatile structure and the second non-volatile structure is A first layer including a first refractive intermetallic compound, the first layer adjacent to the drain or source of the first transistor or the second transistor, A second layer including a first conductive oxide, the second layer adjacent to the first layer, A third layer including a perovskite material, the third layer adjacent to the second layer, A fourth layer including a second conductive oxide, the fourth layer adjacent to the third layer, A fifth layer comprising a second refractory intermetallic compound, the fifth layer adjacent to the PL and adjacent to the fourth layer A system comprising.

[0090] Example 15: Each of the first non-volatile structure and the second non-volatile structure A sixth layer adjacent to a first side of the first layer, the second layer, the third layer, the fourth layer and the fifth layer A seventh layer adjacent to a second side of the first layer, the second layer, the third layer, the fourth layer and the fifth layer, the sixth layer and the seventh layer comprising a barrier material, the seventh layer The system according to Example 14, comprising.

[0091] Example 16: The first transistor and the second transistor are of the same conductivity type, and the first transistor and the second transistor are one of a planar transistor or a non-planar transistor, the system according to Example 14.

[0092] Example 17: The barrier material comprises one or more of oxides of Ti, Al or Mg The perovskite material is doped with La or a lanthanide The refractory intermetallic compound comprises one or more of Ti, Al, Ta, W or Co The first conductive oxide or the second conductive oxide comprises an oxide of one or more of Ir, Ru, Pd, Os or Re, the system according to Example 14.

[0093] Example 18: The first transistor and the second transistor are disposed at the back end of the die, or the transistor is disposed at the front end of the die, the system according to Example 14.

[0094] Example 19: The perovskite material-containing system according to Example 14, which contains one of LaCoO3, SrCoO3, SrRuO3, LaMnO3, SrMnO3, YBa2Cu3O7, Bi2Sr2CaCu2O8, or LaNiO3.

[0095] Example 20: The perovskite material-containing system according to Example 14, which contains one of La, Sr, Co, Ru, Mn, Y, Na, Cu, or Ni.

[0096] Example 21: A method for forming differential bit cells, comprising: manufacturing a first transistor having a gate terminal coupled to a word line (WL) and one of a source terminal or a drain terminal coupled to a first bit line (BL); manufacturing a second transistor having a gate terminal coupled to the WL and one of a source terminal or a drain terminal coupled to a second bit line (BLB), wherein the BLB provides a signal that is the inverse of the signal on the BL; forming a first ferroelectric structure coupled to one of the drain or source of the first transistor and further coupled to a plate line (PL); forming a second ferroelectric structure coupled to one of the drain or source of the second transistor and further coupled to the PL, wherein the first ferroelectric structure and the second ferroelectric structure contain a perovskite material. A method comprising the above steps.

[0097] Example 22: The step of forming the first ferroelectric structure or the step of forming the second ferroelectric structure comprises: forming a first layer containing a first refractive intermetallic compound, wherein the first layer is adjacent to the drain or source of the first transistor or the second transistor. Forming a second layer comprising a first conductive oxide, said second layer being adjacent to said first layer, and a step; Forming a third layer comprising a perovskite material, said third layer being adjacent to said second layer, and a step; Forming a fourth layer comprising a second conductive oxide, said fourth layer being adjacent to said third layer, and a step; Forming a fifth layer comprising a second refractive intermetallic compound, said fifth layer being adjacent to said PL and adjacent to said fourth layer, and a step The method according to Example 21, comprising.

[0098] Example 23: The step of forming said first ferroelectric structure or the step of forming said second ferroelectric structure is Forming a sixth layer adjacent to a first side surface of said first layer, said second layer, said third layer, said fourth layer and said fifth layer; Forming a seventh layer adjacent to a second side surface of said first layer, said second layer, said third layer, said fourth layer and said fifth layer, said sixth layer and said seventh layer comprising a barrier material, and a step The method according to Example 22, comprising.

[0099] Example 24: Said barrier material comprises one or more of oxides of Ti, Al or Mg, Said transistor is one of a planar transistor or a non-planar transistor, Said perovskite material is doped with La or a lanthanide, Said refractive intermetallic compound comprises one or more of Ti, Al, Ta, W or Co, The method according to Example 23, wherein said first conductive oxide or said second conductive oxide comprises an oxide of one or more of Ir, Ru, Pd, Os or Re.

[0100] Example 25: A differential bit cell, A first transistor having a gate terminal coupled to a word line (WL) and one of a source terminal or a drain terminal coupled to a first bit line (BL); A second transistor having a gate terminal coupled to the WL and one of a source terminal or a drain terminal coupled to a second bit line (BLB), wherein the BLB provides a signal that is the inverse of the signal on the BL; A first non-volatile structure coupled to one of the drain or source of the first transistor and further coupled to a plate line (PL); A second non-volatile structure coupled to one of the drain or source of the second transistor and further coupled to the PL; Including; Each of the first non-volatile structure and the second non-volatile structure; A first layer including a first refractive intermetallic compound, the first layer adjacent to the drain or source of the first transistor or the second transistor; A second layer including a first conductive oxide, the second layer adjacent to the first layer; A third layer including a hexagonal ferroelectric, the third layer adjacent to the second layer; A fourth layer including a second conductive oxide, the fourth layer adjacent to the third layer; A fifth layer including a second refractive intermetallic compound, the fifth layer adjacent to the PL and adjacent to the fourth layer; Including a differential bit cell.

[0101] Example 26: Each of the first non-volatile structure and the second non-volatile structure; A sixth layer adjacent to a first side surface of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer; A seventh layer adjacent to a second side surface of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer, wherein the sixth layer and the seventh layer include a barrier material; Including the differential bit cell according to Example 25.

[0102] Example 27: The differential bit cell according to Example 26, wherein the first transistor and the second transistor have the same conductivity type.

[0103] Example 28: The differential bit cell according to Example 25, wherein the first transistor and the second transistor are one of a planar transistor or a non-planar transistor.

[0104] Example 29: The differential bit cell according to Example 26, wherein the barrier material includes one or more of oxides of Ti, Al, or Mg.

[0105] Example 30: The differential bit cell according to Example 26, wherein the refractive intermetallic compound includes one or more of Ti, Al, Ta, W, or Co.

[0106] Example 31: The differential bit cell according to Example 26, wherein the first transistor and the second transistor are disposed at the back end of the die, or the transistor is disposed at the front end of the die.

[0107] Example 32: The differential bit cell according to Example 26, wherein the first conductive oxide or the second conductive oxide includes In2O3, Fe2O3, Fe3O4, PtCoO3, PdCoO2, Al-doped ZnO, or Sn-doped In2O3.

[0108] Example 33: The differential bit cell according to Example 26, wherein the hexagonal ferroelectric includes one of YMNO3 or LuFeO3.

[0109] Example 34: The hexagonal ferroelectric is of the h-RMnO3 type, where R is a rare earth element including one of cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y), the differential bit cell according to Example 26.

[0110] Example 35: The capacitor structure is cylindrical in shape, the differential bit cell according to Example 26.

[0111] Example 36: The reference power line is grounded, the differential bit cell according to Example 26.

[0112] Example 37: The first transistor, the first capacitor, and the first non-volatile structure are controlled to store data of a first value, the second transistor, the second capacitor, and the second non-volatile structure are controlled to store data of a second value, and the first value is the inverse of the second value, the differential bit cell according to Example 26.

[0113] Example 38: An artificial intelligence (AI) processor, A non-volatile memory coupled to the AI processor and including differential bit cells A system including One of the differential bit cells is A first transistor having a gate terminal coupled to a word line (WL) and one of a source terminal or a drain terminal coupled to a first bit line (BL), A second transistor having a gate terminal coupled to the WL and one of a source terminal or a drain terminal coupled to a second bit line (BLB), where the BLB provides a signal that is the inverse of the signal on the BL, A first non-volatile structure coupled to one of the drain or source of the first transistor and further coupled to a plate line (PL); A second non-volatile structure coupled to one of the drain or source of the second transistor and further coupled to the PL and comprising each of the first non-volatile structure and the second non-volatile structure is a first layer including a first refractive intermetallic compound, a first layer adjacent to the drain or source of the first transistor or the second transistor; is a second layer including a first conductive oxide, a second layer adjacent to the first layer; is a third layer including a hexagonal ferroelectric, a third layer adjacent to the second layer; is a fourth layer including a second conductive oxide, a fourth layer adjacent to the third layer; is a fifth layer including a second refractive intermetallic compound, a fifth layer adjacent to the PL and adjacent to the fourth layer and a system.

[0114] Example 39: each of the first non-volatile structure and the second non-volatile structure is a sixth layer adjacent to a first side surface of the first layer, the second layer, the third layer, the fourth layer and the fifth layer; is a seventh layer adjacent to a second side surface of the first layer, the second layer, the third layer, the fourth layer and the fifth layer, and the sixth layer and the seventh layer include a barrier material, and a seventh layer and a system according to Example 38.

[0115] Example 40: The first transistor and the second transistor are of the same conductivity type, and the first transistor and the second transistor are one of a planar transistor or a non-planar transistor, and a system according to Example 38.

[0116] Example 41: The barrier material is the system according to Example 39, including one or more of oxides of Ti, Al, or Mg.

[0117] Example 42: The refractive intermetallic compound is the system according to Example 38, including one or more of Ti, Al, Ta, W, or Co.

[0118] Example 43: The first conductive oxide or the second conductive oxide is the system according to Example 38, including one or more oxides of In2O3, Fe2O3, Fe3O4, PtCoO3, PdCoO2, Al-doped ZnO, or Sn-doped In2O3.

[0119] Example 44: The first transistor and the second transistor are the system according to Example 38, which are arranged at the back end of the die, or the transistor is arranged at the front end of the die.

[0120] Example 45: The hexagonal ferroelectric is the system according to Example 38, including one of YMNO3 or LuFeO3.

[0121] Example 46: The hexagonal ferroelectric is of the h-RMnO3 type, and R is a rare earth element including one of cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y), which is the system according to Example 38.

[0122] Example 47: A method for forming a differential bit cell, A step of manufacturing a first transistor having a gate terminal coupled to a word line (WL) and one of a source terminal or a drain terminal coupled to a first bit line (BL); A step of manufacturing a second transistor having a gate terminal coupled to the WL and one of a source terminal or a drain terminal coupled to a second bit line (BLB), wherein the BLB provides a signal that is the inverse of the signal on the BL; A step of forming a first ferroelectric structure coupled to one of the drain or source of the first transistor and further coupled to a plate line (PL); A step of forming a second ferroelectric structure coupled to one of the drain or source of the second transistor and further coupled to the PL, wherein the first ferroelectric structure and the second ferroelectric structure include a hexagonal ferroelectric; A method comprising the above steps.

[0123] Example 48: The step of forming the first ferroelectric structure or the step of forming the second ferroelectric structure includes: A step of forming a first layer including a first refractive intermetallic compound, wherein the first layer is adjacent to the drain or source of the first transistor or the second transistor; A step of forming a second layer including a first conductive oxide, wherein the second layer is adjacent to the first layer; A step of forming a third layer including a hexagonal ferroelectric, wherein the third layer is adjacent to the second layer; A step of forming a fourth layer including a second conductive oxide, wherein the fourth layer is adjacent to the third layer; A step of forming a fifth layer including a second refractive intermetallic compound, wherein the fifth layer is adjacent to the PL and adjacent to the fourth layer; The method according to Example 47, comprising the above steps.

[0124] Example 49: The step of forming the first ferroelectric structure or the step of forming the second ferroelectric structure is forming a sixth layer adjacent to a first side surface of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer; forming a seventh layer adjacent to a second side surface of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer, wherein the sixth layer and the seventh layer include a barrier material; The method according to Example 48, comprising

[0125] Example 50: A differential bit cell, comprising a first transistor having a gate terminal coupled to a word line (WL) and one of a source terminal or a drain terminal coupled to a first bit line (BL); a second transistor having a gate terminal coupled to the WL and one of a source terminal or a drain terminal coupled to a second bit line (BLB), wherein the BLB provides a signal that is the inverse of the signal on the BL; a first non-volatile structure coupled to one of the drain or source of the first transistor and further coupled to a plate line (PL); a second non-volatile structure coupled to one of the drain or source of the second transistor and further coupled to the PL; wherein each of the first non-volatile structure and the second non-volatile structure includes a first layer including a first refractive intermetallic compound, the first layer adjacent to the drain or source of the first transistor or the second transistor; a second layer including a first conductive oxide, the second layer adjacent to the first layer; a third layer including an irregular ferroelectric, the third layer adjacent to the second layer; a fourth layer including a second conductive oxide, the fourth layer adjacent to the third layer; A fifth layer comprising a second refractory intermetallic compound, the fifth layer adjacent to the PL and adjacent to the fourth layer A differential bit cell comprising

[0126] Example 51: Each of the first non-volatile structure and the second non-volatile structure A sixth layer adjacent to a first side of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer A seventh layer adjacent to a second side of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer, the sixth layer and the seventh layer comprising a barrier material, the seventh layer The differential bit cell according to Example 50, comprising

[0127] Example 52: The differential bit cell according to Example 51, wherein the first transistor and the second transistor are of the same conductivity type

[0128] Example 53: The differential bit cell according to Example 51, wherein the first transistor and the second transistor are one of a planar transistor or a non-planar transistor

[0129] Example 54: The differential bit cell according to Example 53, wherein the barrier material comprises one or more of oxides of Ti, Al, or Mg

[0130] Example 55: The differential bit cell according to Example 51, wherein the refractory intermetallic compound comprises one or more of Ti, Al, Ta, W, or Co

[0131] Example 56: The differential bit cell according to Example 51, wherein the first transistor and the second transistor are disposed at the back end of the die, or the transistor is disposed at the front end of the die

[0132] Example 57: The first conductive oxide or the second conductive oxide includes In2O3, Fe2O3, Fe3O4, PtCoO3, PdCoO2, Al-doped ZnO, or Sn-doped In2O3, and is the differential bit cell described in Example 51.

[0133] Example 58: The ferroelectric random access memory includes one of [PTO / STO]n or [LAO / STO]n, where "n" ranges from 1 to 100, and is the differential bit cell described in Example 51.

[0134] Example 59: The capacitor structure has a cylindrical shape and is the differential bit cell described in Example 51.

[0135] Example 60: The reference power line is grounded, and is the differential bit cell described in Example 51.

[0136] Example 61: The first transistor, the first capacitor, and the first non-volatile structure are controlled to store data of a first value, the second transistor, the second capacitor, and the second non-volatile structure are controlled to store data of a second value, and the first value is the inverse of the second value, and is the differential bit cell described in Example 51.

[0137] Example 62: An artificial intelligence (AI) processor, A non-volatile memory coupled to the AI processor and including differential bit cells A system including: One of the differential bit cells includes A first transistor having a gate terminal coupled to a word line (WL) and one of a source terminal or a drain terminal coupled to a first bit line (BL); A second transistor having a gate terminal coupled to the WL and one of a source terminal or a drain terminal coupled to a second bit line (BLB), where the BLB provides a signal that is the inverse of the signal on the BL. A first non-volatile structure coupled to one of the drain or source of the first transistor and further coupled to a plate line (PL); A second non-volatile structure coupled to one of the drain or source of the second transistor and further coupled to the PL comprising Each of the first non-volatile structure and the second non-volatile structure is a first layer including a first refractive intermetallic compound, a first layer adjacent to the drain or source of the first transistor or the second transistor; is a second layer including a first conductive oxide, a second layer adjacent to the first layer; is a third layer including an irregular ferroelectric, a third layer adjacent to the second layer; is a fourth layer including a second conductive oxide, a fourth layer adjacent to the third layer; is a fifth layer including a second refractive intermetallic compound, a fifth layer adjacent to the PL and adjacent to the fourth layer A system comprising.

[0138] Example 63: Each of the first non-volatile structure and the second non-volatile structure is a sixth layer adjacent to a first side surface of the first layer, the second layer, the third layer, the fourth layer and the fifth layer; is a seventh layer adjacent to a second side surface of the first layer, the second layer, the third layer, the fourth layer and the fifth layer, and the sixth layer and the seventh layer include a barrier material, a seventh layer The system according to Example 62, comprising.

[0139] Example 64: The system according to Example 63, wherein the first transistor and the second transistor have the same conductivity type, and the first transistor and the second transistor are one of a planar transistor or a non-planar transistor.

[0140] Example 65: The barrier material is a system according to Example 63, including one or more of oxides of Ti, Al, or Mg.

[0141] Example 66: The refractive intermetallic compound is a system according to Example 63, including one or more of Ti, Al, Ta, W, or Co.

[0142] Example 67: The first conductive oxide or the second conductive oxide is a system according to Example 63, including one or more oxides of In2O3, Fe2O3, Fe3O4, PtCoO3, PdCoO2, Al-doped ZnO, or Sn-doped In2O3.

[0143] Example 68: The first transistor and the second transistor are a system according to Example 63, which are arranged at the back end of the die, or the transistor is arranged at the front end of the die.

[0144] Example 69: The ferroelectric random access memory includes one of [PTO / STO]n or [LAO / STO]n, where "n" ranges from 1 to 100, which is a system according to Example 63.

[0145] Example 70: A method for forming a differential bit cell, manufacturing a first transistor having a gate terminal coupled to a word line (WL) and one of a source terminal or a drain terminal coupled to a first bit line (BL); manufacturing a second transistor having a gate terminal coupled to the WL and one of a source terminal or a drain terminal coupled to a second bit line (BLB), where the BLB provides a signal that is the inverse of the signal on the BL; forming a first ferroelectric structure coupled to one of the drain or source of the first transistor and further coupled to a plate line (PL); Forming a second ferroelectric structure coupled to one of the drain or source of the second transistor and further coupled to the PL, wherein the first ferroelectric structure and the second ferroelectric structure include an irregular ferroelectric, and A method comprising.

[0146] Example 71: The step of forming the first ferroelectric structure or the step of forming the second ferroelectric structure is Forming a first layer including a first refractive intermetallic compound, the first layer being adjacent to the drain or source of the first transistor or the second transistor, and Forming a second layer including a first conductive oxide, the second layer being adjacent to the first layer, and Forming a third layer including a hexagonal ferroelectric, the third layer being adjacent to the second layer, and Forming a fourth layer including a second conductive oxide, the fourth layer being adjacent to the third layer, and Forming a fifth layer including a second refractive intermetallic compound, the fifth layer being adjacent to the PL and adjacent to the fourth layer, and The method according to Example 70, comprising.

[0147] Example 72: The step of forming the first ferroelectric structure or the step of forming the second ferroelectric structure is Forming a sixth layer adjacent to a first side surface of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer, and Forming a seventh layer adjacent to a second side surface of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer, wherein the sixth layer and the seventh layer include a barrier material, and The method according to Example 71, comprising.

[0148] Example 73: A capacitor structure, a first structure containing a refractive intermetallic compound, the first structure adjacent to the source or drain of a transistor, and a second structure containing a first conductive oxide, and a third structure containing a ferroelectric material, the third structure adjacent to the second structure, and a fourth structure containing a second conductive oxide, the fourth structure adjacent to the third structure, the third structure being between the second structure and the fourth structure, the fourth structure, and a fifth structure containing a refractive intermetallic compound, the fifth structure adjacent to the fourth structure, and a sixth structure adjacent to a first side surface of the first structure, the second structure, the third structure, the fourth structure, and the fifth structure, and a seventh structure adjacent to a second side surface of the first structure, the second structure, the third structure, the fourth structure, and the fifth structure, the sixth structure and the seventh structure containing a barrier material, the seventh structure comprising a capacitor structure.

[0149] Example 74: The capacitor structure according to Example 73, wherein the ferroelectric material is one of a perovskite material, a hexagonal ferroelectric, or a random ferroelectric.

[0150] Example 75: The ferroelectric material is a perovskite material containing one of LaCoO3, SrCoO3, SrRuO3, LaMnO3, SrMnO3, YBa2Cu3O7, Bi2Sr2CaCu2O8, or LaNiO3, a hexagonal ferroelectric containing one of YMnO3 or LuFeO3, A hexagonal ferroelectric of the h-RMnO3 type, where R is a rare earth element, i.e., cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb) or yttrium (Y), or An irregular ferroelectric containing one of [PTO / STO]n or [LAO / STO]n, where "n" ranges from 1 to 100, the irregular ferroelectric The capacitor structure according to Example 74, containing one of them.

[0151] Example 76: The capacitor structure according to Example 73, where the barrier material contains one or more of the oxides of Ti, Al or Mg.

[0152] Example 77: The capacitor structure according to Example 73, where the first refractive intermetallic compound or the second refractive intermetallic compound contains one or more of Ti, Al, Ta, W or Co.

[0153] Example 78: The first conductive oxide and the second conductive oxide are When the ferroelectric material is a perovskite material, Ir, Ru, Pd, Os or Re, When the ferroelectric material is a hexagonal ferroelectric, PtCo, PdCo, a hexagonal metal of the delafossite structure, Fe, LiV, or InTi The capacitor structure according to Example 73, containing one of the oxides.

[0154] Example 79: The capacitor structure according to Example 73, where the ferroelectric material is doped with Sc or Mn to control the leakage through the ferroelectric material.

[0155] Example 80: A method for forming a capacitor structure, comprising: forming a first structure comprising a refractive intermetallic compound, the first structure being adjacent to a source or drain of a transistor; forming a second structure comprising a first conductive oxide; forming a third structure comprising a ferroelectric material, the third structure being adjacent to the second structure; forming a fourth structure comprising a second conductive oxide, the fourth structure being adjacent to the third structure, and the third structure being between the second structure and the fourth structure; forming a fifth structure comprising a refractive intermetallic compound, the fifth structure being adjacent to the fourth structure; forming a sixth structure adjacent to a first side surface of the first structure, the second structure, the third structure, the fourth structure, and the fifth structure; forming a seventh structure adjacent to a second side surface of the first structure, the second structure, the third structure, the fourth structure, and the fifth structure, the sixth structure and the seventh structure comprising a barrier material; and a method comprising the steps of:

[0156] Example 81: The method according to Example 80, wherein the ferroelectric material is one of a perovskite material, a hexagonal ferroelectric, or a random ferroelectric.

[0157] Example 82: The ferroelectric material is a perovskite material containing one of LaCoO3, SrCoO3, SrRuO3, LaMnO3, SrMnO3, YBa2Cu3O7, Bi2Sr2CaCu2O8, or LaNiO3; a hexagonal ferroelectric containing one of YMnO3 or LuFeO3; A hexagonal ferroelectric of the h-RMnO3 type, where R is a rare earth element, i.e., cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y), or An irregular ferroelectric containing one of [PTO / STO]n or [LAO / STO]n, where "n" is from 1 to 100, the irregular ferroelectric One of the methods according to Example 81.

[0158] Example 83: The method according to Example 81, wherein the barrier material contains one or more of oxides of Ti, Al, or Mg.

[0159] Example 84: The method according to Example 80, wherein the first refractive intermetallic compound or the second refractive intermetallic compound contains one or more of Ti, Al, Ta, W, or Co.

[0160] Example 85: The first conductive oxide and the second conductive oxide are When the ferroelectric material is a perovskite material, Ir, Ru, Pd, Os, or Re, When the ferroelectric material is a hexagonal ferroelectric, PtCo, PdCo, a hexagonal metal of the delafossite structure, Fe, LiV, or InTi One of the methods according to Example 80, which contains an oxide of one of them.

[0161] Example 86: The method according to Example 80, wherein the ferroelectric material is doped with Sc or Mn to control leakage through the ferroelectric material.

[0162] Example 87: A memory including a capacitor structure, and an artificial intelligence (AI) processor coupled to the memory, and A system comprising: wherein the capacitor structure is a first structure including a refractive intermetallic compound, the first structure adjacent to a source or drain of a transistor, and a second structure including a first conductive oxide, and a third structure including a ferroelectric material, the third structure adjacent to the second structure, and a fourth structure including a second conductive oxide, the fourth structure adjacent to the third structure, the third structure being between the second structure and the fourth structure, a fourth structure, and a fifth structure including a refractive intermetallic compound, the fifth structure adjacent to the fourth structure, and a sixth structure adjacent to a first side surface of the first structure, the second structure, the third structure, the fourth structure, and the fifth structure, and a seventh structure adjacent to a second side surface of the first structure, the second structure, the third structure, the fourth structure, and the fifth structure, the sixth structure and the seventh structure including a barrier material, a seventh structure Including the system.

[0163] Example 88: The system according to Example 87, wherein the ferroelectric material is one of a perovskite material, a hexagonal ferroelectric, or a random ferroelectric.

[0164] Example 89: The ferroelectric material is a perovskite material including one of LaCoO3, SrCoO3, SrRuO3, LaMnO3, SrMnO3, YBa2Cu3O7, Bi2Sr2CaCu2O8, or LaNiO3, a hexagonal ferroelectric including one of YMnO3 or LuFeO3, It is a hexagonal ferroelectric of the h-RMnO3 type, where R is a rare earth element, i.e., cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb) or yttrium (Y), a hexagonal ferroelectric, or An irregular ferroelectric containing one of [PTO / STO]n or [LAO / STO]n, where "n" is from 1 to 100, an irregular ferroelectric The system according to Example 88, containing one of them.

[0165] Example 90: The system according to Example 88, where the barrier material contains one or more of the oxides of Ti, Al or Mg.

[0166] Example 91: The system according to Example 88, where the first refractive intermetallic compound or the second refractive intermetallic compound contains one or more of Ti, Al, Ta, W or Co.

[0167] Example 92: The first conductive oxide and the second conductive oxide are When the ferroelectric material is a perovskite material, Ir, Ru, Pd, Os or Re, When the ferroelectric material is a hexagonal ferroelectric, PtCo, PdCo, a hexagonal metal with a delafossite structure, Fe, LiV, or InTi The system according to Example 88, containing one of the oxides.

[0168] The abstract is provided to enable the reader to confirm the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it is not to be used to limit the scope or meaning of the claims. The following claims are incorporated into the detailed description, and each claim exists as a separate embodiment in itself.

Claims

1. A processor circuit; a non-volatile memory coupled to the processor circuit; A system comprising: the non-volatile memory includes differential bit cells; One of the differential bit cells is The two bit cells have a first bit line (BL), a second bit line (BLB), a word line (WL), and a shared plate line (PLP) shared between the two bit cells; each of the two bit cells includes a corresponding non-volatile structure; The corresponding non-volatile structure comprises: a ferroelectric material; A first layer; a second layer or a fourth layer comprising a first conductive oxide or a second conductive oxide, respectively; a third layer comprising the ferroelectric material; and The fifth layer, a sixth layer adjacent to a first side of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer; and a seventh layer adjacent to a second side of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer; Including, the sixth layer and the seventh layer comprise a barrier material having a first lattice parameter that substantially matches a second lattice parameter of the first conductive oxide, the second conductive oxide, or the ferroelectric material.

2. The system of claim 1 , wherein the corresponding non-volatile structure can switch its state with a voltage of about 100 mV.

3. The system of claim 1 , wherein the differential bitcells are configured to compensate for asymmetries in the corresponding non-volatile structures.

4. the first layer includes a first refractive intermetallic material, the first layer is adjacent to a drain or a source of a transistor of one of the two bit cells; the second layer is adjacent to the first layer, and the third layer is adjacent to the second layer; the fourth layer is adjacent to the third layer; The system of claim 1 , wherein the fifth layer comprises a second refractive intermetallic material, the fifth layer adjacent to the shared PL and adjacent to the fourth layer.

5. 10. The system of claim 1, wherein the ferroelectric material is doped with Sc or Mn dopants to control leakage through the third layer.

6. The system of claim 5 , wherein the Sc or Mn dopant achieves a spontaneous strain in the ferroelectric material in the range of 0.3% to 2%.

7. the barrier material comprises one or more of an oxide of Ti, Al or Mg; the first or second refractive intermetallic material comprises one or more of Ti, Al, Ta, W, Co, Ni, Ga, Mn, B, C, N, or Fe; The first or second conductive oxide is In 2 O 3 , Fe 2 O 3 , Fe 3 O 4 , PtCoO 3 , PdCoO 2 , Al-doped ZnO or Sn-doped In 2 O 3 The system of claim 4 , further comprising one or more oxides of

8. The system of claim 1 , wherein the first lattice parameter substantially matches the second lattice parameter of the first or second conductive oxide.

9. The system of claim 1 , wherein the first lattice parameter substantially matches the second lattice parameter of the ferroelectric material.

10. 5. The system of claim 4, wherein the barrier material is adjacent to the first refractive intermetallic material, the barrier material comprising one or more of an oxide of Ti, Al, or Mg.

11. The system of claim 1 , wherein the differential bit cells are organized in rows or columns.

12. 2. The system of claim 1, wherein the processor circuitry includes an address decoder, a sense amplifier, and a write driver.

13. The ferroelectric material is ABO where "A" and "B" are two cations of different sizes and "O" is oxygen, an anion that binds to the two cations. 3 a first perovskite material of the type a second perovskite material comprising one or more of La, Sr, Co, Sr, Ru, Y, Ba, Cu, Bi, Ca, or Ni; (La,Sr)CoO 3 , SrRuO 3 , (La,Sr)MnO 3 , YBa 2 Cu 3 O 7 , Bi 2 Sr 2 CaCu 2 O 8 or LaNiO 3 or a third perovskite material comprising one or more of: Hexagonal ferroelectrics of h-RMnO3 type, where R is a rare earth element including one of cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb) or yttrium (Y). The system of claim 1 , further comprising one of:

14. 1. A method for forming a differential bit cell, comprising: forming a differential bit cell having a first bit cell and a second bit cell; coupling the first bit cell to a first bit line; coupling the second bit cell to a second bit line; coupling the first bit cell and the second bit cell to a word line; coupling the first bit cell and the second bit cell to a plate line shared between the first bit cell and the second bit cell; forming a first ferroelectric structure coupled to a first transistor of the first bit cell and further coupled to the plate line; forming a second ferroelectric structure coupled to a second transistor of the second bit cell and further coupled to the plate line; Including, The first and second ferroelectric structures include a ferroelectric material; A first layer; a second layer or a fourth layer comprising a first conductive oxide or a second conductive oxide, respectively; a third layer comprising the ferroelectric material; and The fifth layer, a sixth layer adjacent to a first side of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer; and a seventh layer adjacent to a second side of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer; Including, the sixth layer and the seventh layer comprise a barrier material having a first lattice parameter that substantially matches a second lattice parameter of the first conductive oxide, the second conductive oxide, or the ferroelectric material.

15. The step of forming a differential bit cell comprises: fabricating the first transistor having a gate terminal coupled to a word line; coupling one of a source terminal or a drain terminal of the first transistor to the first bit line; fabricating the second transistor having a gate terminal coupled to the word line; coupling one of the source or drain terminals of the second transistor to the second bit line, the second bit line providing a signal that is the inverse of the signal on the first bit line; 15. The method of claim 14, comprising:

16. the first layer includes a first refractive intermetallic material, the first layer adjacent the drain terminal or the source terminal of the first transistor; the second layer is adjacent to the first layer, and the third layer is adjacent to the second layer; the fourth layer is adjacent to the third layer; 16. The method of claim 15, wherein the fifth layer comprises a second refractive intermetallic material, the fifth layer adjacent the plate line and adjacent the fourth layer.

17. the barrier material comprises one or more of an oxide of Ti, Al or Mg; the first refractive intermetallic material or the second refractive intermetallic material comprises one or more of Ti, Al, Ta, W, Co, Ni, Ga, Mn, B, C, N, or Fe; The first or second conductive oxide is In 2 O 3 , Fe 2 O 3 , Fe 3 O 4 , PtCoO 3 , PdCoO 2 , Al-doped ZnO or Sn-doped In 2 O 3 The method of claim 16 , further comprising the step of:

18. The ferroelectric material is ABO where "A" and "B" are two cations of different sizes and "O" is oxygen, an anion that binds to the two cations. 3 a first perovskite material of the type a second perovskite material comprising one or more of La, Sr, Co, Sr, Ru, Y, Ba, Cu, Bi, Ca, or Ni; (La,Sr)CoO 3 , SrRuO 3 , (La,Sr)MnO 3 , YBa 2 Cu 3 O 7 , Bi 2 Sr 2 CaCu 2 O 8 or LaNiO 3 or a third perovskite material comprising one or more of: Hexagonal ferroelectrics of h-RMnO3 type, where R is a rare earth element including one of cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb) or yttrium (Y). The method of claim 14, comprising one of:

19. a first bitcell including a first ferroelectric capacitor controllable by a word line and a first transistor, the first transistor coupled to a first bitline and a plateline; a second bit cell including a second ferroelectric capacitor and a second transistor controllable by the word line, the first transistor being coupled to a second bit line and the plate line; An apparatus comprising: the plate line is shared between the first bit cell and the second bit cell, the first bit line carries a first signal, the second bit line carries a second signal, the second signal being an inverse of the first signal, and the first ferroelectric capacitor or the second ferroelectric capacitor is A first layer; a second layer or a fourth layer comprising a first conductive oxide or a second conductive oxide, respectively; a third layer comprising a ferroelectric material; The fifth layer, a sixth layer adjacent to a first side of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer; and a seventh layer adjacent to a second side of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer; Including, the sixth layer and the seventh layer comprise a barrier material having a first lattice parameter that substantially matches a second lattice parameter of the first conductive oxide, the second conductive oxide, or the ferroelectric material.

20. the first layer includes a first refractive intermetallic material, the first layer is adjacent to a drain or a source of the first transistor; the second layer is adjacent to the first layer, and the third layer is adjacent to the second layer; the fourth layer is adjacent to the third layer; 20. The device of claim 19, wherein the fifth layer comprises a second refractive intermetallic material, the fifth layer adjacent the plate line and adjacent the fourth layer.

21. 20. The apparatus of claim 19, wherein the first bitcell and the second bitcell are configured to compensate for an asymmetry in the first ferroelectric capacitor and the second ferroelectric capacitor.

22. 20. The device of claim 19, wherein the ferroelectric material is doped with Sc or Mn dopants to control leakage through the third layer.

23. 23. The device of claim 22, wherein the Sc or Mn dopant achieves a spontaneous strain in the ferroelectric material in the range of 0.3% to 2%.

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