Display board and display device

Abstract

To provide a display board and a display device.SOLUTION: A display board has a first side and a second side for display, includes a base board, and comprises a base board, and a display area including a first display area and a second display area, the first display area including multiple pixel unit groups, each of the multiple pixel unit groups including first multiple pixel units, each of the first multiple pixel units including a pixel area and an opening area, first multiple power lines positioned in the pixel area, and a shielding layer including a hollow area and a shielding area. For one pixel unit group, the opening areas of the first respective pixel units overlap with the shielding area of the shielding layer at least locally; the opening area of at least one first pixel unit includes a first shielding connection section overlapping with the shielding area of the shielding layer at least locally; and the shielding layer is connected to at least one first power line from among first multiple power lines via the first shielding connection section.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] This disclosure claims the priority of Chinese Patent Application No. 202010623663.4 filed on June 30, 2020, and the entire content disclosed in the above Chinese patent application is incorporated herein by reference in its entirety.

[0002] At least one embodiment of this disclosure relates to a display substrate and a display device.

Background Art

[0003] Based on the design of an under-screen camera, a display panel generally includes a high pixel density (Pixels Per Inch, PPI) region and a low PPI region. However, in a general display panel, the light transmittance of the low PPI region is low, which is disadvantageous for improving the display effect in the imaging region.

Summary of the Invention

Means for Solving the Problems

[0004] At least one embodiment of the present disclosure provides a display substrate having a first side for display and a second side facing the first side. The display substrate includes a base substrate and a display area installed on the base substrate and including a first display area and a second display area at least locally surrounding the first display area. The first display area enables light from the first side of the display substrate to at least partially transmit through the second side of the display substrate for detection. The first display area includes a plurality of pixel unit groups arranged at intervals. Each of the plurality of pixel unit groups includes a plurality of first pixel units. Each of the plurality of first pixel units includes a display area including a pixel area and an opening area, a plurality of first power lines located in the pixel area and connected to the plurality of pixel unit groups and configured to provide a first power supply voltage to the plurality of pixel unit groups, and a shielding layer installed on the base substrate and located on a side of the first power lines close to the base substrate and including a hollow area and a shielding area. For one pixel unit group, the opening area of each first pixel unit at least locally overlaps with the shielding area of the shielding layer. The opening area of the at least one first pixel unit includes a first shielding connection portion that at least locally overlaps with the shielding area of the shielding layer. The shielding layer is connected to at least one of the plurality of first power lines through the first shielding connection portion to receive the first power supply voltage. The plurality of first power lines are located on a side of the first shielding connection portion away from the base substrate, the shielding layer is located on a side of the first shielding connection portion close to the base substrate, and the first shielding connection portion is located between the shielding layer and the plurality of first power lines.

[0005] For example, in the display substrate according to at least one embodiment of the present disclosure, the shielding layer is connected to the first shielding connection portion through a first through hole, and the first shielding connection portion is connected to the at least one first power line through a second through hole.

[0006] For example, in a display substrate according to at least one embodiment of the present disclosure, the display substrate further includes a first insulating layer, a second insulating layer, and a third insulating layer. The first insulating layer is located between the shielding layer and the first shielding connection portion. The second insulating layer is located between the first insulating layer and the first shielding connection portion. The third insulating layer is located between the first shielding connection portion and the plurality of first power lines, or the second insulating layer is located between the first shielding connection portion and the plurality of first power lines, and the third insulating layer is located between the second insulating layer and the plurality of first power lines. The shielding layer is connected to the first shielding connection portion through a first through hole penetrating the first insulating layer. The first shielding connection portion is connected to the at least one first power line through a second through hole penetrating the second insulating layer and the third insulating layer, or the shielding layer is connected to the first shielding connection portion through a first through hole penetrating the first insulating layer and the second insulating layer, and the first shielding connection portion is connected to the at least one first power line through a second through hole penetrating the third insulating layer.

[0007] For example, in a display substrate according to at least one embodiment of the present disclosure, a positive projection of the first through hole on the base substrate does not overlap with a positive projection of the second through hole on the base substrate. The first power line includes a protruding portion. A positive projection of the second through hole on the base substrate overlaps with a positive projection of the protruding portion on the base substrate. A positive projection of the first through hole on the base substrate overlaps with a positive projection of the first power line on the base substrate.

[0008] For example, in a display substrate according to at least one embodiment of the present disclosure, adjacent pixel unit groups are connected through wirings. Positive projections of the plurality of pixel unit groups on the base substrate and a positive projection of the wiring on the base substrate fall within a positive projection of a shielding region of the shielding layer.

[0009] For example, in a display substrate according to at least one embodiment of the present disclosure, the second display region includes a plurality of second pixel units arranged in an array and a plurality of second power lines. Each of the plurality of second pixel units includes a pixel region and an opening region. The plurality of second power lines are connected to the plurality of second pixel units and are configured to provide the same second power voltage as the first power voltage to the plurality of second pixel units. For one second pixel unit, the opening region of each second pixel unit at least partially overlaps with the shielding region of the shielding layer, and the opening region of the at least one second pixel unit includes a second shielding connection portion that at least partially overlaps with the shielding region of the shielding layer.

[0010] For example, in a display substrate according to at least one embodiment of the present disclosure, the orthographic projection of the second display region on the base substrate falls within the orthographic projection of the shielding region of the shielding layer on the base substrate.

[0011] For example, in a display substrate according to at least one embodiment of the present disclosure, each of the plurality of first pixel units and the plurality of second pixel units includes a pixel driving circuit configured to drive the light-emitting device to emit light and a light-emitting device.

[0012] For example, in a display substrate according to at least one embodiment of the present disclosure, the pixel driving circuit includes a driving transistor, a data writing transistor, a compensation transistor, a first light emission control transistor, a second light emission control transistor, a first reset transistor, a second reset transistor, and a storage capacitor. The active layers of the first reset transistor, the compensation transistor, the second light emission control transistor, and the second reset transistor are located in a first semiconductor layer extending along a first direction. The active layers of the data writing transistor and the first light emission control transistor are located in a second semiconductor layer extending along a second direction. The first semiconductor layer is connected to and integrally formed with the second semiconductor layer and the active layer of the driving transistor via the active layer of the driving transistor. The active layer of the driving transistor is located on a virtual line in the first direction of the active layer of the first reset transistor. The active layers of the compensation transistor and the data writing transistor are located on both sides of the active layer of the driving transistor, respectively, and are located on the side of the active layer of the driving transistor close to the active layer of the first reset transistor. The active layers of the second light emission control transistor and the first light emission control transistor are located on both sides of the active layer of the driving transistor, respectively, and are located on the side of the active layer of the driving transistor away from the active layer of the first reset transistor. The active layer of the second reset transistor is located on the side of the active layer of the second light emission control transistor away from the active layer of the compensation transistor. The compensation transistor includes a first gate extending along the first direction and a second gate extending along the second direction. The second gate is arranged in parallel in the first direction with the gate of the second light emission control transistor extending along the second direction, the gate of the second reset transistor, and the first direction. The gate of the data writing transistor extends along the second direction and is arranged in parallel in the first direction with the gate of the first light emission control transistor. The gate of the first reset transistor extends along the second direction and is arranged in parallel in the first direction with the gate of the driving transistor. The gate of the driving transistor is integrally formed with the first electrode plate of the storage capacitor.

[0013] For example, a display substrate according to at least one embodiment of the present disclosure further includes a gate line, a light emission control signal line, a first reset signal line, and a second reset signal line that extend along the second direction. The gate of the first reset transistor is connected to and integrally formed with the first reset signal line. The second gate of the compensation transistor and the gate of the data writing transistor are connected to and integrally formed with the gate line. The gate of the second light emission control transistor and the gate of the first light emission control transistor are connected to and integrally formed with the light emission control signal line. The gate of the second reset transistor is connected to and integrally formed with the second reset signal line.

[0014] For example, a display substrate according to at least one embodiment of the present disclosure further includes a data line connected to the active layer of the data writing transistor and configured to provide a data signal. The orthographic projection of the first power supply line on the base substrate at least partially overlaps with the orthographic projection of the active layer of the first reset transistor and the orthographic projection of the active layer of the driving transistor on the base substrate. The orthographic projection of the data line on the base substrate is located on the side away from the orthographic projection of the first power supply line of the orthographic projection of the second semiconductor layer on the base substrate.

[0015] For example, in a display substrate according to at least one embodiment of the present disclosure, the pixel driving circuit further includes a first via electrode connected to the active layer of the second light emission control transistor, the active layer of the second reset transistor, and the first electrode of the light emitting device through a through hole. The orthographic projection of the first via electrode on the base substrate is located between the orthographic projection of the active layer of the second reset transistor and the orthographic projection of the active layer of the driving transistor on the base substrate.

[0016] For example, in a display substrate according to at least one embodiment of the present disclosure, for each of the plurality of second pixel units, the orthographic projection of the second shielding connection portion on the base substrate is located between the orthographic projection of the active layer of the second reset transistor on the base substrate and the orthographic projection of the second power line on the base substrate, and at least partially overlaps with the orthographic projection of the second power line on the base substrate.

[0017] For example, in a display substrate according to at least one embodiment of the present disclosure, for each pixel unit group, the first shielding connection portion is located between two adjacent first pixel units in the first direction in each pixel unit group.

[0018] For example, in a display substrate according to at least one embodiment of the present disclosure, the orthographic projection of the first shielding connection portion on the base substrate is located between the orthographic projection of the active layer of the second reset transistor on the base substrate and the orthographic projection of the first power line on the base substrate, and at least partially overlaps with the orthographic projection of the first power line on the base substrate.

[0019] For example, in a display substrate according to at least one embodiment of the present disclosure, the first shielding connection portion is located at both ends of each pixel unit group respectively, and is connected to at least one of the plurality of first power lines corresponding to each pixel unit.

[0020] For example, in a display substrate according to at least one embodiment of the present disclosure, the first shielding connection portion is located at one end of each pixel unit group respectively, and is connected to at least one of the plurality of first power lines corresponding to the pixel unit group.

[0021] For example, a display substrate according to at least one embodiment of the present disclosure further includes a fourth insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer includes the gate line, the second conductive layer includes the second electrode plate of the storage capacitor, the third conductive layer includes the first power line, and in a direction perpendicular to the base substrate, the fourth insulating layer is located between the shielding layer and the active layer of the transistor, the first insulating layer is located between the active layer and the first conductive layer, the second insulating layer is located between the gate line and the second conductive layer, and the third insulating layer is located between the second electrode plate of the storage capacitor and the third conductive layer.

[0022] For example, in a display substrate according to at least one embodiment of the present disclosure, the first shielding connection portion is located in the first conductive layer or the second conductive layer.

[0023] At least one embodiment of the present invention further provides a display device including a display substrate and a sensor according to any embodiment of the present disclosure. The sensor is provided on a second side of the display substrate and is configured to receive light from a first side of the display substrate, and a positive projection of the sensor on the base substrate at least partially overlaps with the first display area.

Brief Description of the Drawings

[0024] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments are briefly introduced below. Obviously, the drawings in the following description do not limit the present disclosure, but are only related to some embodiments of the present disclosure.

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DETAILED DESCRIPTION OF THE INVENTION

[0025] To further clarify the objectives, technical solutions, and advantages of the embodiments of the present disclosure, the following will clearly and completely describe the technical solutions of the embodiments of the present disclosure with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present disclosure.

[0026] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should have the ordinary meanings understood by those skilled in the art. The "first", "second", and similar terms used in the present disclosure do not indicate any order, quantity, or importance, but are only used to distinguish different components. Similar terms such as "include" and "be included" mean that the elements or things that appear before this term include the elements or things listed after this term and their equivalents, but do not exclude other elements or things. Similar terms such as "connect" and "connect to each other" are not limited to physical or mechanical connections, and may include electrical connections, whether direct or indirect. "Above", "below", "left", "right", etc. are only used to indicate relative positional relationships, and when the absolute position of the object to be described changes, the relative positional relationship may also change accordingly.

[0027] OLED (Organic light-emitting diode) display technology has advantages such as wide viewing angles, high contrast, fast response, low power consumption, foldability, and flexibility, and thus has strong competitiveness in displays. With the extensive development and deep application of OLED technology, the demand for display screens with a relatively high screen ratio is increasing. The front camera of the under-screen camera technology is located below the screen, removing the notch area where the front camera is installed, improving the screen ratio, and providing a better visual experience.

[0028] In order for more light rays to pass through the display panel and reach the front camera, it is necessary to reduce the PPI of the light-transmitting display area of the screen, that is, the reduced pixel density. However, there are many slits between the wirings of the pixel circuit and between the connection lines of the signal lines between pixels. When light rays pass through these slits, diffraction and interference occur, resulting in non-uniform brightness when the light rays reach the camera, and a glare phenomenon occurs (either too high brightness occurs in a certain area of the field of view, or excessive brightness changes occur before and after), reducing the visibility of the object, reducing the imaging quality of the camera, and easily causing visual fatigue.

[0029] Currently, one solution is to add a layer of metal layer as a shielding layer to shield the pixel circuit and wiring positions to prevent light rays from passing through these slits and causing interference. However, since these metal layers are in a floating state, they cause interference to the signals of the pixel circuit and affect the display effect. Therefore, it is necessary to introduce a DC signal into these metal layers to stabilize the voltage. However, when directly drilling holes and connecting to the pixel circuit, a space for placing the connection holes is required, increasing the size of the pixel and reducing the resolution of the screen. On the other hand, when connecting only from the end of the IC (Integrated chip, IC chip), it causes a relatively large voltage drop in the wiring and affects the display quality.

[0030] At least one embodiment of the present disclosure provides a display substrate having a first side for display and a second side facing the first side. The display substrate includes a base substrate and a display area installed on the base substrate and including a first display area and a second display area that at least locally surrounds the first display area. The first display area enables light from the first side of the display substrate to at least partially transmit to the second side of the display substrate for detection. The first display area includes a plurality of pixel unit groups arranged at intervals. Each of the plurality of pixel unit groups includes a plurality of first pixel units. Each of the plurality of first pixel units includes a display area including a pixel area and an opening area, and a plurality of first power lines located in the pixel area and connected to the plurality of pixel unit groups and configured to provide a first power supply voltage to the plurality of pixel unit groups. The display substrate further includes a shielding layer installed on the base substrate and located on the side of the first power line close to the base substrate and including a hollow area and a shielding area. For one pixel unit group, the opening area of each first pixel unit at least locally overlaps with the shielding area of the shielding layer. The opening area of at least one first pixel unit includes a first shielding connection portion that at least locally overlaps with the shielding area of the shielding layer. The shielding layer is connected to at least one of the plurality of first power lines through the first shielding connection portion to receive the first power supply voltage. The plurality of first power lines are located on the side of the first shielding connection portion away from the base substrate, and the shielding layer is located on the side of the first shielding connection portion close to the base substrate. The first shielding connection portion is located between the shielding layer and the plurality of first power lines.

[0031] According to the embodiment of the present disclosure, the display substrate can prevent the shielding layer from being in a floating state by connecting a DC signal to the shielding layer without reducing the pixel density, prevent interference with the pixel driving circuit due to signal transition of the shielding layer, reduce the voltage drop of the first power line, and improve the display quality of the display panel.

[0032] Hereinafter, embodiments of the present disclosure will be introduced in detail with reference to the drawings.

[0033] FIG. 1A is a schematic plan view of a display substrate according to at least one embodiment of the present disclosure, FIG. 1B is a partially enlarged schematic view of the display substrate according to at least one embodiment of the present disclosure, FIG. 1C is a partially enlarged schematic view of the display substrate according to at least another embodiment of the present disclosure, and FIG. 1D is a schematic cross-sectional view taken along line B1-B2 in FIG. 1A.

[0034] For example, as shown in FIG. 1A, a display substrate 1 according to at least one embodiment of the present disclosure includes a base substrate 100 and a display area. The display area is disposed on the base substrate 100, and the display area includes a first display area 10 (e.g., a transmissive display area) and a second display area 20 (e.g., a normal display area). The display substrate 1 may further include a peripheral area 30 surrounding (e.g., locally surrounding) the display area. The second display area 20 surrounds (e.g., locally surrounds) the first display area 10.

[0035] For example, the display substrate 1 according to at least one embodiment of the present disclosure may be a display substrate such as an organic light-emitting diode (OLED) display substrate or a quantum dot light-emitting diode (QLED) display substrate, but the specific type of the display substrate is not limited in the embodiments of the present disclosure.

[0036] For example, as shown in FIG. 1D, the first display area 10 is a transmissive display area, that is, light from the first side S1 (for example, the display side) of the display substrate 1 at least partially passes through the display substrate 1 to the second side S2 (for example, the non-display side), that is, incident light from the display side can pass through the first display area 10 and reach the non-display side of the display substrate 1. A sensor 192 may be further installed on the second side S2 of the display substrate 1 to receive this transmitted light, thereby realizing corresponding functions (such as imaging, infrared detection, distance detection, etc.). For example, this sensor 192 is installed on the second side S2 of the display substrate 1, and the orthographic projection of the sensor 192 on the base substrate 100 at least partially overlaps with the first display area 10 and is configured to receive and process light from the first side S1 of the display substrate 1. The light from the first side S1 of the display substrate 1 may be collimated light along the normal direction (for example, the Z1 direction) of the display substrate 1 or non-collimated light.

[0037] For example, the sensor 192 may be an image sensor, an infrared sensor, a distance sensor, etc., and the sensor 192 may be realized in the form of, for example, a chip. The sensor 192 is installed on the second side S2 (the side away from the user) of the display substrate 1. The sensor 192 at least partially overlaps with the first display area 10 in the normal direction of the display surface of the display substrate.

[0038] For example, the sensor 192 may be an image sensor and may be used to collect an image of the external environment facing the light-collecting surface of the sensor 192. For example, it may be a CMOS image sensor or a CCD image sensor. This sensor 192 may further be an infrared sensor, a distance sensor, etc. This sensor 192 may be realized as, for example, a camera of a mobile terminal such as a mobile phone or a notebook, and may further include an optical device such as a lens, a mirror, or an optical waveguide to modulate the optical path as needed. In the embodiments of the present disclosure, the type, function, and installation form of the sensor 192 are not limited.

[0039] The sensor 192 is installed on the first side S2 of the display substrate by means of a double-sided tape or the like, and the orthographic projection of the sensor 192 on the base substrate 100 overlaps at least locally with the first display area 10 and is configured to receive light from the first side S1. Thereby, the first display area 10 realizes display and also facilitates the installation of the sensor 192.

[0040] For example, as shown in FIGS. 1B and 1C, the first display area 10 includes a first sub-pixel array (composed of gray blocks in the first display area 10), and the first sub-pixel array includes a plurality of pixel unit groups P1 (gray blocks in the first display area 10) arranged in a first direction Y1 and a second direction X1 intersecting the first direction Y1. Each of the plurality of pixel unit groups P1 includes at least one first pixel unit (for example, a plurality of first pixel units) (which will be introduced in detail below). The first pixel unit includes a first light-emitting device and a first pixel driving circuit that are directly connected to each other, and the first pixel driving circuit is configured to drive the first light-emitting device to emit light. The first light-emitting device and the first pixel driving circuit are located in the same pixel area and their positions are not separated from each other.

[0041] It should be noted that the first direction Y1 and the second direction X1 may intersect perpendicularly or may not intersect perpendicularly. For example, the value range of the acute angle at which the first direction Y1 and the second direction X1 intersect each other may be 10° or less and 45° or more. The drawings of the embodiments of the present disclosure illustrate that the first direction Y1 and the second direction X1 intersect perpendicularly.

[0042] There is a gap that allows light to pass through, that is, a blank area in the first display area 10, between the plurality of pixel unit groups P1, and by enabling the incident light from the first side S1 to pass through the gap between the adjacent pixel unit groups P1 and be transmitted, the light transmittance of the first display area 10 is ensured.

[0043] For example, as shown in FIG. 1B, a plurality of first pixel unit groups P1 are arranged shifted in two adjacent columns, that is, the pixel unit group P1 in the first column in the figure is shifted in the second direction X1 from the pixel unit group P1 in the second column and is distributed in different rows. For example, the pixel unit groups P1 in adjacent columns are in different rows.

[0044] For example, as shown in FIG. 1C, a plurality of pixel unit groups P1 are arranged in a plurality of rows and a plurality of columns, that is, the pixel unit group P1 in the first column in the figure is adjacent to the pixel unit group P1 in the second column with a gap in the second direction X1.

[0045] For example, as shown in FIGS. 1B and 1C, the second display area 20 includes a second sub-pixel array (formed by white blocks in the second display area 20), and the second sub-pixel array includes a plurality of second pixel units C (white blocks in the second display area 20). Each of the plurality of second pixel units C includes a second light-emitting device and a second pixel driving circuit that are directly connected to each other, and the second pixel driving circuit is configured to drive the second light-emitting device to emit light. The second light-emitting device and the second pixel driving circuit are located in the same pixel area and their positions are not separated from each other. For example, the arrangement mode of the second pixel units in the second display area 20 is shown in FIG. 2.

[0046] For example, the pixel density of the second display area is larger than that of the first display area. As shown in FIGS. 1B and 1C, the arrangement density of the pixel unit groups P1 in the first display area 10 is smaller than the arrangement density of the second pixel units C in the second display area 20. That is, the resolution of the first display area 10 is set lower than that of the second display area 20, leaving a space to allow light to pass through. That is, the pixel density for display arranged in the first display area 10 is smaller than the pixel density of the second display area 20.

[0047] FIG. 2 is a schematic diagram of the arrangement of pixel units in a second display area according to at least one embodiment of the present disclosure. FIG. 3 is a schematic diagram of a first display area of a display panel according to at least one embodiment of the present disclosure. As shown in FIGS. 2 and 3, the first display area 10 and the second display area 20 of the display substrate each include a plurality of pixel unit groups P1. For example, in FIGS. 2 and 3, it is schematically shown that each pixel unit group P1 includes four pixel units P0. For example, these four pixel units P0 are respectively a first sub-pixel unit 101, a second sub-pixel unit 102, a third sub-pixel unit 103, and a fourth sub-pixel unit 104, but in the embodiments of the present disclosure, it is not limited thereto.

[0048] Note that each pixel unit group P1 may further include two pixel units P0 (shown in FIGS. 14A to 14E) or three pixel units P0 (shown in FIGS. 15A to 15E), etc., but in the embodiments of the present disclosure, it is not limited thereto.

[0049] For example, in the example shown in FIG. 14A, one pixel group may further include two sub-pixels, for example, a first sub-pixel 101 and a second sub-pixel 102. For example, the first sub-pixel 101 is a red sub-pixel, and the second sub-pixel 102 is a green sub-pixel. For example, in the embodiment shown in FIG. 15A, one first pixel group P1 may further include three sub-pixels, for example, a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103. For example, the first sub-pixel 101 is a red sub-pixel, the second sub-pixel 102 is a green sub-pixel, and the third sub-pixel 103 is a blue sub-pixel. For example, these three sub-pixels are located in one row. For example, in the example shown in FIG. 12A, one pixel group may further include four sub-pixels, for example, a first sub-pixel 101, a second sub-pixel 102, a third sub-pixel 103, and a fourth sub-pixel 104. For example, the first sub-pixel 101 is a red sub-pixel, the second sub-pixel 102 is a green sub-pixel, the third sub-pixel 103 is a blue sub-pixel, and the fourth sub-pixel 104 is a green sub-pixel. In other embodiments, the pixel group may use pixel units of other colors. Of course, in other embodiments, the arrangement modes of the plurality of sub-pixels P0 in the display panel are not limited to those shown in FIGS. 2 and 3. In the embodiments of the present disclosure, it is not limited thereto.

[0050] For example, as shown in FIG. 2, in the second display area 20, each pixel unit P0 is arranged uniformly and regularly. The description thereof is omitted here.

[0051] For example, as shown in FIG. 3, the display substrate further includes a gate line 113 and a data line 313. The gate line 113 and the data line 313 are insulated from each other. Each gate line 113 is connected to a row of sub-pixels, and each data line 313 is connected to a column of sub-pixels. For example, the gate line 113 is configured to provide a scanning signal to a row of sub-pixels. The data line 313 is configured to provide a data signal to a column of sub-pixels.

[0052] For example, as shown in FIG. 3, data line 313 includes a first data line DL1. The first data line DL1 is at least located in the first display area 10. For example, the first data line DL1 extends from the first display area 10 to the second display area 20. For example, as shown in FIG. 3, gate line 113 includes a first gate line GL1 that extends from the second display area 20 to the first display area 10.

[0053] For clarity and simplicity of illustration, FIG. 3 schematically shows the connection relationship between adjacent pixel groups P1 in the first display area 10 and does not constitute a limitation to the present disclosure. FIG. 4 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. For example, as shown in FIG. 4, this display substrate further includes a first power line VDD1 that is connected to a plurality of pixel unit groups P1 and is configured to provide a first power supply voltage to the plurality of pixel unit groups P1.

[0054] For example, as shown in FIG. 4, this display substrate further includes a shielding layer LS. This shielding layer LS is installed on the base substrate 100 and is located on the side of the first power line VDD1 closer to the base substrate 100, and includes a hollow region LS2 and a shielding region LS1. For example, the hollow region LS2 corresponds to the light-transmitting region R0 between adjacent first pixel unit groups shown in FIG. 3. As shown in FIGS. 3 and 4, the light-transmitting region R0 is surrounded by, but not limited to, two adjacent first gate lines GL1 and two adjacent first data lines DL1.

[0055] For example, the first display area 10 includes a plurality of light-transmitting regions R0 located between adjacent first pixel groups P1. The light-transmitting region R0 allows environmental light to pass through. For example, the light-transmitting region R0 may include a base substrate and a transparent insulating layer located on the base substrate, and the light-transmitting region R0 has no light-shielding structure, for example, no metal wiring. For example, the light-transmitting region R0 is located within a region surrounded by, but not limited to, four adjacent pixel unit groups P1 and the wiring connecting the pixel unit groups P1.

[0056] For example, as shown in FIG. 4, between adjacent pixel unit groups, wirings (for example, first data line DL1, first power supply line 311, gate line GL1, first reset signal line 111, second reset signal line 112, emission control signal line 110, and initialization signal line 210) are connected. For example, the orthographic projection of a plurality of pixel unit groups P0 on the base substrate 100 and the orthographic projection of the wirings on the base substrate 100 fall within the orthographic projection of the shielding region LS1 of the shielding layer LS on the base substrate 100. That is, the shielding region LS1 shields a large number of slits existing between the wirings connecting each first pixel unit group and between the internal connection lines of each first pixel unit group, thereby avoiding diffraction and interference generated when light rays pass through these slits, and avoiding the glare phenomenon caused by the non-uniformity of the luminance when the light rays reach the camera.

[0057] For example, in an embodiment of the present disclosure, as shown in FIG. 6A, each of a plurality of first pixel units P0 includes a pixel region A11 (i.e., the region of transistors, capacitors, and wirings in the first pixel unit). For example, among the plurality of power lines 311 (for the first pixel unit P0, the power line 311 is the first power line VDD1; for the second pixel unit C, the power line 311 is the second power line VDD2; the same applies to the following embodiments and the description thereof is omitted), they are located in this pixel region A11 and the opening region A12. For example, this opening region is a region where the size of the first pixel unit P0 shown in FIG. 6B is reduced. For example, by appropriately reducing the width of the wiring of the pixel driving circuit shown in FIG. 6B, the width-to-length ratio of each transistor, the size of the capacitor, and the size of the via hole, and integrating the wiring, an opening region A12 (FIG. 6A) is provided in the same solid-line rectangular frame in the first pixel unit P0, thereby improving the light transmittance of the display panel. For example, in an embodiment of the present disclosure, by integrating the pixel region A11 at a position above the pixel unit group P0 (i.e., the solid-line rectangular frame), while reducing the occupied space of the driving circuit and keeping the pixel resolution size constant, a part of the space (i.e., the opening region A12) for arranging the first shielding connection portion SP1 for connecting the shielding layer LS to the first power line 311 and the vias V1 / V2 can be provided. Specific comparison diagrams between the normal pixel unit and the pixel unit after size reduction are shown in FIGS. 6B and 6A.

[0058] For example, the size of the pixel driving circuit in FIG. 6A (i.e., the size of the pixel driving circuit after reduction) is one-fourth of the size of the pixel driving circuit shown in FIG. 6B (i.e., the size of the pixel driving circuit before reduction). Of course, as long as the corresponding functions can be realized, it may be one-sixth, one-half, etc., but in the embodiments of the present disclosure, it is not limited thereto. For example, in some examples, for the screen of an under-screen camera with FHD resolution, while reducing the size of the pixel driving circuit to the QHD level, the pixel resolution at the FHD level can be kept constant, so that a shielding connection portion LS2 connected to the shielding layer LS and some spaces for arranging vias can be provided.

[0059] In the above embodiments of the present disclosure, by reducing the size of the pixel driving circuit of the first pixel unit, it is advantageous for light transmission, and without changing the pixel resolution, it is advantageous for realizing the connection between the shielding layer and the first power line or other power lines. Thus, without reducing the pixel density, a DC signal is connected to the shielding layer, preventing signal interference of the shielding layer in the floating state with respect to the pixel driving circuit, reducing the voltage drop of the first power line, and improving the display quality of the display panel.

[0060] To ensure the etching uniformity of the shielding layer, there is also a shielding layer below the pixel circuit in the normal display area. For example, the orthographic projection of the second display area 20 on the base substrate 100 falls within the orthographic projection of the shielding area LS2 of the shielding layer LS on the base substrate 100. For example, since the second display area 20 does not include the light-transmitting area R0, the portion of the shielding layer LS corresponding to the second display area 20 may be a complete surface, that is, without a hollow area, thereby shielding the gaps generated between the gaps of each pixel driving circuit and the wirings connecting each pixel driving circuit in the second display area 20.

[0061] Generally, since the wirings of the pixel driving circuit (for example, the pixel driving circuit shown in FIG. 6B) are compact and the occupied size of the driving circuit wirings is the size of the pixel density, there is no remaining space for the connection portion and the connection hole connected to the shielding layer LS.

[0062] Regarding this, in order to keep the pixel density constant, the pixel driving circuit in the second display area 20 uses the same structure as the pixel driving circuit in the first display area 10, that is, uses the structure and size shown in FIG. 6A.

[0063] For example, regarding the second display area 20, as shown in FIGS. 1B and 1C, the second display area 20 includes a plurality of second pixel units C arranged in an array and a plurality of second power lines VDD2. The structure of each of the plurality of second pixel units C includes, for example, a pixel area A11 and an opening area A12 as shown in FIG. 6A.

[0064] For example, a plurality of second power supply lines VDD2 are connected to a plurality of second pixel units C and are configured to provide a second power supply voltage to the plurality of second pixel units C. For example, the second power supply voltage is the same as the first power supply voltage. For example, one second power supply line VDD2 extends along the second direction X1 and provides the second power supply voltage to a column of second pixel units C.

[0065] Note that in order to distinguish the differences in the regions where the power supply lines 311 are located, the power supply line 311 located in the first display region 10 is called the first power supply line VDD1, and the power supply line 311 located in the second display region 20 is called the second power supply line VDD2. The signals provided by both are the same, that is, the first power supply voltage is the same as the second power supply voltage, and there is no essential difference.

[0066] For example, for one second pixel unit C, the opening region A12 of each second pixel unit C at least partially overlaps with the shielding region LS1 of the shielding layer LS. That is, when the second pixel unit C uses the pixel structure shown in FIG. 6A after size reduction, the shielding layer LS is connected to the second power supply line VDD2 to provide a DC signal to the shielding layer LS, and an opening region is provided to avoid the floating of the shielding layer LS.

[0067] For example, the opening region A12 of at least one second pixel unit C includes a second shielding connection portion SP2 that at least partially overlaps with the shielding region LS2 of the shielding layer LS. The shielding layer LS is connected to at least one power supply line among the plurality of second power supply lines VDD2 through the second shielding connection portion SP2 to receive the second power supply voltage, thereby providing a DC signal to the shielding layer LS and avoiding the floating of the shielding layer LS.

[0068] FIG. 7 is a cross-sectional schematic view taken along line A - A' according to at least one embodiment of the present disclosure. Hereinafter, the first pixel unit P0 will be taken as an example for introduction. In the embodiments of the present disclosure, it is not limited thereto.

[0069] For example, as shown in FIGS. 6A and 7, the shielding layer LS (for example, its shielding region LS1) is connected to the first shielding connection portion SP1 through the first through-hole V1, and the first shielding connection portion SP1 is connected to at least one first power line VDD1 through the second through-hole V2.

[0070] For example, as shown in FIG. 7, the display substrate further includes a first insulating layer G11, a second insulating layer G12, a third insulating layer ILD, and a fourth insulating layer G10. For example, the first insulating layer G11 is located between the shielding layer LS (for example, its shielding region LS1) and the first shielding connection portion SP1.

[0071] For example, as shown in FIG. 7, the second insulating layer G12 is located between the first insulating layer G11 and the first shielding connection portion SP1, the third insulating layer ILD is located between the first shielding connection portion SP1 and the plurality of first power lines VDD1, or the second insulating layer G12 is located between the first shielding connection portion SP1 and the plurality of first power lines VDD1, and the third insulating layer ILD is located between the second insulating layer G12 and the plurality of first power lines VDD1. In FIG. 7, the positional relationship of the second insulating layer G12 is not specifically shown and depends on the actual situation. In the embodiments of the present disclosure, this is not limited thereto.

[0072] For example, in some examples, the shielding layer LS is connected to the first shielding connection portion SP1 through a first through hole penetrating the first insulating layer G11, and the first shielding connection portion SP1 is connected to at least one first power supply line VDD1 through a second through hole penetrating the second insulating layer G12 and the third insulating layer ILD. Or, for example, in another example, as shown in FIG. 7, the shielding layer LS is connected to the first shielding connection portion SP1 through a first through hole V1 penetrating the first insulating layer G11 and the second insulating layer G12, and the first shielding connection portion SP1 is connected to at least one first power supply line VDD1 through a second through hole penetrating the third insulating layer ILD. That is, the first shielding connection portion SP1 may be located in the first conductive layer or the second conductive layer. FIG. 7 shows a schematic diagram in which the first shielding connection portion SP1 is located in the second conductive layer, and in the embodiments of the present disclosure, it is not limited thereto. The related introduction of the first conductive layer and the second conductive layer is described below. The description is omitted here. For example, hereinafter, the case where the first shielding connection portion is located in the first conductive layer will be taken as an example for introduction. In the embodiments of the present disclosure, it is not limited thereto.

[0073] FIG. 8 is a plan view of the semiconductor pattern of the display substrate shown in FIG. 6A, FIG. 9 is a plan view of the first conductive layer of the display substrate shown in FIG. 6A, FIG. 10 is a plan view of the second conductive layer of the display substrate shown in FIG. 6A, and FIG. 11 is a plan view of the third conductive layer of the display substrate shown in FIG. 6A.

[0074] As shown in FIG. 7, the fourth insulating layer G10 is located between the shielding layer LS and the active layer of the transistor (for example, the active layer A7 of the second reset transistor T1).

[0075] For example, as shown in FIGS. 8 to 11, the first conductive layer LY1 includes the gate line GL1, the second conductive layer LY2 includes the second electrode plate C12 of the storage capacitor C1, and the third conductive layer LY3 includes the first power supply line VDD1. For example, in the direction perpendicular to the base substrate 100, the first insulating layer G11 is located between the active layer A7 and the first conductive layer LY1, the second insulating layer G12 is located between the gate line and the second conductive layer LY2, and the third insulating layer ILD is located between the second electrode plate C12 of the storage capacitor C1 and the third conductive layer LY3. For example, the first shielding connection portion SP1 is located in the first conductive layer LY1 shown in FIG. 9. In the embodiments of the present disclosure, it is not limited thereto.

[0076] For example, as shown in FIG. 5, the pixel driving circuit includes a driving transistor T1, a data writing transistor T2, a compensation transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a first reset transistor T6, a second reset transistor T7, and a storage capacitor C1. For example, each transistor and capacitor includes a first electrode and a second electrode. The introduction of the connection relationship and operating principle of this pixel driving circuit can refer to the description in this field, and the description is omitted here.

[0077] For example, as shown in FIG. 8, the active layers A6, A3, A5, A7 of the first reset transistor T6, the compensation transistor T3, the second light emission control transistor T5, and the second reset transistor T7 are located in the first semiconductor layer A01 extending along the first direction Y1, and the active layers A2, A4 of the data writing transistor T2 and the first light emission control transistor T4 are located in the second semiconductor layer A02 extending along the second direction X1. The first semiconductor layer A01 and the second semiconductor layer A02 are connected to and integrally formed with the active layer A1 of the driving transistor T1.

[0078] For example, as shown in FIGS. 6A and 8, the active layer A1 of the driving transistor T1 is located on the virtual line in the first direction Y1 of the active layer A6 of the first reset transistor T6. The active layers A3 and A2 of the compensation transistor T3 and the data writing transistor T2 are located on both sides of the active layer A1 of the driving transistor T1, and are located on the side closer to the active layer A6 of the first reset transistor T6 of the active layer A1 of the driving transistor T1. That is, in the second direction Y1, the active layers A3 and A2 of the compensation transistor T3 and the data writing transistor T2 are located above the active layer A1 of the driving transistor T1. The active layers A5 and A4 of the second light emission control transistor T5 and the first light emission control transistor T4 are located on both sides of the active layer A1 of the driving transistor T1, and are located on the side away from the active layer A6 of the first reset transistor T6 of the active layer A1 of the driving transistor T1. For example, in the second direction Y1, it is located below the active layer A1 of the driving transistor T1.

[0079] For example, as shown in FIGS. 6A and 9, the active layer A7 of the second reset transistor T7 is located on the side away from the active layer of the compensation transistor T3 of the active layer A5 of the second light emission control transistor T5. The compensation transistor T3 includes a first gate G31 extending along the first direction Y1 and a second gate G32 extending along the second direction X1. The second gate G32 is arranged in parallel in the first direction Y1 with the gate G5 of the second light emission control transistor T5 extending along the second direction X2 and the gate of the second reset transistor T7 (not shown in the figure). The gate G2 of the data writing transistor T2 and the gate G4 of the first light emission control transistor T4 extend along the second direction X1 and are arranged in parallel in the first direction Y1.

[0080] For example, the gate G6 of the first reset transistor T6 extends along the second direction X1 and is arranged in parallel in the first direction Y1 with the gate G1 of the driving transistor T1. The gate G1 of the driving transistor T1 is integrally formed with the first electrode plate C11 of the storage capacitor C1.

[0081] For example, the display substrate further includes a gate line 113 extending along a second direction Y1, a light emission control signal line 110, a first reset signal line 111, and a second reset signal line (formed integrally with the gate of the second reset transistor T7).

[0082] For example, the gate G6 of the first reset transistor T6 is connected to and integrally formed with the first reset signal line 111, the second gate G32 of the compensation transistor T3 and the gate G2 of the data writing transistor T2 are connected to and integrally formed with the gate line 113, the gate G6 of the second light emission control transistor T6 and the gate G5 of the first light emission control transistor T5 are connected to and integrally formed with the light emission control signal line 110, and the gate of the second reset transistor T7 is connected to and integrally formed with the second reset signal line.

[0083] For example, the display substrate further includes a gate line 113 extending along a second direction Y1, a light emission control signal line 110, a first reset signal line 111, and a second reset signal line 112. For example, the gate of the first reset transistor T6 is connected to and integrally formed with the first reset signal line 111, the second gate G32 of the compensation transistor T3 and the gate G2 of the data writing transistor T2 are connected to and integrally formed with the gate line 113. The gate G5 of the second light emission control transistor T5 and the gate G4 of the first light emission control transistor T4 are connected to and integrally formed with the light emission control signal line 110, and the gate G7 of the second reset transistor T7 is connected to and integrally formed with the second reset signal line 112.

[0084] For example, the display substrate further includes a data line 313 connected to the active layer A4 of the data writing transistor T4 and configured to provide a data signal DATA. The orthographic projection of the first power line VDD1 on the base substrate 100 at least partially overlaps with the orthographic projection of the active layer A6 of the first reset transistor T6 and the orthographic projection of the active layer A1 of the driving transistor T1 on the base substrate 100. The orthographic projection of the data line 313 on the base substrate 100 is located on the side away from the orthographic projection of the first power line VDD1 of the orthographic projection of the second semiconductor layer A02 on the base substrate 100.

[0085] For example, as shown in FIGS. 6A and 11, the pixel driving circuit further includes a first via electrode EC1. The first via electrode EC1 is connected to the active layer of the second light emission control transistor T5, the active layer A7 of the second reset transistor T7, and the first electrode E1 of the light emitting device 20 through a through hole. The orthographic projection of the first via electrode EC1 on the base substrate 100 is located between the orthographic projection of the active layer A7 of the second reset transistor T7 and the orthographic projection of the active layer A1 of the driving transistor T1 on the base substrate 100.

[0086] For example, for each of the plurality of second pixel units C, the orthographic projection of the second shielding connection portion SP2 on the base substrate 100 is located between the orthographic projection of the active layer A7 of the second reset transistor T7 and the orthographic projection of the second power line VDD2 on the base substrate 100, and at least partially overlaps with the orthographic projection of the second power line VDD2 on the base substrate 100, so that an opening region A12 can be formed.

[0087] For example, referring to FIG. 5, the gate line 113 is configured to provide a scan signal SCAN to the pixel circuit 10. The emission control signal line 110 is configured to provide an emission control signal EM to the sub-pixel P0. The data line 313 is configured to provide a data signal DATA to the pixel circuit 10, the first power supply line 311 is configured to provide a constant first voltage signal ELVDD to the pixel circuit 10, the third power supply line 312 is configured to provide a constant second voltage signal ELVSS to the pixel circuit 10, and the first voltage signal ELVDD is greater than the second voltage signal ELVSS. The initialization signal line 210 is configured to provide an initialization signal Vinit to the pixel circuit 10. The initialization signal Vinit is a constant voltage signal, and its magnitude may be, for example, between the first voltage signal ELVDD and the second voltage signal ELVSS, but is not limited thereto. For example, the initialization signal Vinit may be equal to or less than the second voltage signal ELVSS. For example, the pixel circuit outputs a drive current under the control of signals such as the scan signal SCAN, the data signal DATA, the initialization signal Vinit, the first voltage signal ELVDD, the second voltage signal ELVSS, and the emission control signal EM, and drives the light-emitting element 20 to emit light. The light-emitting element 20 emits red light, green light, blue light, or white light, etc. under the drive of the corresponding pixel circuit 10.

[0088] As shown in FIG. 5, the drive transistor T1 of this pixel circuit 10 is electrically connected to the light-emitting element 20, and outputs a drive current under the control of signals such as the scan signal SCAN, the data signal DATA, the first voltage signal ELVDD, and the second voltage signal ELVSS, and drives the light-emitting element 20 to emit light.

[0089] For example, the display panel according to an embodiment of the present disclosure further includes a data driving circuit and a scanning driving circuit. The data driving circuit is configured to provide a data signal DATA to the sub-pixel P0 based on an instruction of a control circuit, and the scanning driving circuit is configured to provide signals such as a light emission control signal EM, a scanning signal SCAN, a first reset control signal RST1, and a second reset signal RST2 to the sub-pixel P0 based on an instruction of the control circuit. For example, the control circuit includes, but is not limited to, an external integrated circuit (IC). For example, the scanning driving circuit is a GOA (Gate driver On Array) structure attached to this display panel, or a driving chip (IC) structure bonded to this display panel. For example, different driving circuits may be used to provide the light emission control signal EM and the scanning signal SCAN, respectively. For example, the display panel further includes a power supply (not shown in the figure) for providing the above voltage signals, and the power supply may be a voltage source or a current source as required. The power supply is configured to provide a first voltage signal ELVDD, a second power supply voltage ELVSS, an initialization signal Vinit, etc. to the sub-pixel P0 via a first power supply line 311, a third power supply line 312, and an initialization signal line 210, respectively.

[0090] As shown in FIG. 5, the second pole C12 of the storage capacitor C1 is electrically connected to the first power supply line 311, and the first pole C11 of the storage capacitor C1 is electrically connected to the second pole T12 of the threshold compensation transistor T1. The gate T20 of the data writing transistor T2 is electrically connected to the gate line 113, and the first pole T21 and the second pole T22 of the data writing transistor T2 are electrically connected to the data line 313 and the first pole T11 of the driving transistor T1, respectively. The gate T30 of the threshold compensation transistor T3 is electrically connected to the gate line 113, the first pole T31 of the threshold compensation transistor T3 is electrically connected to the second pole T12 of the driving transistor T1, and the second pole T32 of the threshold compensation transistor T3 is electrically connected to the gate T10 of the driving transistor T1.

[0091] For example, as shown in FIG. 5, the gate T40 of the first light emission control transistor T4 and the gate T50 of the second light emission control transistor T5 are both connected to the light emission control signal line 110.

[0092] For example, as shown in FIG. 5, the first pole T41 and the second pole T42 of the first light emission control transistor T4 are electrically connected to the first power line 311 and the first pole T11 of the drive transistor T1, respectively. The first pole T51 and the second pole T52 of the second light emission control transistor T5 are electrically connected to the second pole T12 of the drive transistor T16 and the pixel electrode E1 (which may be the anode of the OLED) of the light emitting element 20, respectively. The common electrode E2 (which may be the common electrode of the OLED, for example, the cathode) of the light emitting element 20 is electrically connected to the third power line 312.

[0093] For example, as shown in FIG. 5, the gate T60 of the first reset transistor T6 is electrically connected to the first reset control signal line 111, the first pole T61 of the first reset transistor T6 is electrically connected to the initialization signal line 210 (the first initialization signal line 211), and the second pole T62 of the first reset transistor T6 is electrically connected to the gate T10 of the drive transistor T1. The gate T70 of the second reset transistor T7 is electrically connected to the second reset control signal line 112, the first pole T71 of the second reset transistor T7 is electrically connected to the initialization signal line 210 (the second initialization signal line 212), and the second pole T72 of the second reset transistor T7 is electrically connected to the pixel electrode E1 of the light emitting element 20.

[0094] FIG. 8 shows a semiconductor pattern SCP, and FIG. 9 shows a first conductive layer LY1 in which a first insulating layer G11 is provided between the semiconductor pattern SCP. By doping the semiconductor pattern SCP using the first conductive layer LY1 as a reticle, the region not covered by the first conductive layer LY1 of the semiconductor pattern SCP maintains semiconductor characteristics and forms a channel of a thin film transistor, while the region covered by the first conductive layer LY1 of the semiconductor pattern SCP is made conductive and forms a source electrode or a drain electrode of the thin film transistor. FIG. 6A shows an active layer formed by locally making the semiconductor pattern SCP conductive.

[0095] As shown in FIG. 9, the first conductive layer LY1 includes a first reset control signal line 111, a second reset control signal line (not shown), a light emission control signal line 110, a gate line 113, and a first electrode C11 of a storage capacitor C1.

[0096] FIG. 10 shows a second conductive layer LY2 in which a second insulating layer G12 is provided between the second conductive layer LY2 and the first conductive pattern layer LY1. The second conductive layer LY2 includes an initialization signal line 210 and a second electrode C12 of the storage capacitor C1. The second electrode C12 of the storage capacitor C1 has an opening. The interlayer insulating layer ILD is located between the second conductive layer LY2 and the third conductive layer LY3. For the first gate insulating layer, the second gate insulating layer, the interlayer insulating layer, the first conductive layer LY1, the second conductive layer LY2, and the third conductive layer LY3, reference can be made to the introduction in this field. The description is omitted here.

[0097] FIG. 11 shows a third conductive layer LY3 including a first power supply line 311, a data line 313, a first connection electrode EC1, a second connection electrode EC2, and a first electrode E1 of a light emitting element 20.

[0098] For example, as shown in FIG. 11, the first power line 311 includes a protruding portion 3111, and the orthographic projection of the second through hole V2 on the base substrate overlaps with the orthographic projection of the protruding portion 3111 on the base substrate. That is, the first shielding connection portion SP1 is connected to the protruding portion 3111 of the first power line S11 through the second through hole V2. The orthographic projection of the first through hole V1 on the base substrate overlaps with the orthographic projection of the first power line 311 on the base substrate. For example, as shown in FIGS. 6A and 7, the first through hole V1 and the second through hole V2 are installed left and right. Of course, they may also be installed vertically in the first direction Y1. In the embodiments of the present disclosure, it is not limited thereto.

[0099] For example, in the embodiments of the present disclosure, the orthographic projection of the first through hole V1 on the base substrate does not overlap with the orthographic projection of the second through hole V2 on the base substrate. That is, the two are installed vertically or horizontally. In this way, the process is simplified, and problems such as the film layer being easily cut due to the orthographic projection of the first through hole on the base substrate overlapping with the orthographic projection of the second through hole on the base substrate, the process being difficult to realize, the gradient of the first power line 311 being large and not flat can be avoided.

[0100] Note that the transistors employed in some embodiments of the present disclosure may all be thin film transistors or field effect transistors or other switch devices with the same characteristics. Since the source electrode and the drain electrode of the transistor employed here may be structurally symmetric, their source electrode and drain electrode may not be structurally distinguishable. In an embodiment of the present disclosure, in order to distinguish the two poles other than the gate of the transistor, one of them is directly described as the first pole and the other as the second pole. Therefore, the first pole and the second pole of all or some of the transistors in the embodiments of the present disclosure can be interchanged as needed. For example, the first pole of the transistor described in the embodiments of the present disclosure may be the source electrode and the second pole may be the drain electrode. Or, the first pole of the transistor may be the drain electrode and the second pole may be the source electrode.

[0101] Note that, when distinguished according to the characteristics of the transistor, the transistor can be divided into an N-type transistor and a P-type transistor. In the embodiments of the present disclosure, the case where all the transistors use P-type transistors will be taken as an example for description. Those skilled in the art can, based on the description and teaching of this implementation mode of the present disclosure, without the need for creative labor, easily conceive that at least some of the transistors in the pixel circuit of the embodiments of the present disclosure employ N-type transistors, that is, adopt an implementation mode of N-type transistors or a combination of N-type transistors and P-type transistors. Therefore, these implementation modes also belong to the protection scope of the present disclosure.

[0102] FIG. 6A is described by taking the pixel circuit of 7T1C as an example. The embodiments of the present disclosure include this, but are not limited thereto. Note that, in the embodiments of the present disclosure, the number of thin-film transistors and the number of capacitors included in the pixel circuit are not limited. For example, in some other embodiments, the pixel circuit of the display substrate may further have a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T3C structure. The embodiments of the present disclosure are not particularly limited thereto.

[0103] For example, the base substrate 100 in at least one embodiment of the present disclosure may be a glass plate, a quartz plate, a metal plate, or a resin panel, etc. For example, the material of the base substrate may include an organic material. For example, this organic material may be a resin material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. For example, the base substrate 100 may be a flexible substrate or a non-flexible substrate. The embodiments of the present disclosure are not limited thereto.

[0104] For example, the materials of the first insulating layer G11, the second insulating layer G12, the third insulating layer ILD, and the fourth insulating layer BL may include inorganic insulating materials such as SiNx, SiOx, SiNxOy, etc., organic insulating materials such as organic resins, or other suitable materials. The embodiments of the present disclosure are not particularly limited thereto.

[0105] For example, the material of the third conductive layer LY3 may include titanium, titanium alloy, aluminum, aluminum, copper, copper alloy, or any other suitable composite material. In the embodiments of the present disclosure, it is not particularly limited in this regard. For example, the materials of the shielding layer LS, the first conductive layer LY1, and the second conductive layer LY2 may be the same as the material of the third conductive layer LY3. The description thereof is omitted here.

[0106] For example, the material of the semiconductor layer 310 may include an oxide semiconductor, an organic semiconductor, or amorphous silicon, polycrystalline silicon, etc. For example, the oxide semiconductor includes a metal oxide semiconductor (such as indium gallium zinc oxide (IGZO)), and the polycrystalline silicon includes low-temperature polycrystalline silicon or high-temperature polycrystalline silicon, etc. In the embodiments of the present disclosure, it is not particularly limited in this regard. Note that the above source electrode region and drain electrode region may be regions doped with n-type impurities or p-type impurities. In the embodiments of the present disclosure, it is not limited in this regard.

[0107] Hereinafter, schematic diagrams of some examples of the first shielding connection portion are shown. For example, the first shielding connection portion may be located in the middle, at both ends, or at one end of the two rows of the first pixel units in the first display region. In the embodiments of the present disclosure, it is not limited in this regard.

[0108] FIG. 12A is a schematic diagram of an example of a display substrate according to at least one embodiment of the present disclosure, FIG. 12B is a plan view of the shielding region LS1 of the shielding layer LS of the display substrate shown in FIG. 12A, FIG. 12C is a plan view of the semiconductor pattern of the display substrate shown in FIG. 12A, FIG. 12D is a plan view of the first conductive layer of the display substrate shown in FIG. 12A, FIG. 12E is a plan view of the second conductive layer of the display substrate shown in FIG. 12A, and FIG. 12F is a plan view of the third conductive layer of the display substrate shown in FIG. 12A.

[0109] For example, as shown in FIG. 12A, one pixel unit group includes four first pixel units 101, 102, 103, and 104. For example, as shown in FIG. 12A, for each pixel unit group, the first shielding connection portion SP1 is located between two adjacent first pixel units in the first direction Y1 among each pixel unit group. For the related introductions in FIGS. 12B to 12F, reference can be made to the descriptions in FIGS. 8 to 11.

[0110] For example, in the example shown in FIG. 12A, the orthographic projection of the first shielding connection portion SP1 on the base substrate 100 is located between the orthographic projection of the active layer A7 of the second reset transistor T7 on the base substrate 100 and the orthographic projection of the first power line VDD1 on the base substrate 100, and at least partially overlaps with the orthographic projection of the first power line VDD1 on the base substrate 100 (for example, as shown in FIG. 6A).

[0111] For example, as shown in FIG. 12A, in the first direction Y1, the first power line 311 between two adjacent pixel unit groups is connected via one third conductor L3. The first data line DL1 includes a first portion DL11 and a second portion DL12. The first portion DL11 of the first data line DL1 is locally overlapped with the third conductor L3, and the second portion DL12 of the first data line DL1 is at least locally overlapped with the third conductor L3. The first portion DL11 of the first data line DL1 and the second portion DL12 of the first data line DL1 are located in different layers. For example, the first portion DL11 of the left first data line DL1 in FIG. 12A is located in the second conductive layer LY2 shown in FIG. 12E, and the second portion DL12 of the right first data line DL1 is located in the first conductive layer LY1 shown in FIG. 12D. For example, referring to FIGS. 12A, 12D, and 12E, the first portion DL11, the second portion DL12 of the first data line DL1, and the third conductor L3 are located between adjacent pixel unit groups.

[0112] For example, as shown in FIG. 12F, the third conductor L3 is integrally formed with the first power supply line 311 and connected to the first power supply lines 311 of two adjacent pixel unit groups, so that the adjacent pixel unit groups are connected through only one third conductor, thereby reducing the wiring area and improving the light transmittance.

[0113] For example, referring to FIG. 12F, two first data lines DL1 respectively connected to two adjacent columns of sub-pixels are provided. For example, as shown in FIG. 12F, the first portion DL11 and the second portion DL12 are respectively connected to the two first data lines DL1 and locally overlap with the orthographic projection of the same third conductor L3 on the base substrate BS. In this installation form, the data lines located between the pixel unit groups in two adjacent columns of sub-pixels can be hidden under the third conductor, thereby reducing the wiring area and improving the light transmittance.

[0114] For example, as shown in FIG. 12B, the shielding region LS1 includes a first portion LS11, a second portion LS12, a third portion LS13, and a fourth portion LS14, and overlaps with the wirings connected to the pixel unit group shown in FIG. 12A respectively. For example, the orthographic projection of the third portion LS13 of the shielding region LS1 on the base substrate overlaps with the orthographic projections of the third conductor L3, the first portion DL11, and the second portion DL12 of the first data line DL1 connected to the previous pixel unit group in FIG. 12A, so that the third conductor L3, the first portion DL11, the second portion DL12 of the first data line DL1, and the gap therebetween can be shielded. The orthographic projection of the fourth portion LS14 of the shielding region LS1 on the base substrate overlaps with the orthographic projections of the third conductor L3, the first portion DL11, and the second portion DL12 of the first data line DL1 connected to the next pixel unit group in FIG. 12A. The orthographic projections of the first portion LS11 and the second portion LS12 of the shielding region LS1 on the base substrate respectively overlap with the orthographic projections of the wirings connected to the left and right pixel unit groups on the base substrate.

[0115] As shown in FIG. 12C, since the shielding connection portion SP1 is located in the middle of the first pixel units adjacent thereto, in order to easily install the shielding connection portion SP1, the active layer of the second reset transistor in the previous first pixel unit located in the same column of the same pixel unit group extends along the first direction Y1 and is connected to the active layer of the first reset transistor T6 located in the next first pixel unit located in the same column. Note that in the embodiments of the present disclosure, this is not limited thereto.

[0116] FIG. 13A is a schematic diagram of an example of another display substrate according to at least one embodiment of the present disclosure, FIG. 13B is a plan view of the shielding region LS1 of the shielding layer LS of the display substrate shown in FIG. 13A, FIG. 13C is a plan view of the semiconductor pattern of the display substrate shown in FIG. 13A, FIG. 13D is a plan view of the first conductive layer of the display substrate shown in FIG. 13A, FIG. 13E is a plan view of the second conductive layer of the display substrate shown in FIG. 13A, and FIG. 13F is a plan view of the third conductive layer of the display substrate shown in FIG. 13A.

[0117] For example, the display substrate shown in FIG. 13A is the same as the display substrate shown in FIG. 12A, and the difference is that the first shielding connection portions SP1 are located at both ends of each pixel unit group and are connected to at least one of a plurality of first power supply lines VDD1 corresponding to each of the pixel units. For example, the first shielding connection portions SP1 located at both ends may both be connected to the same first power supply line VDD1, or may be respectively connected to two different ones of the plurality of first power supply lines VDD1 corresponding to this pixel unit group. That is, the two first shielding connection portions may both be located in the same column or in different columns. In the embodiments of the present disclosure, this is not limited thereto.

[0118] As shown in FIG. 13B, the shielding region LS1 includes only portions LS21, LS22, LS23, and LS24 that extend along the second direction X1, and shields the wirings connected to the left and right pixel unit groups, respectively. Since the third conductor, the first part and the second part of the first data line DL1, which connect the upper pixel unit group and the lower pixel unit group in FIG. 13A, each extend along the second direction X1, compared with the example in FIG. 12B, the shielding region LS1 shown in FIG. 13B does not include a portion extending along the first direction Y1.

[0119] In addition, when the shielding connection part SP1 is located at both ends, as shown in FIG. 13B, the semiconductor layers of each first pixel unit coincide, that is, the first pixel units located in the same column are not connected, and the active layer of the second reset transistor further includes a bent portion T74, which is different from that in FIG. 12C.

[0120] FIG. 14A is a schematic diagram of an example of another display substrate according to at least one embodiment of the present disclosure, FIG. 14B is a plan view of the shielding region LS1 of the shielding layer LS of the display substrate shown in FIG. 14A, FIG. 14C is a plan view of the semiconductor pattern of the display substrate shown in FIG. 14A, FIG. 14D is a plan view of the first conductive layer of the display substrate shown in FIG. 14A, FIG. 14E is a plan view of the second conductive layer of the display substrate shown in FIG. 14A, and FIG. 14F is a plan view of the third conductive layer of the display substrate shown in FIG. 14A. FIG. 15A is a schematic diagram of an example of another display substrate according to at least one embodiment of the present disclosure, FIG. 15B is a plan view of the shielding region LS1 of the shielding layer LS of the display substrate shown in FIG. 15A, FIG. 15C is a plan view of the semiconductor pattern of the display substrate shown in FIG. 15A, FIG. 15D is a plan view of the first conductive layer of the display substrate shown in FIG. 15A, FIG. 15E is a plan view of the second conductive layer of the display substrate shown in FIG. 15A, and FIG. 15F is a plan view of the third conductive layer of the display substrate shown in FIG. 15A.

[0121] For example, as shown in FIG. 14A, one pixel unit group includes two first pixel units 101 and 102. For example, as shown in FIG. 15A, one pixel unit group includes three first pixel units 101, 102, and 103.

[0122] The shielding region in FIG. 15B is the same as the shielding region in FIG. 12B, and the difference is that it further includes a protrusion. The description of the similar parts will be omitted.

[0123] For example, as shown in FIGS. 14A and 15A, the first shielding connection portion SP1 is located at one end of each pixel unit group and is connected to at least one of a plurality of first power supply lines VDD1 corresponding to the pixel unit group. For example, the first shielding connection portion SP1 is connected to the first power supply line VDD1 connected to the first pixel unit 101. In the embodiments of the present disclosure, it is not limited thereto.

[0124] For example, as shown in FIG. 14B, when the first shielding connection portion SP1 is located at one end or both ends of each pixel unit group, the shielding region LS1 of the shielding layer LS further includes a protrusion LS11, and by overlapping with the first shielding connection portion SP1, phenomena such as diffraction of light can be avoided.

[0125] It should be noted that the above embodiments only schematically show the number and position of the first shielding connection portion SP1. Naturally, the number of the first shielding connection portions SP1 corresponding to the display substrates of different embodiments may be more or less, and the position may also change. In the embodiments of the present disclosure, it is not limited thereto.

[0126] Note that the manner in which the second shielding portion SP2 in the second display region 20 is connected to the shielding layer LS and the second power supply line VDD2 is basically the same as the connection manner of the first shielding portion SP2 in the first display region 10. Specifically, reference can be made to the relevant descriptions in FIGS. 7, 12A to 15F above, and the description is omitted here. For example, since each second pixel unit C in the second display region 20 corresponds to one second shielding portion, the ELVDD signal is connected to the shielding layer LS in each pixel circuit, and a stable DC signal is input to the shielding layer LD. Also, a large ELVDD signal network is configured throughout the display region, which is advantageous for reducing the wiring voltage drop, improving the display uniformity, and improving the display effect. Further, since the light shielding layer LS in the first display region 10 is connected to and integrally formed with the light shielding layer LS in the second display region 20, an integrated ELVDD signal network is configured, and further, the wiring voltage drop of the power supply lines (i.e., the first power supply line VDD1 and the second power supply line VDD2) that provide the ELVDD signal is reduced, improving the display effect.

[0127] FIG. 16 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. At least one embodiment of the present disclosure provides a display device 2. This display device 2 may include the display substrate 1 of any of the above embodiments.

[0128] For example, as shown in FIG. 16, the display device 2 may further include a flexible circuit board and a control chip. For example, the flexible circuit board is bonded to the bonding region of the display substrate 1, and the control chip is attached to the flexible circuit board to be electrically connected to the display region, or the control chip is directly bonded to the bonding region to be electrically connected to the display region.

[0129] For example, the control chip may be a central processor, a digital signal processor, a system-on-chip (SoC), etc. For example, the control chip may further include memory, or may further include a power module, etc., and realizes the power supply and signal input / output functions through separately installed conducting wires, signal lines, etc. For example, the control chip may further include a hardware circuit and computer-executable code, etc. The hard circuit may include conventional semiconductors such as ordinary very large scale integration (VLSI) circuits or gate arrays and logic chips, transistors, or other individual elements, and the hard circuit may further include a field programmable gate array, a programmable array logic, a programmable logic device, etc.

[0130] For example, the display device 2 according to at least one embodiment of the present disclosure may be any product or component having a display function such as an OLED panel, an OLED TV, a QLED panel, a QLED TV, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc. This display device 2 may further include other components, such as a data driving circuit, a timing controller, etc. In the embodiments of the present disclosure, there is no particular limitation on this.

[0131] For example, as shown in FIGS. 16 and 1, the display device 2 further includes a sensor 192. The sensor 192 is provided on the second side S2 (for example, the non-display side) of the display substrate 1. The sensor 192 is configured to receive light (for example, collimated light or collimated light) from the first side S1 (for example, the display side of the display substrate) of the display substrate 1. The orthographic projection of the sensor 192 on the base substrate 100 overlaps at least locally with the first display region 10.

[0132] For example, the sensor 192 may be an image sensor, an infrared sensor, a distance sensor, etc., and the sensor 192 may be realized in the form of a chip, etc. The sensor 192 is installed on the non-display side S2 (the side away from the user) of the display substrate.

[0133] For example, the sensor 192 at least locally overlaps with the first display area 10 in the normal direction of the display surface of the display substrate.

[0134] For example, the sensor 192 may be an image sensor, may be used to collect an image of the external environment facing the light collecting surface of the sensor 192, and may be, for example, a CMOS image sensor or a CCD image sensor. This sensor 192 may further be an infrared sensor, a distance sensor, etc. This sensor 192 may be realized, for example, as a camera of a mobile phone or a notebook mobile terminal, and may further include an optical device such as a lens, a mirror, or an optical waveguide to modulate the optical path as needed. In the embodiments of the present disclosure, the type, function, and installation form of the sensor 192 are not limited.

[0135] The sensor 192 is installed on the non-display side S2 of the display panel by means of a double-sided tape or the like. The orthographic projection of the sensor 192 on the base substrate 100 at least locally overlaps with the first display area 10 and is configured to receive light from the first side S1. Thereby, the first display area 10 realizes display and also facilitates the installation of the sensor 192.

[0136] Note that in the embodiments of the present disclosure, not all components of the display device are given for the sake of clear and concise illustration. To realize the functions of the substrate of this display device, those skilled in the art can provide and install other configurations not shown according to specific needs, but the embodiments of the present disclosure are not limited thereto.

[0137] Regarding the technical effects of the display device according to the above embodiments, reference can be made to the technical effects of the display substrate according to the embodiments of the present disclosure, but the description is omitted here.

[0138] Note that the following points will be described.

[0139] (1) The drawings of the embodiments of the present disclosure relate only to the configurations according to the embodiments of the present disclosure, and other configurations can refer to normal designs.

[0140] (2) If there is no conflict, new embodiments can be obtained by combining the embodiments and features of the present disclosure.

[0141] What has been described above is only specific embodiments of the present disclosure, and the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope disclosed in the present disclosure should be included within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate having a first side for display and a second side opposite the first side, a base substrate including a display area and a peripheral area surrounding the display area at least locally, the display area including a first display area and a second display area surrounding the first display area at least locally, the first display area allowing light from a first side of the display substrate to be at least partially transmitted to a second side of the display substrate for detection, the first display area including a plurality of pixel unit groups arranged at intervals and light-transmitting areas between the pixel unit groups, each of the pixel unit groups including a plurality of first pixel units; a plurality of first power supply lines connected to the plurality of pixel unit groups and configured to provide a first power supply voltage to the plurality of pixel unit groups, the first power supply lines extending along the first display area to the second display area; a plurality of data lines connected to the plurality of pixel unit groups and configured to provide data signals to the plurality of pixel unit groups, the data lines extending along from the first display area to the second display area; Including, a first power line extending from the first pixel unit group to the first pixel unit group and extending from the first pixel unit group to the first pixel unit group;

2. 2 . The display substrate according to claim 1 , wherein, between adjacent pixel unit groups, the orthogonal projections of the respective partial line segments of two adjacent data lines on the base substrate are within the orthogonal projections of the same first power line on the base substrate.

3. The display substrate of claim 1 , wherein a portion of the at least one data line extends along a direction in which adjacent pixel unit groups face each other.

4. 2. The display substrate according to claim 1, wherein, between adjacent pixel unit groups, orthogonal projections of partial segments of two data lines on the base substrate overlap with orthogonal projections of the same first power supply line on the base substrate, and the orthogonal projections of the partial segments of one of the data lines on the base substrate are on the orthogonal projections of the first power supply line on the base substrate, and the orthogonal projections of the partial segments of the other data line on the base substrate and the orthogonal projections of the first power supply line on the base substrate overlap in a width direction of the partial segments of the other data line.

5. The display substrate of claim 4 , wherein some of the two data lines extend in a direction perpendicular to a direction in which the adjacent pixel unit groups face each other.

6. 2. The display substrate of claim 1, wherein each of the first pixel units includes a pixel circuit, the pixel circuit includes a driving transistor and a data writing transistor, an arrangement direction of the driving transistor and the data writing transistor is an arrangement direction of the pixel circuits, the arrangement directions of the pixel circuits of the first pixel units in each of the plurality of pixel unit groups are the same, and the arrangement directions of the pixel circuits of the first pixel units in adjacent pixel unit groups are the same or opposite.

7. 2. The display substrate of claim 1, wherein the pixel unit groups are arranged with a shift in a first direction and a shift in a second direction, the first direction intersects with the second direction, and the first pixel units in each pixel unit group are arranged in at least one row in the second direction and at least two columns in the first direction.

8. 2. The display substrate of claim 1, wherein the first pixel units in each pixel unit group are two in number, arranged in one row in the second direction and two columns in the first direction, and the first power line is connected to pixel circuits in one of the two columns.

9. 2. The display substrate of claim 1, wherein the first pixel units in each pixel unit group are four in number, arranged in two rows in the second direction and two columns in the first direction, and the first power line is connected to a pixel circuit in one of the two columns.

10. 2. The display substrate of claim 1, wherein the first pixel units in each pixel unit group are three in number, arranged in one row in the second direction and three columns in the first direction, and the first power line is connected to a pixel circuit in a central column of the three columns.

11. a shielding layer disposed on the base substrate and located on a side of the first power line close to the base substrate, the shielding layer including a hollow region and a shielding region; Each of the plurality of first pixel units includes a pixel region and an opening region, and for one pixel unit group, the opening region of each of the first pixel units at least locally overlaps with the shielding region of the shielding layer; an opening region of the at least one first pixel unit including a first shielding connection portion at least locally overlapping with a shielding region of the shielding layer, and the shielding layer is connected to at least one first power line of the plurality of first power lines via the first shielding connection portion to receive the first power supply voltage; 2. The display substrate according to claim 1, wherein the plurality of first power lines are located on a side of the first shielding connection portion away from the base substrate, the shielding layer is located on a side of the first shielding connection portion closer to the base substrate, and the first shielding connection portion is located between the shielding layer and the plurality of first power lines.

12. The display substrate of claim 11 , wherein the shielding layer is connected to the first shielding connection portion via a first through hole, and the first shielding connection portion is connected to the at least one first power line via a second through hole.

13. The display substrate further includes a first insulating layer, a second insulating layer, and a third insulating layer, the first insulating layer being located between the shielding layer and the first shielding connection part; the second insulating layer is located between the first insulating layer and the first shielding connection portion, and the third insulating layer is located between the first shielding connection portion and the first power supply lines, or the second insulating layer is located between the first shielding connection portion and the first power supply lines, and the third insulating layer is located between the second insulating layer and the first power supply lines, 13. The display substrate of claim 12, wherein the shielding layer is connected to the first shielding connection portion via a first through hole penetrating the first insulating layer, and the first shielding connection portion is connected to the at least one first power line via a second through hole penetrating the second insulating layer and the third insulating layer; or the shielding layer is connected to the first shielding connection portion via a first through hole penetrating the first insulating layer and the second insulating layer, and the first shielding connection portion is connected to the at least one first power line via a second through hole penetrating the third insulating layer.

14. an orthogonal projection of the first through hole on the base substrate does not overlap with an orthogonal projection of the second through hole on the base substrate; 14. The display substrate of claim 13, wherein the first power line includes a protrusion, an orthogonal projection of the second through hole on the base substrate overlaps with an orthogonal projection of the protrusion on the base substrate, and an orthogonal projection of the first through hole on the base substrate overlaps with an orthogonal projection of the first power line on the base substrate.

15. The display substrate according to any one of claims 1 to 14, wherein adjacent pixel unit groups are connected via wiring, and orthogonal projections of the plurality of pixel unit groups on the base substrate and orthogonal projections of the wiring on the base substrate are within orthogonal projections of a shielding region of the shielding layer on the base substrate.

16. the second display region includes a plurality of second pixel units arranged in an array and a plurality of second power lines, each of the second pixel units including a pixel region and an aperture region; the second power supply lines are connected to the second pixel units and configured to provide a second power supply voltage, which is the same as the first power supply voltage, to the second pixel units; For one second pixel unit, an opening region of each of the second pixel units at least locally overlaps with a shielding region of the shielding layer; The display substrate of claim 1 , wherein the opening area of ​​the at least one second pixel unit includes a second shielding connection that at least locally overlaps the shielding area of ​​the shielding layer.

17. The display substrate according to claim 1 , wherein an orthogonal projection of the second display region on the base substrate falls within an orthogonal projection of the shielding region of the shielding layer on the base substrate.

18. 6. The display substrate of claim 1, wherein each of the first pixel units and the second pixel units includes a pixel driving circuit configured to drive the light emitting device to emit light, and a light emitting device.

19. the pixel driving circuit includes a driving transistor, a data writing transistor, a compensation transistor, a first light emission control transistor, a second light emission control transistor, a first reset transistor, a second reset transistor, and a storage capacitor; active layers of the first reset transistor, the compensation transistor, the second light emission control transistor and the second reset transistor are located in a first semiconductor layer extending along a first direction, active layers of the data write transistor and the first light emission control transistor are located in a second semiconductor layer extending along a second direction, and the first semiconductor layer is connected to and integrally formed with the second semiconductor layer via an active layer of the driving transistor; an active layer of the drive transistor is located on a virtual line in the first direction of an active layer of the first reset transistor; the active layers of the compensation transistor and the data write transistor are located on both sides of the active layer of the driving transistor, and the active layer of the driving transistor is located on a side closer to the active layer of the first reset transistor; the active layers of the second emission control transistor and the first emission control transistor are located on both sides of the active layer of the driving transistor, and are located on a side of the active layer of the driving transistor that is away from the active layer of the first reset transistor; an active layer of the second reset transistor is located on a side of an active layer of the second light-emission control transistor that is farther away from an active layer of the compensation transistor; the compensation transistor includes a first gate extending along the first direction and a second gate extending along the second direction; the second gate is arranged in parallel in the first direction with a gate of the second light-emission control transistor and a gate of the second reset transistor, the gate extending along the second direction; a gate of the data write transistor extends along the second direction and is juxtaposed with a gate of the first light emission control transistor in the first direction; a gate of the first reset transistor extends along the second direction and is arranged in parallel with a gate of the drive transistor in the first direction; The display substrate of claim 18 , wherein the gate of the driving transistor is integral with the first plate of the storage capacitor.

20. a gate line, a light emission control signal line, a first reset signal line, and a second reset signal line extending in the second direction; a gate of the first reset transistor is connected to the first reset signal line and is formed integrally therewith; a second gate of the compensation transistor and a gate of the data write transistor are connected to the gate line and are integrally formed; a gate of the second light emission control transistor and a gate of the first light emission control transistor are connected to the light emission control signal line and are integrally formed; 20. The display substrate of claim 19, wherein a gate of the second reset transistor is connected to and integrally formed with the second reset signal line.

21. The data line is connected to an active layer of the data write transistor; an orthogonal projection of the first power supply line on the base substrate at least locally overlaps with an orthogonal projection of an active layer of the first reset transistor on the base substrate and an orthogonal projection of an active layer of the drive transistor on the base substrate; The display substrate of claim 20 , wherein an orthogonal projection of the data line on the base substrate is located on a side of an orthogonal projection of the second semiconductor layer on the base substrate that is away from an orthogonal projection of the first power line on the base substrate.

22. the pixel driving circuit further includes a first via electrode connected to an active layer of the second light-emitting control transistor, an active layer of the second reset transistor, and a first electrode of the light-emitting device via a through hole; The display substrate of claim 21 , wherein the orthogonal projection of the first via electrode on the base substrate is located between the orthogonal projection of the active layer of the second reset transistor on the base substrate and the orthogonal projection of the active layer of the driving transistor on the base substrate.

23. 23. The display substrate of claim 22, wherein for each of the plurality of second pixel units, a positive projection of the second shielding connection portion on the base substrate is located between a positive projection of the active layer of the second reset transistor on the base substrate and a positive projection of the second power line on the base substrate, and at least locally overlaps with a positive projection of the second power line on the base substrate.

24. The display substrate of claim 23 , wherein, for each pixel unit group, the first shielding connection part is located between two first pixel units adjacent to each other in the first direction in each pixel unit group.

25. A display device including the display substrate according to any one of claims 1 to 14 and a sensor, the sensor is disposed on a second side of the display substrate and configured to receive light from a first side of the display substrate; A display device, wherein an orthogonal projection of the sensor on the base substrate at least locally overlaps with the first display area.

26. The display device of claim 25 , wherein the sensor includes a camera.

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