Semiconductor device

Abstract

To provide a semiconductor device capable of a fast operation; and provide a semiconductor device which is unlikely to cause fluctuation in electrical characteristics due to short-channel effects.SOLUTION: A transistor comprises: a semiconductor layer formed by using a crystalline oxide semiconductor; a channel formation region, a source region and a drain region which are formed in the semiconductor layer. The source region and drain region are formed in a self-alignment process of adding one of or a plurality of group 15 elements to the semiconductor layer by using a gate electrode as a mask. A wurtzite type crystalline structure can be provided to the source region and the drain region.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device having a circuit including a semiconductor element such as a transistor and a method for manufacturing the same. . For example, a power device mounted on a power supply circuit, a memory, a thyristor, a converter, an image sensor, etc., a semiconductor integrated circuit including the same, an electro-optical device represented by a liquid crystal display panel, a light emitting device having a light emitting element, etc. are mounted as components on an electronic device.

[0002] Note that in this specification, the semiconductor device refers to a device that can function by utilizing semiconductor characteristics in general, and an electro-optical device, a light emitting device, a semiconductor circuit, and an electronic device are all semiconductor devices. .

Background Art

[0003] As represented by a liquid crystal display device, a transistor formed on a glass substrate or the like is made of amorphous silicon, polycrystalline silicon, or the like. Although a transistor using amorphous silicon has a low field-effect mobility, it can correspond to the enlargement of the area of the glass substrate. In addition, a transistor using polycrystalline silicon has a high field-effect mobility but has a drawback that it is not suitable for the enlargement of the area of the glass substrate.

[0004] Regarding a transistor using silicon, a technique of manufacturing a transistor using an oxide semiconductor and applying it to an electronic device or an optical device has been attracting attention. For example, as an oxide semiconductor, a transistor is manufactured using zinc oxide, an In-Ga-Zn-based oxide, and a technique of using the same for a switching element of a pixel of a display device is disclosed in Patent Document 1 and Patent Document 2.

[0005] In Patent Document 3, in a staggered transistor using an oxide semiconductor, between the source region and the drain region and between the source electrode and the drain electrode, an oxide semiconductor containing nitrogen with high conductivity is provided as a buffer layer, and a technique for reducing the contact resistance between the oxide semiconductor and the source electrode and the drain electrode is disclosed.

[0006] In addition, in Non-Patent Document 1, as a method for forming the source region and the drain region of a transistor using an oxide semiconductor by using a self-alignment process, a method of exposing the surface of the oxide semiconductor, performing argon plasma treatment, and reducing the resistivity of the oxide semiconductor in that portion is disclosed.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Patent Document 3

Non-Patent Documents

[0008]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0009] One of the problems is to provide a semiconductor device capable of high-speed operation.

[0010] One of the problems is to provide a semiconductor device in which variations in electrical characteristics due to the short-channel effect are less likely to occur. is.

[0011] Also, one of the problems is to provide a semiconductor device in which a source region and a drain region are formed by a self-alignment process and which is easy to miniaturize. is.

[0012] Also, by forming a source region and a drain region having a lower resistance than the channel portion, the contact resistance with the source electrode and the drain electrode can be reduced, and one of the problems is to provide a semiconductor device with improved on-current. is.

[0013] One of the problems is to provide a highly reliable semiconductor device.

Means for Solving the Problems

[0014] One aspect of the present invention is a semiconductor device having a crystalline oxide semiconductor layer, a gate insulating layer, and a gate electrode, wherein the oxide semiconductor layer has a first oxide semiconductor region and a pair of second oxide semiconductor regions, the pair of second oxide semiconductor regions are formed sandwiching the first oxide semiconductor region, and the first oxide semiconductor region overlaps with the gate electrode via the gate insulating layer. is a semiconductor device.

[0015] Also, one aspect of the present invention is a semiconductor device having a crystalline oxide semiconductor layer, a gate insulating layer, and a gate electrode, wherein the oxide semiconductor layer has a first oxide semiconductor region, a pair of second oxide semiconductor regions, and a pair of third oxide semiconductor regions, and the pair of third oxide semiconductor regions are the first Formed with an oxide semiconductor region interposed therebetween, the pair of second oxide semiconductor regions are formed with a pair of third oxide semiconductor regions interposed therebetween, and the first oxide semiconductor region is superimposed on a gate electrode via a gate insulating layer. A semiconductor device characterized by this.

[0016] A non-single crystal semiconductor is used for the oxide semiconductor layer.

[0017] The first oxide semiconductor region has CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor). CAAC-OS has a crystal part in which the c-axis is aligned in a direction parallel to the normal vector of the formation surface or the surface normal vector of CAAC-OS, and has a triangular or hexagonal atomic arrangement when viewed from a direction perpendicular to the ab-plane. and when viewed from a direction perpendicular to the c-axis, the metal atoms are arranged in layers or the metal atoms and oxygen atoms are arranged in layers.

[0018] The second oxide semiconductor region contains at least one element of Group 15 elements at a concentration of 5×10 19 atoms / cm 3 or more and 1×10 22 atoms / cm 3 or less. Also, a wurtzite-type crystal structure can be imparted to the second oxide semiconductor region.

[0019] The third oxide semiconductor region contains at least one element of Group 15 elements at a concentration of 5×10 18 atoms / cm 3 or more and 5×10 19 atoms / cm 3 less. Also, a wurtzite-type crystal structure can be imparted to the third oxide semiconductor region.

[0020] ​​​​The second oxide semiconductor region and the third oxide semiconductor region are different from the first oxide semiconductor region. It is possible to have a different crystal structure. In this case, the oxide semiconductor layer included in the semiconductor device has a heterojunction. By using an oxide semiconductor having a heterojunction as the semiconductor layer of a transistor, an effect of increasing the on-current can be expected. Also, an effect of reducing the off-current can be expected.

[0021] The oxide semiconductor can contain two or more elements selected from In, Ga, Sn, and Zn. It is possible.

[0022] The first oxide semiconductor region serves as the channel formation region of the transistor, the pair of second oxide semiconductor regions serve as the source region and the drain region of the transistor, and the pair of third oxide semi- conductor regions serve as the low-concentration regions of the transistor.

[0023] In a transistor having a top gate structure, the source region and the drain region can be formed by adding a dopant to the oxide semiconductor layer using the gate electrode as a mask. By forming the source region and the drain region using the gate electrode as a mask, no overlap occurs between the source region and the drain region and the gate electrode, and the parasitic capacitance can be reduced. Since the parasitic capacitance can be reduced, the transistor can operate at high speed. When forming a low-concentration region between the channel formation region and the source region and the drain region in a transistor having a top gate structure, first, a dopant for forming the low-concentration region is added to the oxide semiconductor layer using the gate electrode as a mask, and then, on the side surface of the gate electrode

[0024] Also, in a transistor having a top gate structure, when forming a low-concentration region between the channel formation region and the source region and the drain region, first, a dopant for forming the low-concentration region is added to the oxide semiconductor layer using the gate electrode as a mask, and then, on the side surface of the gate electrode When forming a low-concentration region between the channel formation region and the source region and the drain region in a transistor having a top gate structure, first, a dopant for forming the low-concentration region is added to the oxide semiconductor layer using the gate electrode as a mask, and then, on the side surface of the gate electrode a dopant for forming the low-concentration region is added to the oxide semiconductor layer using the gate electrode as a mask, and then, on the side surface of the gate electrode A sidewall is formed, and an oxide semiconductor layer is formed by using the gate electrode and the sidewall as a mask. The source and drain regions can be formed by adding dopants to the .

[0025] In a bottom gate transistor, the source and drain regions are The protective layer is used as a mask to add a dopant to the oxide semiconductor layer. The panel protection layer is formed to protect the back channel portion of the active layer and is made of silicon oxide. A material selected from silicon nitride, aluminum oxide, aluminum nitride, etc. is used as a single layer or It is preferable to use the same in a laminated state.

[0026] Dopants for forming the source, drain and lightly doped regions of the transistor The addition can be performed by ion doping or ion implantation. As dopants, elements from Group 15 (Group 5B) such as nitrogen (N) and phosphorus (P) can be used. One or more of these elements can be used. or an ion implantation method, By adding the dopant to the oxide semiconductor layer through the insulating layer, In addition, excessive damage to the oxide semiconductor layer can be reduced. The interface between the semiconductor and the insulating layer is kept clean, improving the transistor characteristics and reliability. The doping depth (doped region) of the dopant becomes easier to control, and the dopant can be precisely doped into the oxide semiconductor layer. It can be added well.

[0027] Increasing the concentration of the dopant increases the carrier density in the oxide semiconductor region. However, if the concentration of the dopant added is too high, it will inhibit the movement of carriers and reduce the conductivity. This will lead to a decrease in conductivity.

[0028] By using the oxide semiconductor doped with a dopant for the source region and the drain region, it is possible to reduce the bending of the band edge in the channel formation region where no dopant is added. On the other hand, when the source region and the drain region are provided with a metal material, the bending of the band edge of the channel, which is an oxide semiconductor region, cannot be ignored, and the effective channel length may become short. This tendency is more prominent when the channel length of the transistor is shorter. This tendency is more prominent when the channel length of the transistor is shorter. This tendency is more prominent when the channel length of the transistor is shorter.

[0029] In addition, by forming the oxide semiconductor region doped with a dopant as the source region and the drain region of the transistor, the on-current of the transistor can be increased without increasing the off-current of the transistor. This can increase the on-current of the transistor without increasing the off-current of the transistor.

[0030] Also, the resistivity of the third oxide semiconductor region is made higher than that of the second oxide semiconductor region. By providing the third oxide semiconductor region, the electric field generated between the first oxide semiconductor region and the second oxide semiconductor region can be relaxed, and the deterioration of the transistor characteristics can be reduced. In addition, the negative shift of the threshold voltage due to the short-channel effect can be reduced.

[0031] An oxide semiconductor (purified OS) with reduced impurities such as moisture or hydrogen that act as electron donors (donors) and highly purified is then supplied with oxygen to the oxide semiconductor to reduce the oxygen vacancies in the oxide semiconductor, thereby making it type-i (intrinsic semiconductor) or approaching type-i as closely as possible. thereby making it type-i (intrinsic semiconductor) or approaching type-i as closely as possible. It can be an i-type (substantially i-type) oxide semiconductor. Therefore, for a semiconductor layer in which a channel is formed a transistor using an i-type or substantially i-type oxide semiconductor has the characteristic that the off-current is extremely low. Specifically, a highly purified oxide semiconductor has a measured hydrogen concentration by secondary ion mass spectrometry (SIMS) of 5×10 / cm 18 less than, preferably 3 1×10 / cm 18 or less, more preferably 5×10 3 / cm 17 or less, even more preferably 3 1×10 / cm 16 or less. Also, the carrier density of an i-type or substantially i-type oxide semiconductor layer that can be measured by Hall effect measurement is 1×10 3 / cm less than, preferably 14 1×10 3 / cm less than, more preferably 1×10 12 / cm 3 less than, even more preferably 1×10 11 / cm 3 less than . Also, the bandgap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. By using an i-type or substantially i-type oxide semiconductor for the semiconductor layer in which a channel is formed, the off-current of the transistor can be reduced .

[0032] Here, the SIMS analysis of the hydrogen concentration in the oxide semiconductor will be mentioned. SIMS analysis is known to have difficulty in accurately obtaining data near the sample surface or near the laminated interface with a film of different materials due to its principle. Therefore, the thickness direction distribution of the hydrogen concentration in the film is When analyzing fabrics with SIMS, extreme fluctuations in values ​​can occur in areas where the film of interest is present. The average value in the region where the hydrogen concentration is almost constant is adopted as the hydrogen concentration. When the thickness of the film to be measured is small, the hydrogen concentration in the adjacent film affects the measurement. In some cases, it may not be possible to find a region where a constant value is obtained. In this case, The maximum or minimum value of the hydrogen concentration in the film is adopted as the hydrogen concentration in the film. In the region where the film exists, a mountain-shaped peak having a maximum value and a valley-shaped peak having a minimum value are formed. If no peak is present, the value at the inflection point is taken as the hydrogen concentration. Effect of the Invention

[0033] According to one embodiment of the present invention, a semiconductor device using an oxide semiconductor which has good electrical characteristics and can be easily miniaturized can be obtained. A semiconductor device can be provided.

[0034] Also, the present invention provides a semiconductor device in which fluctuations in electrical characteristics due to short channel effects are unlikely to occur.

[0035] In addition, by adding a dopant to the oxide semiconductor through the insulating layer, This prevents the thinning of the oxide semiconductor and keeps the interface between the oxide semiconductor and the insulating layer clean, improving the characteristics of the semiconductor device. This can improve the reliability and security of the system. [Brief description of the drawings]

[0036]

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Embodiments for Carrying Out the Invention

[0037] Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the present invention described below, the same reference numerals are commonly used among different drawings for the same part or parts having the same or similar functions, and the repeated description thereof will be omitted. ​​​​​

[0038] In addition, the positions, sizes, ranges, etc. of the respective components shown in the drawings and the like may not represent the actual positions, sizes, ranges, etc. for the sake of simplicity of understanding. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings and the like. In addition, the terms such as "first", "second", and "third" used in this specification are for avoiding confusion of components and are not numerically limiting. Therefore, for example, " first" can be appropriately replaced with "

[0039] second" or " third" and so on for explanation.

[0040] A transistor is a form of semiconductor device and can realize operations such as amplification of current or voltage and switching operations for controlling conduction or non-conduction. The transistors in this specification include IGFETs (Insulated Gate Field Effect Trans istors) and thin film transistors (TFTs: Thin Film Transistor s).

[0041] In addition, the functions of the "source" and "drain" of a transistor may be interchanged when transistors of different polarities are employed or when the direction of current changes in a circuit operation. Therefore, in this specification, the terms "source" and "drain" are assumed to be interchangeable.

[0042] In addition, the terms "electrode" and "wiring" in this specification and the like do not functionally limit these components. For example, an "electrode" may be used as a part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" may refer to a plurality of "electrodes" and "wires" ​ This includes cases where a "line" is integrally formed, etc.

[0043] (Embodiment 1) In this embodiment, a transistor using an oxide semiconductor as a channel and a method for manufacturing the same will be described with reference to FIGS. 1 to 4.

[0044] FIG. 1(A) is a top view for explaining the structure of a transistor 100 which is one form of the configuration of a semiconductor device, and FIG. 1(B) is a cross-sectional view for explaining the laminated structure of the portion indicated by the chain line A1 - A2 in FIG. 1(A). In FIG. 1(A), the description of the substrate and the insulating layer is omitted. .

[0045] In the transistor 100 shown in FIG. 1, a base layer 102 is formed on a substrate 101, and an oxide semiconductor layer 103 is formed on the base layer 10 2. Further, a gate insulating layer 104 is formed on the oxide semiconductor layer 103, and a gate electrode 105 is formed on the gate insulating layer 104. Also, an insulating layer 107 and an insulating layer 108 are formed on the gate electrode 105, and a , a source electrode 110a and a drain electrode 110b are formed on the insulating layer 108. The source electrode 110a and the drain electrode 110b are electrically connected to the oxide semiconductor layer 103 through a contact hole 109 provided in the gate insulating layer 104, the insulating layer 107, and the insulating layer 108.

[0046] The oxide semiconductor layer 103 has a channel formation region 103c that overlaps with the gate electrode 105 through the gate insulating layer 104, a source region 103a that is electrically connected to the source electrode 110a, and a drain region 103b that is electrically connected to the drain electrode 110b.

[0047] Further, the gate electrode 105 has a gate electrode 105a in contact with the gate insulating layer 104 and a gate electrode 105b laminated on the gate electrode 105a.

[0048] In FIG. 1(A), an example is shown in which a plurality of contact holes 109 are provided on the source region 103a and the drain region 103b, respectively. However, a configuration in which one contact hole 109 is provided on each of the source region 103a and the drain region 103b may also be used. Further, in order to reduce the contact resistance between the source electrode 110a and the source region 103a and the contact resistance between the drain electrode 110b and the drain region 103b, the contact hole 109 is preferably as large as possible, and the number of contact holes 109 is preferably increased.

[0049] The transistor 140 shown in FIG. 2 has a sidewall 111 on the side surface of the gate electrode 105 in addition to the configuration of the transistor 100, and has a low-concentration region 103d and a low-concentration region 103e in a region overlapping with the sidewall 111 of the oxide semiconductor layer 103. The low-concentration region 103d is formed between the channel formation region 103c and the source region 103a, and the low-concentration region 103e is formed between the channel formation region 103c and the drain region 103b. FIG. 2(A) is a top view for explaining the configuration of the transistor 140, and FIG. 2(B) is a cross-sectional view for explaining the laminated structure of the portion indicated by the chain line B1-B2 in FIG. 2 (A).

[0050] By providing the low-concentration region 103d and the low-concentration region 103e, it is possible to reduce the deterioration of the transistor characteristics and the negative shift of the threshold voltage due to the short-channel effect.

[0051] Transistors 100 and 140 are one form of transistors with a top gate structure. It is a state.

[0052] Next, the manufacturing method of transistor 100 shown in FIG. 1 will be described with reference to FIGS. 3 and 4. Note that FIGS. 3 and 4 correspond to the cross-section of the part indicated by the chain line A1 - A2 in FIG. 1(A). It is.

[0053] First, an underlayer 102 is formed on the substrate 101 with a thickness of 50 nm or more and 300 nm or less, preferably 100 nm or more and 200 nm or less. The substrate 101 can be a glass substrate, a ceramic substrate, or other plastic substrates having heat resistance sufficient to withstand the processing temperature of this manufacturing process. In addition, when the substrate does not require light transmittance, a substrate with an insulating layer provided on the surface of a metal substrate such as a stainless steel alloy may be used. As the glass substrate, for example, a non-alkali glass substrate such as barium borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass may be used. Alternatively, a quartz substrate, a sapphire substrate, etc. can be used. Also, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, and SOI substrates can be applied, and those with semiconductor elements provided on these substrates can be used as the substrate 101. The underlayer 102 can be formed of a material selected from aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, silicon nitride, silicon oxide, silicon oxynitride, or silicon nitride oxide, either as a single layer or as a laminate, and has a function of preventing the diffusion of impurity elements from the substrate 101. Note that in this specification, oxynitride refers to

[0054] ​​​​​​​​​​ As for the composition, the nitrogen content is higher than the oxygen content, and the oxynitride means that the composition has a higher oxygen content than nitrogen. Note that the content of each element can be measured using, for example, the Rutherford Backscatteri ng Spectrometry (RBS) or the like.

[0055] The underlayer 102 can be appropriately formed using a sputtering method, a CVD method, a coating method, a printing method, or the like. In this embodiment, a laminate of silicon nitride and silicon oxide is used as the underlayer 102. Specifically, silicon nitride is formed on the substrate 101 with a thickness of 50 nm, and silicon oxide is formed on the silicon nitride with a thickness of 150 nm. Note that phosphorus (P) or boron (B) may be doped in the underlayer 102.

[0056] Further, by including a halogen element such as chlorine or fluorine in the underlayer 102, the function of preventing the diffusion of impurity elements from the substrate 101 can be further enhanced. The concentration of the halogen element to be included in the underlayer 102 is 1 × 10 / cm or more and 1 × 10 / cm 15 3 20 3 or less at the concentration peak obtained by analysis using SIMS (Secondary Ion Mass Spectrometer).

[0057] In addition, the underlayer 102 may be made of a material that releases oxygen by heating. "Releasing oxygen by heating" means that the amount of oxygen released in terms of oxygen atoms is 1. 0 × 10 by TDS (Thermal Desorption Spectro scopy: Temperature Programmed Desorption Gas Spectroscopy) analysis. 18 atoms / cm​​​​​​​3 Preferably, it is 3.0×10 20 atoms / cm 3 or more.

[0058] Here, regarding the method for measuring the amount of oxygen released in terms of oxygen atoms by TDS analysis, it will be described below as follows.

[0059] The amount of gas released during TDS analysis is proportional to the integrated value of the spectrum. Therefore, the amount of gas released can be calculated from the integrated value of the spectrum of the insulating layer and the ratio to the reference value of the standard sample. The reference value of the standard sample is the ratio of the atomic density to the integrated value of the spectrum of the sample containing a predetermined atom.

[0060] For example, from the TDS analysis results of a silicon wafer containing hydrogen with a predetermined density as a standard sample and the TDS analysis results of the insulating layer, the amount of oxygen molecules released from the insulating layer (N O2 ) can be obtained by Equation 1. Here, it is assumed that all the spectra detected with a mass number of 32 obtained by TDS analysis are derived from oxygen molecules. Although there is CH3OH with a mass number of 32, it is not considered here as the possibility of its existence is low. Also, regarding oxygen molecules containing oxygen atoms with a mass number of 17 and oxygen atoms with a mass number of 18, which are isotopes of oxygen atoms, they are not considered because their abundance ratios in nature are extremely small.

[0061] N O2 =N H2 / S H2 ×S O2 ×α (Equation 1)

[0062] N H2 is the value obtained by converting the density of hydrogen molecules desorbed from the standard sample. S H2 is the standard sample ​​​​​It is the integrated value of the spectrum when the material is subjected to TDS analysis. Here, the reference value of the standard sample is N H2 / S H2 is defined as. S O2 is the integrated value of the spectrum when the insulating layer is subjected to TDS analysis α is a coefficient that affects the spectrum intensity in TDS analysis. For details of Equation 1, refer to Japanese Patent Laid-Open No. 6-275697. The oxygen release amount of the insulating layer is measured using a temperature programmed desorption analyzer EMD-WA1000S / W manufactured by Electronic Science Co., Ltd. with a silicon wafer containing 1×10 atoms / cm of hydrogen atoms as a standard sample 16 atoms / cm 3 of hydrogen atoms as a standard sample .

[0063] In addition, in TDS analysis, part of the oxygen is detected as oxygen atoms. The ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. Since the above-mentioned α includes the ionization rate of oxygen molecules, by evaluating the release amount of oxygen molecules, the release amount of oxygen atoms can also be estimated In addition, in TDS analysis, part of the oxygen is detected as oxygen atoms. The ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. Since the above-mentioned α includes the ionization rate of oxygen molecules, by evaluating the release amount of oxygen molecules, the release amount of oxygen atoms can also be estimated In addition, in TDS analysis, part of the oxygen is detected as oxygen atoms. The ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. Since the above-mentioned α includes the ionization rate of oxygen molecules, by evaluating the release amount of oxygen molecules, the release amount of oxygen atoms can also be estimated .

[0064] Note that N O2 is the release amount of oxygen molecules. In the insulating layer, the oxygen release amount in terms of oxygen atoms is twice the release amount of oxygen molecules .

[0065] In the above configuration, the insulating layer that releases oxygen upon heating may be silicon oxide (SiO iO X (X>2)) with excessive oxygen. Silicon oxide (SiO X (X>2)) means that it contains more oxygen atoms per unit volume than twice the number of silicon atoms. The number of silicon atoms and oxygen atoms per unit volume are values measured by the Rutherford backscattering method . ​

[0066] By supplying oxygen from the underlying layer to the oxide semiconductor, the interface levels between the underlying layer and the oxide semiconductor can be reduced. As a result, it is possible to suppress charges and the like that may be generated due to the operation of the transistor from being trapped at the interface between the underlying layer and the oxide semiconductor described above, and a transistor with less degradation of electrical characteristics can be obtained.

[0067] Furthermore, charges may be generated due to oxygen deficiency in the oxide semiconductor. Generally, some of the oxygen deficiency in the oxide semiconductor becomes donors and generates electrons that are carriers. As a result, the threshold voltage of the transistor shifts in the negative direction. This tendency is prominent in the oxygen deficiency that occurs on the back-channel side. Note that the back-channel in this specification refers to the vicinity of the interface of the underlying layer in the oxide semiconductor. By sufficiently releasing oxygen from the underlying layer to the oxide semiconductor, the oxygen deficiency of the oxide semiconductor, which is a factor causing the threshold voltage to shift in the negative direction, can be compensated for. That is, when oxygen deficiency occurs in the oxide semiconductor, it becomes difficult to suppress the trapping of charges at the interface between the underlying layer and the oxide semiconductor. However, by providing an insulating layer in the underlying layer that releases oxygen by heating, the interface levels between the oxide semiconductor and the underlying layer, as well as the oxygen deficiency of the oxide semiconductor, can be reduced, and the influence of charge trapping at the interface between the oxide semiconductor and the underlying layer can be minimized.

[0068]

[0069] ​An insulating material containing components of the same type as the oxide semiconductor may be used. Such a material has good compatibility with the oxide semiconductor, and by using it as the underlying layer 102, the state of the interface with the oxide semiconductor can be favorably maintained. Here, "components of the same type as the oxide semiconductor" means one or more elements selected from the constituent elements of the oxide semiconductor. For example, when the oxide semiconductor is composed of an In-Ga-Zn-based oxide semiconductor material, examples of the insulating material containing components of the same type include gallium oxide. This is because it has good compatibility with the oxide semiconductor, and by using it as the underlying layer 102, the state of the interface with the oxide semiconductor can be favorably maintained. Here, "components of the same type as the oxide semiconductor" means one or more elements selected from the constituent elements of the oxide semiconductor. For example, when the oxide semiconductor is composed of an In-Ga-Zn-based oxide semiconductor material, examples of the insulating material containing components of the same type include gallium oxide. For example, when the oxide semiconductor is composed of an In-Ga-Zn-based oxide semiconductor material, examples of the insulating material containing components of the same type include gallium oxide. For example, when the oxide semiconductor is composed of an In-Ga-Zn-based oxide semiconductor material, examples of the insulating material containing components of the same type include gallium oxide.

[0070] Next, an oxide semiconductor is formed on the underlying layer 102. As a pretreatment, in order to minimize the inclusion of hydrogen, hydroxyl groups, and moisture in the oxide semiconductor, it is preferable to preheat the substrate 101 in the preheating chamber of the film-forming apparatus to desorb and exhaust impurities such as hydrogen and moisture adsorbed on the substrate 101 and the underlying layer 102. The exhaust means provided in the preheating chamber is preferably a cryopump. Note that this preheating process can also be omitted. Also, this preheating may be similarly performed on the substrate 101 before forming the underlying layer 102. Next, an oxide semiconductor is formed on the underlying layer 102. As a pretreatment, in order to minimize the inclusion of hydrogen, hydroxyl groups, and moisture in the oxide semiconductor, it is preferable to preheat the substrate 101 in the preheating chamber of the film-forming apparatus to desorb and exhaust impurities such as hydrogen and moisture adsorbed on the substrate 101 and the underlying layer 102. Next, an oxide semiconductor is formed on the underlying layer 102. As a pretreatment, in order to minimize the inclusion of hydrogen, hydroxyl groups, and moisture in the oxide semiconductor, it is preferable to preheat the substrate 101 in the preheating chamber of the film-forming apparatus to desorb and exhaust impurities such as hydrogen and moisture adsorbed on the substrate 101 and the underlying layer 102. Next, an oxide semiconductor is formed on the underlying layer 102. As a pretreatment, in order to minimize the inclusion of hydrogen, hydroxyl groups, and moisture in the oxide semiconductor, it is preferable to preheat the substrate 101 in the preheating chamber of the film-forming apparatus to desorb and exhaust impurities such as hydrogen and moisture adsorbed on the substrate 101 and the underlying layer 102. Next, an oxide semiconductor is formed on the underlying layer 102. As a pretreatment, in order to minimize the inclusion of hydrogen, hydroxyl groups, and moisture in the oxide semiconductor, it is preferable to preheat the substrate 101 in the preheating chamber of the film-forming apparatus to desorb and exhaust impurities such as hydrogen and moisture adsorbed on the substrate 101 and the underlying layer 102. The exhaust means provided in the preheating chamber is preferably a cryopump. Note that this preheating process can also be omitted. Also, this preheating may be similarly performed on the substrate 101 before forming the underlying layer 102. Next, an oxide semiconductor is formed on the underlying layer 102. As a pretreatment, in order to minimize the inclusion of hydrogen, hydroxyl groups, and moisture in the oxide semiconductor, it is preferable to preheat the substrate 101 in the preheating chamber of the film-forming apparatus to desorb and exhaust impurities such as hydrogen and moisture adsorbed on the substrate 101 and the underlying layer 102. The exhaust means provided in the preheating chamber is preferably a cryopump. Note that this preheating process can also be omitted. Also, this preheating may be similarly performed on the substrate 101 before forming the underlying layer 102.

[0071] The oxide semiconductor preferably contains at least indium (In) or zinc (Zn). Particularly, it is preferable to contain both In and Zn. Also, in order to reduce the variation in the electrical characteristics of the transistor using the oxide semiconductor, it is preferable to have gallium (Ga) in addition to them as a stabilizer. Also, it is preferable to have tin (Sn) as a stabilizer. Also, it is preferable to have hafnium (Hf) as a stabilizer. Also, it is preferable to have aluminum (Al) as a stabilizer. The oxide semiconductor preferably contains at least indium (In) or zinc (Zn). Particularly, it is preferable to contain both In and Zn. The oxide semiconductor preferably contains at least indium (In) or zinc (Zn). Particularly, it is preferable to contain both In and Zn. Also, in order to reduce the variation in the electrical characteristics of the transistor using the oxide semiconductor, it is preferable to have gallium (Ga) in addition to them as a stabilizer. The oxide semiconductor preferably contains at least indium (In) or zinc (Zn). Particularly, it is preferable to contain both In and Zn. Also, in order to reduce the variation in the electrical characteristics of the transistor using the oxide semiconductor, it is preferable to have gallium (Ga) in addition to them as a stabilizer. The oxide semiconductor preferably contains at least indium (In) or zinc (Zn). Particularly, it is preferable to contain both In and Zn. Also, in order to reduce the variation in the electrical characteristics of the transistor using the oxide semiconductor, it is preferable to have gallium (Ga) in addition to them as a stabilizer. Also, it is preferable to have tin (Sn) as a stabilizer. The oxide semiconductor preferably contains at least indium (In) or zinc (Zn). Particularly, it is preferable to contain both In and Zn. Also, in order to reduce the variation in the electrical characteristics of the transistor using the oxide semiconductor, it is preferable to have gallium (Ga) in addition to them as a stabilizer. Also, it is preferable to have tin (Sn) as a stabilizer. Also, it is preferable to have hafnium (Hf) as a stabilizer.

[0072] Also, as other stabilizers, any one or more of lanthanoids such as lanthanum (La), cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol mium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lut etium (Lu) may be included.

[0073] For example, as oxide semiconductors, indium oxide, tin oxide, zinc oxide, binary metal oxides such as In-Zn-based oxides, Sn-Zn-based oxides, Al-Zn-based oxides, Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, In-Ga-based oxides, ternary metal oxides such as In-Ga-Zn-based oxides (also denoted as IGZO), In-Al-Zn-based oxides, In-Sn-Zn-based oxides, Sn-Ga-Zn-based oxides, Al-Ga-Zn-based oxides, Sn-Al-Zn-based oxides, In-Hf-Zn-based oxides, In-La-Zn-based oxides such as In-Ce-Zn-based oxides, In-Pr-Zn-based oxides, In-Nd-Zn-based oxides such as In-Sm-Zn-based oxides, In-Eu-Zn-based oxides, In-Gd-Zn-based oxides, In-Tb-Zn-based oxides, In-Dy-Zn-based oxides, In-Ho-Zn-based oxides, I n-Er-Zn-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn-based oxides, In -Lu-Zn-based oxides, quaternary metal oxides such as In-Sn-Ga-Zn-based oxides, I n-Hf-Ga-Zn-based oxides, In-Al-Ga-Zn-based oxides, In-Sn-Al- Zn-based oxides, In-Sn-Hf-Zn-based oxides, In-Hf-Al-Zn-based oxides can be used.

[0074] The oxide semiconductor layer is preferably an oxide semiconductor containing In, more preferably an oxide semiconductor containing In, and Ga.

[0075] Here, for example, an In-Ga-Zn-based oxide means an oxide having indium (In), gallium (Ga ), and zinc (Zn), and the ratio of In, Ga, and Zn is not limited. Also, it may contain metal elements other than In, Ga, and Zn.

[0076] Further, as the oxide semiconductor layer, a thin film represented by the chemical formula InMO3(ZnO) m (m>0) can be used. Here, M represents one or more metal elements selected from Sn, Zn, Ga, Al, Mn, and Co. Also, as the oxide semiconductor, In3SnO5(Zn O) (n>0) can be used. O) n (n>0).

[0077] For example, In-Ga-Zn-based oxides with an atomic ratio of In:Ga:Zn = 1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G a:Zn = 2:2:1 (=2 / 5:2 / 5:1 / 5) and oxides in the vicinity of their compositions can be used. Alternatively, In:Sn:Zn = 1 :1:1 (=1 / 3:1 / 3:1 / 3), In:Sn:Zn = 2:1:3 (=1 / 3:1 / 6:1 / 2), or In:Sn:Zn = 2:1:5 (=1 / 4:1 / 8:5 / 8) atomic ratio of In-Sn-Zn-based oxides and oxides in the vicinity of their compositions are preferably used. However, it is not limited to these, and those with an appropriate composition may be used according to the required semiconductor characteristics (mobility, threshold value, variation, etc.). Also, in order to obtain the required semiconductor characteristics, the

[0078] However, it is not limited to these, and those with an appropriate composition may be used according to the required semiconductor characteristics (mobility, threshold value, variation, etc.). Also, in order to obtain the required semiconductor characteristics, the responding composition can be used. Also, in order to obtain the required semiconductor characteristics, the It is preferable to make the carrier density, impurity concentration, defect density, atomic number ratio of metal elements and oxygen, interatomic bond distance, density, etc. appropriate. and the like are preferably made appropriate.

[0079] For example, in an In-Sn-Zn-based oxide, relatively high mobility can be obtained relatively easily. However, even in an In-Ga-Zn-based oxide, the mobility can be increased by reducing the defect density in the bulk.

[0080] Incidentally, for example, when the atomic number ratio of In, Ga, and Zn is In:Ga:Zn = a:b:c (a + b + c = 1), the composition of the oxide is in the vicinity of the composition of the oxide with an atomic number ratio of In:Ga:Zn = A:B:C (A + B + C = 1), it means that a, b, and c satisfy (a - A) 2 + (b - B) 2 + (c - C) 2 ≦ r 2 and r may be, for example, 0.05. The same applies to other oxides.

[0081] The oxide semiconductor may be single crystal or polycrystal. In the latter case, it may be amorphous or polycrystalline. Also, a structure including a crystalline portion in the amorphous state or a non-amorphous state is also acceptable.

[0082] Since an amorphous oxide semiconductor can relatively easily obtain a flat surface, interface scattering when manufacturing a transistor using this can be reduced, and relatively easily, relatively high mobility can be obtained.

[0083] Also, in a crystalline oxide semiconductor, more defects in the bulk can be reduced, and if the flatness of the surface is enhanced, mobility higher than that of an amorphous oxide semiconductor can be obtained. ​​In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface. , specifically, it is preferably formed on a surface with an average surface roughness (Ra) of 1 nm or less, more preferably 0.3 nm or less, and even more preferably 0.1 nm or less. Note that Ra can be evaluated using an atomic force microscope (AFM :Atomic Force Microscope).

[0084] As the oxide semiconductor having crystallinity, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) is preferable. C AAC-OS is neither a perfect single crystal nor a perfect amorphous material. CAAC-OS is an oxide semiconductor having a crystal-amorphous mixed phase structure with a crystal part in an amorphous phase. Note that the crystal part is often sized to fit within a cube with a side length of less than 100 nm. Also, in an observation image by a transmission electron microscope (TEM:Transmission Electron Microscop e), the boundary between the amorphous part and the crystal part contained in CAAC-OS is not clear. Also, no grain boundaries (also referred to as grain boundaries. ) can be confirmed in CAAC-OS by TEM. Therefore, in CAAC-OS, a decrease in electron mobility due to grain boundaries is suppressed. )

[0085] The crystal parts contained in CAAC-OS have their c-axes aligned in a direction parallel to the normal vector of the surface to be formed or the normal vector of the surface of CAAC-OS, and have a triangular or hexagonal atomic arrangement when viewed from a direction perpendicular to the ab plane, and when viewed from a direction perpendicular to the c-axis, the metal atoms are arranged in layers or the metal atoms and oxygen atoms are arranged in layers. Note that between different crystal parts, the a-axis and respectively The direction of the b-axis may be different. In this specification, when simply described as perpendicular, the range of 85° or more and 95° or less is also included. Also, when simply described as parallel, the range of -5° or more and 5° or less is also included.

[0086] Note that in CAAC-OS, the distribution of the crystal portions may not be uniform. For example, in the process of forming CAAC -OS, when crystal growth is performed from the surface side of the oxide semiconductor film, the proportion of the crystal portions may be higher near the surface than near the surface of the surface to be formed. Also, by adding impurities to CAAC -OS, the crystal portions may be amorphized in the impurity addition region. -OS, the crystal portions may be amorphized in the impurity addition region.

[0087] Since the c-axes of the crystal portions included in CAAC-OS are aligned in a direction parallel to the normal vector of the surface to be formed of CAAC-OS or the normal vector of the surface, depending on the shape of CAAC-OS (the cross-sectional shape of the surface to be formed or the cross-sectional shape of the surface), they may face different directions. Note that the direction of the c-axis of the crystal portions is parallel to the normal vector of the surface to be formed or the surface when CAAC-OS is formed. The crystal portions are formed by film formation or by performing a crystallization treatment such as heat treatment after film formation. Since the c-axes of the crystal portions included in CAAC-OS are aligned in a direction parallel to the normal vector of the surface to be formed of CAAC-OS or the normal vector of the surface, depending on the shape of CAAC-OS (the cross-sectional shape of the surface to be formed or the cross-sectional shape of the surface), they may face different directions. Note that the direction of the c-axis of the crystal portions is parallel to the normal vector of the surface to be formed or the surface when CAAC-OS is formed. The crystal portions are formed by film formation or by performing a crystallization treatment such as heat treatment after film formation. Since the c-axes of the crystal portions included in CAAC-OS are aligned in a direction parallel to the normal vector of the surface to be formed of CAAC-OS or the normal vector of the surface, depending on the shape of CAAC-OS (the cross-sectional shape of the surface to be formed or the cross-sectional shape of the surface), they may face different directions. Note that the direction of the c-axis of the crystal portions is parallel to the normal vector of the surface to be formed or the surface when CAAC-OS is formed. The crystal portions are formed by film formation or by performing a crystallization treatment such as heat treatment after film formation. Since the c-axes of the crystal portions included in CAAC-OS are aligned in a direction parallel to the normal vector of the surface to be formed of CAAC-OS or the normal vector of the surface, depending on the shape of CAAC-OS (the cross-sectional shape of the surface to be formed or the cross-sectional shape of the surface), they may face different directions. Note that the direction of the c-axis of the crystal portions is parallel to the normal vector of the surface to be formed or the surface when CAAC-OS is formed. The crystal portions are formed by film formation or by performing a crystallization treatment such as heat treatment after film formation. Since the c-axes of the crystal portions included in CAAC-OS are aligned in a direction parallel to the normal vector of the surface to be formed of CAAC-OS or the normal vector of the surface, depending on the shape of CAAC-OS (the cross-sectional shape of the surface to be formed or the cross-sectional shape of the surface), they may face different directions. Note that the direction of the c-axis of the crystal portions is parallel to the normal vector of the surface to be formed or the surface when CAAC-OS is formed. The crystal portions are formed by film formation or by performing a crystallization treatment such as heat treatment after film formation. Since the c-axes of the crystal portions included in CAAC-OS are aligned in a direction parallel to the normal vector of the surface to be formed of CAAC-OS or the normal vector of the surface, depending on the shape of CAAC-OS (the cross-sectional shape of the surface to be formed or the cross-sectional shape of the surface), they may face different directions. Note that the direction of the c-axis of the crystal portions is parallel to the normal vector of the surface to be formed or the surface when CAAC-OS is formed. The crystal portions are formed by film formation or by performing a crystallization treatment such as heat treatment after film formation.

[0088] Depending on its composition and the like, CAAC-OS can be a conductor, a semiconductor, or an insulator. Also, depending on its composition and the like, it can be transparent or opaque to visible light. Note that a part of CAAC-OS may be substituted with nitrogen. Depending on its composition and the like, CAAC-OS can be a conductor, a semiconductor, or an insulator. Also, depending on its composition and the like, it can be transparent or opaque to visible light. Note that a part of CAAC-OS may be substituted with nitrogen. Depending on its composition and the like, CAAC-OS can be a conductor, a semiconductor, or an insulator. Also, depending on its composition and the like, it can be transparent or opaque to visible light. Note that a part of CAAC-OS may be substituted with nitrogen.

[0089] A transistor using CAAC-OS has fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light. ​It is possible to reduce. Therefore, the transistor has high reliability.

[0090] An example of the crystal structure included in CAAC-OS will be described in detail with reference to FIGS. 15 to 17. Unless otherwise specified, in FIGS. 15 to 17, the upward direction is the c-axis direction, and the plane orthogonal to the c-axis direction is the ab plane. When simply referring to the upper half and the lower half, it means the upper half and the lower half with the ab plane as the boundary. In FIG. 15, the O surrounded by a circle represents a 4-coordinate O, and the O surrounded by a double circle represents a 3-coordinate O.

[0091] FIG. 15(A) shows a structure having one 6-coordinate In and six 4-coordinate oxygen atoms (hereinafter referred to as 4-coordinate O) adjacent to In. Here, the structure showing only the adjacent oxygen atoms for one metal atom is called a small group. The structure of FIG. 15(A) has an octahedral structure, but is shown in a planar structure for simplicity. In the upper half and the lower half of FIG. 15(A), there are three 4-coordinate O each. The small group shown in FIG. 15(A) has a charge of 0.

[0092] FIG. 15(B) shows a structure having one 5-coordinate Ga, three 3-coordinate oxygen atoms (hereinafter referred to as 3-coordinate O) adjacent to Ga, and two 4-coordinate O adjacent to Ga. All the 3-coordinate O are present on the ab plane. In the upper half and the lower half of FIG. 15(B), there is one 4-coordinate O each. Also, since In can also have a 5-coordinate structure, the structure shown in FIG. 15(B) can be taken. The small group shown in FIG. 15(B) has a charge of 0.

[0093] FIG. 15(C) shows a structure having one 4-coordinate Zn and four 4-coordinate O adjacent to Zn. In the upper half of FIG. 15(C), there is one 4-coordinate O, and in the lower half, there are three 4-coordinate O.​​​​​​​​​​​ There is an O. Or, there are three 4 - coordinated Os in the upper half of FIG. 15(C) and one 4 - coordinated O may be in the lower half. The small group shown in FIG. 15(C) has a charge of 0.

[0094] FIG. 15(D) shows a structure having one 6 - coordinated Sn and six 4 - coordinated Os adjacent to the Sn. There are three 4 - coordinated Os in the upper half of FIG. 15(D) and three 4 - coordinated Os in the lower half. The small group shown in FIG. 15(D) has a charge of +1.

[0095] FIG. 15(E) shows a small group containing two Zns. There is one 4 - coordinated O in the upper half of FIG. 15(E) and one 4 - coordinated O in the lower half. The small group shown in FIG. 15(E) has a charge of -1.

[0096] Here, an aggregate of a plurality of small groups is called a middle group, and an aggregate of a plurality of middle groups is called a large group (also referred to as a unit cell).

[0097] Here, the rule for the combination of these small groups will be described. The three Os in the upper half of the 6 - coordinated In shown in FIG. 15(A) each have three adjacent Ins downward, and the three Os in the lower half each have three adjacent Ins upward. The one O in the upper half of the 5 - coordinated Ga shown in FIG. 15(B) has one adjacent Ga downward, and the one O in the lower half has one adjacent Ga upward. The one O in the upper half of the 4 - coordinated Zn shown in FIG. 15(C) has one adjacent Zn downward, and the three Os in the lower half each have three adjacent Zns upward. Thus, the number of 4 - coordinated Os above the metal atom and the number of adjacent metal atoms below that O are equal. Similarly, the number of 4 - coordinated Os below the metal atom and the number of those Os above that O are equal. are equal. are equal. Similarly, the number of 4 - coordinated Os below the metal atom and the number of adjacent metal atoms above that O are equal. are equal. The number of adjacent metal atoms is equal. Since O is 4-coordinated, the number of adjacent metal atoms below is equal to the number of adjacent metal atoms above. The sum of the number of adjacent metal atoms in the direction is 4. Therefore, the number of 4-coordinated atoms in the direction above the metal atom is When the sum of the number of O atoms and the number of O atoms below another metal atom is 4, the metal atom is Two small groups can be bonded together. For example, a 6-coordinate metal atom (In or Sn) is bonded through the lower half of the tetracoordinate O, there are three tetracoordinate Os, , bound to either a five-coordinate metal atom (Ga or In) or a four-coordinate metal atom (Zn). It will be combined.

[0098] Metal atoms with these coordination numbers are bonded in the c-axis direction via four-coordinate oxygen atoms. In addition, multiple small groups are bonded together so that the total charge of the layer structure is zero. Forms a medium group.

[0099] Figure 16(A) shows a model diagram of the middle group that constitutes the layered structure of In-Sn-Zn oxide. FIG. 16B shows a large group consisting of three medium groups. FIG. 16C shows the atomic arrangement when the layer structure of FIG. 16B is observed from the c-axis direction.

[0100] In FIG. 16(A), for simplicity, the tricoordinate O is omitted, and only the number of the tetracoordinate O is shown. For example, the upper and lower halves of Sn each contain three 4-coordinate O atoms, as shown in the circle. Similarly, in FIG. 16(A), the upper and lower halves of In are Each has one 4-coordinate O atom, which is indicated by the circle 1. Similarly, in Figure 16 In (A), there is one tetracoordinate O in the lower half and three tetracoordinate O in the upper half. Zn with one four - coordinated O in the upper half and three four - coordinated O in the lower half is shown.

[0101] In Fig. 16(A), in the middle group constituting the layer structure of the In - Sn - Zn - based oxide, in order from the top, Sn with three four - coordinated O in both the upper and lower halves, In with one four - coordinated O in both the upper and lower halves are combined, and the In is combined with Zn having three four - coordinated O in the upper half, and through one four - coordinated O in the lower half of the Zn, it is combined with In having three four - coordinated O in both the upper and lower halves, and the In is combined with Zn having one four - coordinated O in the upper half to form a small group consisting of two, and through one four - coordinated O in the lower half of this small group it is combined with Sn having three four - coordinated O in both the upper and lower halves. This is the structure where the middle group is combined in multiple to form a large group. Here, in the case of three - coordinated O and four - coordinated O, the charge per bond can be considered as - 0.6

[0102] 67 and - 0.5 respectively. For example, the charges of In (6 - coordinated or 5 - coordinated), Zn (4 - coordinated), Sn (5 - coordinated or 6 - coordinated) are + 3, + 2, + 4 respectively. Therefore, the small group containing Sn has a charge of + 1. So, in order to form a layer structure containing Sn, a charge of - 1 to cancel out the charge + 1 is required. As a structure with a charge of - 1, as shown in Fig. 1 5(E), a small group containing two Zn can be cited. For example, if there is one small group containing Sn and one small group containing two Zn, the charges can be cancelled out so that the total charge of the layer structure can be made 0.

[0103] ​​​Specifically, by repeating the large group shown in Fig. 16(B), a crystal of In-Sn-Zn -based oxide (In2SnZn3O8) can be obtained. The obtained In-S n-Zn-based oxide layer structure can be represented by the composition formula of In2SnZn2O7(ZnO) m (where m is 0 or a natural number .).

[0104] In addition to this, there are also In-Sn-Ga-Zn-based oxides which are quaternary metal oxides, and ternary ary metal oxides such as In-Ga-Zn-based oxides (also denoted as IGZO), In- Al-Zn-based oxides, Sn-Ga-Zn-based oxides, Al-Ga-Zn-based oxides, Sn-A l-Zn-based oxides, In-Hf-Zn-based oxides, In-La-Zn-based oxides, In-C e-Zn-based oxides, In-Pr-Zn-based oxides, In-Nd-Zn-based oxides, In-Sm -Zn-based oxides, In-Eu-Zn-based oxides, In-Gd-Zn-based oxides, In-Tb- Zn-based oxides, In-Dy-Zn-based oxides, In-Ho-Zn-based oxides, In-Er-Z n-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn-based oxides, In-Lu-Zn -based oxides, and binary metal oxides such as In-Zn-based oxides, Sn-Zn-based oxides, Al -Zn-based oxides, Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, and I n-Ga-based oxides, etc. The same applies when they are used.

[0105] For example, Fig. 17(A) shows a model diagram of the middle group that constitutes the layer structure of the In-Ga-Zn-based oxide. .

[0106] In Fig. 17(A), the middle group that constitutes the layer structure of the In-Ga-Zn-based oxide is the upper In with three 4 - coordinate O atoms each in the upper and lower halves in order from the top is bonded to Zn with one 4 - coordinate O atom in the upper half. Through the three 4 - coordinate O atoms in the lower half of the Zn, it is bonded to Ga with one 4 - coordinate O atom each in the upper and lower halves. Through the one 4 - coordinate O atom in the lower half of the Ga, it is bonded to In with three 4 - coordinate O atoms each in the upper and lower halves. This is the structure where such groups are bonded together in multiple to form a large group. Figure 17(B) shows a large group composed of three middle groups. Note that Figure 17(C) shows the atomic arrangement when observing the layer structure of Figure 17(B) from the c - axis direction. Here, since the charges of In (6 - coordinate or 5 - coordinate), Zn (4 - coordinate), and Ga (5 - coordinate) are +3, +2, and +3 respectively, a small group containing any of In, Zn, and Ga has a charge of 0. Therefore, for any combination of these small groups, the total charge of the middle group is always 0. Also, the middle groups that make up the layer structure of the In - Ga - Zn - based oxide are not limited to the middle groups shown in Figure 17(A), and large groups combined with middle groups having different arrangements of In, Ga, and Zn are also possible.

[0107] Specifically, by repeating the large group shown in Figure 17(B), a crystal of the In - Ga - Zn - based oxide can be obtained. The layer structure of the obtained In - Ga - Zn - based oxide can be represented by the composition formula InGaO3(ZnO)n (n is a natural number).

[0108]

[0109]

[0110] n

[0111] In the case of n = 1 (InGaZnO4), for example, it can have the crystal structure shown in Fig. 18(A). . In the crystal structure shown in Fig. 18(A), as described in Fig. 15(B), since Ga and In take a 5 - coordinate structure, a structure in which Ga is replaced by In is also possible.

[0112] Also, in the case of n = 2 (InGaZn2O5), for example, it can have the crystal structure shown in Fig. 18(B). . In the crystal structure shown in Fig. 18(B), as described in Fig. 15(B), since Ga and In take a 5 - coordinate structure, a structure in which Ga is replaced by In is also possible.

[0113] In this embodiment, first, a first oxide semiconductor with a thickness of 1 nm or more and 10 nm or less is formed on the underlying layer 102 by sputtering. The substrate temperature when forming the first oxide semiconductor is set to be 200°C or more and 400°C or less.

[0114] Here, the sputtering apparatus for forming the oxide semiconductor will be described in detail below.

[0115] The film - forming chamber for forming the oxide semiconductor preferably has a leak rate of 1×10 -10 Pa·m 3 / s or less, so that when forming a film by sputtering, the incorporation of impurities into the film can be reduced.

[0116] To lower the leak rate, it is necessary to reduce not only external leaks but also internal leaks. External leaks refer to the inflow of gas from outside the vacuum system due to minute holes, seal failures, etc. Internal leaks are caused by leaks from partitions such as valves within the vacuum system and outgassing from internal components. The leak rate is 1×10 Pa·m -10 3 ​​​​To make it below [X] per second, it is necessary to take measures against both external leakage and internal leakage.

[0117] To reduce external leakage, the opening and closing part of the film forming chamber may be sealed with a metal gasket. The me tal gasket is preferably made of a metal material coated with iron fluoride, aluminum oxide, or chromium oxide. The metal gasket has higher adhesion compared to an O-ring and can reduce external li eakage. Also, by using a metal material coated with passivation such as iron fluoride, aluminum oxide, chromium oxide, etc., the release gas containing hydrogen generated from the metal gasket can be suppressed, and internal leakage can also be reduced.

[0118] As the member constituting the inner wall of the film forming chamber, use aluminum, chromium, titanium, zirconium, nickel, or vanadium with less release gas containing hydrogen. Also, the aforementioned materials may be used after being coated with an alloy material containing iron, chromium, and nickel, etc. The alloy material containing iron, chromium, and nickel, etc. is rigid, heat-resistant, and suitable for processing. Here, if the surface unevenness of the member is reduced by polishing, etc. to reduce the surface area, the release gas can be reduced. Alternatively, the members of the aforementioned film forming apparatus may be coated with passivation such as iron fluoride, aluminum oxide, chromium oxide, etc.

[0119] Furthermore, it is preferable to provide a purifier for the sputtering gas immediately before introducing the sputtering gas into the film forming chamber. At this time, the length of the piping from the purifier to the film forming chamber is set to 5 m or less, preferably 1 m or less. By setting the length of the piping to 5 m or less or 1 m or less, the influence of the release gas from the piping can be reduced according to the length.

[0120] ​​​​​​​​​The evacuation of the film deposition chamber is preferably carried out by appropriately combining a roughing pump such as a dry pump and a high-vacuum pump such as a sputter ion pump, a turbo molecular pump, and a cryopump. Also, in order to remove residual moisture in the film deposition chamber, it is preferable to use an adsorption-type vacuum pump, for example, a cryopump, an ion pump, or a titanium sublimation pump. While a turbo molecular pump is excellent in evacuating large-sized molecules, its evacuation ability for hydrogen and water is low. Therefore, it is effective to combine a cryopump with a high water evacuation ability and a sputter ion pump with a high hydrogen evacuation ability. Also, a cold trap may be added to the turbo molecular pump. The film deposition chamber evacuated using an adsorption-type vacuum pump such as a cryopump can evacuate, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well). Therefore, the concentration of impurities contained in the oxide semiconductor layer formed in the film deposition chamber can be reduced. The adsorbates present inside the film deposition chamber are adsorbed on the inner wall and do not affect the pressure of the film deposition chamber, but they cause gas release when the film deposition chamber is evacuated. Therefore, although there is no correlation between the leak rate and the evacuation speed, it is important to use a pump with a high evacuation ability to desorb as much as possible the adsorbates present in the film deposition chamber and evacuate it in advance. In addition, in order to promote the desorption of the adsorbates, the film deposition chamber may be baked. Baking can increase the desorption rate of the adsorbates by about 10 times. Baking may be carried out at 100°C or higher and 450°C or lower. At this time, when removing the adsorbates while adding an inert gas, the desorption rate of water and the like that are difficult to desorb by simply evacuating can be further increased.

[0121] The adsorbates present inside the film deposition chamber are adsorbed on the inner wall and do not affect the pressure of the film deposition chamber, but they cause gas release when the film deposition chamber is evacuated. Therefore, although there is no correlation between the leak rate and the evacuation speed, it is important to use a pump with a high evacuation ability to desorb as much as possible the adsorbates present in the film deposition chamber and evacuate it in advance. In addition, in order to promote the desorption of the adsorbates, the film deposition chamber may be baked. Baking can increase the desorption rate of the adsorbates by about 10 times. Baking may be carried out at 100°C or higher and 450°C or lower. At this time, when removing the adsorbates while adding an inert gas, the desorption rate of water and the like that are difficult to desorb by simply evacuating can be further increased. This can be done. Baking may be carried out at 100°C or higher and 450°C or lower. At this time, when removing the adsorbates while adding an inert gas, the desorption rate of water and the like that are difficult to desorb by simply evacuating can be further increased. The evacuation of the film deposition chamber is preferably carried out by appropriately combining a roughing pump such as a dry pump and a high-vacuum pump such as a sputter ion pump, a turbo molecular pump, and a cryopump. Also,

[0122] In sputtering, as a power supply for generating plasma, an RF power supply, an A C power supply, a DC power supply, etc. can be appropriately used.

[0123] For forming an In-Ga-Zn-based oxide material as an oxide semiconductor by sputtering, an In-Ga-Zn-based oxide target can be, for example, a target having a composition ratio of In2O3:Ga2O3:ZnO = 1 :1:1 [mole ratio]. Also, a target having a composition ratio of In 2O3:Ga2O3:ZnO = 1:1:2 [mole ratio], or a target having a composition ratio of In2O3:Ga2O3:ZnO = 1:1:4 [mole ratio], a target having a composition ratio of In2O3:Ga2O3:ZnO = 2:1:8 [mole ratio] can also be used. Also, an In-Ga-Zn-based oxide target having an atomic ratio of In:Ga:Zn = 1:1:1, 4:2:3, 3:1:2, 1:1:2, 2:1:3, or 3:1:4 can be used. By forming an oxide semiconductor using an In-Ga-Zn-based oxide target having the aforementioned atomic ratio, polycrystals or CA AC-OS are likely to be formed. a-Zn-based oxide target having the aforementioned atomic ratio, polycrystals or CAAC-OS are likely to be formed. is likely to be formed.

[0124] Also, when forming an In-Sn-Zn-based oxide as an oxide semiconductor by sputtering, preferably, an In-Sn-Zn-based oxide target having an atomic ratio of In:Sn:Zn = 1:1:1, 2:1:3, 1:2:2, or 20:45:35 is used. By forming an oxide semiconductor using an In-Sn-Zn-based oxide target having the aforementioned atomic ratio, polycrystals or CAAC-OS are likely to be formed. is likely to be formed.

[0125] In addition, the relative density of the metal oxide target for forming the oxide semiconductor is 90% or more and 10 0% or less, preferably 95% or more and 99.9% or less. By using a metal oxide target with a high relative density, the formed oxide semiconductor layer can be made into a dense film.

[0126] Note that as the sputtering gas, a noble gas (typically argon) atmosphere, an oxygen atmosphere, a mixed gas of noble gas and oxygen is appropriately used. Further, it is preferable to use a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed. For example, when argon is used as the sputtering gas, a purity of 9N, a dew point of -121°C, an H2O content of 0.1 ppb or less, and an H2 content of 0.5 ppb or less are preferable. When oxygen is used, a purity of 8N, a dew point of -112°C, an H2O content of 1 ppb or less, and an H2 content of 1 ppb or less are preferable.

[0127] In addition, the substrate temperature during film formation is 150°C or more and 450°C or less, preferably 200°C or more and 350°C or less. By forming the film while heating the substrate to 150°C or more and 450°C or less, preferably 200°C or more and 350°C or less, it is possible to prevent the incorporation of moisture (including hydrogen) and the like into the film.

[0128] By forming the film while heating the substrate, the concentration of impurities such as hydrogen, moisture, hydrides, or hydroxides contained in the formed oxide semiconductor can be reduced. Also, the damage caused by sputtering is reduced. Then, while removing the residual moisture in the film formation chamber, a sputtering gas from which hydrogen and moisture have been removed is added, and using the above target, a first oxide semiconductor is formed with a thickness of 1 nm or more and 10 nm or less, preferably 2 nm or more and 5 nm or less.

[0129] In this embodiment, an In-Ga-Zn-based oxide semiconductor is used as a target for an oxide semiconductor target (In2O3:Ga2O3:ZnO = 1:1:2 [molar ratio]) is used, and a first oxide semiconductor with a film thickness of 5 nm is formed at a distance of 170 mm between the substrate and the target, a substrate temperature of 250 °C, a pressure of 0.4 Pa, a direct current (DC) power supply of 0.5 kW, in an atmosphere of only oxygen, only argon, or argon and oxygen

[0130] Next, the chamber atmosphere where the substrate is placed is set to nitrogen or dry air, and a first heat treatment is performed The temperature of the first heat treatment is set to 400 °C or higher and 750 °C or lower. By the first heat treatment, the first oxide semiconductor is crystallized to form a first crystalline oxide semiconductor

[0131] Depending on the temperature of the first heat treatment, crystallization occurs from the film surface by the first heat treatment and crystal growth proceeds from the surface to the inside of the film, and C-axis oriented crystals are obtained. By the first heat treatment, zinc and oxygen gather in large amounts on the film surface, and a graphene-type two-dimensional crystal composed of zinc and oxygen with a hexagonal upper plane is formed in one or more layers on the outermost surface, and this grows in the film thickness direction and overlaps and stacks. When the temperature of the heat treatment is increased, crystal growth proceeds from the surface to the inside and from the inside to the bottom

[0132] By the first heat treatment, oxygen in the underlayer 102 is diffused to the interface with the first crystalline oxide semiconductor or the vicinity thereof (±5 nm from the interface) to reduce the oxygen deficiency of the first crystalline oxide semiconductor. Therefore, the underlayer 102 is in the underlayer 102 (in the bulk), or ​​​​​​​​、At least a stoichiometric ratio of oxygen is preferably present at the interface between the first crystalline oxide semiconductor and the underlying layer 102.

[0133] Next, a second oxide semiconductor thicker than 10 nm is formed on the first crystalline oxide semiconductor. The second oxide semiconductor is formed by a sputtering method, and the substrate temperature during film formation is set to 200°C or higher and 400°C or lower. By setting the substrate temperature during film formation to 200°C or higher and 400°C or lower, alignment of precursors occurs in the oxide semiconductor formed in contact with the surface of the first crystalline oxide semiconductor, and so-called orderliness can be imparted.

[0134] In this embodiment, as the oxide semiconductor target, an In-Ga-Zn-based oxide semiconductor target (In2O3:Ga2O3:ZnO = 1:1:2 [molar ratio]) is used, and a second oxide semiconductor with a film thickness of 25 nm is formed at a distance of 170 mm between the substrate and the target, a substrate temperature of 400°C, a pressure of 0.4 Pa, a direct current (DC) power supply of 0.5 kW, in an atmosphere of only oxygen, only argon, or an argon and oxygen atmosphere.

[0135] Next, the chamber atmosphere in which the substrate is placed is set to nitrogen or dry air, and a second heat treatment is performed. The temperature of the second heat treatment is set to 400°C or higher and 750°C or lower. By the second heat treatment, a second crystalline oxide semiconductor is formed. The second heat treatment is performed in a nitrogen atmosphere, an oxygen atmosphere, or a mixed atmosphere of nitrogen and oxygen to increase the density of the second crystalline oxide semiconductor and reduce the number of defects. By the second heat treatment, crystal growth proceeds in the film thickness direction, that is, from the bottom to the inside, with the first crystalline oxide semiconductor as a nucleus, to form the second crystalline oxide semiconductor. A conductor is formed. At this time, when the first crystalline oxide semiconductor and the second crystalline oxide semiconductor are composed of the same element, it is called homoepitaxial growth. Or, when the first crystalline oxide semiconductor and the second crystalline oxide semiconductor are composed of at least one different element, it is called hetero epitaxial growth.

[0136] Thus, in the process of forming the oxide semiconductor, by suppressing the incorporation of impurities as much as possible in terms of the pressure of the film formation chamber and the leak rate of the film formation chamber, the incorporation of hydrogen and moisture and other impurities into the oxide semiconductor can be reduced. The hydrogen contained in the oxide semiconductor reacts with the oxygen bonded to the metal atom to form water, and at the same time, defects are formed in the lattice (or the part where oxygen has desorbed) where oxygen has desorbed.

[0137] Therefore, in the process of forming the oxide semiconductor, by extremely reducing impurities, it is possible to reduce the defects of the oxide semiconductor. From these facts, by removing impurities as much as possible and using an oxide semiconductor made of highly purified CAAC-OS in the channel region, the change amount of the threshold voltage before and after light irradiation or BT test on the transistor is small, so that stable electrical characteristics can be obtained.

[0138] Also, after performing the second heat treatment, it is preferable to switch to an oxidizing atmosphere while maintaining the temperature and perform further heat treatment. By the heat treatment in the oxidizing atmosphere, the oxygen defects in the oxide semiconductor can be reduced.

[0139] In addition, the metal oxide that can be used for the oxide semiconductor has a band gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. Thus, the band gap​​​​​ By using a wide metal oxide for the top, the off-current of the transistor can be reduced. .

[0140] Also, it is preferable to perform the steps from the formation of the underlying layer 102 to the second heat treatment continuously without exposure to the atmosphere. The steps from the formation of the underlying layer 102 to the second heat treatment are preferably controlled under an atmosphere containing little hydrogen and moisture (such as an inert atmosphere, a reduced-pressure atmosphere, a dry air atmosphere, etc.). For example, regarding moisture, a dry nitrogen atmosphere with a dew point of -40°C or lower, preferably a dew point of -50°C or lower is used.

[0141] Next, a stack of an oxide semiconductor composed of a first crystalline oxide semiconductor and a second crystalline oxide semiconductor is processed to form an island-shaped oxide semiconductor layer 103 (see Fig. 3(A)).

[0142] The processing of the oxide semiconductor can be performed by forming a mask with a desired shape on the oxide semiconductor and then etching the oxide semiconductor. The above-mentioned mask can be formed by using a method such as photolithography. Alternatively, any method such as an inkjet method or a printing method can be used to form the mask.

[0143] Note that the etching of the oxide semiconductor can be either a dry etching method or a wet etching method. Of course, these can be used in combination.

[0144] Also, as one of the characteristics, the first crystalline oxide semiconductor and the second crystalline oxide semiconductor obtained by the above manufacturing method have a C-axis orientation. However, the first crystalline oxide semiconductor and the second crystalline oxide semiconductor are neither a single crystal structure nor an amorphous structure. It is a structure and is a crystalline oxide semiconductor (CAAC-OS) having a C-axis orientation.

[0145] Moreover, it is not limited to a two-layer structure in which a second crystalline oxide semiconductor is formed on the first crystalline oxide semiconductor. The process of film formation and heat treatment for forming a third crystalline oxide semiconductor after the formation of the second crystalline oxide semiconductor may be repeated to form a stacked structure of three or more layers. By using a stack of a first crystalline oxide semiconductor and a second crystalline oxide semiconductor like the oxide semiconductor layer 103 in a transistor, a transistor having stable electrical characteristics and high reliability can be realized.

[0146] Next, a gate insulating layer 104 is formed on the oxide semiconductor layer 103. The gate insulating layer 104 can be formed of a material selected from aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, silicon nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, tantalum oxide, or lanthanum oxide, either as a single layer or as a stack.

[0147] Moreover, as the gate insulating layer 104, hafnium silicate (HfSiO (x>0)), hafnium silicate with nitrogen added (HfSi O N

[0148] (x>0, y>0, z>0 x ), hafnium aluminate with nitrogen added (HfAl x O y N z (x>0, y>0 ), z>0)), hafnium oxide, yttrium oxide, or other high-k materials can be used. x O y N z (x>0, y>0 ), z>0)), hafnium oxide, yttrium oxide, or other high-k materials can be used. While keeping the thickness of the substantial (e.g., in terms of silicon oxide equivalent) gate insulating film unchanged, the gate leakage can be reduced by thickening the physical gate insulating film. Furthermore, it can be formed into a stacked structure with one or more of an h-k material and any one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, and gallium oxide. The thickness of the gate insulating layer 104 is preferably 1 nm or more and 300 nm or less, more preferably 5 nm or more and 50 nm or less. By setting the thickness of the gate insulating layer 104 to 5 nm or more, the gate leakage current can be reduced. The gate insulating layer 104 is formed by a sputtering method, a CVD method, or the like. The formation of the gate insulating layer 104 can apply a film formation method such as a sputtering method, a plasma CVD method, or a high-density plasma CVD method using microwaves (e.g., a frequency of 2.45 GHz). Also, the gate insulating layer 104 is not limited to a single layer and may be a stack of different layers. Note that it is preferable that the portion of the gate insulating layer 104 in contact with the oxide semiconductor layer 103 is an insulating layer containing oxygen, and particularly preferably an oxide insulating layer that releases oxygen by heating. For example, by using silicon oxide for the gate insulating layer 104, oxygen can be diffused into the oxide semiconductor layer 103, reducing the oxygen deficiency in the oxide semiconductor layer 103 and improving the characteristics of the transistor. In the structure shown in this embodiment, the structure that causes unevenness on the substrate is only the oxide semiconductor layer 103, and there is almost no step-over portion in the gate insulating layer 104. Therefore, the leakage current caused by the gate insulating layer 104 can be reduced, and the breakdown voltage of the gate insulating layer 104 can be increased. The thickness of the gate insulating layer 104 is preferably 1 nm or more and 300 nm or less, more preferably 5 nm or more and 50 nm or less. By setting the thickness of the gate insulating layer 104 to 5 nm or more, the gate leakage current can be reduced. The gate insulating layer 104 is formed by a sputtering method, a CVD method, or the like. The formation of the gate insulating layer 104 can apply a film formation method such as a sputtering method, a plasma CVD method, or a high-density plasma CVD method using microwaves (e.g., a frequency of 2.45 GHz). Also, the gate insulating layer 104 is not limited to a single layer and may be a stack of different layers. Note that it is preferable that the portion of the gate insulating layer 104 in contact with the oxide semiconductor layer 103 is an insulating layer containing oxygen, and particularly preferably an oxide insulating layer that releases oxygen by heating. For example, by using silicon oxide for the gate insulating layer 104, oxygen can be diffused into the oxide semiconductor layer 103, reducing the oxygen deficiency in the oxide semiconductor layer 103 and improving the characteristics of the transistor.

[0149] The gate insulating layer 104 is formed by a sputtering method, a CVD method, or the like. The formation of the gate insulating layer 104 can apply a film formation method such as a sputtering method, a plasma CVD method, or a high-density plasma CVD method using microwaves (e.g., a frequency of 2.45 GHz). Also, the gate insulating layer 104 is not limited to a single layer and may be a stack of different layers. Note that it is preferable that the portion of the gate insulating layer 104 in contact with the oxide semiconductor layer 103 is an insulating layer containing oxygen, and particularly preferably an oxide insulating layer that releases oxygen by heating. For example, by using silicon oxide for the gate insulating layer 104, oxygen can be diffused into the oxide semiconductor layer 103, reducing the oxygen deficiency in the oxide semiconductor layer 103 and improving the characteristics of the transistor. In the structure shown in this embodiment, the structure that causes unevenness on the substrate is only the oxide semiconductor layer 103, and there is almost no step-over portion in the gate insulating layer 104. Therefore, the leakage current caused by the gate insulating layer 104 can be reduced, and the breakdown voltage of the gate insulating layer 104 can be increased. The gate insulating layer 104 is formed by a sputtering method, a CVD method, or the like. The formation of the gate insulating layer 104 can apply a film formation method such as a sputtering method, a plasma CVD method, or a high-density plasma CVD method using microwaves (e.g., a frequency of 2.45 GHz). Also, the gate insulating layer 104 is not limited to a single layer and may be a stack of different layers. Note that it is preferable that the portion of the gate insulating layer 104 in contact with the oxide semiconductor layer 103 is an insulating layer containing oxygen, and particularly preferably an oxide insulating layer that releases oxygen by heating. For example, by using silicon oxide for the gate insulating layer 104, oxygen can be diffused into the oxide semiconductor layer 103, reducing the oxygen deficiency in the oxide semiconductor layer 103 and improving the characteristics of the transistor. In the structure shown in this embodiment, the structure that causes unevenness on the substrate is only the oxide semiconductor layer 103, and there is almost no step-over portion in the gate insulating layer 104. Therefore, the leakage current caused by the gate insulating layer 104 can be reduced, and the breakdown voltage of the gate insulating layer 104 can be increased. The gate insulating layer 104 is formed by a sputtering method, a CVD method, or the like. The formation of the gate insulating layer 104 can apply a film formation method such as a sputtering method, a plasma CVD method, or a high-density plasma CVD method using microwaves (e.g., a frequency of 2.45 GHz). Also, the gate insulating layer 104 is not limited to a single layer and may be a stack of different layers. Note that it is preferable that the portion of the gate insulating layer 104 in contact with the oxide semiconductor layer 103 is an insulating layer containing oxygen, and particularly preferably an oxide insulating layer that releases oxygen by heating. For example, by using silicon oxide for the gate insulating layer 104, oxygen can be diffused into the oxide semiconductor layer 103, reducing the oxygen deficiency in the oxide semiconductor layer 103 and improving the characteristics of the transistor. In the structure shown in this embodiment, the structure that causes unevenness on the substrate is only the oxide semiconductor layer 103, and there is almost no step-over portion in the gate insulating layer 104. Therefore, the leakage current caused by the gate insulating layer 104 can be reduced, and the breakdown voltage of the gate insulating layer 104 can be increased.

[0150] In the structure shown in this embodiment, the structure that causes unevenness on the substrate is only the oxide semiconductor layer 103, and there is almost no step-over portion in the gate insulating layer 104. Therefore, the leakage current caused by the gate insulating layer 104 can be reduced, and the breakdown voltage of the gate insulating layer 104 can be increased. In the structure shown in this embodiment, the structure that causes unevenness on the substrate is only the oxide semiconductor layer 103, and there is almost no step-over portion in the gate insulating layer 104. Therefore, the leakage current caused by the gate insulating layer 104 can be reduced, and the breakdown voltage of the gate insulating layer 104 can be increased. In the structure shown in this embodiment, the structure that causes unevenness on the substrate is only the oxide semiconductor layer 103, and there is almost no step-over portion in the gate insulating layer 104. Therefore, the leakage current caused by the gate insulating layer 104 can be reduced, and the breakdown voltage of the gate insulating layer 104 can be increased. It is possible to do so. Therefore, even if the gate insulating layer 104 is thinned to nearly 5 nm and used, the transistor can be operated. Note that thinning the gate insulating layer 104 has the effect of reducing the short-channel effect and increasing the operating speed of the transistor.

[0151] Before forming the gate insulating layer 104, the surface of the oxide semiconductor layer 103 may be exposed to the plasma of an oxidizing gas such as oxygen, ozone, nitrous oxide, etc., to oxidize the surface of the oxide semiconductor layer 103 and reduce oxygen deficiency. In this embodiment, silicon oxide is formed with a thickness of 100 nm on the oxide semiconductor layer 103 as the gate insulating layer 104.

[0152] Next, a conductive layer is formed on the gate insulating layer 104 using a sputtering method, a vacuum evaporation method, or a plating method, a mask is formed on the conductive layer, and the conductive layer is selectively etched to form a gate electrode 105. As the mask formed on the conductive layer, a printing method, an inkjet method, or a photolithography method can be appropriately used. The gate electrode 105 is formed by a gate electrode 105a in contact with the gate insulating layer 10 4 and a gate electrode 105 b laminated on the gate electrode 105a.

[0153] As the material for forming the gate electrode 105a, indium gallium zinc oxide (In-Ga-Zn-O) containing nitrogen, indium tin oxide (In-Sn-O) containing nitrogen, indium gallium oxide (In-Ga-O) containing nitrogen, indium zinc oxide (In-Zn-O) containing nitrogen, tin oxide (Sn-O) containing nitrogen, indium oxide (In-O) containing nitrogen, or a metal nitride (InN, ZnN, etc.) is preferably used.

[0154] These materials have a work function of 5 eV, preferably 5.5 eV or more, and the gate electrode 105 a is provided between the gate electrode 105b and the gate insulating layer 104, and the gate electrode 105a is superposed on the oxide semiconductor layer 103 through the gate insulating layer 104, so that the threshold voltage of the transistor's electrical characteristics can be made positive, and a so-called normally-off switching element can be realized. For example, when In-Ga-Zn-O containing nitrogen is used for the gate electrode 105a at least a nitrogen concentration higher than that of the oxide semiconductor layer 103, specifically, In-Ga-Zn-O with a nitrogen concentration of 7 atomic% or more is used.

[0155] As the material for forming the gate electrode 105b, aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten( W), neodymium (Nd), scandium (Sc) selected from metal elements, alloys composed of the above-mentioned metal elements as components, alloys combining the above-mentioned metal elements, nitrides of the above-mentioned metal elements etc. can be used for formation. Also, one or more metal elements selected from manganese (Mn), magnesium (Mg), zirconium (Zr), beryllium (Be) can be used.

[0156] Also, the gate electrode 105b may have a single-layer structure or a laminated structure of two or more layers. For example , a single-layer structure using aluminum containing silicon, a two-layer structure with titanium laminated on aluminum , a two-layer structure with titanium laminated on titanium nitride, a two-layer structure with tungsten laminated on titanium nitride , a two-layer structure with tungsten laminated on tantalum nitride, a Cu-Mg-Al alloy ​A two-layer structure in which Cu is laminated on gold, titanium, and a three-layer structure in which aluminum is laminated on the titanium and then titanium is formed thereon, etc. There are also the like.

[0157] Also, the gate electrode 105b can be applied with a conductive material having translucency such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. Further, it can also be a laminated structure of the above-mentioned conductive material having translucency and the above-mentioned metal element. In the present embodiment, indium gallium zinc oxide containing nitrogen is used as the gate electrode 105a. Also, as the gate electrode 105b, a two-layer structure in which tungsten is laminated on titanium nitride is used (see Fig. 3(B)). Note that it is preferable that the end portion of the formed gate electrode 105 has a tapered shape because the covering property of the layer formed later is improved.

[0158]

[0159] Next, the source region 103a and the drain region 103b are formed by a self-alignment process. Specifically, using the gate electrode 105 as a mask, a dopant 106 is added to the oxide semiconductor layer 103 by an ion doping method or an ion implantation method. As the dopant 106, one kind or a plurality of kinds of elements among the group 15 (group 5B) elements such as nitrogen (N) and phosphorus (P) can be used.

[0160] Also, in the region where the oxide semiconductor layer 103 overlaps with the gate electrode 105, the gate electrode 105 serves as a mask and the dopant 106 is not added, and it becomes the channel formation region 103c. ​​​​​​​​​​​

[0161] The source region 103a and the drain region 103b to which the dopant 106 is added become an n-type oxide semiconductor, and the resistivity is lower than that of the channel formation region 103c. Therefore, the resistance values of the source region 103a and the drain region 103b become small, and the transistor 100 can be operated at high speed. In addition, by using a self-alignment process, the overlap between the source region 103a and the drain region 103b and the gate electrode 105 is almost eliminated, and the parasitic capacitance can be reduced, so that the transistor 100 can be operated at an even higher speed.

[0162] Also, using the gate electrode 105 as a mask, the gate insulating layer 104 on the oxide semiconductor layer 103 that becomes the source region and the drain region is removed to expose the oxide semiconductor layer 103, and the dopant 106 is added to the exposed oxide semiconductor layer 103 to form the source region 103a and the drain region 103b. The removal of the gate insulating layer 104 on the oxide semiconductor layer 103 is performed under conditions where the oxide semiconductor layer 103 is difficult to etch.

[0163] The addition of the dopant 106 to the exposed oxide semiconductor layer 103 can be performed not only by the ion doping method or the ion implantation method, but also, for example, by generating plasma in a gas atmosphere containing the element to be added and performing plasma treatment on the exposed portion of the oxide semiconductor layer 103. This can be done by applying a bias to the substrate 101 at this time. It is preferable to apply a bias to the substrate. By increasing the bias applied to the substrate, the dopant 106 can be added deeper into the oxide semiconductor layer 103. As the apparatus for generating the above plasma, a dry ​​​​​An etching apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, etc. can be used. It is possible.

[0164] However, when adding by plasma treatment, there is a risk that the oxide semiconductor will be etched and thinned. Therefore, it is preferable to add the dopant 106 to the exposed oxide semiconductor layer 103 by an ion doping method or an ion implantation method. .

[0165] Also, when removing the gate insulating layer 104 on the oxide semiconductor layer 103 that will become the source region 103a and the drain region 103b, the oxide semiconductor in that part is also etched at the same time, and there is a risk that the source region 103a and the drain region 103b will be thinned. As a result, the resistance of the source region 103a and the drain region 103b increases, and the probability of generating defective products due to overetching accompanying the thinning also tends to increase. This phenomenon becomes prominent when adopting a dry etching method with an insufficiently large selectivity between the oxide semiconductor layer 103 and the gate insulating layer 104. Generally, when manufacturing a transistor with a short channel length, it is necessary to adopt a dry etching method with high processing accuracy, and the source region and the drain region are likely to be thinned.

[0166] Of course, if the oxide semiconductor layer 103 has a sufficient thickness, there will be no problem. However, when the channel length is 200 nm or less, in order to prevent the short-channel effect, the thickness of the oxide semiconductor layer in the part that becomes the channel is required to be 20 nm or less, preferably 10 nm or less. When dealing with such a thin oxide semiconductor layer, the above-mentioned thinning is not preferable.

[0167] Of course, if the oxide semiconductor layer 103 has a sufficient thickness, there will be no problem. However, when the channel length is 200 nm or less, in order to prevent the short-channel effect, the thickness of the oxide semiconductor layer in the part that becomes the channel is required to be 20 nm or less, preferably 10 nm or less. When the channel length is 200 nm or less, in order to prevent the short-channel effect, the thickness of the oxide semiconductor layer in the part that becomes the channel is required to be 20 nm or less, preferably 10 nm or less. When dealing with such a thin oxide semiconductor layer, the above-mentioned thinning is not preferable. ​​​​​​

[0168] Therefore, when adding the dopant 106 to the oxide semiconductor layer 103 by the ion doping method or the ion implantation method, it is preferable to perform the process without exposing the oxide semiconductor layer 103 and leaving the gate insulating layer 104. By adding the dopant 106 through the gate insulating layer 104 to the oxide semiconductor layer 103, excessive damage to the oxide semiconductor layer 103 can be reduced. Also, since the interface between the oxide semiconductor layer 103 and the gate insulating layer 1 04 is kept clean, the characteristics and reliability of the transistor are enhanced. Further, the depth of addition (addition region) of the dopant 106 becomes easier to control, and the dopant 106 can be accurately added to the oxide semiconductor layer 103. In this embodiment, nitrogen (N) is used as the dopant 106, and nitrogen is added to the oxide semiconductor layer 103 through the gate insulating layer 104 by the ion implantation method. Also, the nitrogen concentration in the source region 103a and the drain region 103b formed by the addition of nitrogen is 5×10 atoms / cm

[0169] or more, 1×10 atoms / cm or less, preferably 1×10 atoms / cm 19 atoms / cm 3 or more and less than 7 atomic% ( 22 atoms / cm 3 see Fig. 3(C)). Subsequently, under a reduced pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, an oxygen gas atmosphere, or 20 atoms / cm 3 when measured using a dew point meter of the CRDS (cavity ring-down laser spectroscopy) method, the moisture content is 20 ppm or less (dew point conversion of -55 °C), preferably 1 pp see Fig. 3(C)).

[0170] subsequently, under a reduced pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, an oxygen gas atmosphere, or ultra-dry air (when measured using a dew point meter of the CRDS (cavity ring-down laser spectroscopy) method), the moisture content is 20 ppm or less (dew point conversion of -55 °C), preferably 1 pp when measured using a dew point meter of the CRDS (cavity ring-down laser spectroscopy) method, the moisture content is 20 ppm or less (dew point conversion of -55 °C), preferably 1 pp m or less, preferably 10 ppb or less in air) at a temperature of 300°C to 600°C. In this embodiment, the heat treatment is performed at 100° C. using an electric furnace, which is one of the heat treatment apparatuses. Heat treatment is performed at 450°C for 1 hour in an atmosphere.

[0171] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heating element such as a resistance heating element. The apparatus may be equipped with a device for heating the object to be treated by radiation. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid Thermal Annealing equipment such as RTA (Rapid Thermal Annealing) The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas to perform heat treatment. The gas used is a rare gas such as argon or nitrogen, which does not react with the workpiece during heat treatment. A suitable inert gas is used.

[0172] For example, the heat treatment may involve moving the substrate into an inert gas heated to a high temperature and heating it for several minutes. After heating, the substrate may be moved and removed from the inert gas heated to a high temperature for GRTA. stomach.

[0173] When heat treatment is performed under an atmosphere of inert gas such as nitrogen or rare gas, or ultra-dry air In the case of the heat treatment apparatus, it is preferable that the atmosphere does not contain water, hydrogen, etc. The purity of the added nitrogen, oxygen, or rare gas should be 6N (99.9999%) or more. It is preferable that the purity is 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower). pm or lower).

[0174] By performing the above heat treatment, a wurtzite-type crystal structure can be imparted to the source region 103a and the drain region 103b. Also, it is possible to impart a wurtzite-type crystal structure to the low-concentration regions 103d and 103e. Note that the above heat treatment may be performed at any time after the addition of the dopant 106. Also, when adding the dopant 106 by an ion doping method or an ion implantation method, etc., by performing the addition while heating the substrate, a wurtzite-type crystal structure can be imparted without performing the subsequent heat treatment. Note that the above heat treatment may be performed at any time after the addition of the dopant 106. Note that the above heat treatment may be performed at any time after the addition of the dopant 106.

[0175] Also, when adding the dopant 106 by an ion doping method or an ion implantation method, etc., by performing the addition while heating the substrate, a wurtzite-type crystal structure can be imparted without performing the subsequent heat treatment. Also, when adding the dopant 106 by an ion doping method or an ion implantation method, etc., by performing the addition while heating the substrate, a wurtzite-type crystal structure can be imparted without performing the subsequent heat treatment. Also, when adding the dopant 106 by an ion doping method or an ion implantation method, etc., by performing the addition while heating the substrate, a wurtzite-type crystal structure can be imparted without performing the subsequent heat treatment.

[0176] Next, an insulating layer 107 and an insulating layer 108 are formed by a sputtering method, a CVD method, or the like so as to cover the oxide semiconductor layer 103 and the gate electrode 105. The insulating layer 107 and the insulating layer 108 can be formed using a material selected from aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, silicon nitride, silicon oxide, silicon oxynitride, or silicon nitride oxide. Next, an insulating layer 107 and an insulating layer 108 are formed by a sputtering method, a CVD method, or the like so as to cover the oxide semiconductor layer 103 and the gate electrode 105. The insulating layer 107 and the insulating layer 108 can be formed using a material selected from aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, silicon nitride, silicon oxide, silicon oxynitride, or silicon nitride oxide. Next, an insulating layer 107 and an insulating layer 108 are formed by a sputtering method, a CVD method, or the like so as to cover the oxide semiconductor layer 103 and the gate electrode 105. The insulating layer 107 and the insulating layer 108 can be formed using a material selected from aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, silicon nitride, silicon oxide, silicon oxynitride, or silicon nitride oxide. Next, an insulating layer 107 and an insulating layer 108 are formed by a sputtering method, a CVD method, or the like so as to cover the oxide semiconductor layer 103 and the gate electrode 105. The insulating layer 107 and the insulating layer 108 can be formed using a material selected from aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, silicon nitride, silicon oxide, silicon oxynitride, or silicon nitride oxide. Next, an insulating layer 107 and an insulating layer 108 are formed by a sputtering method, a CVD method, or the like so as to cover the oxide semiconductor layer 103 and the gate electrode 105. The insulating layer 107 and the insulating layer 108 can be formed using a material selected from aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, silicon nitride, silicon oxide, silicon oxynitride, or silicon nitride oxide.

[0177] The film thicknesses of the insulating layer 107 and the insulating layer 108 are 50 nm or more, preferably 200 nm or more and 50 0 nm or less. In this embodiment, a silicon oxide film with a film thickness of 300 nm is formed as the insulating layer 107, and an aluminum oxide film with a film thickness of 100 nm is formed as the insulating layer 108. The film thicknesses of the insulating layer 107 and the insulating layer 108 are 50 nm or more, preferably 200 nm or more and 500 nm or less. In this embodiment, a silicon oxide film with a film thickness of 300 nm is formed as the insulating layer 107, and an aluminum oxide film with a film thickness of 100 nm is formed as the insulating layer 108.

[0178] The insulating layer 108 is made of silicon nitride or aluminum oxide to prevent the intrusion of impurities from the outside. It is preferably formed using niobium. In this embodiment, as the insulating layer 108, aluminum oxide with a film thickness of 100 nm is formed (see FIG. 3(D)). Further, either one or both of the insulating layer 107 and the insulating layer 108 may be omitted.

[0179] After the formation of the insulating layer 108, if necessary, under an atmosphere containing almost no hydrogen and moisture (nitrogen atmosphere, oxygen atmosphere, dry air atmosphere (for example, for moisture, dew point -40 °C or lower, preferably dew point -60 °C or lower), etc.), heat treatment (temperature range 150 °C or higher and 650 °C or lower, preferably 200 °C or higher and 500 °C or lower) may be performed.

[0180] Next, a mask is formed on the insulating layer 108, and using the mask, a part of the gate insulating layer 104, the insulating layer 107, and the insulating layer 108 is selectively etched to expose a part of the source region 103a and the drain region 103b, and a contact hole 109 is formed (see FIG. 4(A)).

[0181] Next, a conductive layer is formed on the insulating layer 108, a mask is formed on the conductive layer, and the conductive layer is selectively etched to form a source electrode 110a and a drain electrode 110b (see FIG. 4(B)). The conductive layer for forming the source electrode 110a and the drain electrode 110b can apply the same material as the gate electrode 105b.

[0182] In this embodiment, as the conductive layer for forming the source electrode 110a and the drain electrode 110b, a conductive layer in which Cu is laminated on a Cu-Mg-Al alloy is used. By providing a Cu-Mg-Al alloy material in contact with the insulating layer 108, the adhesion of the conductive layer can be improved.

[0183] Note that the channel length of the transistor 100 corresponds to the length of the channel formation region 103c sandwiched between the source region 103a and the drain region 103b in FIG. 1(B). Also, the channel length of the transistor 100 is substantially equal to the width of the gate electrode 105.

[0184] Through the above steps, even when the transistor is miniaturized and the channel length is reduced, a transistor 100 using an oxide semiconductor with good electrical characteristics and high reliability can be fabricated.

[0185] The transistor 140 has a low concentration region 103d and a low concentration region 103e in the oxide semiconductor layer 103. The transistor 140 can be fabricated by adding a sidewall 111 fabrication process to the fabrication process of the transistor 100 and performing the addition of the dopant 106 to the oxide semiconductor layer 103 in two steps.

[0186] The low concentration region 103d and the low concentration region 103e can be formed by a self-alignment process using the gate electrode 105 as a mask. Specifically, after the gate electrode 105 is formed, using the gate electrode 105 as a mask, the dopant 106 is added to the oxide semiconductor layer 103 in the same manner as the transistor 100 (also referred to as the first doping step). As the dopant 106 added to the oxide semiconductor layer 103 in the first doping step, the same elements as the dopant 106 used in the transistor 100 can be used. In the first doping step, the concentration of the dopant 106 in the oxide semiconductor layer 103 is 5×10 atoms / cm or more, 5×10 atoms / cm 18 atoms / cm 3 or more 、5×10 19 atoms / cm3 Add it so as to be less than.

[0187] Next, a sidewall 111 is formed on the side surface of the gate electrode 105. The sidewall 11 1 can be formed by a known method.

[0188] Next, using the gate electrode 105 and the sidewall 111 as a mask, a dopant 106 is added to the oxide semiconductor layer 103 (also referred to as the second doping step). In the second doping step, the acid As the dopant 106 added to the oxide semiconductor layer 103, the same element as the dopant 106 used in the transistor 100 can be used. In the second doping step, the oxide semi conductor layer 103, the concentration of the dopant 106 is 5×10 atoms / cm 19 atoms / cm 3 or more, 1× 10 22 atoms / cm 3 or less, preferably 1×10 20 atoms / cm 3 or more, less than 7 atomic %.

[0189] In this way, a source region 103a, a drain region 103b, a low concentration region 103d, and a low concentration region 103e can be formed in the transistor 140. The low concentration regions 103 d and the low concentration region 103e have a lower dopant concentration and a higher resistivity than the source region 103a and the drain region 103b. By providing the low concentration regions 103d and 103e, deterioration of transistor characteristics and a negative shift of the threshold voltage due to the short channel effect can be reduced, and a more

[0190] reliable transistor can be fabricated. reliable transistor can be fabricated. reliable transistor can be fabricated.

[0191] Note that the channel length of the transistor 140 corresponds to the length of the channel formation region 103c sandwiched between the low concentration regions 103d and 103e in Fig. 2(B). Also, the channel length of the transistor 140 is almost equal to the width of the gate electrode 105.

[0192] This embodiment can be implemented in appropriate combination with other embodiments.

[0193] (Embodiment 2) In this embodiment, an example of a transistor having a configuration different from the transistor disclosed in Embodiment 1 will be described.

[0194] Fig. 5(A) is a top view for explaining the configuration of the transistor 150, and Fig. 5(B) is a cross-sectional view for explaining the laminated structure of the portion indicated by the chain line C1-C2 in Fig. 5 (A). Note that in Fig. 5(A), the description of the substrate and the insulating layer is omitted.

[0195] The transistor 150 shown in Fig. 5(B) has different laminated positions of the source electrode 110a and the drain electrode 110b compared to the transistor 100 disclosed in Embodiment 1. The transistor 150 has the source electrode 110a and the drain electrode 110b formed on the underlying layer 102, and an oxide semiconductor layer 103 is formed on the underlying layer 102, the source electrode 110a, and the drain electrode 110b.

[0196] In the transistor 150, since the source electrode 110a and the drain electrode 110b are connected to the source region 103a and the drain region 10 3b of the oxide semiconductor layer 103 without passing through the contact hole 109, it is easy to increase the connection area and reduce the contact resistance. ​​​​​​​

[0197] Note that the channel length of the transistor 150 corresponds to the length of the channel formation region 103c sandwiched between the source region 103a and the drain region 103b in FIG. 5(B). Also, the channel length of the transistor 150 is approximately equal to the width of the gate electrode 105.

[0198] The transistor 160 shown in FIG. 6 has, in addition to the configuration of the transistor 150, sidewalls 111 on the side surfaces of the gate electrode 10 5, and has low concentration regions 103d and 103e in regions overlapping with the sidewalls 111 of the oxide semiconductor layer 103. The low concentration reg ion 103d is formed between the channel formation region 103c and the source region 103a, and the low concentration reg ion 103e is formed between the channel formation region 103c and the drain region 103b. FIG. 6(A) is a top view for explaining the configuration of the transistor 160, and FIG. 6(B) is a cross-sectional view for explaining the stacked structure of the portion indicated by the chain line D1 - D2 in FIG. 6 (A). (A).

[0199] By providing the low concentration region 103d or the low concentration region 103e in the oxide semiconductor layer 103, the electric field generated between the channel formation region 103c and the source region 103a or the drain region 103b can be relaxed, and deterioration of transistor characteristics can be reduced. In particular, relaxation of the electric field generated in the channel formation region 103c and the drain region 103b is effective in reducing deterioration of transistor characteristics. Also, by providing the low concentration region 103d or the low concentration region 103e, the short channel effect accompanying miniaturization of the transistor can be suppressed. Note that the channel length of the transistor 160 corresponds to the length between the low concentration region 103d and in FIG. 6(B).

[0200] Note that the channel length of the transistor 160 corresponds to the length between the low concentration region 103d and This corresponds to the length of the channel forming region 103c sandwiched between the low concentration regions 103e. The channel length of the transistor 160 is approximately equal to the width of the gate electrode 105 .

[0201] The transistor 170 illustrated in FIG. 7A is one type of bottom-gate transistor. do.

[0202] FIG. 7A illustrates a cross-sectional structure of a transistor 170. The transistor 170 has a base A gate electrode 105 is formed on the plate 101, and a gate insulating layer 104 is formed on the gate electrode 105. The gate electrode 105 is formed by stacking the gate electrode 105a on the gate electrode 105b. Between the substrate 101 and the gate electrode 105, the A base layer may be provided.

[0203] In addition, the oxide semiconductor layer 103 is formed over the gate insulating layer 104. A channel protection layer 112, a source electrode 110a, and a drain electrode 110b are formed on the The oxide semiconductor layer 103 has a channel formation region 1 overlapping with the channel protection layer 112. 03c, a source region 103a electrically connected to the source electrode 110a, and a drain electrode It has a drain region 103b electrically connected to 110b.

[0204] The channel protection layer 112 is formed using the same material and method as the gate insulating layer 104. The thickness of the channel protection layer 112 is preferably 10 nm or more and 500 nm or less. The thickness is preferably 100 nm or more and 300 nm or less.

[0205] The source region 103a and the drain region 103b are formed by using the channel protection layer 112 as a mask. It can be formed in the same manner as transistor 100.

[0206] Also, an insulating layer 108 is formed over the channel protection layer 112, the source electrode 110a, and the drain electrode 110b. The insulating layer 108 may be a stack of a plurality of insulating layers.

[0207] Note that the channel length of transistor 170 corresponds to the length of the channel formation region 103c sandwiched between the source region 103a and the drain region 103b in FIG. 7(A). Also, the channel length of transistor 170 is substantially equal to the width of the channel protection layer 112.

[0208] FIG. 7(B) shows a cross-sectional structure of transistor 180. Transistor 180 has a structure in which a back gate electrode 115 and an insulating layer 113 are provided to transistor 100. In transistor 180, a back gate electrode 115 is formed over the base layer 102, and an insulating layer 113 is formed over the back gate electrode 115. Also, the oxide semiconductor layer 103 of transistor 180 is formed to overlap with the back gate electrode 115 with the insulating layer 113 therebetween.

[0209] The back gate electrode 115 is arranged so as to sandwich the channel formation region 103c of the oxide semiconductor layer 103 with the gate electrode 105 and the back gate electrode 115. The back gate electrode 115 is formed of a conductive layer and can function in the same manner as the gate electrode 105. Also, by changing the potential of the back gate electrode 115, the threshold voltage of the transistor can be changed.

[0210] The back gate electrode 115 can be formed of the same material and by the same method as the gate electrode 105b. This is possible. Also, a layer similar to the gate electrode 105a may be provided between the back gate electrode 115 and the insulating layer 113. This is possible.

[0211] The insulating layer 113 can be formed by the same material and method as the gate insulating layer 104. Also, it is possible to configure such that the insulating layer 113 also serves as the underlying layer 102 without forming the underlying layer 102. This is possible.

[0212] Note that the channel length of the transistor 180 corresponds to the length of the channel formation region 103c sandwiched between the source region 103a and the drain region 103b in FIG. 7(B). Also, the channel length of the transistor 180 is substantially equal to the width of the gate electrode 105. This is possible.

[0213] This embodiment can be implemented in appropriate combination with other embodiments.

[0214] (Embodiment 3) In this embodiment, a method for forming an oxide semiconductor film made of CAAC-OS will be described below for methods other than those disclosed in Embodiment 1. This is possible.

[0215] First, an oxide semiconductor film having a thickness of 1 nm or more and 50 nm or less is formed on the underlying layer 102.

[0216] The substrate temperature during film formation is 150°C or more and 450°C or less, preferably 200°C or more and 350°C or less. By heating the substrate to 150°C or more and 450°C or less, preferably 200°C or more and 350°C or less, and performing film formation, it is possible to prevent the incorporation of moisture (including hydrogen) into the film. Also, it is possible to form CAAC-OS, which is an oxide semiconductor film including crystallinity. This is possible. This is possible.

[0217] Furthermore, after forming the oxide semiconductor, the substrate 101 is heat-treated to release hydrogen from the oxide semiconductor and diffuse a part of the oxygen contained in the underlayer 102 near the interface of the oxide semiconductor in the underlayer 102. It is preferable. Also, by performing the heat treatment, an oxide semiconductor having a more highly crystalline CAAC-OS can be formed. It is preferable to release hydrogen and diffuse a part of the oxygen contained in the underlayer 102 near the interface of the oxide semiconductor in the underlayer 102. Furthermore, by performing the heat treatment, an oxide semiconductor having a more highly crystalline CAAC-OS can be formed. It is possible to form an oxide semiconductor having a more highly crystalline CAAC-OS.

[0218] The temperature of the heat treatment is preferably a temperature at which hydrogen is released from the oxide semiconductor, a part of the oxygen contained in the underlayer 102 is released, and further diffused into the oxide semiconductor. Typically, it is 200 °C or higher and less than the strain point of the substrate 101, preferably 250 °C or higher and 450 °C or lower. By diffusing oxygen into the oxide semiconductor, oxygen vacancies in the oxide semiconductor can be reduced. That is, it is 200 °C or higher and less than the strain point of the substrate 101, preferably 250 °C or higher and 450 °C or lower. By diffusing oxygen into the oxide semiconductor, oxygen vacancies in the oxide semiconductor can be reduced. It is possible to reduce the oxygen vacancies in the oxide semiconductor.

[0219] Also, the heat treatment can be performed using an RTA (Rapid Thermal Anneal) apparatus. By using RTA, heat treatment can be performed at a temperature equal to or higher than the strain point of the substrate for a limited time. Therefore, the time required to form an oxide semiconductor having a large ratio of the crystalline region to the amorphous region can be shortened. Therefore, the time required to form an oxide semiconductor having a large ratio of the crystalline region to the amorphous region can be shortened.

[0220] The heat treatment can be performed in an inert gas atmosphere. Typically, it is preferably performed in a rare gas such as helium, neon, argon, xenon, krypton, or a nitrogen atmosphere. Also, it may be performed in an oxygen atmosphere or a reduced pressure atmosphere. The treatment time is 3 minutes to 24 hours. The longer the treatment time, the more an oxide semiconductor having a large ratio of the crystalline region to the amorphous region can be formed. However, heat treatment exceeding 24 hours is not preferable because it causes a decrease in productivity. The longer the treatment time, the more an oxide semiconductor having a large ratio of the crystalline region to the amorphous region can be formed. However, heat treatment exceeding 24 hours is not preferable because it causes a decrease in productivity. ​​

[0221] By the above method, an oxide semiconductor composed of CAAC-OS can be formed.

[0222] This embodiment can be implemented in appropriate combination with other embodiments.

[0223] (Embodiment 4) In this embodiment, the influence on the electrical characteristics of the transistor using the oxide semiconductors shown in Embodiment 1 and Embodiment 2 will be described with reference to the band diagram.

[0224] FIG. 8 is a cross-sectional view of a transistor having a stacked structure equivalent to the transistor 100 shown in FIG. 1. FIG. 9 shows the energy band diagram (schematic diagram) in the X1-X2 cross section shown in FIG. 8. Furthermore, FIG. 9(B) shows the case where the voltage between the source and the drain is set to an equipotential (VD = 0V). FIG. 8 shows an oxide semiconductor layer composed of a first oxide semiconductor region (referred to as OS1) and a pair of second oxide semiconductor regions (referred to as OS2), and a transistor formed by a source electrode and a drain electrode (referred to as metal).

[0225] The channel formation region of the transistor in FIG. 8 is formed by OS1, and OS1 is made highly pure by removing and desorbing impurities such as moisture (including hydrogen) from the film as much as possible, and further reducing oxygen vacancies in the film to make it intrinsic (i-type), or an oxide semiconductor that approaches intrinsic as much as possible. By doing so, the Fermi level (Ef) can be made the same level as the intrinsic Fermi level (Ei).

[0226]

[0226] Also, the source region and the drain region of the transistor in FIG. 8 are formed by a pair of OS2. Like the OS1, the OS2 is formed by removing impurities such as moisture (including hydrogen) from the film. By removing and desorbing as many impurities as possible to achieve high purification, and by reducing oxygen vacancies in the film, An oxide semiconductor that is more intrinsic (i-type) or as close to intrinsic as possible is then At least one of group 15 elements such as nitrogen, phosphorus, or arsenic is selected. By adding elements, OS2 has a higher crystallinity than OS1. The rear density increases and the Fermi level moves closer to the conduction band.

[0227] FIG. 9A shows a state where a first oxide semiconductor region (OS1) is in a vacuum state (Evac). , a second oxide semiconductor region (referred to as OS2), and a source electrode and a drain electrode (met al), where IP is the ionization potential and Ea is Electron affinity, Eg is the energy gap, Wf is the work function. Also, Ec is the conduction band The lower end of the valence band, Ev, the upper end of the valence band, and Ef, the Fermi level. The numbers are 1 for OS1, 2 for OS2, and m for metal. We assume that Wf_m is 4.1 eV (e.g. titanium).

[0228] OS1 is an i-type or substantially i-type oxide semiconductor with extremely low carrier density. Therefore, Ef_1 is approximately in the middle between Ec and Ev. Also, OS2 is the carrier density. It is a high n-type oxide semiconductor, and Ec_2 and Ef_2 are roughly the same.

[0229] The oxide semiconductor shown in OS1 has an energy gap (Eg) of 3.15 eV and an electron affinity of (Ea) is said to be 4.3 eV. The oxide semiconductor shown in OS2 is Depending on the amount, the energy gap (Eg) can be made smaller than 3.15. In this case, the ionization potential hardly changes, so the electron affinity and The work function becomes larger. Figure 9 shows the case where Eg of OS2 is smaller than that of OS1. (That is, Eg_1>Eg_2.)

[0230] As shown in FIG. 9B, the channel forming region OS1 and the source and drain regions When the OS2 regions come into contact, carriers move so that the Fermi levels match, The band edge of OS1 is bent. Furthermore, the band edge of OS2 and the source and drain electrodes, me When two tal contact each other, carriers move so that the Fermi levels match, and the OS The end of band 2 is bent.

[0231] In this way, the OS1 which becomes the channel formation region and the met which becomes the source electrode and the drain electrode are The n-type oxide semiconductor OS2 is formed between Al and the oxide semiconductor The contact between the metal and the semiconductor can be made ohmic, and the contact resistance can be reduced. As a result, the on-state current of the transistor can be increased. , the bending of the OS1 band edge can be reduced, resulting in a short channel transistor. The effect can be suppressed.

[0232] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0233] (Embodiment 5) FIG. 10A is a circuit diagram of a memory element (hereinafter also referred to as a memory cell) constituting a semiconductor device. An example of a memory cell is shown in FIG. The transistor 1162 using the resistor 1160 and the oxide semiconductor in the channel formation region is configured as follows. It is configured.

[0234] The transistor 1162 using the oxide semiconductor in the channel formation region can be manufactured according to the first embodiment. It can be manufactured.

[0235] As shown in FIG. 10(A), one of the gate electrode of the transistor 1160 and the source electrode or the drain electrode of the transistor 1162 is electrically connected. Also, the first wiring (1st Line: also called source line) and the source electrode of the transistor 1160 are electrically connected, and the second wiring (2nd Line: also called bit line) and the drain electrode of the transistor 1160 are electrically connected. And the third wiring (3rd Line: also called first signal line) and the other of the source electrode or the drain electrode of the transistor 1162 are electrically connected, and the fourth wiring (4th Line: also called second signal line) and the gate electrode of the transistor 1162 are electrically connected. electrically connected. And the third wiring (3rd Line: also called first signal line) and the other of the source electrode or the drain electrode of the transistor 1162 are electrically connected, and the fourth wiring (4th Line: also called second signal line) and the gate electrode of the transistor 1162 are electrically connected. are electrically connected.

[0236] A transistor 1160 using a material other than an oxide semiconductor, for example, single crystal silicon, in the channel formation region can operate at a sufficient high speed. Therefore, by using the transistor 1160, it is possible to read the stored content at high speed. Also, the transistor 1162 using the oxide semiconductor in the channel formation region has a characteristic that the off-current is smaller than that of the transistor 1160. For this reason, by turning off the transistor 1162, it is possible to hold the potential of the gate electrode of the transistor 1160 for an extremely long time. it is possible. the potential of the gate electrode of the transistor 1160 can be held for an extremely long time. It is possible.

[0237] By taking advantage of the feature that the potential of the gate electrode can be held, writing, holding, and reading of information can be performed as follows.

[0238] First, writing and holding of information will be described. First, the potential of the fourth wiring is set to a potential at which the transistor 1162 is turned on, and the transistor 1162 is turned on . As a result, the potential of the third wiring is applied to the gate electrode of the transistor 1160 ( writing). Thereafter, the potential of the fourth wiring is set to a potential at which the transistor 1162 is turned off, and by turning off the transistor 1162, the potential of the gate electrode of the transistor 1160 is held (holding).

[0239] Since the off-current of the transistor 1162 is smaller than that of the transistor 1160, the potential of the gate electrode of the transistor 1160 is held for a long time. For example, if the potential of the gate electrode of the transistor 1160 is a potential that turns on the transistor 1160, the on-state of the transistor 1160 will be held for a long time. Also, if the potential of the gate electrode of the transistor 1160 is a potential that turns off the transistor 1160, the off-state of the transistor 1160 will be held for a long time.

[0240] Next, reading of information will be described. As described above, in a state where the on-state or off-state of the transistor 1160 is held, when a predetermined potential (low potential) is applied to the first wiring, the potential of the second wiring takes different values according to the on-state or off-state of the transistor 1160. For example, when the transistor 1160 is in the on-state, the first wiring With respect to the potential, the potential of the second wiring will decrease. Also, when the transistor 1160 is in the off state, the potential of the second wiring does not change.

[0241] In this way, in the state where the information is retained, by comparing the potential of the second wiring with a predetermined potential the information can be read out.

[0242] Next, the rewriting of information will be described. The rewriting of information is performed in the same manner as the writing and retention of the above information. That is, with the potential of the fourth wiring being the potential at which the transistor 1162 becomes on, the transistor 1162 is turned on. As a result, the potential of the third wiring (the potential related to the new information) is applied to the gate electrode of the transistor 1160. Then, with the potential of the fourth wiring being the potential at which the transistor 1162 becomes off, the transistor 1162 is turned off, whereby a state where the new information is retained is achieved.

[0243] As described above, the memory cell according to the disclosed invention can directly rewrite the information by writing the information again. For this reason, the erasing operation required in a flash memory or the like is unnecessary, and it is possible to suppress a decrease in the operation speed due to the erasing operation. That is, high-speed operation of the semiconductor device having the memory cell is realized.

[0244] Also, an example of a circuit diagram of a memory cell developed from FIG. 10(A) is shown in FIG. 10(B).

[0245] The memory cell 1100 shown in FIG. 10(B) includes a first wiring SL (source line), a second wiring BL (bit line), a third wiring S1 (first signal line), and a fourth wiring S2 (second signal line) ​​​​​​​and a fifth wiring WL (word line), a transistor 1164 (first transistor), and a transistor 1161 (second transistor) and a transistor 1163 (third tran sistor). Transistors 1164 and 1163 use a material other than an oxide semiconductor for the channel formation region, and transistor 1161 uses an oxide semiconductor for the channel formation region.

[0246] Here, one of the gate electrode of transistor 1164 and the source electrode or drain electrode of transistor 1161 is electrically connected. Also, the first wiring SL and the source electrode of transistor 1164 are electrically connected, the drain electrode of transistor 1164 and the source electrode of transistor 1163 are electrically connected. And the second wiring BL and the drain electrode of transistor 1163 are electrically connected, the third wiring S1 and the other of the source electrode or drain electrode of transistor 1161 are electrically connected, the fourth wiring S2 and the gate electrode of transistor 1161 are electrically connected, and the fifth wiring WL and the gate electrode of transistor 1163 are electrically connected.

[0247] Next, the operation of the circuit will be specifically described.

[0248] When writing to the memory cell 1100, the first wiring SL is set to 0V, the fifth wiring WL is set to 0V, the second wiring BL is set to 0V, and the fourth wiring S2 is set to 2V. When writing data "1", the third wiring S1 is set to 2V, and when writing data "0", the third wiring S1 is set to 0V. At this time, transistor 1163 is in the off state and transistor 1161 is in the on state. ​ This occurs. At the end of writing, before the potential of the third wiring S1 changes, the fourth wiring S2 is set to 0V and the transistor 1161 is turned off.

[0249] As a result, after writing data "1", the potential of the node (hereinafter referred to as node A) connected to the gate electrode of the transistor 1164 is about 2V, and after writing data "0", the potential of node A is about 0V. Charge corresponding to the potential of the third wiring S1 is accumulated in node A, but the off-current of the transistor 1161 is smaller than that of a transistor using single-crystalline silicon in the channel formation region, and the potential of the gate electrode of the transistor 1164 is held for a long time.

[0250] Next, when reading the memory cell, the first wiring SL is set to 0V, the fifth wiring WL is set to 2 V, the fourth wiring S2 is set to 0V, the third wiring S1 is set to 0V, and the read circuit connected to the second wiring BL is set to the operating state. At this time, the transistor 1163 is in the on state and the transistor 1161 is in the off state.

[0251] If the data is "0", that is, when node A is in a state of about 0V, the transistor 1164 is in the off state , so the resistance between the second wiring BL and the first wiring SL is in a high state. On the other hand, if the data is "1", that is, when node A is in a state of about 2V, the transistor 1164 is in the on state , so the resistance between the second wiring BL and the first wiring SL is in a low state. The read circuit can read data "0" and "1" based on the difference in the resistance state of the memory cell. Note that the second wiring BL was set to 0V during writing, but it is in a floating state or charged to a potential of 0V or higher. ​​​​​It may also be in a floating state even if the third wiring S1 at the time of reading is set to 0V. It may also be charged to a potential of floating state or 0V or higher.

[0252] Note that the data "1" and the data "0" are for convenience of definition and may be reversed. Also the operating voltages described above are just examples. The operating voltage is such that transistor 1 164 is in the off state when the data is "0", and transistor 1164 is in the on state when the data is "1" In addition, transistor 1161 is in the on state during writing and in the off state otherwise and transistor 1163 is in the on state during reading. It is sufficient to select the operating voltage accordingly. In particular, instead of 2V, the power supply potential VDD of the peripheral logic circuit may be used.

[0253] In this embodiment, for simplicity of understanding, the memory cell of the minimum storage unit (1 bit) has been described However, the configuration of the memory cell is not limited to this. A plurality of memory cells can be appropriately connected to form a more advanced semiconductor device. For example, using the above memory cells in multiple numbers, it is possible to form NAND-type or NOR-type semiconductor devices. The configuration of the wiring is not limited to FIGS. 10(A) and 10(B) and can be changed as appropriate.

[0254] FIG. 11 shows a block circuit diagram of a semiconductor device according to an aspect of the present invention having a storage capacity of m×n bits.

[0255] The semiconductor device shown in FIG. 11 includes m fifth wirings and fourth wirings, n second wirings and third wirings, and a memory cell array 11 in which a plurality of memory cells 1100(1, 1) to 1100(m, n) are arranged in a matrix of m (rows )×n (columns) (m and n are natural numbers). 10, the second wiring and the third wiring drive circuit 1111, the fourth wiring and the fifth wiring drive circuit 1113, and peripheral circuits such as the read circuit 1112. As other peripheral circuits, a refresh circuit or the like may be provided.

[0256] As a representative of each memory cell, consider the memory cell 1100(i, j). Here, the memory cell 1100(i, j) (i is an integer from 1 to m, j is an integer from 1 to n) is connected to the second wiring BL(j), the third wiring S1(j), the fifth wiring WL(i), and the fourth wiring S2(i ), and the first wiring, respectively. The first wiring potential Vs is applied to the first wiring. Also, the second wirings BL(1) to BL(n) and the third wirings S1(1) to S 1(n) are connected to the second wiring and the third wiring drive circuit 1111 and the read circuit 1112, and the fifth wirings WL(1) to WL(m) and the fourth wirings S2(1) to S2(m) are connected to the fourth wiring and the fifth wiring drive circuit 1113, respectively.

[0257] The operation of the semiconductor device shown in FIG. 11 will be described. In this configuration, writing and reading are performed for each row.

[0258] When writing to the memory cells 1100(i, 1) to 1100(i, n) in the i-th row, the first wiring potential Vs is set to 0V, the fifth wiring WL(i) is set to 0V, the second wirings BL(1) to BL( n) are set to 0V, and the fourth wiring S2(i) is set to 2V. At this time, the transistor 1161 is in the on state. The third wirings S1(1) to S1(n) are set to 2V for the columns where data "1" is to be written and 0V for the columns where data "0" is to be written. At the end of writing, the third wiring Before the potentials of the wirings S1(1) to S1(n) change, the fourth wiring S2(i) is set to 0V, and the transistor 1161 is turned off. Also, the non-selected fifth wiring WL is set to 0V, and the non-selected fourth wiring S2 is set to 0V.

[0259] As a result, the potential of the node (hereinafter referred to as node A) connected to the gate electrode of the transistor 1164 of the memory cell in which data "1" has been written is approximately 2V, and the potential of node A of the memory cell in which data "0" has been written is approximately 0V. Also, the potential of node A of the non-selected memory cell does not change.

[0260] When reading the memory cells 1100(i, 1) to 1100(i, n) in the i-th row, the potential of the first wiring Vs is set to 0V, the potential of the fifth wiring WL(i) is set to 2V, the potential of the fourth wiring S2(i) is set to 0V , the potentials of the third wirings S1(1) to S1(n) are set to 0V, and the readout circuit connected to the second wirings BL(1) to BL(n) is put into an operating state. In the readout circuit, for example, data "0" and "1" can be read out based on the difference in the resistance states of the memory cells. Note that the non-selected fifth wiring WL is set to 0V, and the non-selected fourth wiring S2 is set to 0V. Note that the potential of the second wiring BL was set to 0V during writing, but it may be in a floating state or charged to a potential of 0V or higher . The potential of the third wiring S1 during reading was set to 0V, but it may be in a floating state or charged to a potential of 0V or higher .

[0261] Note that data "1" and data "0" are for convenience of definition and may be reversed. Also, the above-described operating voltages are just examples. The operating voltages are such that the transistor 1 164 is turned off in the case of data "0" and the transistor 1164 is turned on in the case of data "1". Also, transistor 1161 is in the on state during writing and in the off state otherwise. Also, if it is selected such that transistor 1163 is in the on state during reading, it is good. In particular, instead of 2V, the power supply potential VDD of the peripheral logic circuit may be used.

[0262] This embodiment can be implemented in appropriate combination with other embodiments.

[0263] (Embodiment 6) In this embodiment, an example of a circuit diagram of a memory cell having a capacitive element is shown. In FIG. 12(A), the memory cell 1170 shown includes a first wiring SL, a second wiring BL, a third wiring S1, a fourth wiring S2, a fifth wiring WL, a transistor 1171 (first transistor), and a trans istor 1172 (second transistor), and a capacitive element 1173. Transistor 1171 uses a material other than an oxide semiconductor for the channel formation region, and trans istor 1172 uses an oxide semiconductor for the channel formation region.

[0264] Here, the gate electrode of transistor 1171, one of the source electrode or the drain electrode of transistor 1172, and one electrode of capacitive element 1173 are electrically connected. Also, the first wiring SL and the source electrode of transistor 1171 are electrically connected, the second wiring BL and the drain electrode of transistor 1171 are electrically connected, and the third wiring S1 and the other of the source electrode or the drain electrode of transistor 1172 are electrically connected, the fourth wiring S2 and the gate electrode of transistor 1172 are electrically connected, and the fifth wiring WL and the other electrode of capacitive element 1173 are electrically connected.

[0265] Next, the operation of the circuit will be specifically described.

[0266] When writing to the memory cell 1170, the first wiring SL is set to 0V, the fifth wiring WL is set to 0V, the second wiring BL is set to 0V, and the fourth wiring S2 is set to 2V. When writing data "1", the third wiring S1 is set to 2V, and when writing data "0", the third wiring S1 is set to 0V. At this time, the transistor 1172 is turned on. When the writing is completed, before the potential of the third wiring S1 changes, the fourth wiring S2 is set to 0V to turn off the transistor 1172.

[0267] As a result, after writing data "1", the potential of the node (hereinafter referred to as node A) connected to the gate electrode of the transistor 1171 is about 2V, and after writing data "0", the potential of node A is about 0V.

[0268] When reading the memory cell 1170, the first wiring SL is set to 0V, the fifth wiring WL is set to 2V, the fourth wiring S2 is set to 0V, the third wiring S1 is set to 0V, and the reading circuit connected to the second wiring BL is set to the operating state. At this time, the transistor 1172 is turned off. .

[0269] The state of the transistor 1171 when the fifth wiring WL is set to 2V will be described. The potential of node A that determines the state of the transistor 1171 depends on the capacitance C1 between the fifth wiring WL and node A, the gate electrode of the transistor 1171, and the capacitance C2 between the source electrode and the drain electrode.

[0270] Note that although the third wiring S1 is set to 0V during reading, in a floating state or a potential of 0V or higher It may be charged. Data "1" and data "0" are for convenience of definition and may be reversed. It doesn't matter either.

[0271] The potential of the third wiring S1 during writing is such that the transistor 1172 is turned off after writing, and within the range where the transistor 1171 is turned off when the potential of the fifth wiring is 0V, the potentials of data "0" and "1" can be selected respectively. The potential of the fifth wiring during reading is such that the transistor 1171 is turned off in the case of data "0" and the transistor 1171 is turned on in the case of data "1". Also, the threshold voltage of the transistor 1171 is just an example. Any threshold voltage may be used as long as it doesn't change the state of the transistor 1171 as described above. As long as it is within the range that doesn't change the state of the transistor 1171 described above, any threshold value is acceptable.

[0272] Also, an example of a NOR-type semiconductor memory device using a selection transistor having a first gate electrode and a second gate electrode and a memory cell having a capacitive element will be described with reference to FIG. 12(B). Using FIG. 12(B), it will be explained.

[0273] The semiconductor device according to one aspect of the present invention shown in FIG. 12(B) includes a memory cell array comprising a plurality of memory cells arranged in a matrix in I rows (I is a natural number of 2 or more) and J columns (J is a natural number).

[0274] The memory cell array shown in FIG. 12(B) includes a plurality of memory cells 1180 arranged in a matrix in i rows (i is a natural number of 3 or more) and j columns (j is a natural number of 3 or more), i word lines WL (word lines WL_1 to word line WL_i), i capacitive lines CL (capacitive lines CL_1 to capacitive line CL_i), and i gate lines BGL (gate lines BGL_1 to gate line BGL_i). _i) and j bit lines BL (bit lines BL_1 to BL_j), and a source line SL, and includes them.

[0275] Furthermore, each of the plurality of memory cells 1180 (memory cell 1180(M,N) (where , M is a natural number from 1 to i, and N is a natural number from 1 to j) is also referred to as) includes a transistor 1181(M,N), a capacitance element 1183(M,N), and a transistor 1182(M,N ).

[0276] In the semiconductor memory device, the capacitance element is composed of a first capacitance electrode, a second capacitance electrode, and a dielectric layer that overlaps the first capacitance electrode and the second capacitance electrode. The capacitance element accumulates charges according to the voltage applied between the first capacitance electrode and the second capacitance electrode.

[0277] Transistor 1181(M,N) is an N-channel transistor and has a source electrode, a drain electrode, a first gate electrode, and a second gate electrode. In the semiconductor memory device of the present embodiment , transistor 1181 does not necessarily have to be an N-channel transistor .

[0278] One of the source electrode and the drain electrode of transistor 1181(M,N) is connected to bit line BL _N, the first gate electrode of transistor 1181(M,N) is connected to word line WL _M, and the second gate electrode of transistor 1181(M,N) is connected to gate line BG L_M. By configuring one of the source electrode and the drain electrode of transistor 1181(M,N) to be connected to bit line BL_N, data can be selectively read for each memory cell . read out.

[0279] Transistor 1181(M,N) functions as a selection transistor in memory cell 1180(M,N).

[0280] As transistor 1181(M,N), a transistor using an oxide semiconductor for the channel formation region can be used.

[0281] Transistor 1182(M,N) is a P-channel transistor. Note that in the semiconductor memory device of this embodiment, transistor 1182 does not necessarily have to be a P-channel transistor.

[0282] One of the source electrode and the drain electrode of transistor 1182(M,N) is connected to source line SL, the other of the source electrode and the drain electrode of transistor 1182(M,N) is connected to bit line BL_N, and the gate electrode of transistor 1182(M,N) is connected to the other of the source electrode and the drain electrode of transistor 1181(M,N).

[0283] Transistor 1182(M,N) functions as an output transistor in memory cell 1180(M,N). As transistor 1182(M,N), for example, a transistor using single-crystalline silicon for the channel formation region can be used.

[0284] The first capacitor electrode of capacitor element 1183(M,N) is connected to capacitor line CL_M, the second capacitor electrode of capacitor element 1183(M,N) is connected to the other of the source electrode and the drain electrode of transistor 1181(M,N). Note that capacitor element 1183(M,N) functions as a holding capacitor.

[0285] ​​​​​​​​​​​​ The voltages of each of word lines WL_1 to WL_i are controlled by a driving circuit using, for example, a decoder.

[0286] The voltages of each of bit lines BL_1 to BL_j are controlled by a driving circuit using, for example, a decoder.

[0287] The voltages of each of capacitance lines CL_1 to CL_i are controlled by a driving circuit using, for example, a decoder.

[0288] The voltages of each of gate lines BGL_1 to BGL_i are controlled using, for example, a gate line driving circuit.

[0289] The gate line driving circuit is constituted by a circuit including, for example, a diode and a capacitive element in which a first capacitive electrode is electrically connected to the anode of the diode and the gate line BGL.

[0290] By adjusting the voltage of the second gate electrode of transistor 1181, the threshold voltage of transistor 1181 can be adjusted. Therefore, the threshold voltage of transistor 1181 that functions as a selection transistor can be adjusted, and the current flowing between the source electrode and the drain electrode of transistor 1181 in the off state can be made as small as possible. Thus, the data holding period in the memory circuit can be lengthened. Also, since the voltages required for data writing and reading can be made lower than those of conventional semiconductor devices, power consumption can be reduced.

[0291] This embodiment can be implemented in appropriate combination with other embodiments.

[0292] (Embodiment 7) In this embodiment, an example of a semiconductor device using the transistor shown in the previous embodiment will be described with reference to FIG. 13.

[0293] FIG. 13(A) shows an example of a semiconductor device having a configuration corresponding to a so-called DRAM (Dynamic Random Access Memory). The memory cell array 1120 shown in FIG. 13(A) has a configuration in which a plurality of memory cells 1130 are arranged in a matrix . Further, the memory cell array 1120 has m first wirings and n second wirings . In this embodiment, the first wiring is referred to as a bit line BL, and the second wiring is referred to as a word line WL.

[0294] The memory cell 1130 is composed of a transistor 1131 and a capacitor element 1132 . The gate electrode of the transistor 1131 is connected to the first wiring (word line WL) . Further, one of the source electrode or the drain electrode of the transistor 1131 is connected to the second wiring (bit line BL), and the other of the source electrode or the drain electrode of the transistor 1131 is connected to one of the electrodes of the capacitor element. Also, the other electrode of the capacitor element is connected to a capacitor line CL, and a constant potential is applied. The transistor 1131 is applied with the transistor shown in the previous embodiment.

[0295] The transistor using the oxide semiconductor shown in the previous embodiment for the channel formation region has a feature that the off-current is smaller than that of a transistor using single-crystalline silicon for the channel formation region . Therefore, as shown in FIG. 13(A), which is recognized as a so-called DRAM When the transistor is applied to a semiconductor device, a substantial non-volatile memory can be obtained. It is possible.

[0296] FIG. 13(B) shows an example of a semiconductor device having a configuration corresponding to a so-called SRAM (Static Random Access Memory). The memory cell array 1140 shown in FIG. 13(B) may have a configuration in which a plurality of memory cells 1150 are arranged in a matrix. The memory cell array 1140 has a plurality of first wirings (word lines WL), a plurality of second wirings (bit lines BL), and a plurality of third wirings (inverted bit lines / BL). The memory cell array 1140 may have a configuration in which a plurality of memory cells 1150 are arranged in a matrix. The memory cell 1150 has a first transistor 1151, a second transistor 1152, a third transistor 1153, a fourth transistor 1154, a fifth transistor 1155, and a sixth transistor 1156. The first transistor 1151 and the second transistor 1152 function as selection transistors. Of the third transistor 1153 and the fourth transistor 1154, one is an n-channel transistor (here, the fourth transistor 1154), and the other is a p-channel transistor (here, the third transistor 1153). That is, a CMOS circuit is formed by the third transistor 1153 and the fourth transistor 1154. Similarly, a CMOS circuit is formed by the fifth transistor 1155 and the sixth transistor 1156.

[0297] The first transistor 1151, the second transistor 1152, the fourth transistor 1154, and the sixth transistor 1156 are n-channel transistors, as in the previous embodiment. The memory cell 1150 has a first transistor 1151, a second transistor 1152, a third transistor 1153, a fourth transistor 1154, a fifth transistor 1155, and a sixth transistor 1156. The first transistor 1151 and the second transistor 1152 function as selection transistors. Of the third transistor 1153 and the fourth transistor 1154, one is an n-channel transistor (here, the fourth transistor 1154), and the other is a p-channel transistor (here, the third transistor 1153). That is, a CMOS circuit is formed by the third transistor 1153 and the fourth transistor 1154. Similarly, a CMOS circuit is formed by the fifth transistor 1155 and the sixth transistor 1156. The first transistor 1151, the second transistor 1152, the fourth transistor 1154, and the sixth transistor 1156 are n-channel transistors. As in the previous embodiment, the third transistor 1153 and the fourth transistor 1154 form a CMOS circuit. Similarly, a CMOS circuit is formed by the fifth transistor 1155 and the sixth transistor 1156.

[0298] The first transistor 1151, the second transistor 1152, the fourth transistor 1154, and the sixth transistor 1156 are n-channel transistors, as in the previous embodiment. The first transistor 1151, the second transistor 1152, the fourth transistor 1154, and the sixth transistor 1156 are n-channel transistors, as in the previous embodiment. The transistor shown in the state can be applied. The third transistor 1153 and The fifth transistor 1155 is a p-channel transistor and uses a material other than an oxide semiconductor (e.g., single crystal silicon, etc.) for the channel formation region.

[0299] The configurations, methods, etc. shown in this embodiment can be appropriately combined with those shown in other embodiments and used.

[0300] This embodiment can be implemented in appropriate combination with other embodiments.

[0301] (Embodiment 8) A CPU (Central Processing Unit) can be configured by using at least a part of transistors using an oxide semiconductor for the channel formation region.

[0302] FIG. 14(A) is a block diagram showing a specific configuration of the CPU. The CPU shown in FIG. 14(A) has, on a substrate 1190, an arithmetic circuit (ALU: Arithmetic logic u nit) 1191, an ALU controller 1192, an instruction decoder 1193 , an interrupt controller 1194, a timing controller 1195, a register 11 96, a register controller 1197, a bus interface (Bus I / F) 119 8, a rewritable ROM 1199, and a ROM interface (ROM I / F) 1 189. The substrate 1190 uses a semiconductor substrate, an SOI substrate, a glass substrate, etc. The ROM 1199 and the ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in FIG. 14(A) is only an example showing a simplified configuration thereof, and the actual CPUs have a wide variety of configurations depending on their applications.

[0303] Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, and after being decoded, are input to the ALU controller 1192, the inter- rupt controller 1194, the register controller 1197, and the timing controller 1195.

[0304] The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. Also, the interrupt controller 1194 determines and processes interrupt requests from external input / output devices and peripheral circuits during the execution of the CPU program according to their priorities and mask states. The register controller 1197 generates addresses for the register 1196 and reads from and writes to the register 1196 according to the state of the CPU. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. Also, the interrupt controller 1194 determines and processes interrupt requests from external input / output devices and peripheral circuits during the execution of the CPU program according to their priorities and mask states. Also, the interrupt controller 1194 determines and processes interrupt requests from external input / output devices and peripheral circuits during the execution of the CPU program according to their priorities and mask states. The register controller 1197 generates addresses for the register 1196 and reads from and writes to the register 1196 according to the state of the CPU. The register controller 1197 generates addresses for the register 1196 and reads from and writes to the register 1196 according to the state of the CPU.

[0305] Also, the timing controller 1195 generates signals for controlling the operation timings of the ALU 1191, the ALU controller 119 2, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the clock signal CLK2 to the above various circuits. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the clock signal CLK2 to the above various circuits. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the clock signal CLK2 to the above various circuits. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the clock signal CLK2 to the above various circuits.

[0306] In the CPU shown in FIG. 14(A), a memory element is provided in register 1196. The register memory element of 1196 can use the memory element described in Embodiment 5.

[0307] In the CPU shown in FIG. 14(A), register controller 1197 selects the holding operation in register 1196 according to an instruction from ALU 1191. That is, in the memory element included in register 1196, it is selected whether to hold data by a phase inversion element or to hold data by a capacitance element. When holding data by a phase inversion element is selected, a power supply voltage is supplied to the memory element in register 1196. When holding data in a capacitance element is selected, data is rewritten to the capacitance element, and the supply of the power supply voltage to the memory element in register 1196 can be stopped.

[0308] Regarding power supply stop, as shown in FIG. 14(B) or FIG. 14(C), a switching element is provided between the memory element group and the node to which the power supply potential VDD or the power supply potential VSS is applied. The circuits of FIG. 14(B) and FIG. 14(C) will be described below.

[0309] In FIGS. 14(B) and 14(C), an example of a configuration of a memory circuit including a transistor using an oxide semiconductor in a channel formation region is shown for a switching element that controls the supply of a power supply potential to a memory element.

[0310] The memory device shown in FIG. 14(B) includes a switching element 1141 and a memory element group 1143 having a plurality of memory elements 1142. Specifically, each memory element 1142 can use the memory element described in Embodiment 5. ​​​​​​​​​​​​​The memory element described in Form 5 can be used. Each of the memory elements 1143 included in the memory element group The memory element 1142 is supplied with a high-level power supply potential VD D via the switching element 1141. Further, each memory element 1142 included in the memory element group 1143 is supplied with the potential of the signal IN and the potential of the low-level power supply potential VSS.

[0311] In FIG. 14(B), as the switching element 1141, a transistor having an oxide semiconductor in the channel formation region is used, and the switching of the transistor is controlled by a signal SigA applied to its gate electrode.

[0312] Note that in FIG. 14(B), the configuration in which the switching element 1141 has only one transistor is shown, but it is not particularly limited, and it may have a plurality of transistors. When the switching element 1141 has a plurality of transistors that function as switching elements the plurality of transistors may be connected in parallel, may be connected in series, or may be connected in a combination of series and parallel.

[0313] Also, in FIG. 14(B), the supply of the high-level power supply potential VDD to each memory element 1142 included in the memory element group 1143 is controlled by the switching element 1141, but the supply of the low-level power supply potential VSS may be controlled by the switching element 1141.

[0314] Also, in FIG. 14(C), a memory device in which a low-level power supply potential VSS is supplied to each memory element 1142 included in the memory element group 1143 via a switching element 1141 is shown. ​​​​​​​​​An example will be shown. The switching element 1141 can control the supply of the low-level power supply potential VSS to each memory element 1142 in the memory element group 1143.

[0315] A switching element is provided between the memory element group and a node to which the power supply potential VDD or the power supply potential VSS is supplied. Even when the operation of the CPU is temporarily stopped and the supply of the power supply voltage is stopped, it is possible to hold data and reduce power consumption. Specifically, for example, even while a user of a personal computer has stopped inputting information to an input device such as a keyboard, the operation of the CPU can be stopped, thereby reducing power consumption. Here, the CPU has been described as an example, but it is also applicable to LSIs such as DSP (Digital Signal Processor), custom LSI, and FPGA (Field Programmable e Gate Array). This embodiment can be implemented in appropriate combination with the above embodiment.

[0316]

[0317]

[0318]

Explanation of symbols

[0318] 100 Transistor 101 Substrate 102 Underlayer 103 Oxide semiconductor layer 104 Gate insulating layer 105 Gate electrode 106 Dopant 107 Insulating layer 108 Insulating layer 109 Contact hole 111 Sidewall 112 Channel protection layer 113 Insulating layer 115 Back gate electrode 140 Transistor 150 Transistor 160 Transistor 170 Transistor 180 Transistor 1100 Memory cell 1110 Memory cell array 1111 Wiring drive circuit 1112 Circuit 1113 Wiring drive circuit 1120 Memory cell array 1130 Memory cell 1131 Transistor 1132 Capacitive element 1140 Memory cell array 1141 Switching element 1142 Memory element 1143 Memory element group 1150 Memory cell 1151 Transistor 1152 Transistor 1153 Transistor 1154 Transistor 1155 Transistor 1156 Transistor 1160 Transistor 1161 Transistor 1162 Transistor 1163 Transistor 1164 Transistor 1170 Memory cell 1171 Transistor 1172 Transistor 1173 Capacitive element 1180 Memory cell 1181 Transistor 1182 Transistor 1183 Capacitive element 1189 ROM interface 1190 Substrate 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM 103a Source Region 103b Drain Region 103c Channel Formation Region 103d Low Concentration Region 103e Low Concentration Region 105a Gate Electrode 105b Gate Electrode 110a Source Electrode 110b Drain Electrode

Claims

1. A semiconductor device having a first transistor having an oxide semiconductor in a channel formation region and a second transistor having silicon in a channel formation region, wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor, comprising: a first insulating layer; an oxide semiconductor layer having a region in contact with an upper surface of the first insulating layer and having a channel formation region of the first transistor; a first conductive layer provided above the oxide semiconductor layer and functioning as a gate electrode of the first transistor; a second conductive layer provided below the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the first transistor; a second insulating layer having a region in contact with the first conductive layer and having a region located above the oxide semiconductor layer; wherein the oxide semiconductor layer contains In, Ga, and Zn and has a crystalline region; the first insulating layer contains silicon oxide; in a cross-sectional view in a channel length direction of the first transistor, the oxide semiconductor layer has: a first region overlapping with the first conductive layer; a second region not overlapping with the first conductive layer and the second conductive layer; a third region not overlapping with the first conductive layer but overlapping with the second conductive layer; the second region has a first portion overlapping with the second insulating layer and a second portion not overlapping with the second insulating layer; the first portion is located between the first region and the second portion; the second portion is located between the first portion and the third region; the third region has a region in contact with an upper surface of the first conductive layer and a region in contact with a side surface of the first conductive layer.

2. The semiconductor device according to claim 1, wherein the second portion has a region having a lower resistivity than the first region, and the first portion has a region having a lower resistivity than the first region and a higher resistivity than the second portion.

3. The semiconductor device according to claim 1 or 2, wherein the second portion has a region having a higher dopant concentration than the first region, and the first portion has a region having a higher dopant concentration than the first region and a lower dopant concentration than the second portion. ​ ​ ​ ​ ​ ​

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