Differential communication circuit

Abstract

To suppress the effect of common-mode noise signals superimposed on differential communication signals on communication.SOLUTION: A transmitting / receiving circuit 11 includes an attenuator 26 that attenuates a differential communication signal input via an insulation circuit 8 and supplies the attenuated signal to a receiving circuit 25, and a common mode signal suppression circuit 28 that suppresses a common mode noise signal superimposed on the differential communication signal based on an output signal of the attenuator 26. The common mode signal suppression circuit 28 includes a common mode signal detection circuit that detects a common mode voltage in the output signal of the attenuator 26, a first current generation circuit that generates a first correction current proportional to a first different voltage when the first different voltage obtained by subtracting a first reference voltage from the detected common mode voltage is a negative voltage, and supplies the first correction current to an input / output terminal of the transmitting / receiving circuit 11, and a second current generation circuit that generates a second correction current proportional to a second different voltage when the second different voltage obtained by subtracting the detected common mode voltage from a second reference voltage is a positive voltage, and supplies the second correction current to the input / output terminal of the transmitting / receiving circuit 11.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a differential communication circuit used in an insulated differential communication system including a differential communication transmission line and a plurality of differential communication circuits that communicate with each other in an insulated state via the differential communication transmission line.

Background Art

[0002] For example, an in-vehicle insulated communication circuit mounted on a vehicle such as an automobile needs to pass a CMTI test, which is a common mode transient immunity test typified by a BCI test or an ISO7637-3 test. Note that BCI is an abbreviation for Bulk Current Injection, and CMTI is an abbreviation for Common Mode Transient Immunity. Patent Document 1 discloses a configuration for passing such a test in an insulated communication circuit in which a transmitter and a receiver are capacitively insulated from each other, and a common-mode noise suppression circuit including a cross-coupling circuit and a common-phase feedback circuit is provided on the receiver side to suppress only the common-phase noise. Hereinafter, the configuration disclosed in Patent Document 1 may be referred to as the prior art.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The in-phase noise suppression circuit of the prior art has a narrow linear operating region. Also, the in-phase feedback circuit of the prior art is a pseudo-differential amplifier circuit. When it deviates from the linear region operation, the input in-phase noise is in-phase-to-differential converted, so there is a possibility that differential noise is input to the differential communication signal, causing communication errors. Further, in the prior art, when considering the application to uses where a relatively large noise such as about 20V is injected as the in-phase noise to be injected, a MOS transistor with high breakdown voltage with respect to the gate-source voltage Vgs and the drain-source voltage Vds is required as the transistor constituting the circuit.

[0005] Since the in-phase feedback circuit of the prior art is a pseudo-differential amplifier circuit as described above, a certain amount of steady bias current is required, and thus the power consumption inevitably increases accordingly. Also, since the in-phase feedback circuit of the prior art has a narrow linear region operation and a narrow frequency region where in-phase feedback is possible, a feedback current corresponding to the magnitude of the in-phase noise cannot be passed. Therefore, in the prior art, there is a possibility that the input in-phase noise is in-phase-to-differential converted into differential noise, deteriorating the SNR and causing communication errors. Note that SNR is an abbreviation of Signal to Noise Ratio.

[0006] The present invention has been made in view of the above circumstances, and an object thereof is to provide a differential communication circuit capable of suppressing the influence of an in-phase noise signal superimposed on a differential communication signal on communication.

Means for Solving the Problems

[0007] The differential communication circuit according to claim 1 is the differential communication circuit used in an insulated differential communication system (1) including a differential communication transmission line (4, 4a to 4d) and a plurality of differential communication circuits (20) that communicate with each other in an insulated state via the differential communication transmission line. The differential communication circuit includes a transmission circuit (24) that transmits a differential communication signal corresponding to transmission data to another differential communication circuit via the differential communication transmission line, and a reception circuit (25) that receives a differential communication signal transmitted from another differential communication circuit via the differential communication transmission line, generates reception data, and outputs the reception data. The differential communication circuit further includes a transmission-reception circuit (11, 11a, 11b) including the transmission circuit and the reception circuit, an insulation circuit (8, 8a, 8b) that insulates between the differential communication transmission line and the transmission-reception circuit, and a communication control circuit (12) that generates the transmission data, outputs the transmission data to the transmission-reception circuit, and inputs the reception data output from the transmission-reception circuit.

[0008] The transmission-reception circuit includes an attenuator (26) that attenuates the differential communication signal input via the insulation circuit and supplies the attenuated differential communication signal to the reception circuit, and a common-phase signal suppression circuit (28, 41, 51) that suppresses a common-phase noise signal superimposed on the differential communication signal based on an output signal of the attenuator. The common-phase signal suppression circuit includes a common-phase signal detection circuit (33) that detects a common-phase voltage in the output signal of the attenuator, a first current generation circuit (34, 43, 53) that generates a first correction current proportional to a first differential voltage when the first differential voltage obtained by subtracting a first reference voltage from the common-phase voltage detected by the common-phase signal detection circuit becomes a negative voltage, and supplies the generated first correction current to input-output terminals of the transmission-reception circuit, and a second current generation circuit (35, 44, 54) that generates a second correction current proportional to a second differential voltage when the second differential voltage obtained by subtracting the common-phase voltage detected by the common-phase signal detection circuit from a second reference voltage becomes a positive voltage, and supplies the generated second correction current to the input-output terminals of the transmission-reception circuit.

[0009] According to such a configuration, since the differential communication signal is attenuated by the attenuator and then input to the in-phase signal suppression circuit, even when an in-phase noise signal with a relatively large voltage amplitude is superimposed on the differential communication signal, the in-phase signal suppression circuit can function normally. Therefore, according to the above configuration, even when an in-phase noise signal with a relatively large voltage amplitude is superimposed on the differential communication signal, the in-phase noise signal is canceled by the operation of the in-phase signal suppression circuit. As a result, the influence of the in-phase noise signal superimposed on the differential communication signal on communication can be suppressed.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Modes for Carrying Out the Invention

[0011] Hereinafter, a plurality of embodiments will be described with reference to the drawings. In each embodiment, substantially the same components are denoted by the same reference numerals and the description thereof will be omitted. (First Embodiment) Hereinafter, the first embodiment will be described with reference to FIGS. 1 to 9.

[0012] <Overall Configuration> As shown in FIG. 1, the battery monitoring system 1 of the present embodiment is a system for monitoring a battery pack 2 mounted on a vehicle such as an automobile. The battery pack 2 has a configuration in which a plurality of battery cells Cb are connected in series between a pair of DC power lines L1 and L2. In the present embodiment, each battery cell Cb is composed of a secondary battery such as a lithium ion battery. Note that in FIG. 1, only a part of the plurality of battery cells Cb is shown.

[0013] Each battery cell Cb is grouped into one battery module 3 for every predetermined number. In other words, the battery module 3 is composed of some of the plurality of battery cells Cb. Specifically, each battery cell Cb is grouped into one battery module 3 for every N. However, N is a positive integer of 2 or more. That is, the battery module 3 has a configuration in which N battery cells Cb are connected in series. The battery pack 2 is composed of a plurality of battery modules 3 connected in series.

[0014] However, in FIG. 1, only three of the plurality of battery modules 3 are shown, and in order to distinguish these three battery modules 3, an alphabet is attached to the end of the reference numeral. For each configuration provided in the battery monitoring system 1 corresponding to each of the three battery modules 3A, 3B, and 3C, a similar alphabet may be attached to the end of the reference numeral for distinction. However, when it is not necessary to distinguish these configurations, the alphabet at the end will be omitted and they will be collectively referred to.

[0015] The battery monitoring system 1 includes a plurality of battery monitoring devices 5 that monitor each of the plurality of battery packs 3, and a battery monitoring ECU 6 that controls the plurality of battery monitoring devices 5. However, in FIG. 1 and the like, only three of the plurality of battery monitoring devices 5, namely, the battery monitoring device 5A that monitors the battery pack 3A, the battery monitoring device 5B that monitors the battery pack 3B, and the battery monitoring device 5C that monitors the battery pack 3C, are shown in the figure.

[0016] The battery monitoring device 5 includes a battery monitoring IC 7 which is an integrated circuit in which circuits for performing various operations for battery monitoring are integrated, insulation circuits 8a, 8b provided outside the battery monitoring IC 7, a filter circuit 9, and the like. Note that IC is an abbreviation for Integrated Circuit. The battery monitoring IC 7 executes various processes for monitoring the battery pack 3. Examples of the various processes executed by the battery monitoring IC 7 include a process of detecting the voltage of the battery cell Cb, a process for communication with an external device, and a cell equalization process for equalizing the voltages of the respective battery cells Cb.

[0017] The battery monitoring IC 7, the insulation circuits 8a, 8b, and the filter circuit 9 are formed on the same board. The battery monitoring IC 7 includes transmission / reception circuits 11a, 11b, a communication control circuit 12, a clock generation circuit 13, a battery monitoring circuit 14, a memory circuit 15, and the like. In this case, the insulation circuits 8a, 8b, the transmission / reception circuits 11a, 11b of the battery monitoring IC 7, and the communication control circuit 12 constitute a differential communication circuit 20 used in an insulation differential communication system. The insulation circuits 8a, 8b are constituted by insulation filters adopting insulation methods such as insulation by capacitance and insulation by an insulation transformer.

[0018] In the above configuration, since the insulation circuits 8a, 8b have the same configuration, when there is no need to distinguish between them, the last alphabet is omitted and they are collectively referred to as the insulation circuit 8. Also, in the above configuration, since the transmission / reception circuits 11a, 11b have the same configuration, when there is no need to distinguish between them, the last alphabet is omitted and they are collectively referred to as the transmission / reception circuit 11.

[0019] The filter circuit 9 is a low-pass filter such as an RC filter, which inputs the voltage of each battery cell Cb, removes its high-frequency components, and outputs the result. In this specification, the low-pass filter may be referred to as an LPF. The voltage output from the filter circuit 9 is supplied to the battery monitoring circuit 14 of the battery monitoring IC 7. The battery monitoring circuit 14 performs A / D conversion on the voltage output from the filter circuit 9 and executes various processes based on the digital value obtained thereby. The battery monitoring device 5 operates based on the clock signal generated by the clock generation circuit 13 and is configured to perform the various processes described above by executing the program stored in the memory circuit 15.

[0020] The clock generation circuit 13 is composed of an RC oscillator or a ring oscillator and can only generate a clock signal with lower accuracy than the clock generation circuit 21 of the battery monitoring ECU 6 described later. However, in this case, the clock generation circuit 13 adopts configurations such as using a variable capacitor for the capacitor constituting the oscillator described above, or making the bias current variable. Thereby, the clock generation circuit 13 can easily change the oscillation frequency by changing the capacitance of the variable capacitor or changing the bias current based on the correction instruction from the communication control circuit 12.

[0021] The battery monitoring ECU 6 is an electronic control device that controls the overall operation of the battery monitoring system 1, and includes an insulation circuit 8a, 8b, transmission / reception circuits 11a, 11b, a communication control circuit 12, a clock generation circuit 21, a memory circuit 22, and the like. These circuits are formed on the same board. In this case, the insulation circuit 8a, 8b, transmission / reception circuits 11a, 11b, and the communication control circuit 12 constitute a differential communication circuit 20 used in the insulation differential communication system. Since the differential communication circuit 20 in the battery monitoring device 5 and the differential communication circuit 20 in the battery monitoring ECU 6 have the same configuration, they are given the same reference numerals, and the circuits constituting them are also given the same reference numerals.

[0022] The battery monitoring ECU 6 operates based on the clock signal generated by the clock generation circuit 21 and is configured to perform various processes by executing the program stored in the memory circuit 22. The clock generation circuit 21 is configured using, for example, a crystal oscillator and can generate a clock signal with higher precision than the clock generation circuit 13 used in the battery monitoring device 5. The clock generation circuit 21 may use a silicon MEMS oscillator instead of the crystal oscillator, or may receive a GNSS reference frequency from a GNSS satellite to generate a clock signal.

[0023] Between the transmission / reception circuit 11a of the battery monitoring ECU 6 and the transmission / reception circuit 11a of the battery monitoring device 5A, they are connected via the insulation circuit 8a, the differential communication transmission line 4a, and the insulation circuit 8a. Between the transmission / reception circuit 11b of the battery monitoring device 5A and the transmission / reception circuit 11a of the battery monitoring device 5B, they are connected via the insulation circuit 8b, the differential communication transmission line 4b, and the insulation circuit 8a. Between the transmission / reception circuit 11b of the battery monitoring device 5B and the transmission / reception circuit 11a of the battery monitoring device 5C, they are connected via the insulation circuit 8b, the differential communication transmission line 4c, and the insulation circuit 8a.

[0024] Between the transmission / reception circuit 11b of the battery monitoring device 5C and the transmission / reception circuit 11b of the battery monitoring ECU 6, they are connected via the insulation circuit 8b, the differential communication transmission line 4d, and the insulation circuit 8b. In the following description, for the differential communication transmission lines 4a to 4d, when there is no need to distinguish them, the trailing alphabet will be omitted and they will be collectively referred to as the differential communication transmission line 4. That is, the communication network in the battery monitoring system 1 has a configuration in which the differential communication circuits 20 provided in each of the plurality of battery monitoring devices 5 and the differential communication circuit 20 provided in the battery monitoring ECU 6 are connected in a ring shape via the differential communication transmission line 4.

[0025] As a result, in the battery monitoring system 1, communication is performed between the plurality of battery monitoring devices 5 and between the plurality of battery monitoring devices 5 and the battery monitoring ECU 6 in a state of being insulated from each other via the differential communication transmission line 4. That is, the battery monitoring system 1 is an example of an insulation differential communication system. In this case, the battery monitoring ECU 6 becomes the master node and the battery monitoring device 5 becomes the slave node, and master-slave communication is performed between them.

[0026] According to the above configuration, the battery monitoring ECU 6 can transmit data such as various commands to the battery monitoring ICs 7 of the plurality of battery monitoring devices 5 via communication. Also, according to the above configuration, the battery monitoring ICs 7 of the plurality of battery monitoring devices 5 can transmit data such as the state of the battery monitoring device 5 and each measurement result obtained by executing each process to the battery monitoring ECU 6 via communication. Further, according to the above configuration, when the battery monitoring ICs 7 of the plurality of battery monitoring devices 5 receive a correction instruction for the clock signal of the clock generation circuit 13 from the battery monitoring ECU 6, they can correct the frequency of the clock signal of the clock generation circuit 13 using insulation communication so as to approach the frequency of the high-precision clock signal of the battery monitoring ECU 6.

[0027] In this case, each circuit constituting each battery monitoring device 5 is configured to obtain the ground voltage, which is the reference potential of the circuit, from the battery cell Cb to be monitored. Therefore, between the battery monitoring IC 7 of each battery monitoring device 5 and the transmission / reception circuit 11 of the battery monitoring ECU 6, insulation is provided by the insulation circuit 8. According to the above configuration, when the battery monitoring ECU 6 and the plurality of battery monitoring devices 5 communicate with differential signals, the S / N ratio can be ensured even if the communication cycle is shortened, and power consumption can be reduced.

[0028] According to the above configuration, the differential communication circuit 20 provided in each of the plurality of battery monitoring devices 5 and the battery monitoring ECU 6 performs bidirectional insulated differential communication with another differential communication circuit 20 facing each other across the differential communication transmission line 4. An insulated differential communication circuit is configured by these two differential communication circuits 20 that perform insulated differential communication. For example, as shown in FIG. 2, the differential communication circuit 20 of the battery monitoring ECU 6 performs bidirectional insulated differential communication with the differential communication circuit 20 of the battery monitoring device 5A facing each other across the differential communication transmission line 4a.

[0029] Therefore, an insulated differential communication circuit 23 is configured by the differential communication circuit 20 of the battery monitoring ECU 6 and the differential communication circuit 20 of the battery monitoring device 5A. Note that in FIG. 2, only the configuration related to the communication performed between the differential communication circuit 20 of the battery monitoring ECU 6 and the battery monitoring device 5A is shown, and only the configuration related to the communication performed between the differential communication circuit 20 of the battery monitoring device 5A and the battery monitoring ECU 6 is shown.

[0030] Hereinafter, a specific encoding method of communication symbols will be described. The battery monitoring ECU 6 and each battery monitoring device 5 constitute communication data by values represented by a ternary or higher integer including a zero state "0" that does not cause current consumption, a positive state "1" with a voltage level higher than this zero state "0", and a negative state "-1" with a voltage level lower than the zero state "0", and communicate by communication symbols obtained by grouping the communication data. In the present embodiment, as a feature of encoding, the average value of the transmission voltage values per symbol, that is, the DC component, is exemplified to be 0, and it is devised to be convenient for insulated communication. A form in which the positive state of the state represented by an integer is "1" and the negative state is "-1" will be described, but a combination of positive and negative states with the same absolute value such as "2" as the positive state and "-2" as the negative state may be configured so that the average value has a DC component of 0.

[0031] <Specific configuration of differential communication circuit 20> As a specific configuration of the differential communication circuit 20, for example, a configuration example as shown in FIG. 3 can be adopted. In this case, a specific configuration example of the differential communication circuit 20 will be described by taking the differential communication circuit 20 of the battery monitoring device 5A as an example. Further, in FIG. 3, only the configuration related to the communication performed between the differential communication circuit 20 of the battery monitoring device 5A and the battery monitoring ECU 6 is shown, but the same applies to the configuration related to the communication performed between the battery monitoring device 5B.

[0032] As shown in FIG. 3, the insulation circuit 8a insulates between the differential communication transmission line 4a and the transmission / reception circuit 11a. As a specific configuration of the insulation circuit 8, for example, a configuration example as shown in FIG. 4 can be adopted. As shown in FIG. 4, the insulation circuit 8 of this configuration example is an insulation filter adopting an insulation method by capacitance, and includes capacitors C1 to C5, resistors R1 to R4, and a common-mode filter 31. One terminal of each of the capacitors C1 and C2 is connected to the differential communication transmission line 4, and the other terminals thereof are connected to nodes N1 and N2 via resistors R1 and R2, respectively.

[0033] The nodes N1 and N2 are connected to a node N3 to which the ground voltage GND2 of each circuit constituting the battery monitoring device 5A is applied via capacitors C3 and C4, respectively. According to such a configuration, resistors R1, R2, and capacitors C3, C4 constitute an LPF provided in the previous stage of the common-mode filter 31. The nodes N1 and N2 are connected to two input terminals of the common-mode filter 31, respectively. The common-mode filter 31 is, for example, a common-mode choke filter having a high impedance with respect to a common-phase signal. Two output terminals of the common-mode filter 31 are connected to nodes N4 and N5, respectively. The nodes N4 and N5 are connected to a node N6 via resistors R3 and R4, respectively.

[0034] One terminal of the capacitor C5 is connected to the node N6, and the ground voltage GND2 is applied to the other terminal. According to such a configuration, the resistor R3, R4, and the capacitor C5 constitute an LPF provided at the subsequent stage of the in-phase filter 31. The nodes N4 and N5 are respectively connected to the two input / output terminals SD_P2 and SD_N2 of the transmission / reception circuit 11. Thus, the insulation circuit 8 of this configuration example not only has the function of insulating between the differential communication transmission line 4 and the transmission / reception circuit 11, but also has the function of filtering out noise outside the communication band for the input signal and supplying it to the transmission / reception circuit 11.

[0035] The transmission / reception circuit 11 includes a transmission circuit 24, a reception circuit 25, an attenuator 26, an in-phase bias circuit 27, an in-phase signal suppression circuit 28, and a wake-up circuit 29. In FIG. 3, the in-phase bias circuit is abbreviated as the CMB circuit, and the wake-up circuit is abbreviated as the WU circuit. The transmission circuit 24 transmits differential communication signals COM_P2 and COM_N2 corresponding to the transmission data TXData2 to another differential communication circuit 20 via the differential communication transmission line 4. In this case, the transmission circuit 24 has the function of supplying a differential communication signal in the positive state "1" or the negative state "-1" corresponding to the transmission data TXData2 to the differential communication transmission line 4 via the insulation circuit 8.

[0036] The reception circuit 25 receives the differential communication signals COM_P2 and COM_N2 transmitted from another differential communication circuit 20 via the differential communication transmission line 4 and generates and outputs reception data RXData2. In this case, the reception circuit 25 has the function of determining the positive state "1" or the negative state "-1" for the differential communication signals COM_P2 and COM_N2 input via the attenuator 26, and generating the reception data RXData2 based on the determination result.

[0037] The communication control circuit 12 generates transmission data TXData2 and outputs it to the transceiver circuit 11, and also inputs received data RXData2 output from the transceiver circuit 11. The communication control circuit 12 supplies a clock signal SCLK2 corresponding to the clock signal supplied from the clock generation circuit 13 to the transmission circuit 24 and the reception circuit 25. The attenuator 26 attenuates the differential communication signals COM_P2 and COM_N2 input via the insulation circuit 8 and supplies them to the reception circuit 25. The in-phase bias circuit 27 supplies an in-phase voltage to the insulation circuit 8 and the reception circuit 25 via the attenuator 26.

[0038] In this case, the transceiver circuit 11 is configured to be switchable between a communication state in which normal communication can be performed and a standby state in which the power consumption is lower than that in the communication state, by an activation signal from the communication control circuit 12. When the wake-up circuit 29 receives, via the attenuator 26, the differential communication signal that is the activation signal, it issues an activation signal WCK2 and transmits it to the communication control circuit 12. The communication control circuit 12 transmits an activation signal EN2 to the reception circuit 25 and also transmits an activation signal EN_CMSUP2 to the in-phase signal suppression circuit 28, to set the communication state to a state in which normal communication can be performed. Note that the transceiver circuit 11 can also be configured to be switchable between a communication state in which normal communication can be performed and a standby state in which the power consumption is lower than that in the communication state, by communication via the differential communication transmission line 4.

[0039] As a specific configuration of the attenuator 26 and the in-phase bias circuit 27, for example, a configuration example as shown in FIG. 5 can be adopted. As shown in FIG. 5, the attenuator 26 of this configuration example includes resistors R5 to R8. One terminal of each of the resistors R5 and R6 is connected to two input / output terminals SD_P2 and SD_N2 of the transceiver circuit 11, respectively. The other terminal of each of the resistors R5 and R6 is connected to nodes N7 and N8, respectively.

[0040] Nodes N7 and N8 are each connected to node N9 via resistors R7 and R8. Also, nodes N7 and N8 serve as the output terminals of attenuator 26 and are respectively connected to the two input terminals of receiving circuit 25. The output terminal of in-phase bias circuit 27 is connected to node N9. According to the above configuration, resistors R5 to R8 form a resistor voltage dividing circuit that divides differential communication signals COM_P2 and COM_N2. Thereby, attenuator 26 outputs signals ATT_OUTP and ATT_OUTN, which are the attenuated differential communication signals COM_P2 and COM_N2, to receiving circuit 25.

[0041] As shown in FIG. 5, the in-phase bias circuit 27 of this configuration example includes an operational amplifier 32. An in-phase voltage VCM is applied to the non-inverting input terminal of operational amplifier 32. The inverting input terminal of operational amplifier 32 is connected to its output terminal. That is, operational amplifier 32 functions as a voltage follower. The output terminal of operational amplifier 32 serves as the output terminal of in-phase bias circuit 27 and is connected to node N9 of attenuator 26.

[0042] The in-phase signal suppression circuit 28 is a circuit that suppresses the in-phase noise signal superimposed on the differential communication signals COM_P2 and COM_N2 based on the output signals ATT_OUTP and ATT_OUTN of attenuator 26. As shown in FIG. 6, the in-phase signal suppression circuit 28 includes an in-phase signal detection circuit 33, a first current generation circuit 34, and a second current generation circuit 35. Signals ATT_OUTP and ATT_OUTN output from attenuator 26 are input to in-phase signal detection circuit 33. In-phase signal detection circuit 33 detects the in-phase voltage in signals ATT_OUTP and ATT_OUTN and outputs a detection voltage CM_NOISE corresponding to the detection result.

[0043] The first current generation circuit 34 receives the detected voltage CM_NOISE and the first reference voltage VREF_CM1. When the first differential voltage obtained by subtracting the first reference voltage VREF_CM1 from the common-phase voltage detected by the common-phase signal detection circuit 33 is a negative voltage, the first current generation circuit 34 generates a first correction current proportional to the first differential voltage, and supplies the generated first correction current to the input / output terminals SD_P2 and SD_N2 of the transceiver circuit 11. The first reference voltage VREF_CM1 is a voltage corresponding to the target bias current.

[0044] The second current generation circuit 35 receives the detected voltage CM_NOISE and the second reference voltage VREF_CM2. When the second differential voltage obtained by subtracting the common-phase voltage detected by the common-phase signal detection circuit 33 from the second reference voltage VREF_CM2 is a positive voltage, the second current generation circuit 35 generates a second correction current proportional to the second differential voltage, and supplies the generated second correction current to the input / output terminals SD_P2 and SD_N2 of the transceiver circuit 11. The second reference voltage VREF_CM2 is a voltage corresponding to the target bias current.

[0045] As a specific configuration of the common-phase signal suppression circuit 28, for example, a configuration example as shown in FIG. 7 can be adopted. As shown in FIG. 7, the common-phase signal detection circuit 33 included in the common-phase signal suppression circuit 28 of this configuration example includes resistors R11 and R12. One terminal of the resistor R11 is connected to the input terminal of the common-phase signal suppression circuit 28 to which the signal ATT_OUTP is applied, and the other terminal is connected to the node N11. One terminal of the resistor R12 is connected to the input terminal of the common-phase signal suppression circuit 28 to which the signal ATT_OUTN is applied, and the other terminal is connected to the node N11. The node N11 serves as the output terminal of the common-phase signal detection circuit 33 that outputs the voltage CM_NOISE.

[0046] The first current generation circuit 34 included in the in-phase signal suppression circuit 28 of this configuration example includes an operational amplifier 36, transistors Q1 and Q2, and diodes D1 and D2. A voltage CM_NOISE is applied to the non-inverting input terminal of the operational amplifier 36, and a first reference voltage VREF_CM1 is applied to the inverting input terminal thereof. In this case, the output voltage of the operational amplifier 36 corresponds to the first differential voltage described above. Both transistors Q1 and Q2 are P-channel MOS transistors.

[0047] The power supply voltage VDD of the circuit is applied to the sources of transistors Q1 and Q2. The gates of transistors Q1 and Q2 are connected to the output terminal of the operational amplifier 36. The drain of transistor Q1 is connected to the anode of diode D1. The cathode of diode D1 is connected to node N12. The drain of transistor Q2 is connected to the anode of diode D2. The cathode of diode D2 is connected to node N13. Nodes N12 and N13 are connected to the two input / output terminals SD_P2 and SD_N2 of the transceiver circuit 11, respectively.

[0048] According to the first current generation circuit 34 of the above configuration, when the output voltage of the operational amplifier 36 corresponding to the first differential voltage becomes a negative voltage, a first correction current proportional to the first differential voltage flows from the drains of transistors Q1 and Q2 toward nodes N12 and N13. The first correction current becomes a source current generated from the power supply. The first current generation circuit 34 of the above configuration supplies the first correction current to the input / output terminals SD_P2 and SD_N2 of the transceiver circuit 11 via the diodes D1 and D2 in the forward direction. The diodes D1 and D2 are provided for the purpose of preventing reverse current and improving withstand voltage, and correspond to the first diodes.

[0049] The second current generation circuit 35 included in the in-phase signal suppression circuit 28 of this configuration example includes an operational amplifier 37, transistors Q3 and Q4, and diodes D3 and D4. A voltage CM_NOISE is applied to the inverting input terminal of the operational amplifier 37, and a second reference voltage VREF_CM2 is applied to the non-inverting input terminal thereof. In this case, the output voltage of the operational amplifier 37 corresponds to the second differential voltage described above. Both transistors Q3 and Q4 are N-channel MOS transistors.

[0050] A ground voltage GND2, which is the reference potential of the circuit, is applied to the sources of transistors Q3 and Q4. The gates of transistors Q3 and Q4 are connected to the output terminal of the operational amplifier 37. The drain of transistor Q3 is connected to the cathode of diode D3. The anode of diode D3 is connected to node N12. The drain of transistor Q4 is connected to the cathode of diode D4. The anode of diode D4 is connected to node N13.

[0051] According to the second current generation circuit 35 configured as described above, when the output voltage of the operational amplifier 37 corresponding to the second differential voltage becomes a positive voltage, a second correction current proportional to the second differential voltage flows from nodes N12 and N13 toward the drains of transistors Q3 and Q4. The second correction current becomes a sink current generated from the ground. The second current generation circuit 35 configured as described above supplies the second correction current to the input / output terminals SD_P2 and SD_N2 of the transmission / reception circuit 11 via diodes D3 and D4 in the reverse direction. Diodes D3 and D4 are provided for the purpose of preventing reverse current and improving withstand voltage, and correspond to the second diodes.

[0052] As a specific configuration of the operational amplifier 36 included in the first current generation circuit 34, for example, a configuration example shown in FIG. 8 can be adopted. As shown in FIG. 8, the operational amplifier 36 included in the first current generation circuit 34 of this configuration example includes P-channel MOS transistors Q11 to Q15 and N-channel MOS transistors Q16 to Q18. In this case, the gates of transistors Q11 and Q12 serve as the non-inverting input terminal and the inverting input terminal of the operational amplifier 36, respectively. Voltage CM_NOISE and the first reference voltage VREF_CM1 are input to the gates of transistors Q11 and Q12, respectively.

[0053] The sources of transistors Q11 and Q12 are connected to the drain of transistor Q13. The power supply voltage VDD is applied to the source of transistor Q13. The gate of transistor Q13 is connected to the gate of transistor Q14. The power supply voltage VDD is applied to the source of transistor Q14. The gate of transistor Q14 is connected to its drain. That is, transistor Q14 is diode-connected. The drain current of transistor Q14 becomes a constant first bias current IBIAS1.

[0054] The drain of transistor Q11 is connected to the drain of transistor Q16. The drain of transistor Q12 is connected to the drain of transistor Q17. The ground voltage GND2 is applied to the sources of transistors Q16 and Q17. The gate of transistor Q16 is connected to its drain, and the gate of transistor Q17 is connected to its drain. That is, both transistors Q16 and Q17 are diode-connected.

[0055] The gate of transistor Q16 is connected to the gate of transistor Q18. The source of transistor Q18 is supplied with the ground voltage GND2. The drain of transistor Q18 is connected to the drain of transistor Q15. The source of transistor Q15 is supplied with the power supply voltage VDD. The gate of transistor Q15 is connected to its drain. That is, transistor Q15 is diode-connected. Also, the gate of transistor Q15 serves as the output terminal of operational amplifier 36 and is connected to the gates of transistors Q1 and Q2.

[0056] As a specific configuration of operational amplifier 37 included in the second current generation circuit 35, for example, a configuration example shown in FIG. 9 can be adopted. As shown in FIG. 9, the operational amplifier 37 included in the second current generation circuit 35 of this configuration example includes transistors Q21 to Q25 which are N-channel MOS transistors and transistors Q26 to Q28 which are P-channel MOS transistors. In this case, the gates of transistors Q21 and Q22 serve as the inverting input terminal and the non-inverting input terminal of operational amplifier 37, respectively. The voltage CM_NOISE and the second reference voltage VREF_CM2 are input to the gates of transistors Q21 and Q22, respectively.

[0057] The sources of transistors Q21 and Q22 are connected to the drain of transistor Q23. The source of transistor Q23 is supplied with the ground voltage GND2. The gate of transistor Q23 is connected to the gate of transistor Q24. The source of transistor Q24 is supplied with the ground voltage GND2. The gate of transistor Q24 is connected to its drain. That is, transistor Q24 is diode-connected. The drain current of transistor Q24 becomes a constant second bias current IBIAS2.

[0058] The drain of transistor Q21 is connected to the drain of transistor Q26. The drain of transistor Q22 is connected to the drain of transistor Q27. The power supply voltage VDD is applied to the sources of transistors Q26 and Q27. The gate of transistor Q26 is connected to its drain, and the gate of transistor Q27 is connected to its drain. That is, both transistors Q26 and Q27 are diode-connected.

[0059] The gate of transistor Q26 is connected to the gate of transistor Q28. The power supply voltage VDD is applied to the source of transistor Q28. The drain of transistor Q28 is connected to the drain of transistor Q25. The ground voltage GND2 is applied to the source of transistor Q25. The gate of transistor Q25 is connected to its drain. That is, transistor Q25 is diode-connected. Also, the gate of transistor Q25 serves as the output terminal of operational amplifier 37 and is connected to the gates of transistors Q3 and Q4.

[0060] Next, the operations related to communication in the above configuration will be described. In the battery monitoring system 1, when the battery monitoring ECU 6 or the battery monitoring device 5 performs communication using insulation communication after power-on, a communication startup operation is performed. The communication startup operation is as follows. In the following description, it is assumed that the differential communication circuit 20 of the battery monitoring ECU 6 is on the transmission side, and the differential communication circuit 20 of the battery monitoring device 5A is on the reception side.

[0061] First, in the differential communication circuit 20 on the transmission side, the communication control circuit 12 reads information necessary for communication control from the memory circuit 22. This information includes communication control information such as the communication symbol length. The communication control circuit 12 generates transmission data, which is an activation signal, modulates it into communication data, and transmits a communication control signal TXData1 to the transceiver circuit 11a. The transceiver circuit 11a transmits differential communication signals COM_P1 and COM_N1 in a positive state "1" or a negative state "-1" to the differential communication circuit 20 of the opposing battery monitoring device 5A via the insulation circuit 8a and the differential communication transmission line 4a according to the communication control signal TXData1.

[0062] In the differential communication circuit 20 on the reception side, when the wake-up circuit 29 receives differential communication signals COM_P2 and COM_N2, which are activation signals, via the attenuator 26, it issues an activation signal WCK2 to the communication control circuit 12. As a result, the communication control circuit 12 transmits an activation signal EN2 to the reception circuit 25 and issues an activation signal EN_CMSUP2 to the common-mode signal suppression circuit 28 to enter the reception state. Also, at this time, the communication control circuit 12 issues a communication control signal associated with the activation signal to the downstream transceiver circuit 11 and transmits the differential communication signals COM_P2 and COM_N2. By repeating such operations, the communication control circuit 12 on the battery monitoring ECU6 side determines that the entire insulation differential communication system has been activated when the transceiver circuit 11 detects the reception of the differential communication signal associated with the activation signal, and completes the communication activation operation and shifts to the communication-enabled state.

[0063] In the communication-enabled state, the communication control circuit 12 of the battery monitoring ECU6 generates transmission data composed of commands and data, modulates it into communication data, and transmits a communication control signal TXData1 to the transceiver circuit 11a. In the differential communication circuit 20 on the reception side, when the reception circuit 25 receives the differential communication signals COM_P2 and COM_N2 via the attenuator 26, it determines whether it is in a positive state "1" or a negative state "-1" and transmits it to the communication control circuit 12 as reception data RXData2.

[0064] The communication control circuit 12 demodulates the received data RXData2 transmitted from the receiving circuit 25 as received data composed of commands and data. At this time, in the above configuration, when a common-mode noise is applied to the differential communication transmission line 4, the common-mode signal suppression circuit 28 detects the common-mode noise signal component in the signal line after the attenuator 26. The common-mode signal suppression circuit 28 supplies a first correction current, which is a common-mode correction source current corresponding to a first differential voltage that is a differential voltage between the detected common-mode noise signal component and a first reference voltage VREF_CM1, or a second correction current, which is a common-mode correction sink current corresponding to a second differential voltage that is a differential voltage between the detected common-mode noise signal component and a second reference voltage VREF_CM2, to the input / output terminals SD_P2 and SD_N2 of the transceiver circuit 11. As a result, the first correction current or the second correction current flows through the insulation circuit 8, and the input common-mode noise signal is canceled, and thus the resistance to the common-mode noise can be enhanced.

[0065] According to the embodiment described above, the following effects can be obtained. The transceiver circuit 11 included in the differential communication circuit 20 of the present embodiment includes an attenuator 26 that attenuates a differential communication signal input via an insulation circuit 8 and supplies the attenuated signal to the receiving circuit 25, and a common-mode signal suppression circuit 28 that suppresses a common-mode noise signal superimposed on the differential communication signal based on the output signal of the attenuator 26. The common-mode signal suppression circuit 28 includes a common-mode signal detection circuit 33 that detects a common-mode voltage in the output signal of the attenuator 26, a first current generation circuit 34, and a second current generation circuit 35.

[0066] The first current generation circuit 34 generates a first correction current proportional to a first differential voltage when the first differential voltage obtained by subtracting a first reference voltage VREF_CM1 from the common-mode voltage detected by the common-mode signal detection circuit 33 becomes a negative voltage, and supplies the generated first correction current to the input / output terminals of the transceiver circuit 11. The second current generation circuit 35 generates a second correction current proportional to a second differential voltage when the second differential voltage obtained by subtracting the common-mode voltage detected by the common-mode signal detection circuit 33 from a second reference voltage VREF_CM2 becomes a positive voltage, and supplies the generated second correction current to the input / output terminals of the transceiver circuit 11.

[0067] According to such a configuration, since the differential communication signal is attenuated by the attenuator 26 and then input to the in-phase signal suppression circuit 28, even when an in-phase noise signal having a relatively large voltage amplitude exceeding the power supply voltage, for example, is superimposed on the differential communication signal, the in-phase signal suppression circuit 28 can function normally. Therefore, according to the present embodiment, even when an in-phase noise signal having a relatively large voltage amplitude is superimposed on the differential communication signal, the in-phase noise signal is canceled by the operation of the in-phase signal suppression circuit 28. As a result, the influence of the in-phase noise signal superimposed on the differential communication signal on communication can be suppressed.

[0068] In the present embodiment, the first current generation circuit 34 is configured to supply a first correction current to the input / output terminals of the transmission / reception circuit 11 via the diodes D1 and D2 in the forward direction, and the second current generation circuit 35 is configured to supply a second correction current to the input / output terminals of the transmission / reception circuit 11 via the diodes D3 and D4 in the reverse direction. According to such a configuration, backflow of the first correction current and the second correction current can be prevented. Further, according to the above configuration, even when transistors Q1 to Q4 constituting the in-phase signal suppression circuit 28 having a relatively low breakdown voltage corresponding to a power supply voltage VDD of, for example, 5V are employed, a breakdown voltage between the differential communication transmission line 4 having a voltage of, for example, 20V can be ensured.

[0069] In the present embodiment, the transmission / reception circuit 11 is configured to be capable of switching between a communication state in which normal communication can be performed by communication via the differential communication transmission line 4 or a start signal from the communication control circuit 12, and a standby state in which the power consumption is reduced compared to the communication state. According to such a configuration, the in-phase signal suppression circuit 28 operates only in the communication state, and the current consumption of the circuit can be suppressed to be lower than when the in-phase signal suppression circuit 28 operates constantly.

[0070] (Second Embodiment) Hereinafter, the second embodiment will be described with reference to FIG. 10. As shown in FIG. 10, the in-phase signal suppression circuit 41 of this embodiment is different from the in-phase signal suppression circuit 28 of the first embodiment shown in FIG. 7 in that an adaptive bias generation circuit 42 is added, and the first current generation circuit 43 and the second current generation circuit 44 are provided instead of the first current generation circuit 34 and the second current generation circuit 35. In FIG. 10, the adaptive bias generation circuit is abbreviated as the AB generation circuit.

[0071] The adaptive bias generation circuit 42 is a circuit that generates a variable bias current that changes according to the amplitude of the in-phase voltage by rectifying and smoothing the in-phase voltage detected by the in-phase signal detection circuit 33. Specifically, the adaptive bias generation circuit 42 generates a variable bias current as follows. That is, since the in-phase noise signal superimposed on the differential communication signal is an AC signal, a DC signal corresponding to the level of the in-phase noise signal can be obtained by detecting and filtering the signal, that is, rectifying and smoothing it.

[0072] Therefore, the adaptive bias generation circuit 42 generates a variable bias current proportional to the amplitude of the in-phase noise signal by rectifying and smoothing the detection voltage CM_NOISE output from the in-phase signal detection circuit 33. Note that the adaptive bias generation circuit 42 can also be configured to generate a variable bias current with the amplitude of the in-phase noise signal boosted. The adaptive bias generation circuit 42 outputs the variable bias current IBV generated in this way to the first current generation circuit 43 and the second current generation circuit 44.

[0073] The first current generation circuit 43 is a circuit that generates a first correction current in the same manner as the first current generation circuit 34. However, the first current generation circuit 43 is configured to generate the first correction current based on the variable bias current IBV or a current obtained by adding the variable bias current IBV to a constant first bias current IBIAS1. The second current generation circuit 44 is a circuit that generates a second correction current in the same manner as the second current generation circuit 35. However, the second current generation circuit 44 is configured to generate the second correction current based on the variable bias current IBV or a current obtained by adding the variable bias current IBV to a constant second bias current IBIAS2.

[0074] According to the present embodiment described above, the following effects can be obtained. In the first current generation circuit 34 and the second current generation circuit 35, since the first bias current IBIAS1 and the second bias current IBIAS2 are fixed, it is necessary to flow a current corresponding to the assumed maximum level of the common-mode noise signal as the above bias current. Then, when the level of the common-mode noise signal is relatively small, a bias current of a magnitude that does not need to be originally flowed is flowed.

[0075] On the other hand, according to the present embodiment, the first current generation circuit 43 and the second current generation circuit 44 are configured to flow a bias current that changes according to the variable bias current IVB proportional to the amplitude of the common-mode noise signal, and an optimal bias current corresponding to the level of the common-mode noise signal can be flowed. Therefore, an effect that the power consumed by the common-mode signal suppression circuit 41 is reduced is obtained. That is, according to the present embodiment, a voltage-current conversion gain corresponding to the amplitude of the common-mode voltage can be given to the first current generation circuit 43 and the second current generation circuit 44, and as a result, the steady-state consumption current can be reduced.

[0076] (Third Embodiment) Hereinafter, the third embodiment will be described with reference to FIG. 11. As shown in Fig. 11, the in-phase signal suppression circuit 51 of this embodiment is different from the in-phase signal suppression circuit 28 of the first embodiment shown in Fig. 7 in that an amplitude determination circuit 52 is added, and the first current generation circuit 53 and the second current generation circuit 54 are provided instead of the first current generation circuit 34 and the second current generation circuit 35.

[0077] The detection voltage CM_NOISE output from the in-phase signal detection circuit 33 is input to the amplitude determination circuit 52. The amplitude determination circuit 52 determines the amplitude of the in-phase voltage by rectifying and smoothing the in-phase voltage detected by the in-phase signal detection circuit 33. The amplitude determination circuit 52 outputs a signal BOOST representing the determination result regarding the amplitude of the in-phase voltage to the first current generation circuit 53 and the second current generation circuit 54. The signal BOOST is a signal representing the amplitude magnitude in two levels. In this embodiment, the signal BOOST is a signal representing the amplitude magnitude in two levels, for example, "1" and "0".

[0078] The first current generation circuit 53 is a circuit that generates a first correction current in the same manner as the first current generation circuit 34. However, the first current generation circuit 53 is configured to be able to change the magnitude of the first correction current, and is configured to change the magnitude of the first correction current according to the determination result by the amplitude determination circuit 52. Specifically, the first current generation circuit 53 is configured such that a plurality of current sources 55 composed of transistors Q1 and Q2 can be connected in parallel. In this embodiment, the first current generation circuit 53 is configured such that two current sources 55 can be connected in parallel. The first current generation circuit 53 is configured to be able to control the amount of the first correction current fed back to the input / output terminals of the transceiver circuit 11 by switching the number of parallel connections of the current sources 55 according to the determination result of the amplitude of the in-phase voltage represented by the signal BOOST.

[0079] The second current generation circuit 54 is a circuit that generates a second correction current in the same manner as the second current generation circuit 35. However, the second current generation circuit 54 is configured to be able to change the magnitude of the second correction current, and is adapted to change the magnitude of the second correction current according to the determination result by the amplitude determination circuit 52. Specifically, the second current generation circuit 54 is configured such that a plurality of current sources 56 each composed of transistors Q3 and Q4 can be connected in parallel. In this embodiment, the second current generation circuit 54 is configured such that two current sources 56 can be connected in parallel. The second current generation circuit 54 is configured to be able to control the amount of the second correction current fed back to the input / output terminals of the transceiver circuit 11 by switching the number of current sources 56 connected in parallel according to the determination result of the amplitude of the in-phase voltage represented by the signal BOOST.

[0080] According to the present embodiment described above, since the first current generation circuit 53 and the second current generation circuit 54 are configured to change the magnitudes of the first correction current and the second correction current according to the determination result by the amplitude determination circuit 52 that determines the amplitude of the in-phase voltage, it is possible to provide the first current generation circuit 53 and the second current generation circuit 54 with a voltage-current conversion gain corresponding to the amplitude of the in-phase voltage. As a result, the quiescent current consumption can be reduced.

[0081] (Other Embodiments) Note that the present invention is not limited to the embodiments described above and shown in the drawings, and can be arbitrarily modified, combined, or extended without departing from the gist thereof. The numerical values and the like shown in the above embodiments are examples and are not limited thereto.

[0082] In the above embodiments, the case where the present invention is applied to a system in which two-way insulated differential communication is performed by a plurality of differential communication circuits 20 has been exemplified. However, the present invention can also be applied to a system in which one-way insulated differential communication is performed by a plurality of differential communication circuits. In each of the above-described embodiments, the case where the plurality of battery monitoring devices 5 are each configured by a separate board has been exemplified, but the plurality of battery monitoring devices 5 can also be formed on the same board. Furthermore, the battery monitoring ECU 6 and the plurality of battery monitoring devices 5 can also be formed on the same board. In such a case, the grounds on the same board are configured to be all common.

[0083] Although the present disclosure has been described based on the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also includes various modifications and modifications within an equivalent range. In addition, various combinations and forms, and further other combinations and forms including only one element, more than one element, or less than one element thereof, are within the scope and spirit of the present disclosure.

Explanation of Signs

[0084] 1…Battery monitoring system, 4, 4a~4d…Differential communication transmission line, 8, 8a, 8b…Insulation circuit, 11, 11a, 11b…Transmission and reception circuit, 12…Communication control circuit, 20…Differential communication circuit, 24…Transmission circuit, 25…Reception circuit, 26…Attenuator, 28, 41, 51…In-phase signal suppression circuit, 33…In-phase signal detection circuit, 34, 43, 53…First current generation circuit, 35, 44, 54…Second current generation circuit, 42…Adaptive bias generation circuit, 52…Amplitude determination circuit, D1, D2…Diode, D3, D4…Diode.

Claims

【Claim 1】 In an insulated differential communication system (1) comprising a differential communication transmission line (4, 4a to 4d) and a plurality of differential communication circuits (20) that communicate with each other in an insulated state via the differential communication transmission line, the differential communication circuit used therein, A transmission circuit (24) that transmits a differential communication signal corresponding to transmission data to other differential communication circuits via the differential communication transmission line, and a reception circuit (25) that receives a differential communication signal transmitted from other differential communication circuits via the differential communication transmission line, generates reception data, and outputs it, a transceiver circuit (11, 11a, 11b) including, An insulation circuit (8, 8a, 8b) that insulates between the differential communication transmission line and the transceiver circuit, A communication control circuit (12) that generates the transmission data and outputs it to the transceiver circuit, and inputs the reception data output from the transceiver circuit, Comprising, The transceiver circuit, An attenuator (26) that attenuates the differential communication signal input via the insulation circuit and supplies it to the reception circuit, A common-phase signal suppression circuit (28, 41, 51) that suppresses a common-phase noise signal superimposed on the differential communication signal based on the output signal of the attenuator, Comprising, The common-phase signal suppression circuit, A common-phase signal detection circuit (33) that detects a common-phase voltage in the output signal of the attenuator, When a first differential voltage obtained by subtracting a first reference voltage from the common-phase voltage detected by the common-phase signal detection circuit becomes a negative voltage, a first correction current proportional to the first differential voltage is generated, and the generated first correction current is supplied to the input / output terminals of the transceiver circuit. A first current generation circuit (34, 43, 53), When a second differential voltage obtained by subtracting the common-phase voltage detected by the common-phase signal detection circuit from a second reference voltage becomes a positive voltage, a second correction current proportional to the second differential voltage is generated, and the generated second correction current is supplied to the input / output terminals of the transceiver circuit. A second current generation circuit (35, 44, 54), A differential communication circuit comprising. Claim 2 The first current generation circuit includes first diodes (D1, D2), and supplies the first correction current to the input / output terminals of the transmission / reception circuit via the first diodes in the forward direction. The differential communication circuit according to claim 1, wherein the second current generation circuit includes second diodes (D3, D4), and supplies the second correction current to the input / output terminals of the transmission / reception circuit via the second diodes in the reverse direction. Claim 3 The transmission / reception circuit is configured to be able to switch between a communication state in which normal communication can be performed by communication via the differential communication transmission line or an activation signal from the communication control circuit, and a standby state in which power consumption is reduced compared to the communication state. The differential communication circuit according to claim 1. Claim 4 The common-mode signal suppression circuit (41) further includes an adaptive bias generation circuit (42) that rectifies and smoothes the common-mode voltage detected by the common-mode signal detection circuit to generate a variable bias current that changes according to the amplitude of the common-mode voltage. The first current generation circuit (43) is configured to generate the first correction current based on the variable bias current or a current obtained by adding the variable bias current to a constant first bias current. The differential communication circuit according to any one of claims 1 to 3, wherein the second current generation circuit (44) is configured to generate the second correction current based on the variable bias current or a current obtained by adding the variable bias current to a constant second bias current. Claim 5 The first current generation circuit (53) is configured to be able to change the magnitude of the first correction current. The second current generation circuit (54) is configured to be able to change the magnitude of the second correction current. The common-mode signal suppression circuit (51) further includes an amplitude determination circuit (52) that rectifies and smoothes the common-mode voltage detected by the common-mode signal detection circuit to determine the amplitude of the common-mode voltage. The first current generation circuit changes the magnitude of the first correction current according to the determination result by the amplitude determination circuit, The differential communication circuit according to any one of claims 1 to 3, wherein the second current generation circuit changes the magnitude of the second correction current according to the determination result by the amplitude determination circuit.

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