Semiconductor device

Abstract

To provide a semiconductor device that can restrain an increase in the on-voltage of an IGBT region while improving the heat dissipation performance of the entire device.SOLUTION: A semiconductor device includes a chip having IGBT regions and diode regions, a lead frame electrically connected to the upper surface of the chip via solder, and an insulating substrate electrically connected to the lower surface of the chip via solder. The IGBT regions and the diode regions are alternately arranged inside the chip, and the cell width of the IGBT region at a portion that is electrically connected to the lead frame via the solder is wider than the cell width of the IGBT region at other portions.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a semiconductor device in which an IGBT region and a diode region are mounted on the same chip.

Background Art

[0002] As a reverse conduction IGBT (Reverse Conduction IGBT, hereinafter referred to as "RC-IGBT") in which an IGBT (Insulated Gate Bipolar Transistor) region and a diode region connected in antiparallel to the IGBT region are mounted on the same chip, the semiconductor device of Patent Document 1 is known.

[0003] For example, in the abstract of the same document, "A semiconductor device (semi-mixed type RC-IGBT) in which a dedicatedly operating IGBT cell region and a diode cell region are alternately arranged adjacent to each other on a semiconductor substrate, and which can suppress the snapback of the IGBT cell region without inhibiting the advantages of high breakdown tolerance and low loss." As a solution to the problem, "A semiconductor device in which a plurality of strip-shaped IGBT cell regions and a plurality of diode cell regions are alternately arranged adjacent to each other, wherein the plurality of IGBT cell regions are composed of a narrow strip width region 10a having a narrow strip shape and at least one wide strip width region 10b wider than the narrow strip width region 10a, and each first region 1a, 1b on the back side of the plurality of IGBT cell regions is connected by a bridging portion region 5a formed in the P conductivity type of the same layer. Semiconductor device 100" is mentioned. Also, in FIG. 1 and the like of the same document, a semiconductor device in which an IGBT cell region and a diode cell region are alternately arranged and there are two regions, a narrow strip width region 10a and a wide strip width region 10b, as the IGBT cell region is disclosed.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Although not particularly mentioned in Patent Document 1, in an RC-IGBT, the IGBT region is cooled by dissipating the Joule heat generated during energization of the IGBT region to the adjacent diode region, and the diode region is cooled by dissipating the Joule heat generated during energization of the diode region to the adjacent IGBT region. Therefore, in an RC-IGBT, if the interfacial area between the IGBT region and the diode region is increased by increasing the number of boundaries between the IGBT region and the diode region, etc., the thermal resistance during heat dissipation from one region to the other region can be reduced, and the heat dissipation performance of the entire RC-IGBT can be improved.

[0006] Here, in the IGBT region of an RC-IGBT, during the period when a positive voltage is applied between the collector and the emitter and the gate voltage is on, carriers (holes) are accumulated in the drift layer to reduce the drift layer resistance, thereby reducing the on-voltage.

[0007] However, if the interfacial area between the IGBT region and the diode region is increased to improve the heat dissipation performance of the RC-IGBT, the carriers accumulated in the drift layer of the IGBT region during energization of the IGBT region are likely to be discharged from the body layer of the diode region, and the electrons accumulated in the drift layer of the IGBT region are likely to be discharged from the cathode layer of the diode region. As a result, carrier accumulation in the IGBT region becomes insufficient at the boundary between the IGBT region and the diode region, and as the drift layer resistance increases, a problem occurs in that the on-voltage of the IGBT region also increases.

[0008] Therefore, an object of the present invention is to provide a semiconductor device capable of suppressing an increase in the on-voltage of the IGBT region while improving the heat dissipation performance of the entire device.

Means for Solving the Problems

[0009] To solve the above problems, a semiconductor device of the present invention includes a chip having an IGBT region and a diode region, a lead frame electrically connected to the upper surface of the chip via solder, and an insulating substrate electrically connected to the lower surface of the chip via solder. In the chip, the IGBT regions and the diode regions are alternately arranged, and a cell width of the IGBT region at a site electrically connected to the lead frame via the solder is wider than a cell width of the IGBT region at other sites.

Effect of the Invention

[0010] According to the semiconductor device of the present invention, it is possible to suppress an increase in the on-voltage of the IGBT region while enhancing the heat dissipation performance of the entire device.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Mode for Carrying Out the Invention

[0012] Hereinafter, an example of a method for manufacturing a semiconductor device of the present invention will be described with reference to the drawings.

Example

[0013] First, a semiconductor device 100 according to Example 1 of the present invention will be described with reference to FIGS. 1 to 4.

[0014] FIG. 1 is an external perspective view of the semiconductor device 100 of this embodiment. As shown here, the semiconductor device 100 has a chip 1, an insulating substrate 2, and a lead frame 3. Each will be described sequentially below.

[0015] The insulating substrate 2 is a rigid body in which metal wirings 2b of a desired number and shape are arranged on the upper surface of a ceramic insulating plate 2a. Note that the lower surface of the chip 1 and the upper surface of the metal wiring 2b are electrically connected via solder 4.

[0016] The lead frame 3 is a copper rigid body for flowing a large current, which includes a plurality of terminals 3a protruding laterally for electrically connecting to the upper surface of the metal wiring 2b of the insulating substrate 2, and a convex portion 3b protruding downward for electrically connecting to the upper surface of the chip 1. Note that the lower surface of the terminal 3a of the lead frame 3 and the upper surface of the metal wiring 2b, and the lower surface of the convex portion 3b and the upper surface of the chip 1 are electrically connected via solder 4.

[0017] The chip 1 is an RC-IGBT in which an IGBT region 11 and a diode region 12 connected in anti-parallel to the IGBT region 11 are mounted within the same chip.

[0018] FIG. 2 is a schematic plan view of the main part of the chip 1 viewed from above, and illustration of an emitter electrode 15 and the like to be described later is omitted. As shown here, in addition to the IGBT region 11 and the diode region 12 described above, the chip 1 has an outer peripheral region 13 and a gate pad region 14. Note that the broken line is a portion that contacts the convex portion 3b of the lead frame 3 via the solder 4.

[0019] As shown in the figure, inside the outer peripheral region 13, cells of the IGBT region 11 and the diode region 12 are alternately arranged, and a gate pad region 14 is arranged so as to straddle cells of a plurality of IGBT regions 11 and diode regions 12 at the left end in the figure. Also, the cell width of the IGBT region 11 below the convex portion 3b is wider than the cell width of the IGBT region 11 not in contact with the convex portion 3b. Hereinafter, the former is referred to as the wide-width IGBT region 11a, and the latter is referred to as the narrow-width IGBT region 11b. In this embodiment, it is assumed that the widths of the wide-width IGBT regions 11a are equal to each other, the widths of the narrow-width IGBT regions 11b are equal to each other, and the widths of the diode regions 12 are equal to each other. The cell width increases in the order of the diode region 12, the narrow-width IGBT region 11b, and the wide-width IGBT region 11a, and the cell width of the wide-width IGBT region 11a is approximately three times (2.5 to 3.5 times) the cell width of the diode region 12.

[0020] Figure 3 is a cross-sectional view of the semiconductor device 100. As shown here, the emitter electrode 15 provided on the upper surface of the chip 1 is electrically and thermally connected to the convex portion 3b of the lead frame 3 via the chip upper solder 4a, and the collector electrode 16 provided on the lower surface of the chip 1 is electrically and thermally connected to the metal wiring 2b of the insulating substrate 2 via the chip lower solder 4b.

[0021] The IGBT region 11 (wide IGBT region 11a, narrow IGBT region 11b) has a drift layer 21, a buffer layer 22, a collector layer 23, a body layer 24, an emitter layer 25, a trench 26, a gate electrode 27, and a gate insulating film 28. The drift layer 21 is an n-type semiconductor layer that occupies the center of the chip 1 and is the thickest layer. The buffer layer 22 is an n-type semiconductor layer provided below the drift layer 21. The collector layer 23 is a p-type semiconductor layer provided below the buffer layer 22 and is in contact with the upper surface of the collector electrode 16. The body layer 24 is a p-type semiconductor layer provided above the drift layer 21 and is in contact with the lower surface of the emitter electrode 15. The emitter layer 25 is an n-type semiconductor layer provided on the upper surface of the body layer 24 and is in contact with the lower surface of the emitter electrode 15. The trench 26 is a hole that penetrates the body layer 24 and the emitter layer 25 and reaches the drift layer 21. The gate electrode 27 is an electrode disposed in the trench 26. The gate insulating film 28 is an insulating film that covers the outer periphery of the gate electrode 27.

[0022] The diode region 12 has, in addition to the above-described drift layer 21, buffer layer 22, body layer 24, and trench 26, a cathode layer 31 and an emitter insulating film 32. The cathode layer 31 is an n-type semiconductor layer provided below the buffer layer 22 and is in contact with the upper surface of the collector electrode 16. The emitter insulating film 32 is an insulating film that covers the outer periphery of the emitter electrode 15 disposed in the trench 26.

[0023] <Heat dissipation path of chip 1> Next, with reference to FIG. 4, the heat dissipation path of the chip 1 when the IGBT region 11 is energized will be described. As shown here, the Joule heat generated in the wide IGBT region 11a is dissipated to the left and right diode regions 12, and is also dissipated to the convex portion 3b (lead frame 3) via the chip upper solder 4a, and is dissipated to the metal wiring 2b (insulating substrate 2) via the chip lower solder 4b. Similarly, the Joule heat generated in the narrow IGBT region 11b is dissipated to the left and right diode regions 12, and is also dissipated to the outside of the device (specifically, a resin mold (not shown) that seals the semiconductor device 100) via the emitter electrode 15, and is dissipated to the metal wiring 2b (insulating substrate 2) via the chip lower solder 4b.

[0024] As is obvious from FIG. 4, since the interface areas with the left and right diode regions 12 are equal in the wide-width IGBT region 11a and the narrow-width IGBT region 11b, the left and right interface area per unit volume of the wide-width IGBT region 11a is narrower than that of the narrow-width IGBT region 11b. Therefore, compared with the narrow-width IGBT region 11b, the wide-width IGBT region 11a has the following advantages and disadvantages. That is, the wide-width IGBT region 11a has the advantage that the carrier accumulation effect is higher than that of the narrow-width IGBT region 11b, so the increase in the on-voltage can be suppressed. On the other hand, compared with the narrow-width IGBT region 11b, the thermal resistance of the heat dissipation path to the diode region 12 is large, so there is a disadvantage that the heat dissipation performance is inferior if the heat dissipation is limited to the diode region 12.

[0025] However, since the wide-width IGBT region 11a of the present embodiment also has a heat dissipation path to the lead frame 3 that also functions as a heat sink, the above disadvantage can be improved by the existence of this heat dissipation path, and sufficient heat dissipation performance equivalent to that of the narrow-width IGBT region 11b can be ensured.

[0026] As described above, according to the semiconductor device of the present embodiment, while enhancing the heat dissipation of the entire device, it is also possible to suppress the increase in the on-voltage of the IGBT region.

Embodiment

[0027] Next, with reference to FIG. 5, the semiconductor device 100 according to Embodiment 2 of the present invention will be described. Note that duplicate descriptions of the common points with Embodiment 1 will be omitted.

[0028] FIG. 5 is a schematic plan view of the main part of chip 1 of this embodiment as seen from above, and like FIG. 2, illustration of the emitter electrode 15 and the like is omitted. As is apparent from the comparison between FIG. 2 and FIG. 5, while the cell width of the diode region 12 of Example 1 is uniform, in this embodiment, the diode region 12 sandwiched between the wide-width IGBT regions 11a is a wide-width diode region 12a with a wide cell width, and the diode regions 12 sandwiched between the narrow-width IGBT regions 11b or between the wide-width IGBT region 11a and the narrow-width IGBT region 11b are narrow-width diode regions 12b with a narrow cell width.

[0029] Thus, by making the diode region 12 sandwiched between the wide-width IGBT regions 11a a wide-width diode region 12a with a wide cell width, at the portion in contact with the convex portion 3b, the number of boundaries (i.e., the boundary area) between the wide-width IGBT region 11a and the diode region 12 can be further reduced, so that an increase in the on-voltage of the IGBT region can be suppressed more than in Example 1.

Explanation of Reference Numerals

[0030] 100 Semiconductor device 1 Chip 11 IGBT region 11a Wide-width IGBT region 11b Narrow-width IGBT region 12 Diode region 12a Wide-width diode region 12b Narrow-width diode region 13 Peripheral region 14 Gate pad region 15 Emitter electrode 16 Collector electrode 2 Insulating substrate 2a Insulating plate 2b Metal wiring 3 Lead frame 3a Terminal 3b Convex portion 4 Solder 4a Solder on chip 4b Solder under chip

Claims

1. A chip having an IGBT region and a diode region, A lead frame electrically connected to the upper surface of the chip via solder, A semiconductor device comprising an insulating substrate electrically connected to the lower surface of the chip via solder, In the chip, the IGBT region and the diode region are alternately arranged, A semiconductor device, wherein the cell width of the IGBT region at a site electrically connected to the lead frame via the solder is wider than the cell width of the IGBT region at other sites.

2. In the semiconductor device according to Claim 1, The alternately arranged IGBT region and diode region are surrounded by an outer peripheral region, A semiconductor device, wherein a gate pad region straddling the IGBT region and the diode region is provided inside the outer peripheral region.

3. In the semiconductor device according to Claim 1 or Claim 2, A semiconductor device, wherein the cell width of the IGBT region at a site electrically connected to the lead frame via the solder is approximately three times the cell width of the diode region at the same site.

4. In the semiconductor device according to Claim 1 or Claim 2, A semiconductor device, wherein the cell width of the diode region at a site electrically connected to the lead frame via the solder is wider than the cell width of the diode region at other sites.

Images