Semiconductor device and manufacturing method thereof

Abstract

To provide a technique for implanting impurity ions into a semiconductor substrate with high precision.SOLUTION: A manufacturing method for a semiconductor device includes the steps of forming a resist film on a surface of a semiconductor substrate, and then removing a part of the resist film to expose a part of the surface of the semiconductor substrate, implanting ions into the resist film to determine a shape of the resist film such that deformation of the resist film is suppressed when an n-type or p-type impurity is ion-implanted into the semiconductor substrate, and ion-implanting the n-type or p-type impurity into the semiconductor substrate.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] This specification discloses technologies related to semiconductor devices and manufacturing methods of semiconductor devices.

Background Art

[0002] Patent Document 1 discloses a method for manufacturing a semiconductor device. In Patent Document 1, a resist film having an opening is formed on the surface of a semiconductor substrate, and impurity ions are irradiated onto the semiconductor substrate to inject the impurity ions into a predetermined range within the semiconductor substrate. In Patent Document 1, after forming the resist film having an opening, UV irradiation (UV cure) is performed on the resist film to cure the resist film.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By curing the resist film through UV cure as in Patent Document 1, the shape of the resist film becomes stable. However, when impurity ions are irradiated onto the semiconductor substrate, impurity ions are also injected into the resist film. When impurity ions are injected into the resist film, the resist film generates heat, and solvents or the like within the resist film may desorb from the resist film. As a result, while injecting impurity ions into the semiconductor substrate, the shape of the resist film may change, and the size of the opening may change. When the opening size changes, the size of the impurity region within the semiconductor substrate may deviate from the design value, and the characteristics of the semiconductor device may deteriorate. Therefore, a technology for injecting impurity ions into a semiconductor substrate with high precision is required. The purpose of this specification is to provide a technology for injecting impurity ions into a semiconductor substrate with high precision.

Means for Solving the Problems

[0005] The method for manufacturing a semiconductor device disclosed in this specification includes a resist film forming step, a resist film ion implantation step, and a semiconductor substrate ion implantation step. In the resist film forming step, after forming a resist film on the surface of the semiconductor substrate, a part of the resist film is removed to expose a part of the surface of the semiconductor substrate. In the resist film ion implantation step, ions are implanted into the resist film to determine the shape of the resist so that the shape change of the resist film is suppressed when n-type or p-type impurities are ion implanted into the semiconductor substrate. In the semiconductor substrate ion implantation step, n-type or p-type ions are ion implanted into the semiconductor substrate.

[0006] In this manufacturing method, after ion implantation is performed on the resist film to determine the shape of the resist film, ion implantation is performed on the semiconductor substrate. When ion implantation is performed on the semiconductor substrate, ions are also implanted into the resist film. However, by performing ion implantation on the resist film prior to ion implantation on the semiconductor substrate, even if ions are implanted into the resist film when ion implantation is performed on the semiconductor substrate, it is possible to suppress the change in the shape of the resist film. The change in the shape of the resist film is suppressed during the ion implantation of the semiconductor substrate, and ion implantation can be performed within a desired range in the semiconductor substrate (it is possible to suppress ion implantation in an undesired range in the semiconductor substrate).

[0007] In the semiconductor device disclosed in this specification, a part of the surface layer of the semiconductor substrate is ion implanted with a noble gas. This semiconductor device shows a form in which a noble gas is ion implanted into the surface layer of the semiconductor substrate through an opening when a resist film having an opening is formed on the surface of the semiconductor substrate and then a noble gas is ion implanted into the resist film. When ion implanting the noble gas, since a resist film is formed on the surface of the semiconductor substrate, the noble gas is not ion implanted into the portion where the resist film is formed. Therefore, the noble gas is ion implanted only into a part of the surface layer of the semiconductor device.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] In an example of the manufacturing method disclosed in this specification, when ion-implanting a resist film, ion-implantation may be performed from an oblique direction with respect to the direction perpendicular to the surface of the semiconductor substrate.

[0010] According to this configuration, in the resist film ion-implantation process, it is possible to suppress ions from being implanted into the semiconductor substrate. The selection range of ion species that can be used in the resist film ion-implantation process is widened.

[0011] In an example of the manufacturing method disclosed in this specification, when performing ion-implantation from an oblique direction with respect to the direction perpendicular to the surface of the semiconductor substrate in the resist film ion-implantation process, when ion-implanting the resist film, n-type or p-type ions that are ion-implanted in the semiconductor substrate ion-implantation process may be ion-implanted.

[0012] According to this configuration, the resist film ion implantation process and the semiconductor substrate ion implantation process can be performed continuously. That is, by simply changing the ion irradiation angle with respect to the semiconductor substrate, both the resist film ion implantation process and the semiconductor substrate ion implantation process can be carried out. As a result, the manufacturing time of the semiconductor device can be shortened.

[0013] In an example of the manufacturing method disclosed in this specification, when ion implanting into the resist film, noble gas may be ion implanted.

[0014] According to this configuration, the resist film ion implantation process can be executed while suppressing the mixing of contaminants (impurities that determine the conductivity type) into the semiconductor device. As a result, when performing the resist film ion implantation process and the semiconductor substrate ion implantation process, it is possible to omit changing the ion irradiation angle with respect to the semiconductor substrate.

[0015] In an example of the manufacturing method disclosed in this specification, when ion implanting n-type or p-type ions into the semiconductor substrate, the ion implantation energy may be changed to form an n-type or p-type column extending in the thickness direction of the semiconductor substrate.

[0016] According to this configuration, a semiconductor device having a super junction structure can be manufactured. In a semiconductor device having a super junction structure, the impurity concentrations of the n-type columns and p-type columns extending in the thickness direction of the semiconductor substrate are adjusted to improve the breakdown voltage while the semiconductor device is off. That is, the breakdown voltage of the semiconductor device is improved by utilizing the depletion layers extending from the n-type columns and p-type columns. In order to ensure the desired breakdown voltage, it is necessary to control the sizes (the areas in the plane direction of the semiconductor device) of the n-type columns and p-type columns to the designed sizes. Since the manufacturing method disclosed in this specification has a resist film ion implantation process, the shape change of the resist film is suppressed in the semiconductor substrate ion implantation process. Therefore, a high-breakdown-voltage semiconductor device with the sizes of the n-type columns and p-type columns well controlled can be manufactured.

[0017] (Semiconductor device) Referring to FIG. 1, the semiconductor device 10 will be described. The semiconductor device 10 is a vertical semiconductor device and includes a semiconductor substrate 14, a source electrode 12 and a gate electrode 4 provided on the surface of the semiconductor substrate 14, and a drain region 26 provided on the back surface of the semiconductor substrate 14. In the semiconductor device 10, an n-type and a p-type impurity are ion-implanted into the n-type semiconductor substrate 14 to form a source region 8, a body region 6, a drift region 23, a p-type column region 22, an n-type column region 24, and a drain region 26. The drift region 23 is composed of a region in the semiconductor substrate 14 where the source region 8, the body region 6, the p-type column region 22, and the drain region 26 are not formed. That is, the n-type column region 24 is a part of the drift region 23.

[0018] On the surface of the semiconductor substrate 14, a p-type body region 6 is dispersedly provided. Also, on the surface of the body region 6, an n- + type source region 8 is provided. The source region 8 is separated from the drift region 23 by the body region 6. The source electrode 12 is electrically connected to the source region 8. Further, the gate electrode 4 is provided on the surface of the body region 6 that separates the source region 8 and the drift region 23 with a gate insulating film 2 interposed therebetween. The semiconductor device 10 is a planar-gate type MOSFET. Note that the source region 8 and the body region 6 are formed by ion-implanting an n-type or p-type impurity into the semiconductor substrate 14 from the surface of the semiconductor substrate 14. Also, although details will be described later, traces of ion-implanted rare gas are confirmed in the source region 8.

[0019] On the back surface of the semiconductor substrate 14, an n- + type drain region 28 is provided. The drain region 28 is formed by ion-implanting an n-type impurity into the semiconductor substrate 14 from the back surface of the semiconductor substrate 14.

[0020] Below the body region 6, a p-type column region 22 is formed. The p-type column region 22 extends in the thickness direction of the semiconductor substrate 14 (the direction connecting the front surface and the back surface). An n-type column region 24 into which no impurities are introduced is formed between the p-type column regions 22, 22. The p-type column region 22 and the n-type column region 24 form a superjunction structure 20. The superjunction structure 20 is formed in the middle portion in the thickness direction of the semiconductor substrate 14, that is, between the p-type column region 22 and the drain region 28. The p-type column region 22 is formed by ion-implanting p-type impurities into the semiconductor substrate 14 from the surface of the semiconductor substrate 14.

[0021] In the semiconductor device 10, when a voltage exceeding the threshold voltage is applied to the gate electrode 4, an inversion layer (channel) is formed on the surface of the body region 6 facing the gate electrode 4. Electrons supplied from the source electrode 12 to the source region 8 pass through the inversion layer and are supplied to the drift region 23. The electrons supplied to the drift region 23 move toward the drain region 26 and are discharged from the drain region 26. That is, the semiconductor device 10 is turned on. When the application of the voltage to the gate electrode 4 is stopped (when the voltage applied to the gate electrode 4 is made lower than the threshold voltage), the inversion layer formed in the body region 6 disappears, and the supply of electrons from the source region 8 to the drift region 23 stops. That is, the semiconductor device 10 is turned off. The semiconductor device 10 is a normally-on type MOSFET that turns on when a voltage exceeding the threshold voltage is applied to the gate electrode 4.

[0022] As described above, in the semiconductor device 10, a super junction structure 20 is formed in the semiconductor substrate 14. Therefore, when the semiconductor device 10 is turned off, a depletion layer extends into the p-type column region 22 from the interface between the p-type column region 22 and the n-type column region 24, and a depletion layer also extends into the n-type column region 24. In the semiconductor device 10, by controlling the length of the p-type column region 22 in the direction orthogonal to the thickness direction (width direction) (the length in the left-right direction in FIG. 1) and the length of the n-type column region 24 in the width direction, the charge amount balance condition between the p-type column region 22 and the n-type column region 24 is ensured. The semiconductor device 10 can almost completely deplete the inside of the semiconductor substrate 14 (the portion where the super junction structure 20 is formed) while the semiconductor device 10 is turned off. Therefore, the semiconductor device 10 has a high breakdown voltage.

[0023] (Method of manufacturing a semiconductor device: First embodiment) As described above, the semiconductor device 10 forms a plurality of impurity regions by ion-implanting n-type or p-type impurities from the front or back surface of the semiconductor substrate 14. When ion-implanting impurities into a part of the semiconductor substrate 14, a resist film (mask layer) having an opening is formed on the front or back surface of the semiconductor substrate 14, and ion irradiation is performed. Although the basic process of the ion implantation technique using a resist film is known, the semiconductor device 10 is characterized in the process from forming the resist film to starting the ion implantation. With reference to FIGS. 2 to 4 below, the ion implantation process for forming the p-type column region 22 in the semiconductor substrate 14 will be described.

[0024] As shown in FIG. 2, after forming a resist film 30 on the surface of the semiconductor substrate 14, a part of the resist film is removed to form an opening 34, and a part of the surface of the semiconductor substrate 14 is exposed (resist film forming step 50). Since the resist film forming step is a known technique, a detailed description thereof will be omitted.

[0025] Next, as shown in FIG. 3, the semiconductor substrate 14 is irradiated with ions of a rare gas. As the rare gas, helium, neon, argon, etc. can be used. When the semiconductor substrate 14 is irradiated with ions of the rare gas, the rare gas is injected into the range 14a where the semiconductor substrate 14 is exposed by the opening 34, and the rare gas is not injected into the range 14b where the semiconductor substrate 14 is covered with the resist film 30. Also, when the semiconductor substrate 14 is irradiated with ions of the rare gas, the rare gas is also injected into the resist film 30 (resist film ion implantation step 52). When the rare gas is injected into the resist film 30, the surface (upper surface and side surface) of the resist film 30 is cured, and a cured region 31 and an uncured region 32 are formed in the resist film 30. When the cured region 31 is formed, the shape of the resist film 30 changes (typically shrinks) in the cured region 31. Whether or not the rare gas is ion-implanted into the range 14a can be confirmed by performing elemental analysis such as SIMS (secondary ion mass spectrometry).

[0026] Next, as shown in FIG. 4, p-type impurities are ion-implanted into the semiconductor substrate 14. When the semiconductor substrate 14 is irradiated with ions of the p-type impurities, the p-type impurities are injected into the range 14a where the semiconductor substrate 14 is exposed by the opening 34, and the rare gas is not injected into the range 14b where the semiconductor substrate 14 is covered with the resist film 30. When ion-implanting the p-type impurities, the ion irradiation energy is changed to change the ion implantation depth as in the ranges 22a, 22b, 22c (semiconductor substrate ion implantation step 54). Thereby, a p-type column region 22 is formed in the semiconductor substrate 14. Note that, among the semiconductor substrate 14, the portion where the p-type impurities are not ion-implanted (p-type column region 22) becomes an n-type column region 24. In the semiconductor device 10, a superjunction structure 20 is formed by ion-implanting p-type impurities into the semiconductor substrate 14 (see also FIG. 1).

[0027] Here, referring to FIGS. 5 and 6, the advantages of the semiconductor device 10 and its manufacturing method will be described. FIGS. 5 and 6 show a conventional resist film forming step 150 and a semiconductor substrate ion implantation step 154. In the resist film forming step 150, the resist film 130 is irradiated with UV light to cure the surface of the resist film 130. As a result, a cured region 131 and an uncured region 132 are formed in the resist film 130.

[0028] Next, as shown in FIG. 6, p-type impurities are ion-implanted toward the semiconductor substrate 14. When p-type impurities are ion-irradiated toward the semiconductor substrate 14, p-type impurities are implanted in the range where the semiconductor substrate 14 is exposed by the opening 34, and p-type impurities are also ion-implanted into the resist film 130. When p-type impurities are ion-implanted into the resist film 130, the range of the cured region 131 expands ((a) → (b)), and the shape of the resist film 130 changes (typically shrinks). As a result, the implantation range of the p-type impurities in the semiconductor substrate 14 changes like ranges 122a, 122b, 122c depending on the ion implantation depth.

[0029] As described above, in the semiconductor device 10, prior to the semiconductor substrate ion implantation step 54 (FIG. 4), the resist film ion implantation step 52 is performed. In the resist film ion implantation step 52, the resist film 30 is ion-implanted to complete the shape change of the resist film 30 in advance (to determine the cured region 31). As a result, even when p-type impurities are ion-implanted into the resist film 30 in the semiconductor substrate ion implantation step 54, the curing of the resist film 30 does not proceed further without being suppressed, and the shape change of the resist film 30 is suppressed. As a result, the change in the implantation range of the p-type impurities in the semiconductor substrate 14 depending on the ion implantation depth is suppressed (compare FIGS. 4 and 6).

[0030] In the semiconductor device 10, by controlling the lengths (widths of the p-type column region 22 and the n-type column region 24) of the p-type column region 22 and the n-type column region 24 in the width direction, the charge amount balance condition between the p-type column region 22 and the n-type column region 24 is ensured. Therefore, by performing the resist film ion implantation step 52 to complete the shape change of the resist film 30 in advance, it is possible to suppress the change in the shape of the resist film 30 in the semiconductor substrate ion implantation step 54. Since the width of the p-type column region 22 is controlled to the desired width (designed value width), the charge amount balance between the p-type column region 22 and the n-type column region 24 can be controlled as designed. As a result, a semiconductor device 10 with high breakdown voltage can be realized.

[0031] On the other hand, in the case of the conventional method for manufacturing a semiconductor device, the shape of the resist film 130 changes in the semiconductor substrate ion implantation step 154, the charge amount balance between the p-type column region and the n-type column region deviates from the designed value, and the breakdown voltage of the semiconductor device decreases (decreases from the designed value).

[0032] Next, with reference to FIGS. 7 and 8, the resist film ion implantation step 52 will be described in detail. As described above, in the resist film ion implantation step 52, a rare gas is ion-implanted into the resist film 30 so as to suppress the change in the shape of the resist film 30 in the semiconductor substrate ion implantation step 54. In the resist film ion implantation step 52, a rare gas is ion-implanted into the resist film 30 so as to obtain a hardened region 31 in a wider range (longer distance from the surface of the resist film 30) than the hardened region 131 obtained in the conventional resist film formation step 150. Thereby, in the semiconductor device 10, the range of the impurity region formed in the semiconductor substrate 14 can be highly controlled as compared with the conventional method for manufacturing a semiconductor device.

[0033] FIG. 7 shows the resist film 30 after the resist film ion implantation step 52 disclosed in this specification, and FIG. 8 shows the resist film 130 after the conventional resist film forming step 150. As shown in FIG. 7, the width h32 of the uncured region 32 is smaller than the thickness t32 of the uncured region 32 (h32 < t32). In this case, the resist film ion implantation step 52 is performed so as to satisfy the following formula 1. Formula 1: 0 ≦ t32 ≦ t132

[0034] The thickness t132 indicates the thickness of the uncured region 132 when the surface of the resist film 130 is cured in the conventional resist film forming step 150. Typically, in the conventional resist film forming step 150 (curing of the resist film 130 by UV irradiation), since the UV absorption rate decreases due to the temperature rise on the surface of the resist film 130, the cured region 131 is formed only up to about 1 μm from the surface of the resist film 130. Therefore, when quantitatively expressing the above formula 1, it can also be shown as 0 ≦ t32 ≦ 1 μm. The thickness t32 can be determined by separately conducting experiments to determine the conditions (ion irradiation time, ion implantation energy, etc.).

[0035] In addition, when the width h32 of the uncured region 32 is larger than the thickness t32 of the uncured region 32 (h32 > t32), the resist film ion implantation step 52 may be performed so as to satisfy the following formula 2. In the following formula 2, the width h132 indicates the width of the uncured region 132 when the surface of the resist film 130 is cured in the conventional resist film forming step 150. The width t32 can also be determined by separately conducting experiments to determine the conditions (ion irradiation time, ion implantation energy, etc.). Formula 2: 0 ≦ h32 ≦ h132

[0036] Furthermore, the conditions of the resist film ion implantation step 52 can be determined without using the conditions such as the thickness t32 and width h32 of the uncured region 32 and the results of the conventional resist film formation step 150. In this case, the resist film ion implantation step 52 is performed so as to satisfy the following formula 3. In the following formula 3, h34a represents the width T34 of the opening 34 before the semiconductor substrate ion implantation step 54, and the width h34b represents the width T34 of the opening 34 after the semiconductor substrate ion implantation step 54. The widths h34 and h34b can also determine the conditions (ion irradiation time, ion implantation energy, etc.) by separately conducting experiments. Formula 3: h34b / h34a ≦ 5%

[0037] In addition, in the resist film ion implantation step 52, the resist film ion implantation step 52 is performed so as to satisfy the following formulas 3 and 4 so that the rare gas is surely implanted into the resist film 30. In the following formula 4, t30 represents the thickness of the resist film 30, and Rp represents the range distance of the rare gas ions. Also, in the following formula 5, W represents the implantation energy of the rare gas, and T represents the output (acceleration energy × beam current) when implanting the rare gas ions. Formula 4: t30 ≦ Rp Formula 5: 2W ≦ T

[0038] (Manufacturing method of semiconductor device: Second embodiment) Referring to FIG. 9, another manufacturing method of the semiconductor device 10 will be described. FIG. 9 shows a resist film ion implantation step 52a. The resist film ion implantation step 52a is a modified example of the resist film ion implantation step 52 (FIG. 3). In the manufacturing method of this embodiment, the resist film formation step 50 (FIG. 2) and the semiconductor substrate ion implantation step 54 (FIG. 4) are the same as those in the first embodiment, and thus the description thereof is omitted.

[0039] In the resist film ion implantation step 52a, a rare gas is ion-implanted from an oblique direction with respect to the direction perpendicular to the surface of the semiconductor substrate 14 (the direction of the normal line 60). The resist film ion implantation step 52a can suppress the implantation of rare gas ions into the semiconductor substrate 14 as compared with the resist film ion implantation step 52. Further, in the case of the resist film ion implantation step 52a, by utilizing the feature that it is difficult for ions to be implanted into the semiconductor substrate 14, the same type of ions (i.e., p-type impurities) as those used in the semiconductor substrate ion implantation step 54 can also be used. By using the same type of ions in the resist film ion implantation step 52a and the semiconductor substrate ion implantation step 54, the two steps 52a and 54 can be continuously performed without switching the irradiated ions.

[0040] Also in the resist film ion implantation step 52a, the conditions of the resist film ion implantation step 52a are determined so as to satisfy any one of the above formulas 1 to 3. Further, in the resist film ion implantation step 52a, in order to implant ions into the entire resist film 30 (upper surface and side surfaces), ion implantation is performed so as to satisfy the following formula 6. In the following formula 6, θ1 represents the angle between the normal line 60 and the ion implantation direction. Formula 6: 30 degrees ≤ θ1 ≤ arctan(t30 / h34) × 190 / 3.14

[0041] Note that in the above formula 6, the thickness t34 and the width h34 may be the thickness t34 and the width h34 before the resist film ion implantation step 52a, or may be the thickness t34 and the width h34 after the resist film ion implantation step 52a. When defined by the thickness t34 and the width h34 after the resist film ion implantation step 52a in the above formula 6, the values of the thickness t34 and the width h34 may be calculated in advance by performing separate experiments.

[0042] In the above embodiments, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), etc. can be used as the material of the semiconductor substrate. When the semiconductor substrate is silicon, boron can be used as the n-type impurity and phosphorus can be used as the p-type impurity. When the semiconductor substrate is SiC, nitrogen can be used as the n-type impurity and aluminum can be used as the p-type impurity. When the semiconductor substrate is GaN, silicon can be used as the n-type impurity and magnesium can be used as the p-type impurity.

[0043] In the above embodiments, the planar gate type MOSFET has been described. However, the technology disclosed in this specification can be applied to various semiconductor devices, and can also be used for, for example, trench gate type MOSFETs, planar gate type or trench gate type IGBTs, etc. That is, as long as it is a semiconductor device that forms an impurity region by ion implanting an n-type or p-type impurity into a semiconductor substrate, the type of the semiconductor device is arbitrary.

[0044] Also, in the above embodiments, an example of forming a superjunction structure by ion implanting a p-type impurity to form a p-type column region has been described. However, a superjunction structure may also be formed by ion implanting an n-type impurity to form an n-type column region.

[0045] Also, in the above embodiments, an example of performing a resist film ion implantation process when forming a p-type column region has been described. However, the above manufacturing method (the manufacturing method that performs a resist film ion implantation process) may also be performed when forming other impurity regions. That is, the technology disclosed in this specification can also be used for manufacturing semiconductor devices that do not have a superjunction structure.

[0046] The configuration of the technology disclosed in this specification is listed below. (Configuration 1) After forming a resist film on the surface of the semiconductor substrate, a step of removing a part of the resist film to expose a part of the surface of the semiconductor substrate; A step of determining the shape of the resist film so that when ion implantation is performed on the resist film and n-type or p-type impurities are ion implanted into the semiconductor substrate, a change in the shape of the resist film is suppressed; A step of ion implanting n-type or p-type impurities into the semiconductor substrate; A method for manufacturing a semiconductor device, comprising: (Configuration 2) The manufacturing method according to Configuration 1, wherein when ion implantation is performed on the resist film, ion implantation is performed from an oblique direction with respect to the direction perpendicular to the surface of the semiconductor substrate. (Configuration 3) The manufacturing method according to Configuration 2, wherein when ion implantation is performed on the resist film, n-type or p-type ions are ion implanted. (Configuration 4) The manufacturing method according to Configuration 1 or 2, wherein when ion implantation is performed on the resist film, a rare gas is ion implanted. (Configuration 5) The manufacturing method according to any one of Configurations 1 to 4, wherein when ion implanting n-type or p-type impurities into the semiconductor substrate, the ion implantation energy is changed to form an n-type or p-type column extending in the thickness direction of the semiconductor substrate. (Configuration 6) A semiconductor device in which a rare gas is ion implanted into a part of the surface layer of a semiconductor substrate.

[0047] Although the embodiments of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. In addition, the technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Also, the technology illustrated in this specification or the drawings achieves a plurality of purposes simultaneously, and has technical usefulness by achieving one of those purposes itself.

Explanation of Reference Numerals

[0048] 10: Semiconductor device, 14: Semiconductor substrate, 22: p-type column, 24: n-type column, 30: Resist film

Claims

1. After forming a resist film (30) on the surface of a semiconductor substrate (14), a step (50) of removing a part of the resist film to expose a part of the surface of the semiconductor substrate; A step (52, 52a) of ion-implanting the resist film to determine the shape of the resist film so that the shape change of the resist film is suppressed when n-type or p-type impurities are ion-implanted into the semiconductor substrate; A step (54) of ion-implanting n-type or p-type impurities into the semiconductor substrate; A method for manufacturing a semiconductor device (10), comprising:

2. The manufacturing method according to claim 1, wherein when ion-implanting the resist film, ion-implanting is performed from an oblique direction with respect to a direction (60) perpendicular to the surface of the semiconductor substrate.

3. The manufacturing method according to claim 2, wherein when ion-implanting the resist film, n-type or p-type ions are ion-implanted.

4. The manufacturing method according to claim 1 or 2, wherein when ion-implanting the resist film, a rare gas is ion-implanted.

5. The manufacturing method according to claim 1 or 2, wherein when ion-implanting n-type or p-type impurities into the semiconductor substrate, the ion-implantation energy is changed to form an n-type or p-type column (22) extending in the thickness direction of the semiconductor substrate.

6. A semiconductor device in which a part of the surface layer of a semiconductor substrate is ion-implanted with a rare gas.

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