Array substrate and display panel

Abstract

To solve the problem that a storage capacitor cannot be set large in an existing OLED panel.SOLUTION: A substrate 10 includes a first thin film transistor 01 disposed in a pixel region, and a first electrode plate 301 and a second electrode plate 302 disposed in a capacitor region so as to face each other in different layers. The first thin film transistor 01 includes a first active layer 012, a first gate layer 017, and a first source drain layer 204. The first capacitor 30 further includes a first dielectric layer 303 disposed between the first electrode plate 301 and the second electrode plate 302. The first dielectric layer 303 includes a first sub-dielectric layer 3031 with a high dielectric constant and a second sub-dielectric layer 3032 with a low dielectric constant. The orthogonal projection of the active layer on the substrate is disposed in the orthogonal projection in the second sub-dielectric layer 3032, so that the capacitance value of the first active layer 012 is increased and at the same time, the failure risk of the first active layer 012 is reduced.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to the field of display technology, particularly to the manufacture of display devices, and specifically to array substrates and display panels.

Background Art

[0002] Panels such as OLED (Organic Light Emitting Diode) have a simple component structure, low production costs, high energy efficiency, are easy to bend, and are used in a wide range of applications.

[0003] Here, the pixel driving circuit of a panel such as OLED generally includes a storage capacitor for storing a grayscale voltage for determining a driving current. If the storage capacitor is set too small, the emission luminance of the light emitting device will decrease. However, if a two-layer or multi-layer capacitor structure is set to increase the capacitor, the number of process lanes of the panel will increase. Also, if the relative area of the capacitor electrode plate is increased, the occupied area of the sub-pixel will increase, which has an adverse effect on high-resolution products.

[0004] Therefore, the storage capacitor of the existing OLED panel cannot be set large, and improvement is urgently needed.

Summary of the Invention

Problems to be Solved by the Invention

[0005] An object of the present invention is to provide an array substrate and a display panel for solving the problem that the storage capacitor in the existing OLED panel cannot be set large.

Means for Solving the Problems

[0006] The array substrate provided by the embodiment of the present invention includes a substrate on which a pixel region and a capacitor region are defined, and a first thin-film transistor disposed in the pixel region on the substrate, the first thin-film transistor including a first active layer, a first gate layer disposed on a side of the first active layer close to the substrate or far from the substrate, and a first source-drain layer disposed on a side of the first active layer far from the substrate and electrically connected to the first active layer; and a first capacitor including a first electrode plate and a second electrode plate that are arranged in different layers and face each other, wherein the first electrode plate and the second electrode plate are disposed in the capacitor region, the first capacitor further includes a first dielectric layer disposed between the first electrode plate and the second electrode plate, the first dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer disposed on a side of the first sub-dielectric layer close to the first active layer, and the second sub-dielectric layer is disposed in the pixel region and the capacitor region. The dielectric constant of the first sub-dielectric layer is greater than that of the second sub-dielectric layer, and the orthographic projection of the first active layer on the substrate is disposed within the orthographic projection of the second sub-dielectric layer on the substrate.

[0007] In one embodiment, the composition material of the first sub-dielectric layer includes at least one of alumina and zirconia, and the composition material of the second sub-dielectric layer includes silicon oxide.

[0008] In one embodiment, the first gate layer is disposed on a side of the first active layer far from the substrate, the first electrode plate and the first gate layer are disposed in the same layer, the composition material of the first electrode plate is the same as that of the first gate layer, and the second electrode plate is disposed on a side of the first electrode plate far from the substrate or close to the substrate.

[0009] In one embodiment, the second electrode plate is disposed on the side of the first electrode plate farther from the substrate, the second electrode plate is disposed between the first electrode plate and the first source-drain layer, or the second electrode plate and the first source-drain layer are disposed in the same layer.

[0010] In one embodiment, the second electrode plate is disposed on the side of the first electrode plate closer to the substrate, the first thin-film transistor further includes a gate insulating layer disposed between the first active layer and the first gate layer, the gate insulating layer is disposed opposite to the first gate layer, and the first dielectric layer and the gate insulating layer are disposed in the same layer.

[0011] In one embodiment, the array substrate further includes a light-shielding layer disposed on the side of the first active layer closer to the substrate, the second electrode plate is disposed on the side of the first electrode plate closer to the substrate, and the second electrode plate and the light-shielding layer are disposed in the same layer.

[0012] In one embodiment, the first gate layer is disposed on the side of the first active layer closer to the substrate, the first electrode plate and the first gate layer are disposed in the same layer, the composition materials of the first electrode plate and the first gate layer are the same, and the second electrode plate is disposed on the side of the first electrode plate farther from the substrate.

[0013] In one embodiment, the first thin-film transistor is a double-gate thin-film transistor, and the double-gate thin-film transistor includes a first sub-gate layer disposed on the side of the first active layer farther from the substrate and a second sub-gate layer disposed on the side of the first active layer closer to the substrate.

[0014] In one embodiment, the first electrode plate and the first sub - gate layer are arranged in the same layer, the first electrode plate and the first sub - gate layer are made of the same composition material, and the second electrode plate is arranged on the side of the first electrode plate far from the substrate or on the side close to the substrate. Alternatively, the first electrode plate and the second sub - gate layer are arranged in the same layer, the first electrode plate and the second sub - gate layer are made of the same composition material, and the second electrode plate is arranged on the side of the first electrode plate far from the substrate or on the side close to the substrate.

[0015] In one embodiment, a non - display area is further defined on the substrate, the array substrate further includes a second thin - film transistor, the second thin - film transistor is arranged in the non - display area, there is a gap between the orthographic projection of the second thin - film transistor on the substrate and the orthographic projection of the first thin - film transistor on the substrate, the second thin - film transistor includes a second active layer, the first active layer is arranged on the side of the second active layer close to the substrate, a first sub - gate insulating layer and a second gate layer are arranged in order from the side of the second active layer far from the substrate, a second sub - gate insulating layer, a third sub - gate insulating layer and a first gate layer are arranged in order from the side of the first active layer far from the substrate, a fourth sub - gate insulating layer is arranged on the side of the second active layer close to the substrate, the composition material of the first sub - gate insulating layer is the same as the composition material of the third sub - gate insulating layer, and the composition material of the second sub - gate insulating layer is the same as the composition material of the fourth sub - gate insulating layer.

[0016] In one embodiment, the second sub - dielectric layer is further arranged in the non - display area, and the orthographic projection of the second active layer on the substrate is arranged within the orthographic projection of the second sub - dielectric layer on the substrate.

[0017] The display panel provided by an embodiment of the present invention includes the array substrate described in any one of the above embodiments, a metal adapter layer disposed on a side of the first thin film transistor away from the substrate, and a pixel layer disposed on a side of the metal adapter layer away from the substrate, wherein the metal adapter layer electrically connects the first source-drain layer and the pixel layer.

[0018] The array substrate and the display panel provided by an embodiment of the present invention include a substrate on which a pixel region and a capacitor region are defined, a first thin film transistor disposed in the pixel region on the substrate, the first thin film transistor including a first active layer, a first gate layer disposed on a side of the first active layer close to the substrate or on a side of the first active layer away from the substrate, and a first source-drain layer disposed on a side of the first active layer away from the substrate and electrically connected to the first active layer, a first capacitor including a first electrode plate and a second electrode plate disposed in different layers and facing each other, (wherein the first electrode plate and the second electrode plate are disposed in the capacitor region), the first capacitor further including a first dielectric layer disposed between the first electrode plate and the second electrode plate, the first dielectric layer including a first sub-dielectric layer and a second sub-dielectric layer disposed on a side of the first sub-dielectric layer close to the first active layer (wherein the second sub-dielectric layer is disposed in the pixel region and the capacitor region),

Advantages of the Invention

[0019] According to the present invention, by setting the dielectric constant of the first sub-dielectric layer to be greater than the dielectric constant of the second sub-dielectric layer, the capacitance value of the first capacitor is increased, and by disposing the orthographic projection of the active layer on the substrate within the orthographic projection of the second sub-dielectric layer on the substrate, the failure risk of the first active layer is reduced.

Brief Description of the Drawings

[0020] The present invention will be described in more detail with reference to the drawings. Of course, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments that can be conceived by those skilled in the art without creative efforts are included in the protection scope of the present invention.

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Embodiments for Carrying Out the Invention

[0021] Hereinafter, the technical solutions of the embodiments of the present invention will be clearly and completely described in conjunction with the drawings of the embodiments of the present invention. Of course, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments that can be conceived by those skilled in the art without creative efforts are included in the protection scope of the present invention.

[0022] In the specification of the present invention, the directions or positional relationships indicated by terms such as "upper", "lower", "near", "far", etc. are based on the directions or positional relationships shown in the drawings. For example, "upper" only refers to the upper surface of the object, and specific designations such as directly above, diagonally above, or on the upper surface are sufficient as long as the object exists above the horizontal level. The above-mentioned directions or positional relationships are only for facilitating the description of the present invention and simplifying the description, and are not intended to indicate or imply that the mentioned devices or components must have a specific direction, be configured in a specific direction, and operate. Therefore, they should not be construed as limitations of the present invention.

[0023] Regarding the drawings, only the relatively precise structures and processes related to the present invention are shown, details not related to the present invention are omitted, and the drawings are presented for the purpose of simplifying the drawings to clarify the points of the invention. They do not indicate that the actual devices and methods are the same as the drawings, nor do they limit the actual devices and methods.

[0024] The present invention provides an array substrate and a display panel including the array substrate. The display panel and the array substrate include, but are not limited to, the following examples and combinations between the following examples.

[0025] In one embodiment, as shown in FIGS. 1 to 9, a display panel 100 and an array substrate 200 included therein include a display area A1 and a non-display area A2, and include a substrate 10, a thin film transistor 20, and a first capacitor 30. The thin film transistor 20 is a thin film transistor 20 disposed on the substrate 10 and corresponding to at least one of the display area A1 and the non-display area A2, and includes an active layer 201, a gate layer 202 disposed on a side of the active layer 201 close to the substrate 10 or far from the substrate 10, and a source-drain layer 204 disposed on a side of the active layer 201 far from the substrate 10 and electrically connected to the active layer 201. The first capacitor 30 is a first capacitor 30 disposed on the substrate 10 and corresponding to the display area A1, and includes a first electrode plate 301 and a second electrode plate 302 disposed in different layers and facing each other, and a first dielectric layer 303 disposed between the first electrode plate 301 and the second electrode plate 302. The first dielectric layer 303 includes the first dielectric layer 303, a first sub-dielectric layer 3031, and a second sub-dielectric layer 3032 disposed on a side of the first sub-dielectric layer 3031 close to the active layer 201. The dielectric constant of the first sub-dielectric layer 3031 is greater than the dielectric constant of the second sub-dielectric layer 3032, and the orthographic projection of the active layer 201 on the substrate 10 is disposed within the orthographic projection of the second sub-dielectric layer 3032 on the substrate 10.

[0026] Here, as shown in FIG. 2, the display area A1 can define a pixel area A11 and a capacitor area A12. In the display area A1, a transistor (i.e., the first thin-film transistor 01) arranged in the pixel area A11 and driving the light emission from the sub-pixels, and a corresponding storage capacitor (i.e., the first capacitor 30) arranged in the capacitor area A12 are provided. FIGS. 1, 3 to 9 can be understood as only illustrating the display area A1, and FIG. 2 also illustrates the non-display area A2 arranged around the display area A1 with respect to FIGS. 1, 3 to 7. The transistor in the display area A1 in FIG. 2 is specifically the first thin-film transistor 01, and the transistor in the non-display area A2 in FIG. 2 is specifically the second thin-film transistor 02.

[0027] It should be noted that the statement "the orthographic projection of the active layer 201 on the substrate 10 is arranged within the orthographic projection of the second sub-dielectric layer 3032 on the substrate 10" has the following two understandings. (1) When the thin-film transistor 20 includes at least the first thin-film transistor 01, as shown in FIGS. 1, 3 to 9, the second sub-dielectric layer 3032 further extends from the capacitor area to the position arranged in the pixel area A11, and the orthographic projection of the first active layer 012 on the substrate 10 in the first thin-film transistor 01 is arranged within the orthographic projection of the second sub-dielectric layer 3032 on the substrate 10. (2) When the thin-film transistor 20 includes at least the second thin-film transistor 02, as shown in FIG. 2, the second sub-dielectric layer 3032 further extends from the capacitor area to the position arranged in the non-display area A2, and the orthographic projection of the second active layer 011 on the substrate 10 in the second thin-film transistor 02 is arranged within the orthographic projection of the second sub-dielectric layer 3032 on the substrate 10.

[0028] As shown in FIGS. 1, 3 to 9, here, the relative positional relationship between the first thin film transistor 01 and the first capacitor 30 will be described by way of example. The first thin film transistor 01 includes a first active layer 012 (included in the active layer 201), a first gate layer 017 (included in the gate layer 202) disposed on the side of the first active layer 012 closer to or farther from the substrate 10, and a first source-drain layer 2041 (included in the source-drain layer 204) disposed on the side of the first active layer 012 farther from the substrate 10 and electrically connected to the first active layer 012.

[0029] Specifically, as shown in FIGS. 1 to 7, the substrate 10 may include a glass substrate 101, a flexible substrate 102, and a barrier layer 103 that are stacked and arranged. The composition material of the glass substrate 101 may include at least one of glass and quartz, but is not limited thereto. The composition material of the flexible substrate 102 may include polyimide, but is not limited thereto. The flexible substrate 102 may include two layers of flexible materials and a buffer material disposed therebetween. The composition material of the barrier layer 103 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride, but is not limited thereto, and is used to prevent the diffusion of impurity ions and the penetration of moisture and external air, and can perform a surface flattening function.

[0030] Here, as shown in FIGS. 1 to 7, the display panel 100 may be disposed on the substrate 10 and include a plurality of thin film transistors 20 that are electrically connected. By loading an electrical signal, the light emission of the display panel 100 can be realized. Specifically, each thin film transistor 20 may include an active layer 201 for realizing on and off. The composition material of the active layer 201 may include amorphous silicon, polycrystalline silicon, or an oxide semiconductor. The polycrystalline silicon may include low-temperature polysilicon. The oxide semiconductor may include any one of oxides of titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn), or indium (In), or their composite oxides. Here, the active layer 201 manufactured using the low-temperature polysilicon technology can have a higher electron mobility in order to have a higher charging speed. The active layer 201 manufactured using amorphous silicon or an oxide can have a low leakage current in order to reduce the interference of the leakage from the thin film transistor 20 to the signal. Further, the active layer 201 may include a channel region and doping regions disposed at both ends of the channel region. The doping regions have higher conductivity and lower resistance than the channel region.

[0031] Specifically, as shown in FIGS. 1 to 7, in addition to including a plurality of first thin film transistors 01, the pixel driving circuit in the display panel 100 includes a storage capacitor for storing a gradation voltage so as to determine a driving current. The first capacitor 30 in this embodiment is used to constitute the above storage capacitor. The first capacitor 30 may include a first electrode plate 301, a second electrode plate 302 which are arranged in different layers and face each other, and a first dielectric layer 303 arranged therebetween. Here, the capacitance value of the first capacitor 30 may be equal to ε*S / (4πkd), where ε is the dielectric constant of the first dielectric layer 303, S is the facing area of the first electrode plate 301 and the second electrode plate 302, d is the distance between the first electrode plate 301 and the second electrode plate 302, and k is the electrostatic constant.

[0032] In this embodiment, for the first capacitor 30, it can be understood that the first dielectric layer 303 is arranged to include a first sub-dielectric layer 3031 and a second sub-dielectric layer 3032 which are stacked, and the dielectric constant of the first sub-dielectric layer 3031 is arranged to be larger than the dielectric constant of the second sub-dielectric layer 3032. Compared with arranging only the second sub-dielectric layer 3032 with a small dielectric constant or other film layers arranged between both electrode plates, arranging the first dielectric layer 303 with a large dielectric constant can effectively increase the dielectric constant ε of the first dielectric layer 303, thereby increasing the capacitance value of the first capacitor 30 and reducing the risk of reducing the light emission luminance of the light emitting device. At the same time, in this embodiment, taking the first active layer 012 as an example, the second sub-dielectric layer 3032 with a small dielectric constant is arranged on the side of the first sub-dielectric layer 3031 close to the first active layer 012, and the orthographic projection of the first active layer 012 on the substrate 10 is arranged within the orthographic projection of the second sub-dielectric layer 3032 on the substrate 10, so that impurities such as hydrogen elements can be effectively prevented from diffusing from above to the first active layer 012, and the risk of the first active layer 012 becoming ineffective is reduced.

[0033] Here, the hydrogen element content in the second sub-dielectric layer 3032 is considered to be lower than that in the first sub-dielectric layer 3031, and the second sub-dielectric layer 3032 is considered to be more stable than the first sub-dielectric layer 3031. The second sub-dielectric layer 3032 may be composed of silicon element, oxygen element, and metal element. For example, it may include silicon oxide, but is not limited thereto. The dielectric constant of the first sub-dielectric layer 3031 may be greater than 4, and the composition material of the first sub-dielectric layer 3031 may include at least one of alumina and zirconia, but is not limited thereto.

[0034] In one embodiment, as shown in FIGS. 1 to 4 and FIG. 9, here, taking the first gate layer 017 in the gate layer 202 as an example for explanation, the first gate layer 017 is disposed on the side of the first active layer 012 far from the substrate 10, the first electrode plate 301 and the first gate layer 017 are disposed in the same layer, the composition material of the first electrode plate 301 and the composition material of the first gate layer 017 are the same, and the second electrode plate 302 is disposed on the side of the first electrode plate 301 far from the substrate 10 (see FIGS. 1 to 3) or on the side close to the substrate 10 (see FIG. 4).

[0035] Here, the composition material of the gate layer 202 (including the first gate layer 017) may include, but is not limited to, one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). As shown in FIGS. 1 and 2, in this embodiment, only an example is shown where the thin-film transistor 20 has a top-gate structure. Specifically, a gate insulating layer 203 may be disposed between the gate layer 202 and the active layer 201. Since the gate insulating layer 203 is used to insulate the gate layer 202 and the active layer 201, the orthographic projection of the gate insulating layer 203 on the substrate 10 exceeds at least the orthographic projection of the gate layer 202 on the substrate 10. Of course, the gate insulating layer 203 can also extend beyond the active layer 201 and the buffer layer 50. Here, the composition material of the gate insulating layer 203 may include, but is not limited to, silicon compounds, metal oxides, etc. For example, it may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, and titanium oxide.

[0036] Here, the composition material of the source-drain layer 204 (including the first source-drain layer 2041) can refer to the composition material of the gate layer 202. They may be the same or different. The array substrate 200 may further include a wiring portion 11 disposed in the same layer as the source-drain layer 204, and the wiring portion 11 may be electrically connected to the first source-drain layer 2041 to enable signal transmission.

[0037] Here, as shown in FIGS. 1 to 4, since the conductivity of the gate layer 202 (including the first gate layer 017) is good, "the first electrode plate 301 and the first gate layer 017 are arranged in the same layer" in this embodiment can be understood as manufacturing the first electrode plate 301 and the first gate layer 017 simultaneously with the same material. Since the first active layer 012 is arranged between the first gate layer 017 and the buffer layer 50, as a result, in the thickness direction of the film layer, the horizontal position of the first gate layer 017 is higher than the horizontal position of the first electrode plate 301. Further, when the gate insulating layer 203 is formed by patterning and arranged to face the first gate layer 017, generally, the entire layer of the gate insulating film for the later manufacturing of the gate insulating layer 203 can be formed first, and then, the patterned first gate layer 017 and the first electrode plate 301 are simultaneously formed on the gate insulating film. Then, the gate insulating film is etched, and by shielding the first gate layer 017 and the first electrode plate 301, it is avoided that the portions of the gate insulating film corresponding to both are etched and remain, and the gate insulating layer 203 corresponding to the lower part of the first gate layer 017 and the first pad portion 3041 corresponding to the lower part of the first gate plate 301 are formed. The thickness of the first pad portion 3041 is close to the thickness of the gate insulating layer 203.

[0038] Specifically, as shown in FIGS. 1 to 3, the second electrode plate 302 is disposed on the side farther from the substrate 10 of the first electrode plate 301 (here, the specific position of the film layer where the second electrode plate 302 is located is not limited). Regarding the first dielectric layer 303 also being disposed on the side farther from the substrate 10 of the first active layer 012, since the first sub-dielectric layer 3031 with a large dielectric constant is disposed on the side farther from the substrate 10 than the second sub-dielectric layer 3032 with a small dielectric constant, the second sub-dielectric layer 3032 is disposed between the first sub-dielectric layer 3031 and the first active layer 012, and the composition material of the second sub-dielectric layer 3032 contains silicon oxide. Since the dielectric constant of the first sub-dielectric layer 3031 is large (its composition material may include, but is not limited to, alumina and zirconia), the second sub-dielectric layer 3032 is considered to have more stable and dense characteristics, and compared with the case where only the first sub-dielectric layer 3031 is disposed, the risk of impurities such as hydrogen elements diffusing from above to the first active layer 012 can be reduced.

[0039] Specifically, as described above, as shown in FIGS. 1 to 3, when the gate insulating layer 203 is disposed opposite to the first gate layer 017, since the orthographic projection of the first active layer 012 on the substrate 10 exceeds the orthographic projection of the gate insulating layer 203 on the substrate 10, both ends thereof will not be shielded by the gate insulating layer 203. In order to reduce the influence of the diffusion of the above hydrogen element on the first active layer 012, it is necessary to dispose the second sub-dielectric layer 3032 that completely exceeds the first active layer 012 on the side farther from the substrate 10 of the first gate layer 017.

[0040] Note that the hydrogen element may be generated during the manufacturing process of other film layers in the array substrate or the corresponding display panel, or may be generated from the external environment, such as water vapor in the air.

[0041] Furthermore, based on the top gate structure, as shown in FIGS. 1 to 3, the array substrate 200 further includes a light-shielding layer 40 disposed on the side of the first active layer 012 closer to the substrate 10. The light-shielding layer 40 may be disposed opposite to the first active layer 012 and is used to block the irradiation or reflection of light to the first active layer 012, reducing the risk of the first active layer 012 becoming ineffective. The composition material of the light-shielding layer 40 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). Furthermore, a buffer layer 50 may be disposed between the light-shielding layer 40 and the first active layer 012 to prevent the penetration of unnecessary components such as impurities or moisture. The composition material of the buffer layer 50 may include at least one of silicon nitride (SiNx) and silicon oxide (SiOx), but is not limited thereto.

[0042] In one embodiment, as shown in FIG. 2, the thin film transistor 20 includes a second thin film transistor 02 disposed in the non-display area A2 and a first thin film transistor 01 disposed in the pixel area A11 in the display area A1. The active layer 201 includes a second active layer 011 of the second thin film transistor 02 and a first active layer 012 of the first thin film transistor 01. The second active layer 011 and the first active layer 012 are disposed in different layers. There is a gap between the orthographic projection of the second thin film transistor 02 on the substrate 10 and the orthographic projection of the first thin film transistor 01 on the substrate 10. The first active layer 012 is disposed on the side of the second active layer 011 closer to the substrate 10. A first subgate insulating layer 013 and a second gate layer 014 are disposed in order from the side of the second active layer 011 farther from the substrate 10. A second subgate insulating layer 015, a third subgate insulating layer 016, and a first gate layer 017 are disposed in order from the side of the first active layer 012 farther from the substrate 10. A fourth subgate insulating layer 018 is disposed on the side of the second active layer 011 closer to the substrate 10. The composition materials of the first subgate insulating layer 013 and the third subgate insulating layer 016 are the same, and the composition materials of the second subgate insulating layer 015 and the fourth subgate insulating layer 018 are the same.

[0043] At this time, based on the fact that the gate layer 202 includes a separately disposed second gate layer 014 and a first gate layer 017, the first electrode plate 301, the second gate layer 014, and the first gate layer 017 may be disposed in the same layer, and the composition materials of the three are all the same.

[0044] Here, the composition materials of the second active layer 011 and the first active layer 012 may be different so that the second thin film transistor 02 and the first thin film transistor 01 are used to form different circuits respectively. For example, both may be used to form a gate driving circuit and a pixel driving circuit respectively. At this time, since the second thin film transistor 02 is arranged in the non-display area A2 and it is considered that light does not irradiate the second active layer 011 of the second thin film transistor 02, it may not be necessary to arrange a light shielding layer 40 below the second active layer 011. Therefore, "the second active layer 011 and the first active layer 012 are arranged in different layers" in this embodiment can be understood as separately manufacturing the second active layer 011 and the first active layer 012 with different materials. For example, here, the first active layer 012 can be formed first in the corresponding area, and then the second active layer 011 can be formed in another area. In order to avoid contact between the two materials, the first active layer 012 can be formed first. Before forming the second active layer 011, the first insulating material (that is, the composition material for forming the above-mentioned second sub-gate insulating layer 015, the fourth sub-gate insulating layer 018, and the first pad height portion 3041) can be formed on the entire surface first. Here, the second gate layer 014 and the first gate layer 017 can also be formed simultaneously using the same material. As can be understood by combining the above, the three of the first electrode plate 301, the second gate layer 014, and the first gate layer 017 can be formed simultaneously, that is, arranged in the same layer. Similarly, in order to avoid contact between the material of the second gate layer 014 and the material of the second active layer 011, before forming the second gate layer 014, the second insulating material (that is, the above-mentioned first sub-gate insulating layer 013, the third sub-gate insulating layer 016, and the composition material for forming the second pad portion 3042 arranged on the first pad portion 3041) can be formed on the entire surface first.

[0045] Similarly, when the gate insulating layer 203 is formed by patterning and disposed opposite to the first gate layer 017, generally, the entire gate insulating film for the later manufacturing of the gate insulating layer 203 is first formed, and then, the patterned first gate layer 017 (including the second gate layer 014 and the first gate layer 017) and the first electrode plate 301 are simultaneously formed on the gate insulating film. Thereafter, the gate insulating film is etched, and by shielding the first gate layer 017 and the first electrode plate 301, it is avoided that the portions of the gate insulating layer corresponding to both are etched and remain. The gate insulating layer 203 corresponding to the lower part of the first gate layer 017 (including the first sub-gate insulating layer 013 corresponding to the lower part of the second gate layer 014 and the third sub-gate insulating layer 016 corresponding to the lower part of the first gate layer 017), and the second pad portion 3042 corresponding to the lower part of the first electrode plate 301 are formed. The thickness of this second pad portion 3042 is close to the thickness of the third sub-gate insulating layer 016.

[0046] Note that in FIG. 2, only the case where the second thin film transistor 02 and the first thin film transistor 01 have a top gate structure is described as an example, but at least one of them may have a bottom gate structure or a double gate structure. Here, the bottom gate structure and the double gate structure can refer to the content described later.

[0047] In one embodiment, taking the top gate structure as an example, the second electrode plate is disposed on the side of the first electrode plate 302 far from the substrate. As shown in FIGS. 1 and 2, the second electrode plate 302 is disposed between the first electrode plate 301 and the first source-drain layer 204, or, as shown in FIG. 3, the second electrode plate 302 and the first source-drain layer 204 are disposed in the same layer.

[0048] Specifically, as shown in FIGS. 1 to 3, the array substrate 200 may further include an interlayer insulating layer 205 disposed between the first gate layer 017 and the first source-drain layer 204. The interlayer insulating layer 205 is used to insulate the first gate layer 017 and the first source-drain layer 204, and can extend over the entire film layer to achieve planarization. The composition material of the interlayer insulating layer 205 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, and titanium oxide, but is not limited thereto.

[0049] As can be understood, as shown in FIGS. 1 and 2, the second electrode plate 302 in this embodiment may be disposed between the first electrode plate 301 and the first source-drain layer 204. For example, after forming the first electrode plate 301 and the first gate layer 017 in the first thin film transistor 01, and before forming the first source-drain layer 204, the second electrode plate 302 can be formed alone (its composition material may include metals and alloys, and must also be disposed under the interlayer insulating layer 205). As a result, the distance between the first electrode plate 301 and the second electrode plate 302 becomes smaller, and the capacitance value of the first capacitor 30 can be increased. At this time, the second sub-dielectric layer 3032 and the first sub-dielectric layer 3031 may be sequentially disposed on the first electrode plate 301.

[0050] As can be understood, as shown in FIG. 3, the second electrode plate 302 and the first source-drain layer 204 in this embodiment may be disposed in the same layer to save the number of process steps. At the same time, since the second electrode plate 302 is disposed on the interlayer insulating layer 205, at this time, the first sub-dielectric layer 3031 disposed on the second sub-dielectric layer 3032 may be multiplexed from the interlayer insulating layer 205. The material and structural characteristics of the interlayer insulating layer 205 at this time need to satisfy both the material and structural characteristics of both the interlayer insulating layer 205 and the first sub-dielectric layer 3031. Specifically, reference can be made to the above description.

[0051] Specifically, based on taking the top gate structure as an example, as shown in FIG. 4, when the second electrode plate 302 is disposed on the side far from the substrate 10 of the first electrode plate 301 (here, the specific position of the film layer where the second electrode plate 302 is located is not limited), the first dielectric layer 303 is also disposed on the side far from the substrate 10 of the first active layer 012. Further, as shown in FIG. 4, based on the presence of the gate insulating layer 203, the first dielectric layer 303 (i.e., the first pad portion 3041 corresponding to the lower part of the first electrode plate 301 described above) and the gate insulating layer 203 are disposed in the same layer. Further, the first dielectric layer 303 is formed to extend at least to the position disposed on the side close to the substrate 10 of the first electrode plate 301 from the gate insulating layer 203, that is, the first pad portion 3041 and the gate insulating layer 203 may be integrally formed.

[0052] Here, the gate insulating layer 203 can also extend from above the first active layer 012 to the position disposed on the side close to the substrate 10 of the first electrode plate 301 in order to form the first dielectric layer 303. Therefore, it can be understood that manufacturing the first dielectric layer 303 alone can be avoided and the number of process paths can be saved. Here, the second electrode plate 302 may be disposed in the same layer as the light shielding layer 40, that is, the composition materials of both are the same and can be manufactured simultaneously, and further the number of process paths can be saved. Further, the second electrode plate 302 is formed to extend to the position disposed opposite to the first electrode plate 301 from the light shielding layer 40. Since the buffer layer 50 disposed on the light shielding layer 40 is disposed between the first electrode plate 301 and the second electrode plate 302, it may be multiplexed as the first dielectric layer 303.

[0053] Here, as shown in FIG. 4, the first dielectric layer 303 in this embodiment may be disposed at least between the first active layer 012 and the buffer layer 50, or between the buffer layer 50 and the light-shielding layer. Further, since the buffer layer 50 and the gate insulating layer 203 are in contact with the lower surface and the upper surface of the first active layer 012 respectively, it is considered that the protective effects of both on the first active layer 012 are equivalent. Therefore, regardless of which of the two is the first sub-dielectric layer 3031 and which is the second sub-dielectric layer 3032, the selection of the materials of the two must make the characteristics of the corresponding first sub-dielectric layer 3031 or second sub-dielectric layer 3032 compatible. Considering the operating characteristics of the gate insulating layer 203 and the buffer layer 50 themselves, the buffer layer 50 can be multiplexed as the second sub-dielectric layer 3032, and the gate insulating layer 203 can be multiplexed as the first sub-dielectric layer 3031.

[0054] In one embodiment, as shown in FIGS. 5 and 6, the first thin-film transistor 01 may also have a bottom-gate structure, that is, the first gate layer 017 is disposed on the side of the first active layer 012 close to the substrate 10, the first electrode plate 301 and the first gate layer 017 are disposed in the same layer, the composition material of the first electrode plate 301 and the composition material of the first gate layer 017 are the same, and the second electrode plate 302 is disposed on the side of the first electrode plate 301 far from the substrate 10.

[0055] Furthermore, for the bottom-gate structure, the orthographic projection of the first active layer 012 on the substrate 10 can be set to be large so that it is disposed within the orthographic projection of the first gate layer 017 on the substrate 10 in FIGS. 5 and 6, and the above light-shielding layer can be omitted. Similarly, a gate insulating layer 203 can be disposed between the first gate layer 017 and the first active layer 012.

[0056] Based on the fact that the first electrode plate 301 and the first gate layer 017 are arranged in the same layer, the second electrode plate 302 can be arranged in the film layer above the first gate layer 017. For example, as shown in FIG. 5, the second electrode plate 302 may be arranged on the first source-drain layer 204. Based on this, in order to achieve both the formation of the first capacitor 30 and the insulation between the first source-drain layer 204 and the second electrode plate 302, the first dielectric layer 303 can be arranged between the first source-drain layer 204 and the second electrode plate 302. Furthermore, the gate insulating layer 203 can also achieve both the formation of the first dielectric layer 303 and the insulation between the first gate layer 017 and the first active layer 012. Here, only an example is shown where the first sub-dielectric layer 3031 is arranged between the first source-drain layer 204 and the second electrode plate 302, and the gate insulating layer 203 is multiplexed as the second sub-dielectric layer 3032, but it is not limited thereto (because the first sub-dielectric layer 3031 and the second sub-dielectric layer 3032 are released from the upper surface and the lower surface of the first active layer 012 respectively). Also, for example, as shown in FIG. 6, the second electrode plate 302 may be arranged in the same layer as the first source-drain layer 204. Based on this, the gate insulating layer 203 may be arranged to include the first sub-dielectric layer 3031 and the second sub-dielectric layer 3032, or may be arranged to bring the second sub-dielectric layer 3032 closer to the first active layer 012.

[0057] In one embodiment, as shown in FIGS. 7 and 8, the first thin film transistor 01 is a double-gate thin film transistor, and the double-gate thin film transistor includes a first sub-gate layer 2021 arranged on the side of the first active layer 012 far from the substrate 10, and a second sub-gate layer 2022 arranged on the side of the first active layer 012 close to the substrate 10.

[0058] Here, the double-gate thin-film transistor has two gates, namely, a control gate and a feedback gate (i.e., a first sub-gate layer 2021 and a second sub-gate layer 2022). By applying a constant voltage between the control gate (one of the first sub-gate layer 2021 and the second sub-gate layer 2022) and the source, the flow of current between the source and the drain in the double-gate thin-film transistor can be controlled. On the other hand, by applying a constant voltage between the feedback gate (the other of the first sub-gate layer 2021 and the second sub-gate layer 2022) and the source, the flow of current between the above-mentioned control gate and the above-mentioned source can be controlled, thereby achieving the control of the entire double-gate thin-film transistor. The double-gate thin-film transistor has advantages such as low power consumption and high speed.

[0059] In one embodiment, as shown in FIG. 7, the first electrode plate 301 and the first sub-gate layer 2021 are arranged in the same layer, the first electrode plate 301 and the first sub-gate layer 2021 are made of the same composition material, and the second electrode plate 302 is arranged on the side of the first electrode plate 301 far from the substrate 10 or on the side close to the substrate 10 (specifically, reference can be made to the description of the related embodiments in FIGS. 1 to 5 above. In FIG. 7, only the case where the second electrode plate 302 is arranged on the side of the first electrode plate 301 far from the substrate 10 is shown), or, as shown in FIG. 8, the first electrode plate 301 and the second sub-gate layer 2022 are arranged in the same layer, the first electrode plate 301 and the second sub-gate layer 2022 are made of the same composition material, and the second electrode plate 302 is arranged on the side of the first electrode plate 301 far from the substrate 10 or on the side close to the substrate 10 (specifically, reference can be made to the description of the related embodiments in FIGS. 1 to 5 above. In FIG. 8, only the case where the second electrode plate 302 is arranged on the side of the first electrode plate 301 far from the substrate 10 is shown).

[0060] Here, even if the first electrode plate 301 is disposed in the same layer as the first subgate layer 2021 or the second subgate layer 2022, when the second electrode plate 302 is disposed closer to the substrate 10 than the first electrode plate 301, it is considered that the second electrode plate 302 is disposed between the substrate 10 and the first electrode plate 301, and the first dielectric layer 303 is disposed between the first electrode plate 301 and the second electrode plate 302.

[0061] As shown in FIGS. 1 to 9, in addition to the array substrate 200 described in any one of the above, the display panel 100 provided by the present invention includes a metal adapter layer 60 disposed on the side of the first thin film transistor 01 (the first source-drain layer 204 in it) far from the substrate 10, and a pixel layer (including an anode layer 70) disposed on the side of the metal adapter layer 60 far from the substrate 10, and the metal adapter layer 60 electrically connects the first source-drain layer 204 and the pixel layer (the anode layer 70 in it).

[0062] Of course, in other selectable embodiments, as shown in FIG. 9, both the first electrode plate 301 and the second electrode plate 302 may be disposed on the first gate layer 017. For example, the first electrode plate 301 may be disposed in the same layer as the first source-drain layer 2041 (included in the source-drain layer 204), and the second electrode plate 302 may be disposed in the same layer as the metal adapter layer 60. Correspondingly, the second flat layer 802 disposed between the first source-drain layer 204 and the metal adapter layer 60 may be disposed to include a first sub-dielectric layer 3031 and a second sub-dielectric layer 3032, and the second sub-dielectric layer 3032 may be disposed closer to the first active layer 012.

[0063] Specifically, as shown in FIGS. 1 to 9, the display panel 100 may further include a first planarization layer 801 that covers and is planarized on the metal adapter layer 60. The thickness of the first planarization layer 801 is usually large and is used to provide a flat surface for the deposition of the anode layer 70. The composition material of the first planarization layer 801 may include at least one of inorganic insulating substances, polyacrylate resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, unsaturated polyester resins, polyphenylene ether resins, polyphenylene sulfide resins, organic insulating substances such as benzocyclobutene, and photosensitive substances, but is not limited thereto. Further, the display panel 100 may further include a pixel definition layer 90 disposed on the first planarization layer 801. The pixel definition layer 90 can form a plurality of openings, and the corresponding anode layer 70 can be disposed in each opening. Further, a second planarization layer 802 may be disposed between the metal adapter layer 60 and the first source-drain layer 204. The thickness of the second planarization layer 802 is also usually large and is used to provide a flat surface for the deposition of the metal adapter layer 60. For the composition material of the second planarization layer 802, reference can be made to the description of the composition material of the first planarization layer 801 described above.

[0064] Furthermore, by combining the embodiment shown in FIG. 3 and the embodiment shown in FIG. 5, based on the fact that the first electrode plate 301 and the first source-drain layer 204 (including those in the source-drain layer 204) in this embodiment are arranged in the same layer, the second electrode plate 302 can be changed to be arranged in the same layer as the metal adapter layer 60. That is, by manufacturing the second electrode plate 302 and the metal adapter layer 60 simultaneously on the second flat layer 802, the number of process paths can be saved. As described above, the second flat layer 802 may include the first sub-dielectric layer 3031 and the second sub-dielectric layer 3032.

[0065] Of course, compared with the embodiment shown in FIG. 9, the first electrode plate 301 can be changed to be arranged in the same layer as the anode layer 70. To save the number of process paths, the first electrode plate 301 and the anode layer 70 arranged in the same layer can be manufactured simultaneously. At this time, it can be understood that the first flat layer 801 may be arranged to include the first sub-dielectric layer 3031 and the second sub-dielectric layer 3032 described above.

[0066] In the above description, only the possibilities of various arrangement forms of the first capacitor 30 are described. However, in reality, based on the above first capacitor 30, a second capacitor (not shown) arranged on the substrate 10 may be arranged. The second capacitor includes a third electrode plate and a fourth electrode plate that are arranged in different layers and face each other, and a second dielectric layer arranged between the third electrode plate and the fourth electrode plate. Based on the above-described specific film layers of the light-shielding layer 40, the metal adapter layer 60, and the first thin-film transistor 01, different from the arrangement form of the above-described first capacitor 30, the second dielectric layer in the second capacitor may not be like the arrangement of the first dielectric layer, but may be composed only of the film layer between the third electrode plate and the fourth electrode plate. For example, the third electrode plate may be arranged in the same layer as one of the light-shielding layer 40, the metal adapter layer 60, the gate layer 202, and the source-drain layer 204, and the fourth electrode plate may be arranged in the same layer as the other of the light-shielding layer 40, the metal adapter layer 60, the gate layer 202, and the source-drain layer 204, or the fourth electrode plate may be arranged in the same layer as the film layer arranged between the source-drain layer 204 and the gate layer 202.

[0067] To better explain the film layer structure of the above display panel, the present invention further provides a method for manufacturing a display panel, which includes the following steps and combinations between the following steps, but is not limited thereto. Hereinafter, a schematic diagram of the scenes shown in FIGS. 10(a), 10(b), and 10(c) and a schematic diagram of the scenes shown in FIGS. 11(a), 11(b), and 11(c) are combined for explanation, and are respectively used to form a display panel as shown in FIGS. 1 and 2.

[0068] S01: Provide a substrate. Specifically, as shown in FIGS. 10(a) to 10(c) and FIGS. 11(a) to 11(c), for the specific structure and composition materials of the substrate 10, reference can be made to the above-related descriptions.

[0069] S02: Clean the substrate, deposit a metal material with a thickness of 1000 angstroms to 10000 angstroms, and pattern it to form a light-shielding layer. Specifically, as shown in FIGS. 10(a) to 10(c) and FIGS. 11(a) to 11(c), the composition material of the light-shielding layer 40 can refer to the above-related descriptions. Furthermore, it may contain at least one of Mo, Cr, Al, Cu, and Ti, but is not limited thereto.

[0070] S03: Deposit a single-layer or multi-layer inorganic material on the light-shielding layer to form a buffer layer. Specifically, as shown in FIGS. 10(a) to 10(c) and FIGS. 11(a) to 11(c), the composition material of the buffer layer 50 can refer to the above-related descriptions. Furthermore, the buffer layer 50 may be a single-layer silicon nitride (SiNx) film layer, a single-layer silicon oxide (SiOx) film layer, or a stacked silicon nitride (SiNx) film layer and silicon oxide (SiOx) film layer. The thickness of the buffer layer 50 is 1000 angstroms to 5000 angstroms.

[0071] S04: Deposit a metal oxide on the buffer layer and pattern it to form a first active layer. Specifically, as shown in FIGS. 10(a) to 10(c) and FIGS. 11(a) to 11(c), the composition material of the first active layer 012 can refer to the above-related descriptions. Furthermore, the metal oxide here may contain at least one of IGTO, ITZO, and IGZTO, but is not limited thereto. The thickness of the first active layer 012 may be 100 angstroms to 1000 angstroms. In particular, as shown in FIG. 5, at this time, it is considered that the first active layer 012 in the first thin-film transistor 01 is formed.

[0072] S05: Deposit an inorganic material on the first active layer to form a gate insulating layer. Here, as shown in FIGS. 10(a) to 10(c) and FIGS. 11(a) to 11(c), the film layer of the inorganic material for forming the gate insulating layer 203 may include, but is not limited to, a single-layer silicon nitride (SiNx) film layer, a single-layer silicon oxide (SiOx) film layer, or a stacked silicon nitride (SiNx) film layer and silicon oxide (SiOx) film layer. As shown in FIGS. 10(a) to 10(c), the thickness of the gate insulating layer 203 may be 1000 angstroms to 3000 angstroms. As shown in FIGS. 11(a) to 11(c), at this time, the gate insulating layer 203 (the second sub-gate insulating layer 015) in the first thin film transistor 01 is formed, and its thickness may be 500 angstroms to 2000 angstroms. At the same time, it is considered that the fourth sub-gate insulating layer 018 as described above is also formed. Furthermore, for FIGS. 11(a) to 11(c), after step S05, it further includes forming the second active layer 011 in the second thin film transistor 02. The thickness and composition material of the second active layer 011 can refer to the description regarding the above-mentioned first active layer 012. Further, after forming the second active layer 011, it further includes forming the first sub-gate insulating layer 013 in the second thin film transistor 02, and its thickness may be 1000 angstroms to 3000 angstroms. At the same time, the third sub-gate insulating layer 016 as described above is also formed.

[0073] S06: Deposit a layer of a metal material for forming a gate layer on the film layer of the inorganic material for forming the gate insulating layer. Specifically, the composition material of the gate layer 202 (including the first gate layer 017 in FIGS. 10(a) to 10(c) and FIGS. 11(a) to 11(c), and the second gate layer 014 in FIGS. 11(a) to 11(c)) can refer to the above-related description. Furthermore, the composition material of the gate layer 202 may include, but is not limited to, at least one of Mo, Al, Cu, and Ti. The thickness of the gate layer 202 may be 2000 angstroms to 8000 angstroms.

[0074] S07: By the yellow light process, in order to form the gate layer, first etch the metal material for forming the gate layer, and then, with the metal pattern of the gate layer being self-aligned, etch the inorganic material for forming the gate insulating layer in order to form the gate insulating layer 203. As shown in FIGS. 10(a) to 10(c) and FIGS. 11(a) to 11(c), it can be understood that the gate insulating layer 203 exists only below the metal pattern having the gate layer 202, and the inorganic materials in the remaining regions are all removed by etching. Furthermore, in order to increase the conductivity of the exposed oxide region in the active layer 201, it is possible to select to perform plasma treatment over the entire surface. As described above, the first electrode plate 301 and the gate layer 202 can be formed by the same patterning. Similarly, as shown in FIGS. 10(a) to 10(c), also before that, a corresponding first pad portion 3041 disposed in the same layer as the gate insulating layer 203 is formed below the first electrode plate 301. In particular, as shown in FIGS. 11(a) to 11(c), this step can simultaneously form the second gate layer 014 in the second thin film transistor 02 and the first gate layer 017 in the first thin film transistor 01. Similarly, as shown in FIG. 5, also before that, a corresponding first pad portion 3041 disposed in the same layer as the fourth sub-gate insulating layer 018 and the second sub-gate insulating layer 015 is formed below the first electrode plate 301. Furthermore, a corresponding second pad portion 3042 disposed in the same layer as the first sub-gate insulating layer 013 and the third sub-gate insulating layer 016 is formed.

[0075] S08: Deposit an insulating material to form a second sub-dielectric layer. Here, as shown in FIGS. 10(a) to 10(c) and FIGS. 11(a) to 11(c), the composition material of the second sub-dielectric layer 3032 may include, but is not limited to, silicon oxide. The thickness of the second sub-dielectric layer 3032 may be from 500 angstroms to 2000 angstroms.

[0076] S09: Deposit an insulating material on the second sub-dielectric layer to form the first sub-dielectric layer. Here, as shown in FIGS. 10(a) to 10(c) and FIGS. 11(a) to 11(c), the dielectric constant of the first sub-dielectric layer 3031 may be greater than 4, and the composition material of the first sub-dielectric layer 3031 can refer to the above related descriptions. As shown in FIG. 4, the thickness of the first sub-dielectric layer 3031 may be 800 angstroms to 3000 angstroms. As shown in FIG. 5, the thickness of the first sub-dielectric layer 3031 may be 500 angstroms to 3000 angstroms.

[0077] S10: Deposit a layer of metal material on the first sub-dielectric layer and pattern it to form the second electrode plate. Here, as shown in FIGS. 10(a) to 10(c) and FIGS. 11(a) to 11(c), the composition material of the second electrode plate 302 can refer to the above related descriptions. For example, it may contain at least one of Mo, Al, Cu, and Ti, but is not limited thereto. The thickness of the second electrode plate 302 may be 2000 angstroms to 8000 angstroms.

[0078] S11: Deposit an insulating material on the second electrode plate and the first sub-dielectric layer to form an interlayer insulating layer, and form a first through hole penetrating at least the interlayer insulating layer. Here, as shown in FIGS. 10(a) to 10(c) and FIGS. 11(a) to 11(c), the interlayer insulating layer 205 may include a single-layer silicon nitride (SiNx) film layer, a single-layer silicon oxide (SiOx) film layer, or a stacked silicon nitride (SiNx) film layer and silicon oxide (SiOx) film layer, but is not limited thereto.

[0079] S12: Deposit a metal material on the interlayer insulating layer and in the first through hole and pattern it to form a source-drain layer. Here, the composition material of the source-drain layer 204 (including the first source-drain layer 2041 shown in FIGS. 10(a) to 10(c) and FIGS. 11(a) to 11(c), and the second source-drain layer 2042 shown in FIGS. 11(a) to 11(c)) can refer to the above related descriptions. For example, it may include at least one of Mo, Al, Cu, and Ti, but is not limited thereto. The thickness of the source-drain layer 204 may be 2000 angstroms to 8000 angstroms, and the source-drain layer 204 can be electrically connected to the active layer 201 and the light-shielding layer 40 through the metal material in the first through-hole.

[0080] S13: Deposit an insulating material on the source-drain layer and the interlayer insulating layer to form a passivation layer. Here, the passivation layer may include a single-layer silicon nitride (SiNx) film layer, a single-layer silicon oxide (SiOx) film layer, or a stacked silicon nitride (SiNx) film layer and silicon oxide (SiOx) film layer, but is not limited thereto. The thickness of the passivation layer may be 1000 angstroms to 5000 angstroms. Further, as shown in FIGS. 10(a) to 10(c) and FIGS. 11(a) to 11(c), a second planarization layer 802 can be formed on the passivation layer, and the composition material of the second planarization layer 802 can refer to the above related descriptions. Further, a second through-hole can be formed in the second planarization layer 802.

[0081] S14: Form an anode layer on the passivation layer. Here, as shown in FIGS. 10(a) to 10(c) and FIGS. 11(a) to 11(c), the composition material of the anode layer 70 can refer to the above related descriptions. As described above, before forming the anode layer 70, a second planarization layer 802, a metal adapter layer 60, a first planarization layer 801, and a pixel definition layer 90 can be formed on the passivation layer.

[0082] Specifically, the above display panel 100 is used as a liquid crystal display panel, a Mini LED (sub - millimeter light - emitting diode), a Micro LED (micro light - emitting diode display), or an organic light - emitting semiconductor.

[0083] In the array substrate and the display panel provided by the embodiments of the present invention, there is a substrate on which a pixel region and a capacitor region are defined, and a first thin - film transistor disposed in the pixel region on the substrate, the first thin - film transistor including a first active layer, a first gate layer disposed on a side of the first active layer close to the substrate or far from the substrate, and a first source - drain layer disposed on a side of the first active layer far from the substrate and electrically connected to the first active layer. a first capacitor including a first electrode plate and a second electrode plate disposed in different layers and facing each other, (wherein the first electrode plate and the second electrode plate are disposed in the capacitor region), the first capacitor further including a first dielectric layer disposed between the first electrode plate and the second electrode plate, the first dielectric layer including a first sub - dielectric layer and a second sub - dielectric layer disposed on a side of the first sub - dielectric layer close to the first active layer (wherein the second sub - dielectric layer is disposed in the pixel region and the capacitor region).

[0084] The structures of the array substrate and the display panel provided by the embodiments of the present invention are described in detail above. Specific examples are applied in this specification to explain the principles and embodiments of the present invention. The description of the above examples is only used to help understand the technical solutions and their core ideas of the present invention. It is still possible to modify the technical solutions described in the foregoing examples or replace some of their technical features with equivalent ones. These modifications or replacements do not exclude the corresponding technical solutions from the scope of the technical solutions in each embodiment of the present invention.

Claims

1. An array substrate, a substrate on which a pixel region and a capacitor region are defined, a first thin film transistor disposed in the pixel region on the substrate, including a first active layer, a first gate layer disposed on a side of the first active layer closer to the substrate or farther from the substrate, and a first source-drain layer disposed on a side of the first active layer farther from the substrate and electrically connected to the first active layer, a first capacitor including a first electrode plate and a second electrode plate disposed in different layers and facing each other, the first electrode plate and the second electrode plate being disposed in the capacitor region, the first capacitor further including a first dielectric layer disposed between the first electrode plate and the second electrode plate, the first dielectric layer including a first sub-dielectric layer and a second sub-dielectric layer disposed on a side of the first sub-dielectric layer closer to the first active layer, the second sub-dielectric layer being disposed in the pixel region and the capacitor region, wherein a dielectric constant of the first sub-dielectric layer is greater than a dielectric constant of the second sub-dielectric layer, and a positive projection of the first active layer on the substrate is disposed within a positive projection of the second sub-dielectric layer on the substrate, characterized by the above.

2. wherein a composition material of the first sub-dielectric layer includes at least one of alumina and zirconia, and a composition material of the second sub-dielectric layer includes silicon oxide, characterized by the array substrate according to claim 1.

3. wherein the first gate layer is disposed on a side of the first active layer farther from the substrate, The first electrode plate and the first gate layer are arranged in the same layer, the composition material of the first electrode plate and the composition material of the first gate layer are the same, and the second electrode plate is arranged on the side of the first electrode plate far from the substrate or on the side close to the substrate. The array substrate according to claim 1, characterized in that.

4. The second electrode plate is arranged on the side of the first electrode plate far from the substrate, the second electrode plate is arranged between the first electrode plate and the first source-drain layer, or the second electrode plate and the first source-drain layer are arranged in the same layer. The array substrate according to claim 3, characterized in that.

5. The second electrode plate is arranged on the side of the first electrode plate close to the substrate, the first thin film transistor further includes a gate insulating layer arranged between the first active layer and the first gate layer, the gate insulating layer is arranged opposite to the first gate layer. The first dielectric layer and the gate insulating layer are arranged in the same layer. The array substrate according to claim 3, characterized in that.

6. The array substrate further includes a light-shielding layer arranged on the side of the first active layer close to the substrate, the second electrode plate is arranged on the side of the first electrode plate close to the substrate. The second electrode plate and the light-shielding layer are arranged in the same layer. The array substrate according to claim 5, characterized in that.

7. The first gate layer is arranged on the side of the first active layer close to the substrate, the first electrode plate and the first gate layer are arranged in the same layer, the composition material of the first electrode plate and the composition material of the first gate layer are the same, and the second electrode plate is arranged on the side of the first electrode plate far from the substrate. The array substrate according to claim 1, characterized in that. Claim 8 The first thin film transistor is a double gate thin film transistor, and the double gate thin film transistor includes a first sub gate layer disposed on the side of the first active layer far from the substrate and a second sub gate layer disposed on the side of the first active layer close to the substrate. The array substrate according to claim 1, characterized in that. Claim 9 The first electrode plate and the first sub gate layer are disposed in the same layer, the first electrode plate and the first sub gate layer are made of the same composition material, and the second electrode plate is disposed on the side of the first electrode plate far from the substrate or on the side of the first electrode plate close to the substrate. Or, the first electrode plate and the second sub gate layer are disposed in the same layer, the first electrode plate and the second sub gate layer are made of the same composition material, and the second electrode plate is disposed on the side of the first electrode plate far from the substrate or on the side of the first electrode plate close to the substrate. The array substrate according to claim 8, characterized in that. Claim 10 A non-display area is further defined on the substrate, and the array substrate further includes a second thin film transistor. The second thin film transistor is disposed in the non-display area, there is a gap between the orthographic projection of the second thin film transistor on the substrate and the orthographic projection of the first thin film transistor on the substrate, the second thin film transistor includes a second active layer, and the first active layer is disposed on the side of the second active layer close to the substrate. A first sub gate insulating layer and a second gate layer are sequentially disposed from the side of the second active layer far from the substrate, a second sub gate insulating layer, a third sub gate insulating layer and a first gate layer are sequentially disposed from the side of the first active layer far from the substrate, and a fourth sub gate insulating layer is disposed on the side of the second active layer close to the substrate. The composition material of the first sub - gate insulating layer is the same as that of the third sub - gate insulating layer, and the composition material of the second sub - gate insulating layer is the same as that of the fourth sub - gate insulating layer. The array substrate according to any one of claims 1 to 9, characterized in that.

11. The second sub - dielectric layer is further disposed in the non - display region, and the orthographic projection of the second active layer on the substrate is disposed within the orthographic projection of the second sub - dielectric layer on the substrate. The array substrate according to claim 10, characterized in that.

12. A display panel, The array substrate according to any one of claims 1 to 9, and A metal adapter layer disposed on the side of the first thin - film transistor far from the substrate, and A pixel layer disposed on the side of the metal adapter layer far from the substrate, and The metal adapter layer electrically connects the first source - drain layer and the pixel layer. The display panel, characterized in that.

Images