Semiconductor element

Abstract

To provide a semiconductor element having a stable electric characteristic.SOLUTION: A semiconductor element according to the present invention includes a channel layer, a barrier layer disposed on the channel layer and containing a substance with an energy band gap different from that of the channel layer, a gate electrode disposed on the barrier layer, a gate semiconductor layer disposed between the barrier layer and the gate electrode, and a source electrode and a drain electrode disposed on both sides of the gate electrode, penetrating at least a part of the barrier layer and the channel layer, and covering a side surface of the barrier layer and a side surface of the channel layer. The side surface of the barrier layer includes a first inclined surface that is inclined from an upper surface of the channel layer and doped with an impurity. The side surface of the channel layer includes a second inclined surface that is inclined from the upper surface of the channel layer. A first angle between a lower surface of the barrier layer and the first inclined surface of the barrier layer is smaller than or equal to a second angle between the upper surface of the channel layer and the second inclined surface of the channel layer.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having stable electrical characteristics.

Background Art

[0002] In modern society, semiconductor devices are closely related to daily life. In particular, in various fields such as transportation fields such as electric vehicles, railways, and trams, renewable energy systems such as solar power generation and wind power generation, and mobile devices, the importance of power semiconductor devices is gradually increasing. A power semiconductor device is a semiconductor device used to handle high voltages and high currents, and performs functions such as power conversion and control in a large power system or a high-power electronic device. A power semiconductor device has the ability to process high power and durability, can handle a large amount of current, and can withstand high voltages.

[0003] For example, a power semiconductor device can handle voltages from several hundred volts to several thousand volts and currents from several tens of amperes to several thousand amperes. A power semiconductor device can reduce (and / or minimize) power loss and improve the efficiency of electrical energy. In addition, a power semiconductor device can be driven more stably even in an environment such as high temperature. Such power semiconductor devices can be classified by material. For example, there are SiC power semiconductor devices and GaN power semiconductor devices. By manufacturing a power semiconductor device using SiC or GaN instead of an existing silicon wafer (Si wafer), the disadvantages of silicon having unstable characteristics at high temperatures can be compensated for.

[0004] SiC power semiconductor devices are strong against high temperatures, have little power loss, and are suitable for electric vehicles, renewable energy systems, etc. Although GaN power semiconductor devices require high costs, they are efficient in terms of speed and are suitable for high-speed charging of mobile devices, etc. It has been an issue to obtain stable electrical characteristics of these power semiconductor devices.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The present invention has been made in view of the problems in the above-described conventional semiconductor devices, and an object of the present invention is to provide a semiconductor device having stable electrical characteristics.

Means for Solving the Problems

[0006] A semiconductor device according to the present invention made to achieve the above object includes a channel layer, a barrier layer disposed on the channel layer and including a substance having an energy band gap different from that of the channel layer, a gate electrode disposed on the barrier layer, a gate semiconductor layer disposed between the barrier layer and the gate electrode, and source and drain electrodes disposed on both sides of the gate electrode and penetrating at least a part of the barrier layer and the channel layer to cover side surfaces of the barrier layer and the channel layer. A side surface of the barrier layer is inclined from an upper surface of the channel layer and includes a first inclined surface doped with impurities. A side surface of the channel layer includes a second inclined surface inclined from an upper surface of the channel layer. A first angle between a lower surface of the barrier layer and the first inclined surface of the barrier layer is smaller than or equal to a second angle between an upper surface of the channel layer and the second inclined surface of the channel layer.

[0007] In addition, a semiconductor device according to the present invention made to achieve the above object includes a channel layer, a barrier layer disposed on the channel layer and containing a substance having an energy band gap different from that of the channel layer, a gate electrode disposed on the barrier layer, a gate semiconductor layer disposed between the barrier layer and the gate electrode, and source and drain electrodes disposed on both sides of the gate electrode, penetrating at least a part of the barrier layer and the channel layer, and covering side surfaces of the barrier layer and the channel layer. A side surface of the barrier layer is inclined from an upper surface of the channel layer and includes a first inclined surface doped with impurities, and a first angle between a lower surface of the barrier layer and the first inclined surface of the barrier layer is greater than 0 degrees and less than or equal to 70 degrees.

[0008] In addition, a semiconductor device according to the present invention made to achieve the above object includes a substrate, a channel layer containing GaN on the substrate, a barrier layer containing AlGaN disposed on the channel layer, a gate electrode extending in a first direction and disposed on the barrier layer and containing a metallic substance, a gate semiconductor layer extending in the first direction and disposed between the barrier layer and the gate electrode and containing GaN doped with a p-type impurity, and source and drain electrodes disposed on both sides of the gate electrode at a distance in a second direction intersecting the first direction, penetrating at least a part of the barrier layer and the channel layer, and covering side surfaces of the barrier layer and the channel layer. Side surfaces of the barrier layer facing each other in the first direction are inclined from an upper surface of the channel layer and include a first inclined surface doped with impurities, side surfaces of the channel layer facing each other in the first direction include a second inclined surface inclined from an upper surface of the channel layer, and a first angle between a lower surface of the barrier layer and the first inclined surface of the barrier layer is smaller than or the same as a second angle between an upper surface of the channel layer and the second inclined surface of the channel layer.

Advantages of the Invention

[0009] According to the semiconductor device of the present invention, since the barrier layer includes a first inclined surface and the channel layer includes a second inclined surface, source and drain electrodes can be easily formed on the side surfaces of the barrier layer and the channel layer, the step coverage of forming the source and drain electrodes can be improved, and thereby the source and drain electrodes can have stable electrical characteristics.

Brief Description of the Drawings

[0010]

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Embodiments for Carrying Out the Invention

[0011] Next, specific examples of embodiments for carrying out the semiconductor device according to the present invention will be described with reference to the drawings.

[0012] The present invention can be realized in various different forms and is not limited to the embodiments described herein. In order to clearly describe the present invention, parts that are unnecessary for the description are omitted, and the same reference numerals are assigned to the same or similar components throughout the specification. In addition, the sizes and thicknesses of the respective components shown in the drawings are arbitrarily shown for convenience of explanation, and thus the present invention is not necessarily limited to those shown in the drawings. In the drawings, the thicknesses are enlarged to clearly show various layers and regions. And, in the drawings, for convenience of explanation, the thicknesses of some layers and regions are exaggerated.

[0013] Also, when a part such as a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the case where it is directly on the other part, but also the case where there are other parts in between. Conversely, when a part is said to be "directly on" another part, it means that there are no other parts in between. Furthermore, being "on" a reference part means being located above or below the reference part, and does not necessarily mean being located "above" in the opposite direction of gravity. Also, throughout the specification, when a part "includes" a certain component, this means that other components can be further included, rather than excluding other components, unless otherwise specified. Furthermore, throughout the specification, when it is "on a plane", this means when the target part is viewed from above, and when it is "in a cross-section", this means when the cross-section obtained by vertically cutting the target part is viewed from the side.

[0014] Hereinafter, with reference to FIGS. 1 to 5, a semiconductor device according to an embodiment of the present invention will be described. FIG. 1 is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention, FIGS. 2 and 3 are cross-sectional views taken along the line A-A' of FIG. 1, FIG. 4 is a cross-sectional view taken along the line B-B' of FIG. 1, and FIG. 5 is a cross-sectional view showing an enlarged A1 region of FIG. 4. FIG. 2 shows the case where the semiconductor device according to the embodiment of the present invention is in the off state, and FIG. 3 shows the case where the semiconductor device according to the embodiment of the present invention is in the on state.

[0015] First, as shown in FIGS. 1 and 2, the semiconductor device according to the embodiment of the present invention includes a channel layer 132, a barrier layer 136 disposed on the channel layer 132, a gate electrode 155 disposed on the barrier layer 136, a gate semiconductor layer 152 disposed between the barrier layer 136 and the gate electrode 155, a protective layer 180 disposed on the barrier layer 136, and source electrodes 173 and drain electrodes 175 spaced apart from each other on the channel layer 132.

[0016] The channel layer 132 is a layer that forms a channel between the source electrode 173 and the drain electrode 175, and a two-dimensional electron gas (2DEG) 134 is disposed inside the channel layer 132. The two-dimensional electron gas 134 is a charge transport model used in solid state physics, which means a group of electrons that can move freely in two dimensions (for example, a plane composed of the first direction (X direction) and the second direction (Y direction)), but cannot move in other one dimensions (for example, the third direction (Z direction)) and are strongly confined within two dimensions. That is, the two-dimensional electron gas 134 exists in the shape of a two-dimensional sheet in three-dimensional space. Such a two-dimensional electron gas 134 mainly appears in a semiconductor heterojunction structure and is generated at the interface between the channel layer 132 and the barrier layer 136 in the semiconductor device according to the present embodiment. For example, the two-dimensional electron gas 134 is generated in the portion of the channel layer 132 closest to the barrier layer 136.

[0017] The channel layer 132 includes one or more substances selected from III-V group substances, for example, nitrides containing Al, Ga, In, B, or combinations thereof. However, it is not limited thereto. The channel layer 132 may be composed of a single layer or multiple layers. The channel layer 132 may be Al x In y Ga 1-x-y N (0 ≤ x ≤ 1, 0 ≤ y ≤ 1, x + y ≤ 1). For example, the channel layer 132 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or a combination thereof. However, it is not limited thereto. The channel layer 132 may be a doped layer or an undoped layer. The thickness of the channel layer 132 may be about several hundred nm or less.

[0018] The channel layer 132 is disposed on the substrate 110, and a seed layer 121, a buffer layer 122, etc. are disposed between the substrate 110 and the channel layer 132. The substrate 110, the seed layer 121, and the buffer layer 122 are layers necessary for forming the channel layer 132, and may be omitted in some cases. For example, when a substrate made of GaN is used as the channel layer 132, at least one of the substrate 110, the seed layer 121, and the buffer layer 122 can be omitted. Considering that the substrate made of GaN is relatively expensive, a channel layer 132 containing GaN is grown using a substrate 110 made of Si. At this time, due to the difference between the lattice structure of Si and that of GaN, it may not be easy to grow the channel layer 132 directly on the substrate 110. Therefore, after growing the seed layer 121 and the buffer layer 122 on the substrate 110 first, the channel layer 132 is grown on the buffer layer 122. Also, after at least one of the substrate 110, the seed layer 121, and the buffer layer 122 is used in the manufacturing process, it can be removed in the final structure of the semiconductor device.

[0019] The substrate 110 contains a semiconductor material. For example, the substrate 110 may include sapphire, Si, SiC, AlN, GaN, or a combination thereof. The substrate 110 may be a SOI (Silicon on Insulator) substrate. However, the material of the substrate 110 is not limited thereto, and all commonly used substrates are applicable. In some cases, the substrate 110 may include an insulating material. For example, after forming various layers including the channel layer 132 on the semiconductor substrate first, the semiconductor substrate can be removed and replaced with an insulating substrate.

[0020] The buffer layer 122 is disposed on the substrate 110. A seed layer 121 is further disposed between the substrate 110 and the buffer layer 122. The seed layer 121 is disposed directly above the substrate 110. However, it is not limited thereto, and a predetermined other layer may be further disposed between the substrate 110 and the seed layer 121. The seed layer 121 is a layer that serves as a seed for growing the buffer layer 122 and is composed of a crystal lattice structure that becomes the seed of the buffer layer 122. The buffer layer 122 is disposed directly above the seed layer 121. However, it is not limited thereto, and a predetermined other layer may be further disposed between the seed layer 121 and the buffer layer 122.

[0021] The seed layer 121 may include one or more substances selected from III-V group substances, for example, nitrides containing Al, Ga, In, B, or a combination thereof. The seed layer 121 is Al x In y Ga 1-x-y N (0≦x≦1, 0≦y≦1, x + y≦1). For example, the seed layer 122 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or a combination thereof. However, it is not limited thereto.

[0022] The buffer layer 122 is disposed between the substrate 110 and the channel layer 132. The buffer layer 122 is a layer for relaxing the difference in lattice constant and thermal expansion coefficient between the substrate 110 and the channel layer 132. The buffer layer 122 may include one or more substances selected from among nitrides containing III-V group substances such as Al, Ga, In, B, or combinations thereof. The buffer layer 122 is Al x In y Ga 1-x-y It may be N (0 ≤ x ≤ 1, 0 ≤ y ≤ 1, x + y ≤ 1). For example, the buffer layer 122 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof. However, it is not limited thereto. The buffer layer 122 may be composed of a single layer or multiple layers.

[0023] The buffer layer 122 of the semiconductor device according to an embodiment of the present invention further includes a superlattice layer and / or a high-resistance layer. The superlattice layer is disposed on the seed layer 121. The superlattice layer is disposed directly above the seed layer 121. However, it is not limited thereto, and a predetermined other layer may be further disposed between the seed layer 121 and the superlattice layer. The superlattice layer is a layer for relaxing the difference in lattice constant and thermal expansion coefficient between the substrate 110 and the channel layer 132.

[0024] The superlattice layer may include one or more substances selected from among nitrides containing III-V group substances such as Al, Ga, In, B, or combinations thereof. The superlattice layer is Al x In y Ga 1-x-y It may be N (0 ≤ x ≤ 1, 0 ≤ y ≤ 1, x + y ≤ 1). For example, the superlattice layer may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or a combination thereof. However, it is not limited thereto. The superlattice layer may be composed of a single layer or multiple layers. For example, the superlattice layer has a structure in which a layer made of AlGaN and a layer made of GaN are repeatedly stacked. For example, on the seed layer 121, AlGaN / GaN / AlGaN / GaN / AlGaN / GaN are sequentially stacked to form a superlattice layer. The number of AlGaN layers and GaN layers constituting the superlattice layer can be variously changed, and the substances constituting the superlattice layer can be variously changed.

[0025] The high-resistance layer is disposed on the superlattice layer. The high-resistance layer is disposed directly above the superlattice layer. However, it is not limited thereto, and a predetermined other layer may be further disposed between the superlattice layer and the high-resistance layer. The high-resistance layer is disposed between the superlattice layer and the channel layer 132. The high-resistance layer prevents the semiconductor element from deteriorating by reducing or blocking the flow of leakage current. The high-resistance layer is made of a material with low conductivity so that the space between the substrate 110 and the channel layer 132 can be electrically insulated. The high-resistance layer may include one or more substances selected from III-V substances, for example, nitrides containing Al, Ga, In, B, or a combination thereof. The high-resistance layer is Al x In y Ga 1-x-y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1). For example, the high-resistance layer may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or a combination thereof. However, it is not limited thereto. The high-resistance layer may be composed of a single layer or multiple layers. The high-resistance layer can also be a layer that is not doped with impurities.

[0026] The barrier layer 136 is disposed on the channel layer 132. The region of the channel layer 132 that overlaps with the barrier layer 136 becomes the drift region DTR. The drift region DTR is disposed between the source electrode 173 and the drain electrode 175. The drift region DTR means a region where carriers move when a potential difference occurs between the source electrode 173 and the drain electrode 175. The semiconductor device according to an embodiment of the present invention can be turned on / off depending on whether a voltage is applied to the gate electrode 155 and / or the magnitude of the voltage applied to the gate electrode 155. As a result, it is possible to cause or block the movement of carriers in the drift region DTR. The barrier layer 136 may include one or more substances selected from III-V group substances, for example, nitrides containing Al, Ga, In, B, or combinations thereof. The barrier layer 136 is Al x In y Ga 1-x-y It can be N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1). The barrier layer 136 may include GaN, InN, AlGaN, AlInN, InGaN, AlN, AlInGaN, or combinations thereof. However, it is not limited thereto.

[0027] The energy band gap of the barrier layer 136 can be adjusted by the composition ratio of Al and / or In. The barrier layer 136 is doped with a predetermined impurity. By increasing or decreasing the impurity doping concentration of the barrier layer 136, the threshold voltage, on-resistance, etc. of the semiconductor device according to an embodiment of the present invention can be adjusted. The barrier layer 136 includes a semiconductor material having characteristics different from those of the channel layer 132. The barrier layer 136 has at least one of a different polarization characteristic, energy band gap, or lattice constant from the channel layer 132. For example, the barrier layer 136 includes a material having an energy band gap different from that of the channel layer 132. At this time, the barrier layer 136 has an energy band gap higher than that of the channel layer 132 and has a higher electric polarization rate than the channel layer 132. Such a barrier layer 136 induces a two-dimensional electron gas 134 in the channel layer 132 having a relatively low electric polarization rate. From this point, the barrier layer 136 may be referred to as a channel supply layer or a two-dimensional electron gas supply layer.

[0028] The two-dimensional electron gas 134 is formed in a portion of the channel layer 132 located under the interface between the channel layer 132 and the barrier layer 136. The two-dimensional electron gas 134 has a very high electron mobility. The barrier layer 136 may be composed of a single layer or multiple layers. When the barrier layer 136 is composed of multiple layers, the materials of the respective layers constituting the multiple layers may have different energy band gaps. At this time, the various layers constituting the barrier layer 136 are arranged such that the energy band gap becomes larger as they are closer to the channel layer 132. In the present embodiment, although the barrier layer 136 has been described as being located directly above the channel layer 132, it is not limited thereto. For example, a spacer layer (135 in FIG. 10) may be further disposed between the barrier layer 136 and the channel layer 132. The description thereof will be given later with reference to FIGS. 9 to 14.

[0029] The gate electrode 155 is disposed on the barrier layer 136. The gate electrode 155 overlaps a partial region of the barrier layer 136. The gate electrode 155 overlaps a part of the drift region DTR of the channel layer 132. The gate electrode 155 is disposed between the source electrode 173 and the drain electrode 175. The gate electrode 155 is separated from the source electrode 173 and the drain electrode 175. For example, the gate electrode 155 is disposed closer to the source electrode 173 than to the drain electrode 175. That is, the separation distance between the gate electrode 155 and the source electrode 173 is smaller than the separation distance between the gate electrode 155 and the drain electrode 175, but is not limited thereto. The gate electrode 155 contains a conductive material. For example, the gate electrode 155 may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal oxynitride.

[0030] For example, the gate electrode 155 may include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or a combination thereof, but is not limited thereto. The gate electrode 155 may be composed of a single layer or multiple layers.

[0031] The gate semiconductor layer 152 is disposed between the barrier layer 136 and the gate electrode 155. That is, the gate semiconductor layer 152 is disposed on the barrier layer 136, and the gate electrode 155 is disposed on the gate semiconductor layer 152. The gate electrode 155 makes an ohmic contact or a schottky contact with the gate semiconductor layer 152. The gate semiconductor layer 152 overlaps with the gate electrode 155. At this time, the gate semiconductor layer 152 may completely overlap with the gate electrode 155 in the vertical direction, or the upper surface of the gate semiconductor layer 152 may be entirely covered by the gate electrode 155. That is, the gate semiconductor layer 152 has substantially the same planar shape as the gate electrode 155. However, it is not limited thereto, and the gate electrode 155 may be disposed so as to cover at least a part of the gate semiconductor layer 152.

[0032] The gate semiconductor layer 152 is disposed between the source electrode 173 and the drain electrode 175. The gate semiconductor layer 152 is separated from the source electrode 173 and the drain electrode 175. The gate semiconductor layer 152 is disposed closer to the source electrode 173 than the drain electrode 175. That is, the separation distance between the gate semiconductor layer 152 and the source electrode 173 is smaller than the separation distance between the gate semiconductor layer 152 and the drain electrode 175, but it is not limited thereto. In one embodiment, the gate semiconductor layer 152 overlaps with the gate electrode 155 in the third direction (Z direction). For example, the gate semiconductor layer 152 completely overlaps with the gate electrode 155 in the third direction (Z direction). That is, the side surface of the gate semiconductor layer 152 can be aligned with the side surface of the gate electrode 155. However, it is not limited thereto, and the gate semiconductor layer 152 may partially overlap with the gate electrode 155.

[0033] The gate semiconductor layer 152 may include one or more substances selected from among nitride substances containing group III-V substances, such as Al, Ga, In, B, or combinations thereof. The gate semiconductor layer 152 is Al x In y Ga 1-x-y N (0 ≤ x ≤ 1, 0 ≤ y ≤ 1, x + y ≤ 1) may be possible. For example, the gate semiconductor layer 152 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof. However, it is not limited thereto. The gate semiconductor layer 152 includes a substance having an energy band gap different from that of the barrier layer 136. For example, the gate semiconductor layer 152 includes GaN, and the barrier layer 136 includes AlGaN.

[0034] The gate semiconductor layer 152 is doped with a predetermined impurity. At this time, the impurity doped into the gate semiconductor layer 152 is a p-type dopant capable of providing holes. For example, the gate semiconductor layer 152 includes GaN doped with a p-type impurity. That is, the gate semiconductor layer 152 is composed of a p-GaN layer. However, it is not limited thereto, and the gate semiconductor layer 152 may be a p-AlGaN layer. The impurity doped into the gate semiconductor layer 152 may be magnesium (Mg). At this time, when a predetermined element adjacent to the impurity (for example, magnesium) doped into the gate semiconductor layer 152 binds, the hole concentration in the gate semiconductor layer 152 decreases, and thereby the characteristics of the semiconductor device may deteriorate. The gate semiconductor layer 152 may be composed of a single layer or a multilayer.

[0035] A depletion region DPR is formed in the channel layer 132 by the gate semiconductor layer 152. The depletion region DPR is located within the drift region DTR and has a width narrower than that of the drift region DTR. When a gate semiconductor layer 152 having an energy band gap different from that of the barrier layer 136 is positioned on the barrier layer 136, the level of the energy band of the portion of the barrier layer 136 overlapping with the gate semiconductor layer 152 becomes higher. Thereby, a depletion region DPR is formed in the region of the channel layer 132 overlapping with the gate semiconductor layer 152. The depletion region DPR can be a region where the two-dimensional electron gas 134 is not formed within the channel path of the channel layer 132, or a region having a lower electron concentration than the remaining region. That is, the depletion region DPR means a region where the flow of the two-dimensional electron gas 134 is interrupted within the drift region DTR. When the depletion region DPR is generated, no current flows between the source electrode 173 and the drain electrode 175, and the channel path can be blocked. Thereby, the semiconductor device according to the embodiment of the present invention has normally-off characteristics.

[0036] That is, the semiconductor device according to the embodiment of the present invention is a normally-off high electron mobility transistor (HEMT). As shown in FIG. 2, in the normal state where no voltage is applied to the gate electrode 155, the depletion region DPR exists, and the semiconductor device according to the embodiment of the present invention is in the off state. As shown in FIG. 3, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 155, the depletion region DPR disappears, the two-dimensional electron gas 134 is not interrupted within the drift region DTR, and can be connected. That is, the two-dimensional electron gas 134 is formed throughout the channel path between the source electrode 173 and the drain electrode 175, and the semiconductor device according to the embodiment of the present invention is in the on state.

[0037] In short, the semiconductor device according to the embodiment of the present invention includes semiconductor layers having different electrical polarization characteristics, and the semiconductor layer having a relatively large polarization rate induces a two-dimensional electron gas 134 in another semiconductor layer hetero-junctioned therewith. Such a two-dimensional electron gas 134 can be used as a channel between the source electrode 173 and the drain electrode 175, and the connection or interruption of the flow of such a two-dimensional electron gas 134 can be controlled by a bias voltage applied to the gate electrode 155. In the gate-off state, the flow of the two-dimensional electron gas 134 is blocked, and no current flows between the source electrode 173 and the drain electrode 175. In the gate-on state, the flow of the two-dimensional electron gas 134 is connected, and a current flows between the source electrode 173 and the drain electrode 175.

[0038] The seed layer 121, buffer layer 122, channel layer 132, barrier layer 136, and gate semiconductor layer 152 described above are sequentially stacked on the substrate 110. In the semiconductor device according to the embodiment of the present invention, at least one of the seed layer 121, buffer layer 122, channel layer 132, barrier layer 136, and gate semiconductor layer 152 may be omitted. Such a seed layer 121, buffer layer 122, channel layer 132, barrier layer 136, and gate semiconductor layer 152 may be made of the same base semiconductor material, or the composition ratio of the materials of each layer may be different in consideration of the role of each layer, the performance required for the semiconductor device, and the like.

[0039] The protective layer 180 is disposed on the barrier layer 136 and the gate electrode 155. The protective layer 180 covers the upper surface and side surface of the gate electrode 155 and the side surface of the gate semiconductor layer 152. The lower surface of the protective layer 180 is in contact with the barrier layer 136 and the gate electrode 155. Thereby, the barrier layer 136, the gate semiconductor layer 152, and the gate electrode 155 are protected by the protective layer 180. However, without being limited thereto, the gate electrode 155 may penetrate the protective layer 180 and be connected to the gate semiconductor layer 152, and the protective layer 180 may not cover the upper surface of the gate electrode 155. Alternatively, the lower surface of the protective layer 180 may be in contact with the gate semiconductor layer 152. In one embodiment, the protective layer 180 is disposed between the barrier layer 136 and the field dispersion layer 177 described later. At least a part of the protective layer 180 overlaps with the field dispersion layer 177 in the third direction (Z direction). Therefore, the portion of the protective layer 180 that overlaps with the field dispersion layer 177 in the third direction (Z direction) covers the gate semiconductor layer 152 and the gate electrode 155.

[0040] In one embodiment, the protective layer 180 includes an insulating material. For example, the protective layer 180 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (Al2O3), or a combination thereof. Thereby, it is possible to reduce or prevent moisture, oxygen, etc. from entering the channel layer 132, and it is possible to remove the dangling bond state of the insulating material located at the interface of the barrier layer 136. In one embodiment, the protective layer 180 may be composed of a single layer or a multilayer. For example, in some cases, the protective layer 180 may include two or more layers.

[0041] Referring further to FIGS. 4 and 5, a semiconductor device according to an embodiment of the present invention includes a source / drain trench CT that penetrates the protective layer 180 and the barrier layer 136 and recesses at least a part of the channel layer 132. A source electrode 173 and a drain electrode 175 are disposed in the source / drain trench CT. The source / drain trench CT includes side surfaces facing each other in the first direction (X direction) and side surfaces facing each other in the second direction (Y direction). Specifically, as shown in FIGS. 3 and 4, source / drain trenches CT that penetrate the protective layer 180 and the barrier layer 136 and recess the upper surface of the channel layer 132 are arranged on both sides of the gate electrode 155 so as to be separated in the first direction (X direction).

[0042] Also, a plurality of source / drain trenches CT are provided, and the plurality of source / drain trenches CT are arranged along the second direction (Y direction). The plurality of source / drain trenches CT are arranged to be separated in the second direction (Y direction). As shown in FIG. 1, the source / drain trench CT has a rectangular shape in a plane. For example, the source / drain trench CT has a rectangular shape in which the long side extends along the first direction (X direction). However, it is not limited thereto, and the source / drain trench CT may have various shapes in a plane. The description regarding this will be described later with reference to FIGS. 15 and 16.

[0043] In one embodiment, the side surface of the source / drain trench CT is defined by the side surface of the channel layer 132, the side surface of the barrier layer 136, and the side surface of the protective layer 180. For example, the side surfaces of the source / drain trench CT that face each other in the first direction (X direction) are defined by the side surfaces of the channel layer 132 that face each other in the first direction (X direction), the side surfaces of the barrier layer 136 that face each other in the first direction (X direction), and the side surfaces of the protective layer 180 that face each other in the first direction (X direction). Also, the side surfaces of the source / drain trench CT that face each other in the second direction (Y direction) are defined by the side surfaces of the channel layer 132 that face each other in the second direction (Y direction), the side surfaces of the barrier layer 136 that face each other in the second direction (Y direction), and the side surfaces of the protective layer 180 that face each other in the second direction (Y direction). At this time, as shown in FIG. 5, the side surface of the barrier layer 136 includes an inclined surface. For example, the side surfaces of the barrier layer 136 that face each other in the second direction (Y direction) include a first inclined surface SL1.

[0044] The first inclined surface SL1 of the barrier layer 136 is a surface inclined at a predetermined angle from the lower surface (136_B) of the barrier layer 136. As an example, the first angle θ1 between the first inclined surface SL1 and the lower surface (136_B) of the barrier layer 136 can be greater than 0° and equal to or less than 70°. Within this range, the impurity ND can be easily doped into the first inclined surface SL1 of the barrier layer 136. As a result, the width along the second direction (Y direction) of the upper surface (136_U) of the barrier layer 136 is smaller than the width along the second direction (Y direction) of the lower surface (136_B) of the barrier layer 136. On the other hand, the side surfaces of the barrier layer 136 facing each other in the first direction (X direction) are vertical surfaces perpendicular to the lower surface (136_B) of the barrier layer 136. In this case, the width along the first direction (X direction) of the upper surface (136_U) of the barrier layer 136 is substantially the same as the width along the first direction (X direction) of the lower surface (136_B) of the barrier layer 136. However, it is not limited thereto, and the side surfaces of the barrier layer 136 facing each other in the first direction (X direction) may include inclined surfaces. The description thereof will be described later with reference to FIG. 9.

[0045] In one embodiment, the impurity ND is doped into the first inclined surface SL1 of the barrier layer 136. For example, an n-type impurity is doped into the first inclined surface SL1 of the barrier layer 136. Si, Ge, or a combination thereof can be doped into the first inclined surface SL1 of the barrier layer 136. The impurity ND is substantially uniformly doped into the first inclined surface SL1 of the barrier layer 136. That is, the entire first inclined surface SL1 of the barrier layer 136 is doped with the impurity ND. The impurity ND doped into the first inclined surface SL1 of the barrier layer 136 can be formed by an ion implantation process, a plasma treatment process, a heat treatment process, or the like. At this time, since the barrier layer 136 includes a first inclined surface SL1 having a predetermined angle from the lower surface of the barrier layer 136, when impurities are implanted into the side surface of the barrier layer 136, the first inclined surface SL1 of the barrier layer 136 is easily doped. Thereby, additional implantation of carriers can be enabled through the first inclined surface SL1 of the barrier layer 136. In other words, the first inclined surface SL1 of the barrier layer 136 can function as an injection path for additional carriers.

[0046] In one embodiment, the side surface of the channel layer 132 includes an inclined surface. For example, the side surfaces of the channel layer 132 facing each other in the second direction (Y direction) include a second inclined surface SL2. The second inclined surface SL2 is a surface inclined at a predetermined angle from the upper surface (132_U) of the channel layer 132. A second angle θ2 between the second inclined surface SL2 and the upper surface (132_U) of the channel layer 132 is greater than or the same as the first angle θ1. This is due to the process characteristics of simultaneously forming the first inclined surface SL1 of the barrier layer 136 and the second inclined surface SL2 of the channel layer 132 using an etching substance with a higher etching rate for the channel layer 132 than for the barrier layer 136 in the process of etching both the channel layer 132 and the barrier layer 136. However, it is not limited thereto, and in the process of etching both the channel layer 132 and the barrier layer 136, the etching conditions may be adjusted so that the etching rate of the channel layer 132 is higher than that of the barrier layer 136 to simultaneously form the first inclined surface SL1 and the second inclined surface SL2. Here, the upper surface (132_U) of the channel layer 132 means a surface that defines the lower surface of the source / drain trench CT. On the other hand, the side surfaces of the channel layer 132 facing each other in the first direction (X direction) are vertical surfaces perpendicular to the upper surface of the channel layer 132, but it is not limited thereto. An explanation regarding this will be described later with reference to FIG. 9.

[0047] In one embodiment, the upper surface (132_U) of the channel layer 132 is doped with an impurity ND. The impurity doped on the upper surface (132_U) of the channel layer 132 contains the same substance as the impurity doped on the first inclined surface SL1 of the barrier layer 136. For example, the upper surface (132_U) of the channel layer 132 is doped with an n-type impurity. Si, Ge, or a combination thereof may be doped on the upper surface (132_U) of the channel layer 132. At this time, the concentration of the impurity doped on the upper surface (132_U) of the channel layer 132 is greater than the concentration of the impurity doped on the first inclined surface SL1 of the barrier layer 136. Also, the impurity ND is doped substantially uniformly on the upper surface of the channel layer 132. That is, the entire upper surface of the channel layer 132 is doped with the impurity ND. The impurity ND doped on the upper surface (132_U) of the channel layer 132 can be formed by an ion implantation process, a plasma treatment process, a heat treatment process, or the like.

[0048] Although FIG. 5 shows the upper surface (132_U) of the channel layer 132 doped with the impurity ND, it is not limited thereto. For example, the second inclined surface SL2 of the channel layer 132 may be doped with an impurity. The impurity doped on the second inclined surface SL2 of the channel layer 132 contains the same substance as the impurity ND doped on the upper surface (132_U) of the channel layer 132. At this time, the concentration of the impurity doped on the second inclined surface SL2 of the channel layer 132 is smaller than the concentration of the impurity ND doped on the upper surface (132_U) of the channel layer 132. Also, due to the area of the exposed side surface, the concentration of the impurity doped on the second inclined surface SL2 of the channel layer 132 is smaller than the concentration of the impurity ND doped on the first inclined surface SL1 of the barrier layer 136. Furthermore, the impurity ND is doped substantially uniformly on the second inclined surface SL2 of the channel layer 132. That is, the entire second inclined surface SL2 of the channel layer 132 is doped with the impurity ND. In the semiconductor device according to one embodiment, the barrier layer 136 includes the first inclined surface SL1, and the channel layer 132 includes the second inclined surface SL2, so that the drift region DTR where the barrier layer 136 and the channel layer 132 overlap in the third direction (Z direction) increases.

[0049] Referring to FIG. 2 again, a source electrode 173 and a drain electrode 175 are respectively disposed in source / drain trenches CT located on both sides of the gate electrode 155. The source electrode 173 and the drain electrode 175 are disposed on the channel layer 132. The source electrode 173 and the drain electrode 175 are in direct contact with the channel layer 132 and are electrically connected to the channel layer 132. The source electrode 173 and the drain electrode 175 can be separated from each other, and the gate electrode 155 and the gate semiconductor layer 152 are disposed between the source electrode 173 and the drain electrode 175. That is, the source electrode 173 and the drain electrode 175 are disposed on both sides of the gate electrode 155 at a distance in the first direction (X direction). Thereby, the gate electrode 155 and the gate semiconductor layer 152 are separated from the source electrode 173 and the drain electrode 175 in the first direction (X direction). For example, the source electrode 173 is electrically connected to the channel layer 132 on one side of the gate electrode 155, and the drain electrode 175 is electrically connected to the channel layer 132 on the other side of the gate electrode 155. The source electrode 173 and the drain electrode 175 are located outside the drift region DTR of the channel layer 132. The interface between the source electrode 173 and the channel layer 132 is one peripheral edge of the drift region DTR. Similarly, the interface between the drain electrode 175 and the channel layer 132 is the other peripheral edge of the drift region DTR.

[0050] In the source / drain trench CT, the source electrode 173 and the drain electrode 175 are in contact with the channel layer 132 and the barrier layer 136. Therefore, the source electrode 173 and the drain electrode 175 are in contact with the upper surface (132_U) and the side surface of the channel layer 132. For example, the source electrode 173 and the drain electrode 175 are in contact with the side surfaces of the channel layer 132 facing each other in the first direction (X direction) and the side surfaces of the channel layer 132 facing each other in the second direction (Y direction). Also, the source electrode 173 and the drain electrode 175 are in contact with the side surface of the barrier layer 136. For example, the source electrode 173 and the drain electrode 175 are in contact with the side surfaces of the barrier layer 136 facing each other in the first direction (X direction) and the side surfaces of the barrier layer 136 facing each other in the second direction (Y direction). In one embodiment, the source electrode 173 and the drain electrode 175 cover the side surface of the protective layer 180. The upper surfaces of the source electrode 173 and the drain electrode 175 protrude from the upper surface of the protective layer 180. Also, at least one of the source electrode 173 and the drain electrode 175 covers at least a part of the upper surface of the protective layer 180.

[0051] In one embodiment, each of the source electrode 173 and the drain electrode 175 extends in the second direction (Y direction). For example, as shown in FIG. 4, in a cross section composed of the second direction (Y direction) and the third direction (Z direction), each of the source electrode 173 and the drain electrode 175 fills a plurality of source / drain trench CTs arranged in the second direction (Y direction). As an example, the source electrode 173 is disposed on the upper surface (132_U) of the channel layer 132, the second inclined surface SL2 of the channel layer 132, the first inclined surface SL1 of the barrier layer 136, the side surface of the protective layer 180, and the upper surface of the protective layer 180. That is, the source electrode 173 and the drain electrode 175 cover the second inclined surface SL2 of the channel layer 132 and the first inclined surface SL1 of the barrier layer 136. At this time, the first thickness T1 of the source electrode 173 located on the upper surface (132_U) of the channel layer 132 is greater than or equal to the second thickness T2 of the source electrode 173 located on the first inclined surface SL1 of the barrier layer 136.

[0052] Also, the thickness of the source electrode 173 located on the side surface of the protective layer 180 is smaller than the second thickness T2 of the source electrode 173 located on the first inclined surface SL1 of the barrier layer 136, but is not limited thereto. According to an embodiment, the barrier layer 136 of the semiconductor element includes a first inclined surface SL1, and the channel layer 132 includes a second inclined surface SL2, so that the source electrode 173 and the drain electrode 175 can be easily formed on the side surface of the barrier layer 136 and the side surface of the channel layer 132. That is, the step coverage for forming the source electrode 173 and the drain electrode 175 can be improved, whereby the source electrode 173 and the drain electrode 175 can have stable electrical characteristics.

[0053] The source electrode 173 and the drain electrode 175 contain a conductive material. For example, the source electrode 173 and the drain electrode 175 may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal oxynitride, etc. However, it is not limited thereto. For example, the source electrode 173 and the drain electrode 175 may include, but are not limited to, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof.

[0054] The source electrode 173 and the drain electrode 175 may be composed of a single layer or multiple layers. The source electrode 173 and the drain electrode 175 are in ohmic contact with the channel layer 132. In the channel layer 132, the region in contact with the source electrode 173 and the drain electrode 175 is doped at a relatively high concentration compared to other regions. In FIGS. 1 to 5, the semiconductor device according to the embodiment of the present invention is shown as including a pair of source electrodes 173 and drain electrodes 175, but the number of the source electrodes 173 and the drain electrodes 175 is not limited thereto. For example, each of the source electrode 173 and the drain electrode 175 may include two or more layers.

[0055] The semiconductor device according to an embodiment of the present invention further includes a field dispersion layer 177 located on the protective layer 180. The field dispersion layer 177 is disposed between the source electrode 173 and the drain electrode 175. The field dispersion layer 177 covers the gate electrode 155. The field dispersion layer 177 overlaps with the gate electrode 155 in the third direction (Z direction). The field dispersion layer 177 may be electrically connected to the source electrode 173. For example, the field dispersion layer 177 may be connected to the source electrode 173. In one embodiment, the field dispersion layer 177 includes the same material as the source electrode 173 and is disposed in the same layer as the source electrode 173. The field dispersion layer 177 may be formed simultaneously with the source electrode 173 in the same process. That is, the boundary between the field dispersion layer 177 and the source electrode 173 is not clear, and the field dispersion layer 177 may be integrated with the source electrode 173. However, the present invention is not limited to this, and the field dispersion layer 177 may be a separate component separated from the source electrode 173.

[0056] Also, the field dispersion layer 177 may be disposed in a layer different from the source electrode 173 or may be formed in a different process. In some cases, the field dispersion layer 177 may be electrically connected to the gate electrode 155. For example, an opening overlapping the gate electrode 155 in the vertical direction may be formed in the protective layer 180, and the field dispersion layer 177 may be connected to the gate electrode 155 through the opening. At this time, the field dispersion layer 177 is not connected to the source electrode 173. The field dispersion layer 177 serves to disperse the electric field concentrated around the gate electrode 155. In the gate-off state, a two-dimensional electron gas 134 is located with a very high concentration in the portion of the channel layer 132 positioned between the gate electrode 155 and the source electrode 173, and in the portion of the channel layer 132 positioned between the gate electrode 155 and the drain electrode 175. In the portion of the channel layer 132 adjacent to the gate electrode 155, an electric field is concentrated especially. As a result, the leakage current increases and the breakdown voltage decreases. The semiconductor element according to one embodiment includes a field dispersion layer 177 to disperse the electric field concentrated around the gate electrode 155. As a result, the leakage current can be decreased and the breakdown voltage can be increased.

[0057] Hereinafter, with further reference to FIGS. 6 to 14, a semiconductor element according to another embodiment of the present invention will be described. FIGS. 6 to 8 show a schematic configuration of a semiconductor element according to another embodiment of the present invention, which is a cross-sectional view corresponding to the A1 region in FIG. 4. FIGS. 9 to 11 are cross-sectional views showing a schematic configuration of a semiconductor element according to another embodiment of the present invention. FIG. 12 is an enlarged cross-sectional view of the A2 region in FIG. 11. FIG. 13 is a cross-sectional view showing a schematic configuration of a semiconductor element according to another embodiment of the present invention, showing the A2 region in FIG. 12. FIG. 14 is a cross-sectional view showing a schematic configuration of a semiconductor element according to another embodiment of the present invention. FIGS. 6 to 14 show various modifications of the semiconductor element according to the embodiment shown in FIGS. 1 to 5. Since the embodiments shown in FIGS. 6 to 14 correspond to the same portions as the embodiments shown in FIGS. 1 to 5, the description thereof will be omitted and the description will be centered on the differences. Also, the same reference numerals are used for the same components as those in the above embodiments. In the embodiments shown in FIGS. 6 to 14, the shape and / or arrangement of the barrier layer may be partly different from those in the above embodiments.

[0058] Referring to FIGS. 2, 4, and 6 to 14, a semiconductor device according to another embodiment of the present invention includes a channel layer 132, a barrier layer 136 located on the channel layer 132, a gate electrode 155 located on the barrier layer 136, a gate semiconductor layer 152 located between the barrier layer 136 and the gate electrode 155, a protective layer 180 located on the barrier layer 136, and source electrodes 173 and drain electrodes 175 spaced apart from each other on the channel layer 132. A semiconductor device according to another embodiment of the present invention includes a source / drain trench CT that penetrates the protective layer 180 and the barrier layer 136 and recesses at least a part of the channel layer 132. The source / drain trench CT includes side surfaces facing each other in a first direction (X direction) and side surfaces facing each other in a second direction (Y direction). The source electrodes 173 and the drain electrodes 175 are disposed in the source / drain trench CT.

[0059] Referring to FIG. 6, in a semiconductor device according to another embodiment of the present invention, the side surfaces of the barrier layer 136 and the side surfaces of the channel layer 132 include curved surfaces. For example, the side surfaces of the barrier layer 136 facing each other in the second direction (Y direction) include a first curved surface PL1. The first curved surface PL1 has a concave shape toward the inside of the barrier layer 136. As an example, a first angle θ1 between a tangent of the first curved surface PL1 and a lower surface (136_B) of the barrier layer 136 is greater than 0° and equal to or less than 70°. Within this range, impurities ND can be easily doped into the first curved surface PL1 of the barrier layer 136. Thereby, the width of the upper surface (136_U) of the barrier layer 136 along the second direction (Y direction) is smaller than the width of the lower surface (136_B) of the barrier layer 136 along the second direction (Y direction). Also, the side surfaces of the channel layer 132 facing each other in the second direction (Y direction) include a second curved surface PL2. The second curved surface PL2 has a concave shape toward the inside of the channel layer 132. The second angle θ2 between the second surface PL2 and the upper surface (132_U) of the channel layer 132 is greater than or equal to the first angle θ1. Here, the upper surface (132_U) of the channel layer 132 means the surface that defines the lower surface of the source / drain trench CT.

[0060] Referring to FIG. 7, the side surface of the barrier layer 136 includes a plurality of inclined portions. For example, the side surfaces of the barrier layer 136 facing each other in the second direction (Y direction) include a first inclined portion SL1a and a second inclined portion SL1b. The first inclined portion SL1a and the second inclined portion SL1b are surfaces inclined at a predetermined angle from the lower surface (136_B) of the barrier layer 136. As an example, the fourth angle θ4 between the first inclined portion SL1a and the lower surface (136_B) of the barrier layer 136 is greater than 0° and less than or equal to 70°, and the fifth angle θ5 between the second inclined portion SL1b and the lower surface (136_B) of the barrier layer 136 is greater than the fourth angle θ4 between the first inclined portion SL1a and the lower surface (136_B) of the barrier layer 136. Within this range, the impurity ND can be easily doped into the first inclined surface SL1 of the barrier layer 136. As a result, the width of the upper surface (136_U) of the barrier layer 136 along the second direction (Y direction) is smaller than the width of the lower surface (136_B) of the barrier layer 136 along the second direction (Y direction).

[0061] However, it is not limited thereto, and the fifth angle θ5 between the second inclined portion SL1b and the lower surface (136_B) of the barrier layer 136 may be smaller than the fourth angle θ4 between the first inclined portion SL1a and the lower surface (136_B) of the barrier layer 136. In FIG. 7, the side surface of the barrier layer 136 is described as including two inclined portions, but it is not limited thereto. For example, the side surface of the barrier layer 136 may include three or more inclined portions. Also, although the side surface of the channel layer 132 is shown as not including an inclined portion, it is not limited thereto. For example, the side surface of the channel layer 132 may include two or more inclined portions.

[0062] Referring to FIG. 8, the side surface of the protective layer 180 of the semiconductor element according to another embodiment of the present invention includes an inclined surface. For example, the side surfaces of the protective layer 180 facing each other in the second direction (Y direction) include a fourth inclined surface SL4. The fourth inclined surface SL4 of the protective layer 180 is a surface inclined at a predetermined angle from the lower surface of the protective layer 180. As an example, the sixth angle θ6 between the fourth inclined surface SL4 and the lower surface of the protective layer 180 is greater than or the same as the first angle θ1 between the first inclined surface SL1 and the lower surface (136_B) of the barrier layer 136. Thereby, the width of the upper surface of the protective layer 180 along the second direction (Y direction) is smaller than the width of the lower surface of the protective layer 180 along the second direction (Y direction). Since the side surface of the protective layer 180 has an inclined surface, the source electrode 173 and the drain electrode 175 can be easily formed on the side surface of the protective layer 180. That is, the step coverage for forming the source electrode 173 and the drain electrode 175 is improved, whereby the source electrode 173 and the drain electrode 175 can have more stable electrical characteristics. However, the present invention is not limited thereto, and the side surface of the protective layer 180 may have a concave shape toward the inside of the protective layer 180 or include a plurality of inclined portions as in the embodiment of FIG. 6.

[0063] Referring to FIG. 9, the side surfaces of the barrier layer 136 facing each other in the first direction (X direction) and the side surfaces of the channel layer 132 facing each other in the first direction (X direction) of the semiconductor element according to another embodiment of the present invention further include inclined surfaces. In another embodiment of the present invention, the side surfaces of the barrier layer 136 facing each other in the first direction (X direction) include a fifth inclined surface SL5. The fifth inclined surface SL5 is a surface inclined at a predetermined angle from the lower surface (136_B) of the barrier layer 136. As an example, the angle between the fifth inclined surface SL5 and the lower surface (136_B) of the barrier layer 136 is greater than 0° and equal to or less than 70°. Within this range, impurities ND can be easily doped into the fifth inclined surface SL5 of the barrier layer 136. As a result, the width of the upper surface (136_U) of the barrier layer 136 along the first direction (X direction) is smaller than the width of the lower surface (136_B) of the barrier layer 136 along the first direction (X direction). As a result, the region of the channel layer 132 that overlaps with the barrier layer 136 in the third direction (Z direction) relatively increases, and the drift region DTR increases.

[0064] In addition, the side surfaces of the channel layer 132 facing each other in the first direction (X direction) include a sixth inclined surface SL6. The sixth inclined surface SL6 is a surface inclined at a predetermined angle from the upper surface (132_U) of the channel layer 132. The angle between the sixth inclined surface SL6 and the upper surface (132_U) of the channel layer 132 is greater than or equal to the angle between the fifth inclined surface SL5 and the lower surface (136_B) of the barrier layer 136. This is due to the process characteristics of simultaneously forming the fifth inclined surface SL5 of the barrier layer 136 and the sixth inclined surface SL6 of the channel layer 132 by using an etching substance with a higher etching rate for the channel layer 132 than for the barrier layer 136 in the process of etching both the channel layer 132 and the barrier layer 136. Here, the upper surface (132_U) of the channel layer 132 means the surface that defines the lower surface of the source / drain trench CT. However, it is not limited to this. In the process of etching both the channel layer 132 and the barrier layer 136, the etching conditions may be adjusted so that the etching rate of the channel layer 132 is higher than that of the barrier layer 136, and the first inclined surface SL1 and the second inclined surface SL2 may be simultaneously formed.

[0065] Referring to FIGS. 10 to 14, a semiconductor device according to another embodiment of the present invention further includes a spacer layer 135 located between the channel layer 132 and the barrier layer 136. The spacer layer 135 is disposed on the channel layer 132. The spacer layer 135 is disposed between the channel layer 132 and the barrier layer 136. The spacer layer 135 overlaps with the barrier layer 136 in the third direction (Z direction). The spacer layer 135 contains AlN. In one embodiment, the source / drain trench CT penetrates the protective layer 180, the barrier layer 136, and the spacer layer 135, and recesses at least a part of the channel layer 132. In one embodiment, the side surfaces of the source / drain trench CT are defined by the side surfaces of the channel layer 132, the side surfaces of the spacer layer 135, the side surfaces of the barrier layer 136, and the side surfaces of the protective layer 180.

[0066] For example, the side surfaces of the source / drain trench CT facing each other in the first direction (X direction) are defined by the side surfaces of the channel layer 132 facing each other in the first direction (X direction), the side surfaces of the spacer layer 135 facing each other in the first direction (X direction), the side surfaces of the barrier layer 136 facing each other in the first direction (X direction), and the side surfaces of the protective layer 180 facing each other in the first direction (X direction). Also, the side surfaces of the source / drain trench CT facing each other in the second direction (Y direction) are defined by the side surfaces of the channel layer 132 facing each other in the second direction (Y direction), the side surfaces of the spacer layer 135 facing each other in the second direction (Y direction), the side surfaces of the barrier layer 136 facing each other in the second direction (Y direction), and the side surfaces of the protective layer 180 facing each other in the second direction (Y direction). At this time, the side surfaces of the spacer layer 135 include inclined surfaces.

[0067] For example, as shown in FIGS. 11 and 12, the side surfaces of the spacer layer 135 facing each other in the second direction (Y direction) include a third inclined surface SL3. The third inclined surface SL3 is a surface inclined at a predetermined angle from the lower surface of the spacer layer 135. As an example, the third angle θ3 between the third inclined surface SL3 and the lower surface of the spacer layer 135 is smaller than the first angle θ1 between the first inclined surface SL1 of the barrier layer 136 and the lower surface (136_B) of the barrier layer 136. This is due to the process characteristics of simultaneously forming the first inclined surface SL1 of the barrier layer 136 and the third inclined surface SL3 of the spacer layer 135 by using an etching substance with a higher etching rate for the barrier layer 136 than the spacer layer 135 in the process of etching both the spacer layer 135 and the barrier layer 136 together. However, it is not limited to this. In the process of etching both the spacer layer 135 and the barrier layer 136 together, the etching conditions may be adjusted so that the etching rate of the barrier layer 136 is higher than that of the spacer layer 135 to simultaneously form the first inclined surface SL1 and the third inclined surface SL3.

[0068] Alternatively, as another example, as shown in FIG. 13, the third angle θ3 between the third inclined surface SL3 of the spacer layer 135 and the lower surface of the spacer layer 135 is substantially the same as the first angle θ1 between the first inclined surface SL1 of the barrier layer 136 and the lower surface (136_B) of the barrier layer 136. That is, the third inclined surface SL3 of the spacer layer 135 and the first inclined surface SL1 of the barrier layer 136 are extended straightly. However, also in this case, it is smaller than the second angle θ2 between the second inclined surface SL2 of the channel layer 132 and the upper surface (132_U) of the channel layer 132. Thereby, the width along the second direction (Y direction) of the upper surface of the spacer layer 135 is smaller than the width along the second direction (Y direction) of the lower surface (135_B) of the spacer layer 135. On the other hand, the side surfaces of the spacer layer 135 facing each other in the first direction (X direction) are vertical surfaces perpendicular to the lower surface of the spacer layer 135, but it is not limited to this.

[0069] In one embodiment, the third inclined surface SL3 of the spacer layer 135 is disposed below the first inclined surface SL1 of the barrier layer 136. The third inclined surface SL3 of the spacer layer 135 is disposed between the first inclined surface SL1 of the barrier layer 136 and the second inclined surface SL2 of the channel layer 132. In one embodiment, the third inclined surface SL3 of the spacer layer 135 is doped with impurities. The impurities doped in the third inclined surface SL3 of the spacer layer 135 include the same substance as the impurities doped in the first inclined surface SL1 of the barrier layer 136 and the impurities doped in the upper surface (132_U) of the channel layer 132. For example, the third inclined surface SL3 of the spacer layer 135 is doped with n-type impurities. The third inclined surface SL3 of the spacer layer 135 is doped with Si, Ge, or a combination thereof. However, it is not limited thereto. The impurity ND can be doped substantially uniformly in the third inclined surface SL3 of the spacer layer 135. That is, the entire third inclined surface SL3 of the spacer layer 135 is doped with the impurity ND.

[0070] Referring to FIG. 14, the side surfaces of the spacer layer 135 facing each other in the first direction (X direction) of the semiconductor device according to another embodiment of the present invention further include inclined surfaces. In one embodiment, the side surfaces of the spacer layer 135 facing each other in the first direction (X direction) include a seventh inclined surface SL7. The seventh inclined surface SL7 is a surface inclined at a predetermined angle from the lower surface (136_B) of the spacer layer 135. As an example, the angle between the seventh inclined surface SL7 and the lower surface of the spacer layer 135 is substantially the same as the angle between the third inclined surface SL3 of the spacer layer 135 and the lower surface of the spacer layer 135 in the embodiment of FIG. 12. Thereby, the width of the upper surface of the spacer layer 135 along the first direction (X direction) is smaller than the width of the lower surface of the spacer layer 135 along the first direction (X direction).

[0071] In the embodiments of FIGS. 10 to 14, a part of the side surfaces of the spacer layer 135, the barrier layer 136, and the channel layer 132 includes inclined surfaces, and the angle between the side surface of the spacer layer 135 and the lower surface of the spacer layer 135 is relatively small. Thereby, as the area of the exposed spacer layer 135 increases, the side surface of the spacer layer 135 is doped with impurities at a high concentration. As a result, the side surface of the spacer layer 135 functions as a carrier injection layer.

[0072] Hereinafter, with reference to FIGS. 2 and 15 to 18, a semiconductor device according to another embodiment of the present invention will be described. FIGS. 15 to 17 are plan views showing a semiconductor device according to another embodiment of the present invention, and FIG. 18 is a cross-sectional view taken along the line C-C' of FIG. 17. Referring to FIGS. 2 and 15 to 17, a semiconductor device according to another embodiment of the present invention includes a channel layer 132, a barrier layer 136 located on the channel layer 132, a gate electrode 155 located on the barrier layer 136, a gate semiconductor layer 152 located between the barrier layer 136 and the gate electrode 155, a protective layer 180 located on the barrier layer 136, and source electrodes 173 and drain electrodes 175 spaced apart from each other on the channel layer 132.

[0073] The semiconductor device according to the present embodiment includes a source / drain trench CT that penetrates the protective layer 180 and the barrier layer 136 and recesses at least a part of the channel layer 132. The source / drain trench CT is disposed on both sides of the gate electrode 155 and spaced apart in the first direction (X direction). Also, a plurality of source / drain trenches CT are provided, and the plurality of source / drain trenches CT are arranged along the second direction (Y direction). The plurality of source / drain trenches CT are disposed spaced apart in the second direction (Y direction). The source electrode 173 and the drain electrode 175 are disposed in the source / drain trench CT. The source / drain trench CT has various shapes in a plane.

[0074] For example, as shown in FIG. 15, the source / drain trench CT includes a round shape in a plane. That is, the side surfaces of the source / drain trench CTs facing each other in the first direction (X direction) have a round shape, and the side surfaces of the source / drain trench CTs facing each other in the second direction (Y direction) are flat. As another example, as shown in FIG. 16, the source / drain trench CT has an elliptical shape on a plane. At this time, the radius along the first direction (X direction) of the source / drain trench CT is larger than the radius along the second direction (Y direction) of the source / drain trench CT. In this case, a plurality of source / drain trench CTs are arranged along the second direction (Y direction). Since the cross-sectional shape of the source / drain trench CT according to the present embodiment is substantially the same as that of the embodiments in FIGS. 1 to 5, it is omitted.

[0075] Referring to FIG. 17, the source / drain trench CT is located on both sides of the gate electrode 155 and extends in the second direction (Y direction). The source / drain trench CT has a square shape on a plane. For example, the source / drain trench CT has a rectangular shape in which the long side extends along the second direction (Y direction). In this case, as shown in FIG. 18, the side surfaces of the barrier layers 136 facing each other in the first direction (X direction) and the side surfaces of the channel layers 132 facing each other in the first direction (X direction) include inclined surfaces. In addition, the side surfaces of the barrier layers 136 facing each other in the first direction (X direction) are doped with impurities. The remaining description regarding the side surfaces of the barrier layers 136 facing each other in the first direction (X direction) and the side surfaces of the channel layers 132 facing each other in the first direction (X direction) is substantially the same as that of the embodiment in FIG. 8, and thus is omitted.

[0076] Hereinafter, with reference to FIGS. 19 to 27, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described. FIGS. 19 to 27 are process cross-sectional views sequentially showing the steps of manufacturing a semiconductor device according to an embodiment of the present invention. FIGS. 19 to 23 and FIG. 26 correspond to cross-sectional views taken along the line A-A' of FIG. 1, and FIGS. 24, 25, and FIG. 27 correspond to cross-sectional views taken along the line B-B' of FIG. 1.

[0077] First, as shown in FIG. 19, a seed layer 121, a buffer layer 122, a channel layer 132, a barrier layer 136, and a gate semiconductor material layer 152a are sequentially formed on a substrate 110. The substrate 110 contains a semiconductor material. For example, the substrate 110 includes sapphire, Si, SiC, AlN, GaN, or a combination thereof. The substrate 110 may be a SOI (Silicon on Insulator) substrate. However, the material of the substrate 110 is not limited thereto, and all commonly used substrates are applicable.

[0078] The seed layer 121, the buffer layer 122, the channel layer 132, the barrier layer 136, and the gate semiconductor material layer 152a are sequentially formed using an epitaxial growth method. The seed layer 121 is first formed on the substrate 110, and the buffer layer 122 is formed on the seed layer 121. Next, the channel layer 132 is formed on the buffer layer 122, the barrier layer 136 is formed on the channel layer 132, and the gate semiconductor material layer 152a is formed on the barrier layer 136. Although omitted in the figure, as in the embodiments of FIGS. 10 to 14, a spacer layer (135 in FIG. 10) may be further formed between the channel layer 132 and the barrier layer 136. Alternatively, the buffer layer 122 may further include a superlattice layer and a high-resistance layer. In the final structure of the semiconductor device according to one embodiment, the superlattice layer and the high-resistance layer are formed in the buffer layer 122 and are located below the channel layer 132.

[0079] The seed layer 121, buffer layer 122, channel layer 132, barrier layer 136, and gate semiconductor material layer 152a are made of semiconductor materials of the same base. However, considering the roles of each layer, the performance required for the semiconductor device, etc., the composition ratios of the materials of each layer may be different. The seed layer, buffer layer 122, channel layer 132, barrier layer 136, and gate semiconductor material layer 152a may include one or more materials selected from among nitride compounds containing III-V group materials such as Al, Ga, In, B, or combinations thereof. The seed layer 121, buffer layer 122, channel layer 132, barrier layer 136, and gate semiconductor material layer 152a may be Al x In y Ga 1-x-y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1). For example, the seed layer 121, buffer layer 122, channel layer 132, barrier layer 136, and gate semiconductor material layer 152a may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof. The barrier layer 136 includes a material having an energy band gap different from that of the channel layer 132. The barrier layer 136 has a higher energy band gap than the channel layer 132. The gate semiconductor material layer 152a includes a material having an energy band gap different from that of the barrier layer 136.

[0080] As an example, the substrate 110 includes Si, the seed layer 121 includes AlN, and the buffer layer 122 includes GaN. The channel layer 132 includes GaN, and the barrier layer 136 includes AlGaN. The channel layer 132 and the barrier layer 136 may or may not be doped with impurities. The gate semiconductor material layer 152a includes GaN and is doped with impurities. The gate semiconductor material layer 152a is doped with a p-type impurity, for example, magnesium (Mg). Due to the difference in the lattice structures of Si and GaN, it may not be easy to grow the channel layer 132 made of GaN directly above the substrate 110 made of Si. In the method for manufacturing a semiconductor device according to this embodiment, after first forming the seed layer 121, the buffer layer 122, etc. on the substrate 110, the channel layer 132 is formed, so that the lattice structure of the channel layer 132 can be stably formed.

[0081] As shown in FIG. 20, a gate electrode material layer 155a is formed on the gate semiconductor material layer 152a. The gate semiconductor material layer 152a is disposed between the barrier layer 136 and the gate electrode material layer 155a. The gate electrode material layer 155a is formed using a deposition process. For example, the gate electrode material layer 155a can be formed using at least one of physical vapor deposition (PVD), thermal chemical vapor deposition (thermal CVD), low-pressure chemical vapor deposition (LP-CVD), plasma-enhanced chemical vapor deposition (PE-CVD), or atomic layer deposition (ALD) techniques, but is not limited thereto.

[0082] The gate electrode material layer 155a contains a conductive material. For example, the gate electrode material layer 155a may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal oxynitride, etc. For example, the gate electrode material layer 155a may include, but is not limited to, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof. The gate electrode material layer 155a may be composed of a single layer or multiple layers.

[0083] Next, as shown in FIG. 21, the gate electrode 155 and the gate semiconductor layer 152 are formed by patterning the gate electrode material layer 155a and the gate semiconductor material layer 152a using photolithography and etching processes. For example, a hard mask layer and a photoresist layer are sequentially formed on the gate electrode material layer 155a. The photoresist layer is patterned using a photolithography process to form a photoresist pattern. A hard mask pattern is formed by etching the hard mask layer using the photoresist pattern as a mask. By using the hard mask pattern as a mask to continuously etch the gate electrode material layer 155a and the gate semiconductor material layer 152a, at least a part of the gate electrode material layer 155a and the gate semiconductor material layer 152a is removed. As a result, the remaining part of the gate electrode material layer 155a becomes the gate electrode 155. Also, the remaining part of the gate semiconductor material layer 152a becomes the gate semiconductor layer 152. The gate semiconductor layer 152 is located between the barrier layer 136 and the gate electrode 155. The gate electrode 155 is in ohmic contact or schottky contact with the gate semiconductor layer 152.

[0084] By patterning the gate semiconductor material layer 152a and the gate electrode material layer 155a using the same mask, the gate semiconductor layer 152 and the gate electrode 155 have the same pattern. That is, the gate semiconductor layer 152 and the gate electrode 155 have the same planar shape. In cross-section, the gate semiconductor layer 152 and the gate electrode 155 have the same width. The gate semiconductor layer 152 completely overlaps the gate electrode 155 in the vertical direction, and the upper surface of the gate semiconductor layer 152 is entirely covered by the gate electrode 155. However, it is not limited to this. For example, the gate electrode 155 and the gate semiconductor layer 152 may have different widths. At this time, the gate electrode 155 and the gate semiconductor layer 152 can be patterned using different masks. As an example, the gate electrode 155 is patterned using a photoresist pattern, and the gate semiconductor layer 152 is patterned using a hard mask pattern.

[0085] As shown in FIG. 22, a protective layer 180 is formed on the barrier layer 136 and the gate electrode 155. The protective layer 180 is formed using a vapor deposition process. In one embodiment, the protective layer 180 includes an insulating material. For example, the protective layer 180 includes silicon oxide (SiO2). Alternatively, the protective layer 180 may include substances such as silicon nitride (SiN), aluminum oxide (Al2O3), and the like. In FIG. 22, the protective layer 180 is shown as a single layer, but in some cases, it may be composed of multiple layers. At this time, the protective layer 180 can be formed by sequentially depositing different substances. Alternatively, by varying the deposition conditions using the same substance, a protective layer 180 composed of various layers with different characteristics may be formed. The side surfaces of the gate electrode 155 and the gate semiconductor layer 152 are covered by the protective layer 180. The side surfaces of the gate electrode 155 and the gate semiconductor layer 152 are in contact with the protective layer 180. A step is generated between the portion of the protective layer 180 that overlaps the gate electrode 155 and the gate semiconductor layer 152 and the remaining portion. However, it is not limited to this, and in some cases, the upper surface of the protective layer 180 may be made entirely flat. For example, when the thickness of the protective layer 180 is formed relatively thick, no step is generated between the portion of the protective layer 180 that overlaps the gate electrode 155 and the gate semiconductor layer 152 and the remaining portion.

[0086] As shown in FIGS. 23 and 24, by patterning the protective layer 180 using photolithography and etching processes, a source / drain trench CT is formed. At this time, not only the protective layer 180 but also at least a part of the barrier layer 136 and the channel layer 132 are patterned together. For example, a photoresist pattern is formed on the protective layer 180, and using this as a mask, the protective layer 180, the barrier layer 136, and the channel layer 132 are sequentially etched to form a source / drain trench CT. At this time, the protective layer 180 and the barrier layer 136 are penetrated by the source / drain trench CT, and the upper surface of the channel layer 132 is recessed. The channel layer 132 is not penetrated by the source / drain trench CT. That is, the depth at which the upper surface of the channel layer 132 is recessed is smaller than the overall thickness of the channel layer 132. At this time, the depth at which the upper surface of the channel layer 132 is recessed is much smaller compared to the overall thickness of the channel layer 132. Also, the depth at which the upper surface of the channel layer 132 is recessed is smaller than the thickness of the barrier layer 136. However, it is not limited to this, and the depth at which the upper surface of the channel layer 132 is recessed can be variously changed.

[0087] In one embodiment, the source / drain trench CT is spaced apart from each other in the first direction (X direction) on both sides of the gate electrode 155. The source / drain trench CT has a rectangular shape in a plane. For example, the source / drain trench CT has a rectangular shape with the long side extending along the first direction (X direction). However, it is not limited to this, and the source / drain trench CT can have various shapes in a plane. The side surface of the source / drain trench CT is defined by the side surface of the channel layer 132, the side surface of the barrier layer 136, and the side surface of the protective layer 180. For example, the side surfaces of the source / drain trench CT facing each other in the first direction (X direction) are defined by the side surfaces of the channel layer 132 facing each other in the first direction (X direction), the side surfaces of the barrier layer 136 facing each other in the first direction (X direction), and the side surfaces of the protective layer 180 facing each other in the first direction (X direction). Also, the side surfaces of the source / drain trench CT facing each other in the second direction (Y direction) are defined by the side surfaces of the channel layer 132 facing each other in the second direction (Y direction), the side surfaces of the barrier layer 136 facing each other in the second direction (Y direction), and the side surfaces of the protective layer 180 facing each other in the second direction (Y direction).

[0088] In one embodiment, the step of forming the source / drain trench CT by etching both the channel layer 132 and the barrier layer 136 is performed using a dry etching process. At this time, the channel layer 132 and the barrier layer 136 are simultaneously etched using an etching material with a higher etching rate for the channel layer 132 than for the barrier layer 136. As an example, when the channel layer 132 contains GaN and the barrier layer 136 contains AlGaN, the channel layer 132 and the barrier layer 136 are etched using a material having a low etching rate with respect to aluminum (Al). In this case, a first angle θ1 between the first inclined surface SL1 of the barrier layer 136 and the lower surface (136_B) of the barrier layer 136 is formed to be smaller than a second angle θ2 between the second inclined surface SL2 of the channel layer 132 and the upper surface (132_U) of the channel layer 132.

[0089] As another example, as in the embodiments of FIGS. 10 to 14, when the channel layer 132 contains GaN, the barrier layer 136 contains AlGaN, and the spacer layer 135 contains AlN, the channel layer 132, the barrier layer 136, and the spacer layer 135 are etched using a material having a low etching rate with respect to aluminum (Al). In this case, a first angle θ1 between the first inclined surface SL1 of the barrier layer 136 and the lower surface (136_B) of the barrier layer 136 is formed to be smaller than a second angle θ2 between the second inclined surface SL2 of the channel layer 132 and the upper surface (132_U) of the channel layer 132. Also, a third angle θ3 between the third inclined surface SL3 of the spacer layer 135 and the lower surface of the spacer layer 135 is formed to be smaller than the first angle θ1 between the first inclined surface SL1 of the barrier layer 136 and the lower surface (136_B) of the barrier layer 136.

[0090] In this embodiment, by forming the first inclined surface SL1 of the barrier layer 136 and the second inclined surface SL2 of the channel layer 132 using a single etching process, the process can be simplified. As a result, as shown in FIG. 24, the side surfaces of the barrier layer 136 facing each other in the second direction (Y direction) include a first inclined surface SL1. The first inclined surface SL1 is a surface inclined at a predetermined angle from the lower surface (136_B) of the barrier layer 136. As an example, the first angle θ1 between the first inclined surface SL1 and the lower surface (136_B) of the barrier layer 136 is greater than 0° and equal to or less than 70°. In addition, the side surfaces of the channel layer 132 facing each other in the second direction (Y direction) include a second inclined surface SL2. The second inclined surface SL2 is a surface inclined at a predetermined angle from the upper surface (132_U) of the channel layer 132. The second angle θ2 between the second inclined surface SL2 and the upper surface (132_U) of the channel layer 132 is greater than or equal to the first angle θ1.

[0091] Referring to FIG. 25, impurities are doped into the first inclined surface SL1 of the barrier layer 136 and the upper surface (132_U) of the channel layer 132. For example, the first inclined surface SL1 of the barrier layer 136 and the upper surface (132_U) of the channel layer 132 are doped with n-type impurities. The first inclined surface SL1 of the barrier layer 136 and the upper surface (132_U) of the channel layer 132 are doped with Si, Ge, or a combination thereof. For example, impurities are doped into the first inclined surface SL1 of the barrier layer 136 and the upper surface (132_U) of the channel layer 132 by an ion implantation process, a plasma treatment process, a heat treatment process, or the like. At this time, since the barrier layer 136 includes the first inclined surface SL1 having a predetermined angle from the lower surface of the barrier layer 136, when the dopant TR is implanted in the third direction (Z direction), the first inclined surface SL1 of the barrier layer 136 can be easily doped. As a result, additional injection of carriers becomes possible through the first inclined surface SL1 of the barrier layer 136. In other words, the first inclined surface SL1 of the barrier layer 136 functions as an injection path for additional carriers.

[0092] Although not shown in the figure, in one embodiment, the second inclined surface SL2 of the channel layer 132 may be doped with impurities. In this case, since the second angle θ2 between the second inclined surface SL2 of the channel layer 132 and the upper surface of the channel layer 132 is greater than or equal to the first angle θ1 between the first inclined surface SL1 of the barrier layer 136 and the lower surface (136_B) of the barrier layer 136, the concentration of the impurities doped on the second inclined surface SL2 of the channel layer 132 is smaller than the concentration of the impurities ND doped on the upper surface (132_U) of the channel layer, but is not limited thereto.

[0093] As shown in FIGS. 26 and 27, a conductive material is deposited in the source / drain trench CT and patterned to form the source electrode 173 and the drain electrode 175. The source electrode 173 and the drain electrode 175 are formed on the upper surface (132_U) of the channel layer 132, the second inclined surface SL2 of the channel layer 132, the first inclined surface SL1 of the barrier layer 136, the side surface of the protective layer 180, and the upper surface of the protective layer 180. In the source / drain trench CT, the source electrode 173 is in contact with the channel layer 132 and the barrier layer 136. The source electrode 173 is in contact with the first inclined surface SL1 of the channel layer 132 and the barrier layer 136. The source electrode 173 covers the first inclined surface SL1 of the channel layer 132 and the barrier layer 136. The source electrode 173 is electrically connected to the channel layer 132 through the source / drain trench CT. Also, in the source / drain trench CT, the drain electrode 175 is in contact with the channel layer 132 and the barrier layer 136. The drain electrode 175 is in contact with the first inclined surface SL1 of the channel layer 132 and the barrier layer 136. The drain electrode 175 covers the first inclined surface SL1 of the channel layer 132 and the barrier layer 136. The drain electrode 175 is electrically connected to the channel layer 132 through the source / drain trench CT.

[0094] The source electrode 173 and the drain electrode 175 contain a conductive material. For example, the source electrode 173 and the drain electrode 175 may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal oxynitride. The source electrode 173 and the drain electrode 175 may be composed of a single layer or multiple layers. For example, after laminating a plurality of conductive layers containing different substances, this is patterned to form the source electrode 173 and the drain electrode 175. At this time, the plurality of conductive layers are etched simultaneously or sequentially using one mask pattern. For example, after sequentially laminating Ti, Al, Ti, and TiN, this is patterned to form the source electrode 173 and the drain electrode 175. At this time, the thicknesses of the four conductive layers constituting the source electrode 173 and the drain electrode 175 may be similar or different. For example, the layer made of Al may be relatively thicker than the other layers.

[0095] The source electrode 173 and the drain electrode 175 are in ohmic contact with the channel layer 132. Inside the channel layer 132, a two-dimensional electron gas 134 is formed in a portion adjacent to the barrier layer 136. The two-dimensional electron gas 134 is located at the interface between the channel layer 132 and the barrier layer 136. The two-dimensional electron gas 134 is located in the drift region DTR between the source electrode 173 and the drain electrode 175. A depletion region DPR is formed in the channel layer 132 by a gate semiconductor layer 152 having an energy band gap different from that of the barrier layer 136. Therefore, the semiconductor device according to the embodiment of the present invention has normally off characteristics. That is, the semiconductor device according to the embodiment of the present invention is a normally-off high electron mobility transistor (HEMT). In the gate-off state, the two-dimensional electron gas 134 is located in the drift region DTR excluding the depletion region DPR of the channel layer 132. In the gate-on state, the flow of the two-dimensional electron gas 134 is connected within the depletion region DPR, and the two-dimensional electron gas 134 is entirely located within the drift region DTR.

[0096] When forming the source electrode 173 and the drain electrode 175, the field dispersion layer 177 is formed together. The field dispersion layer 177 is disposed between the source electrode 173 and the drain electrode 175. The field dispersion layer 177 overlaps with the gate electrode 155. The field dispersion layer 177 is electrically connected to the source electrode 173. The field dispersion layer 177 can be integrated with the source electrode 173. The field dispersion layer 177 contains the same material as the source electrode 173 and is located in the same layer as the source electrode 173.

[0097] According to the method for manufacturing a semiconductor device according to the embodiment of the present invention, the source electrode 173 and the drain electrode 175 are formed on the first inclined surface SL1 having a predetermined angle from the lower surface of the barrier layer 136. At this time, the first inclined surface SL1 of the barrier layer 136 is doped with impurities, which functions as an injection path for carriers. Therefore, additional carrier injection is possible through the first inclined surface SL1 of the barrier layer 136, and the contact resistance between the source electrode 173 and the drain electrode 175 and the semiconductor layer (for example, the barrier layer 136 and the channel layer 132) can be improved. That is, the semiconductor device according to the embodiment of the present invention can have stable electrical characteristics. In addition, since the barrier layer 136 includes the first inclined surface SL1 and the channel layer 132 includes the second inclined surface SL2, the source electrode 173 and the drain electrode 175 can be easily formed on the side surfaces of the barrier layer 136 and the channel layer 132. That is, the step coverage for forming the source electrode 173 and the drain electrode 175 is improved, and thereby, the source electrode 173 and the drain electrode 175 can have stable electrical characteristics.

[0098] Note that the present invention is not limited to the above-described embodiments. Various modifications can be made without departing from the technical scope of the present invention.

Explanation of Reference Numerals

[0099] 110 Substrate 121 Seed layer 122 Buffer layer 132 Channel layer 134 Two-dimensional electron gas 136 Barrier layer 152 Gate semiconductor layer 155 Gate electrode 173 Source electrode 175 Drain electrode 177 Field dispersion layer 180 Protection layer

Claims

1. A channel layer; a barrier layer disposed on the channel layer and including a material having a different energy band gap than the channel layer; a gate electrode disposed on the barrier layer; a gate semiconductor layer disposed between the barrier layer and the gate electrode; a source electrode and a drain electrode disposed on both sides of the gate electrode, penetrating at least a part of the barrier layer and the channel layer to cover a side surface of the barrier layer and a side surface of the channel layer, a side surface of the barrier layer is inclined from an upper surface of the channel layer and includes a first inclined surface doped with an impurity; a side surface of the channel layer including a second inclined surface inclined from an upper surface of the channel layer; a first angle between a lower surface of the barrier layer and a first inclined surface of the barrier layer is smaller than or equal to a second angle between an upper surface of the channel layer and a second inclined surface of the channel layer.

2. The semiconductor device of claim 1 , wherein the first angle is greater than 0 degrees and is equal to or smaller than 70 degrees.

3. The semiconductor device of claim 1 , wherein the first inclined surface of the barrier layer is doped with an n-type impurity.

4. The semiconductor device of claim 1 , wherein the impurities include Si, Ge, or a combination thereof.

5. a spacer layer between the channel layer and the barrier layer; The semiconductor device of claim 1 , wherein a side surface of the spacer layer includes a third inclined surface inclined from an upper surface of the channel layer.

6. The gate electrode extends in a first direction, side surfaces of the barrier layers facing each other in the first direction include first inclined surfaces inclined from an upper surface of the channel layer, side surfaces of the channel layer facing each other in the first direction include second inclined surfaces inclined from an upper surface of the channel layer, 2. The semiconductor device of claim 1, wherein a first angle between a lower surface of the barrier layer and a first inclined surface of the barrier layer is smaller than or equal to a second angle between an upper surface of the channel layer and a second inclined surface of the channel layer.

7. The semiconductor device of claim 6 , wherein a width of the upper surface of the barrier layer in the first direction is smaller than a width of a lower surface of the barrier layer in the first direction.

8. A channel layer; a barrier layer disposed on the channel layer and including a material having a different energy band gap than the channel layer; a gate electrode disposed on the barrier layer; a gate semiconductor layer disposed between the barrier layer and the gate electrode; a source electrode and a drain electrode disposed on both sides of the gate electrode, penetrating at least a part of the barrier layer and the channel layer to cover a side surface of the barrier layer and a side surface of the channel layer, a side surface of the barrier layer is inclined from an upper surface of the channel layer and includes a first inclined surface doped with an impurity; A semiconductor device, wherein a first angle between a lower surface of the barrier layer and a first inclined surface of the barrier layer is greater than 0 degrees and is not greater than 70 degrees.

9. a side surface of the channel layer including a second inclined surface inclined from an upper surface of the channel layer; 9. The semiconductor device of claim 8, wherein the first angle is less than or equal to a second angle between an upper surface of the channel layer and a second inclined surface of the channel layer.

10. A substrate; a channel layer comprising GaN on the substrate; a barrier layer disposed on the channel layer and comprising AlGaN; a gate electrode extending in a first direction and disposed on the barrier layer, the gate electrode including a metal material; a gate semiconductor layer extending in the first direction, disposed between the barrier layer and the gate electrode, and including GaN doped with p-type impurities; a source electrode and a drain electrode disposed on both sides of the gate electrode and spaced apart in a second direction intersecting the first direction, penetrating at least a portion of the barrier layer and the channel layer to cover a side surface of the barrier layer and a side surface of the channel layer, side surfaces of the barrier layers facing each other in the first direction include first inclined surfaces inclined from an upper surface of the channel layer and doped with an impurity; side surfaces of the channel layer facing each other in the first direction include second inclined surfaces inclined from an upper surface of the channel layer, a first angle between a lower surface of the barrier layer and a first inclined surface of the barrier layer is smaller than or equal to a second angle between an upper surface of the channel layer and a second inclined surface of the channel layer.

Images