Liquid crystal display

Abstract

To provide a semiconductor device having a configuration capable of sufficiently reducing parasitic capacitance between wires.SOLUTION: In a thin film transistor of a bottom gate structure, an oxide insulating layer as a channel protection layer is formed on a part of an oxide semiconductor layer overlapping with a gate electrode layer, and when the oxide insulating layer is formed, an oxide insulating layer covering the periphery (including the side) of the oxide semiconductor layer is formed. The oxide insulating layer covering the periphery (including the side) of the oxide semiconductor increases the distance between the gate electrode layer and the wiring layers (source wiring layer, capacitor wiring layer, etc.) formed above or around the gate electrode layer to thereby reduce the parasitic capacitance. Since the oxide insulating layer covering the periphery of the oxide semiconductor layer is formed in the same step as that of the channel protection layer, the parasitic capacitance can be reduced without increasing the number of steps.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device using an oxide semiconductor and a method for manufacturing the same.

[0002] In the present specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. In general, electro-optical devices such as display devices, semiconductor circuits, and electronic devices are all semiconductor devices. There is.

Background Art

[0003] In recent years, a technique for forming a thin film transistor (TFT) using a semiconductor thin film (with a thickness of about several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. The thin film transistor is widely applied to electronic devices such as ICs and electro-optical devices, and in particular, development is being accelerated as a switching element for image display devices. Metal oxides exist in various forms and are used in various applications. Indium oxide is a well-known material and is used as a transparent electrode material required in liquid crystal displays and the like. There are some metal oxides that exhibit semiconductor characteristics. Examples of metal oxides that exhibit semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. A thin film transistor having such a metal oxide exhibiting semiconductor characteristics as a channel formation region is already known (Patent Document 1 and Patent Document 2).

[0004]

[0004] Among metal oxides, some exhibit semiconductor characteristics. Examples of metal oxides that exhibit semiconductor characteristics include, for example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. A thin film transistor having such a metal oxide exhibiting semiconductor characteristics as a channel formation region is already known.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0006] When manufacturing a plurality of thin film transistors on an insulating surface, for example, there is a portion where a gate wiring and a source wiring cross each other. An insulating layer is provided between the crossing portion, between the gate wiring and the source wiring having a different potential from the gate wiring, and the insulating layer becomes a dielectric to form a capacitance. This capacitance is also called a parasitic capacitance between wirings, and there is a risk that the signal waveform will be distorted. Also, if the parasitic capacitance is large, there is a risk that the signal transmission will be slow.

[0007] In addition, an increase in parasitic capacitance leads to a crosstalk phenomenon in which an electrical signal leaks between wirings and an increase in power consumption.

[0008] Also, in an active matrix type display device, particularly when a large parasitic capacitance is formed between a signal wiring for supplying a video signal and another wiring or electrode, there is a risk that the display quality will deteriorate.

[0009] Also, even when attempting to miniaturize a circuit, the wiring interval becomes narrow, and there is a risk that the parasitic capacitance between wirings will increase.

[0010] One aspect of the present invention is to provide a semiconductor device having a configuration capable of sufficiently reducing the parasitic capacitance between wirings. This is one of the problems.

[0011] Also, when forming a drive circuit on an insulating surface, the operating speed of the thin film transistor used in the drive circuit is preferably fast.

[0012] For example, the channel length (L) of a thin-film transistor can be shortened or the channel width (W) can be widened. However, shortening the channel length reduces the switching characteristics, e.g. For example, the on / off ratio becomes smaller. Also, if the channel width W is widened, the thin-film transistor However, this increases the capacity load on the master itself.

[0013] In addition, a semiconductor device having a thin film transistor with stable electrical characteristics even if the channel length is short is also provided. It is also an object of the present invention to provide a body device.

[0014] In addition, when forming a plurality of different circuits on an insulating surface, for example, a pixel portion and a driver circuit may be formed on the same substrate. When formed on a substrate, the thin film transistor used in the pixel portion must have excellent switching characteristics. For example, a large on-off ratio is required, and the thin film transistors used in the drive circuits Fast operation speed is required. In particular, the higher the resolution of the display device, Since the time it takes to write a display image is shortened, the thin-film transistors used in the driver circuits operate faster. It is preferable to use speed.

[0015] In addition, multiple types of circuits can be formed on the same substrate, and multiple It is another object of the present invention to provide a semiconductor device including such a thin film transistor. [Means for solving the problem]

[0016] In a bottom-gate thin film transistor, a gate electrode layer and an oxide semiconductor layer overlap each other. An oxide insulating layer is formed on a part of the channel to serve as a channel protection layer. An oxide insulating layer is formed to cover the periphery (including the side surfaces) of the semiconductor layer.

[0017] The oxide insulating layer that covers the peripheral portion (including the side surface) of the oxide semiconductor layer is separated from the gate electrode layer and the wiring layer (such as the source wiring layer and the capacitor wiring layer) formed above or around it to increase the distance, thereby reducing the parasitic capacitance. Since the oxide insulating layer that covers the peripheral portion of the oxide semiconductor layer is formed in the same process as the channel protection layer, the parasitic capacitance can be reduced without increasing the number of processes. The oxide insulating layer that covers the peripheral portion (including the side surface) of the oxide semiconductor layer can reduce the parasitic capacitance and suppress the signal waveform distortion. In order to reduce the parasitic capacitance, it is preferable to use an insulating material with a low dielectric constant as the oxide insulating layer sandwiched between the wirings. By providing an oxide insulating layer that covers the peripheral portion (including the side surface) of the oxide semiconductor layer, the parasitic capacitance can be minimized as much as possible, and the high-speed operation of the thin-film transistor can be realized. Also, by using a thin-film transistor with a high operating speed, the circuit integration density can be improved.

[0018] One aspect of the present invention disclosed in this specification includes a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, an oxide insulating layer on the oxide semiconductor layer, and a source electrode layer or a drain electrode layer on the oxide insulating layer. The oxide semiconductor layer has a first region in contact with the oxide insulating layer and a second region in contact with the source electrode layer or the drain electrode layer. The first region has a channel formation region overlapping with the gate electrode layer through the gate insulating layer and a region overlapping with the oxide insulating layer that covers the periphery and side surfaces of the oxide semiconductor layer. The end face of the oxide semiconductor layer is separated from the wiring layer through the oxide insulating layer. The oxide insulating layer that covers the peripheral portion (including the side surface) of the oxide semiconductor layer can reduce the parasitic capacitance and suppress the signal waveform distortion.

[0019] In order to reduce the parasitic capacitance, it is preferable to use an insulating material with a low dielectric constant as the oxide insulating layer sandwiched between the wirings. By providing an oxide insulating layer that covers the peripheral portion (including the side surface) of the oxide semiconductor layer, the parasitic capacitance can be minimized as much as possible, and the high-speed operation of the thin-film transistor can be realized. Also, by using a thin-film transistor with a high operating speed, the circuit integration density can be improved.

[0020] One aspect of the present invention disclosed in this specification includes a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, an oxide insulating layer on the oxide semiconductor layer, and a source electrode layer or a drain electrode layer on the oxide insulating layer. The oxide semiconductor layer has a first region in contact with the oxide insulating layer and a second region in contact with the source electrode layer or the drain electrode layer. The first region has a channel formation region overlapping with the gate electrode layer through the gate insulating layer and a region overlapping with the oxide insulating layer that covers the periphery and side surfaces of the oxide semiconductor layer. The end face of the oxide semiconductor layer is separated from the wiring layer through the oxide insulating layer. The oxide insulating layer that covers the peripheral portion (including the side surface) of the oxide semiconductor layer can reduce the parasitic capacitance and suppress the signal waveform distortion. In order to reduce the parasitic capacitance, it is preferable to use an insulating material with a low dielectric constant as the oxide insulating layer sandwiched between the wirings.

[0021] One aspect of the present invention disclosed in this specification includes a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, an oxide insulating layer on the oxide semiconductor layer, and a source electrode layer or a drain electrode layer on the oxide insulating layer. The oxide semiconductor layer has a first region in contact with the oxide insulating layer and a second region in contact with the source electrode layer or the drain electrode layer. The first region has a channel formation region overlapping with the gate electrode layer through the gate insulating layer and a region overlapping with the oxide insulating layer that covers the periphery and side surfaces of the oxide semiconductor layer. The end face of the oxide semiconductor layer is separated from the wiring layer through the oxide insulating layer. The oxide insulating layer that covers the peripheral portion (including the side surface) of the oxide semiconductor layer can reduce the parasitic capacitance and suppress the signal waveform distortion. In order to reduce the parasitic capacitance, it is preferable to use an insulating material with a low dielectric constant as the oxide insulating layer sandwiched between the wirings. One aspect of the present invention disclosed in this specification includes a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, an oxide insulating layer on the oxide semiconductor layer, and a source electrode layer or a drain electrode layer on the oxide insulating layer. The oxide semiconductor layer has a first region in contact with the oxide insulating layer and a second region in contact with the source electrode layer or the drain electrode layer. The first region has a channel formation region overlapping with the gate electrode layer through the gate insulating layer and a region overlapping with the oxide insulating layer that covers the periphery and side surfaces of the oxide semiconductor layer. The end face of the oxide semiconductor layer is separated from the wiring layer through the oxide insulating layer. The oxide insulating layer that covers the peripheral portion (including the side surface) of the oxide semiconductor layer can reduce the parasitic capacitance and suppress the signal waveform distortion. In order to reduce the parasitic capacitance, it is preferable to use an insulating material with a low dielectric constant as the oxide insulating layer sandwiched between the wirings. One aspect of the present invention disclosed in this specification includes a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, an oxide insulating layer on the oxide semiconductor layer, and a source electrode layer or a drain electrode layer on the oxide insulating layer. The oxide semiconductor layer has a first region in contact with the oxide insulating layer and a second region in contact with the source electrode layer or the drain electrode layer. The first region has a channel formation region overlapping with the gate electrode layer through the gate insulating layer and a region overlapping with the oxide insulating layer that covers the periphery and side surfaces of the oxide semiconductor layer. The end face of the oxide semiconductor layer is separated from the wiring layer through the oxide insulating layer. is a semiconductor device that overlaps with the source electrode layer or the drain electrode layer.

[0022] The above configuration solves at least one of the above problems.

[0023] Also, one aspect of the present invention for realizing the above structure includes a gate electrode layer, and on the gate electrode layer a gate insulating layer, an oxide semiconductor layer on the gate insulating layer, and on the oxide semiconductor layer an oxide insulating layer, a source electrode layer or a drain electrode layer on the oxide insulating layer, and on the source electrode layer or the drain electrode layer a protective insulating layer, wherein the oxide semiconductor layer has a first region in contact with the oxide insulating layer, a second region in contact with the source electrode layer or the drain layer, and a third region in contact with the protective insulating layer, and in the first region, a region overlapping through the gate electrode layer and the gate insulating layer is a channel formation region, and the semiconductor device has the third region between the channel formation region and the second region. .

[0024] Also, the oxide semiconductor used in this specification forms a thin film represented by, for example, InMO3(ZnO) m (m>0) and manufactures a thin film transistor using the thin film as an oxide semiconductor layer. Note that M represents one metal element selected from Ga, Fe, Ni, Mn, and Co or a plurality of metal elements. For example, in addition to the case where M is Ga, there may be cases where Ga and Ni or Ga and Fe, etc., and the above metal elements other than Ga are included. Also, in the above oxide semi conductor, in addition to the metal elements included as M, there are those containing impurity elements such as Fe, Ni, and other transition metal elements, or oxides of the transition metals. In this specification InMO3(ZnO) is used.m Among the oxide semiconductor layers having a structure represented by (m>0), an oxide semiconductor having a structure containing Ga as M is referred to as an In-Ga-Zn-O-based oxide semiconductor, and its thin film is also referred to as an In-Ga-Zn-O-based non-single crystal film.

[0025] In addition to the above, as the metal oxide applied to the oxide semiconductor layer, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn -Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In- O system, Sn-O system, Zn-O system metal oxides can be applied. Further, silicon oxide may be included in the oxide semiconductor layer made of the above metal oxide.

[0026] When heat treatment is performed in an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.), the oxide semiconductor layer becomes oxygen-deficient type by heat treatment and has a lower resistance, that is, is N-type ([ N type conversion, etc.). Then, by forming an oxide insulating film in contact with the oxide semiconductor layer or performing heat treatment after formation, the oxide semiconductor layer is made into an oxygen-excessive state, resulting in a higher resistance, that is, - It can also be said that it is converted to the I type. In addition, solid-phase oxidation is performed to make the oxide semiconductor layer in an oxygen-excessive state. By this, it becomes possible to fabricate and provide a semiconductor device having a thin film transistor with good electrical characteristics and high reliability.

[0027] Dehydration or dehydrogenation is performed by heat treatment at 400 °C or higher and lower than the strain point of the substrate, preferably 420 °C or higher and 570 °C or lower, in an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.) to reduce impurities such as the contained moisture in the oxide semiconductor layer.

[0028] ​​​​​​ The oxide semiconductor layer that has undergone dehydration or dehydrogenation is such that when measured by TDS up to 450 °C for the oxide semiconductor layer after dehydration or dehydrogenation, two peaks of water and at least one peak that appears around 300 °C are not detected. Therefore, when measuring up to 450 °C by TDS for a thin film transistor using the oxide semiconductor layer that has undergone dehydration or dehydrogenation, a peak of water that appears around at least 300 °C is not detected. When measuring up to 450 °C by TDS for the oxide semiconductor layer after dehydration or dehydrogenation, two peaks of water and at least one peak that appears around 300 °C are not detected. When measuring up to 450 °C by TDS for the oxide semiconductor layer after dehydration or dehydrogenation, two peaks of water and at least one peak that appears around 300 °C are not detected. When measuring up to 450 °C by TDS for a thin film transistor using the oxide semiconductor layer that has undergone dehydration or dehydrogenation, a peak of water that appears around at least 300 °C is not detected. When measuring up to 450 °C by TDS for a thin film transistor using the oxide semiconductor layer that has undergone dehydration or dehydrogenation, a peak of water that appears around at least 300 °C is not detected.

[0029] Then, when lowering the temperature from the heating temperature T at which dehydration or dehydrogenation is performed on the oxide semiconductor layer, it is important not to expose it to the atmosphere using the same furnace in which dehydration or dehydrogenation has been performed, so that water or hydrogen is not mixed in again. After performing dehydration or dehydrogenation to reduce the resistance of the oxide semiconductor layer, that is, to make it N-type (such as N), etc., and then increasing the resistance to make it an I-type oxide semiconductor layer, when manufacturing a thin film transistor using the oxide semiconductor layer, the threshold voltage value of the thin film transistor can be programmed, and a so-called normally-off switching element can be realized. It is desirable for a semiconductor device (display device) that a channel is formed at a positive threshold voltage as close as possible to 0 V for the gate voltage of the thin film transistor. When the threshold voltage value of the thin film transistor is negative, a current easily flows between the source electrode and the drain electrode even when the gate voltage is 0 V, which is a so-called normally-on state. In an active matrix type display device, the electrical characteristics of the thin film transistors constituting the circuit are important, and these electrical characteristics affect the performance of the display device. In particular, among the electrical characteristics of the thin film transistor, the threshold voltage (Vth) is important. Even if the field effect mobility is high, if the threshold voltage value is high, or if the threshold voltage value is negative, Then, when lowering the temperature from the heating temperature T at which dehydration or dehydrogenation is performed on the oxide semiconductor layer, it is important not to expose it to the atmosphere using the same furnace in which dehydration or dehydrogenation has been performed, so that water or hydrogen is not mixed in again. After performing dehydration or dehydrogenation to reduce the resistance of the oxide semiconductor layer, that is, to make it N-type (such as N), etc., and then increasing the resistance to make it an I-type oxide semiconductor layer, when manufacturing a thin film transistor using the oxide semiconductor layer, the threshold voltage value of the thin film transistor can be programmed, and a so-called normally-off switching element can be realized. After performing dehydration or dehydrogenation to reduce the resistance of the oxide semiconductor layer, that is, to make it N-type (such as N), etc., and then increasing the resistance to make it an I-type oxide semiconductor layer, when manufacturing a thin film transistor using the oxide semiconductor layer, the threshold voltage value of the thin film transistor can be programmed, and a so-called normally-off switching element can be realized. - After performing dehydration or dehydrogenation to reduce the resistance of the oxide semiconductor layer, that is, to make it N-type (such as N), etc., and then increasing the resistance to make it an I-type oxide semiconductor layer, when manufacturing a thin film transistor using the oxide semiconductor layer, the threshold voltage value of the thin film transistor can be programmed, and a so-called normally-off switching element can be realized. After performing dehydration or dehydrogenation to reduce the resistance of the oxide semiconductor layer, that is, to make it N-type (such as N), etc., and then increasing the resistance to make it an I-type oxide semiconductor layer, when manufacturing a thin film transistor using the oxide semiconductor layer, the threshold voltage value of the thin film transistor can be programmed, and a so-called normally-off switching element can be realized. After performing dehydration or dehydrogenation to reduce the resistance of the oxide semiconductor layer, that is, to make it N-type (such as N), etc., and then increasing the resistance to make it an I-type oxide semiconductor layer, when manufacturing a thin film transistor using the oxide semiconductor layer, the threshold voltage value of the thin film transistor can be programmed, and a so-called normally-off switching element can be realized. It is desirable for a semiconductor device (display device) that a channel is formed at a positive threshold voltage as close as possible to 0 V for the gate voltage of the thin film transistor. It is desirable for a semiconductor device (display device) that a channel is formed at a positive threshold voltage as close as possible to 0 V for the gate voltage of the thin film transistor. When the threshold voltage value of the thin film transistor is negative, a current easily flows between the source electrode and the drain electrode even when the gate voltage is 0 V, which is a so-called normally-on state. When the threshold voltage value of the thin film transistor is negative, a current easily flows between the source electrode and the drain electrode even when the gate voltage is 0 V, which is a so-called normally-on state. In an active matrix type display device, the electrical characteristics of the thin film transistors constituting the circuit are important, and these electrical characteristics affect the performance of the display device. In an active matrix type display device, the electrical characteristics of the thin film transistors constituting the circuit are important, and these electrical characteristics affect the performance of the display device. In particular, among the electrical characteristics of the thin film transistor, the threshold voltage (Vth) is important. Even if the field effect mobility is high, if the threshold voltage value is high, or if the threshold voltage value is negative, If it is indium, it is difficult to control as a circuit. The threshold voltage value is high, and in the case of a thin film transistor with a large absolute value of the threshold voltage, when the drive voltage is low, it cannot perform the switching function as a TFT and may become a load. In the case of an n-channel thin film transistor, it is desirable that a channel is formed and a drain current flows only when a positive voltage is applied to the gate voltage. A transistor that cannot form a channel unless the drive voltage is increased, or a transistor that forms a channel and allows a drain current to flow even in a negative voltage state is not suitable as a thin film transistor used in a circuit. In the case of a thin film transistor with a high threshold voltage value and a large absolute value of the threshold voltage, when the drive voltage is low, it cannot perform the switching function as a TFT and may become a load. In the case of an n-channel thin film transistor, it is desirable that a channel is formed and a drain current flows only when a positive voltage is applied to the gate voltage. A transistor that cannot form a channel unless the drive voltage is increased, or a transistor that forms a channel and allows a drain current to flow even in a negative voltage state is not suitable as a thin film transistor used in a circuit. In the case of an n-channel thin film transistor, it is desirable that a channel is formed and a drain current flows only when a positive voltage is applied to the gate voltage. A transistor that cannot form a channel unless the drive voltage is increased, or a transistor that forms a channel and allows a drain current to flow even in a negative voltage state is not suitable as a thin film transistor used in a circuit. A transistor that cannot form a channel unless the drive voltage is increased, or a transistor that forms a channel and allows a drain current to flow even in a negative voltage state is not suitable as a thin film transistor used in a circuit. A transistor that cannot form a channel unless the drive voltage is increased, or a transistor that forms a channel and allows a drain current to flow even in a negative voltage state is not suitable as a thin film transistor used in a circuit.

[0030] Also, the gas atmosphere that is lowered from the heating temperature T may be switched to a gas atmosphere different from the gas atmosphere that has been heated up to the heating temperature T. For example, without exposing to the atmosphere in the same furnace that has been dehydrated or dehydrogenated, the inside of the furnace is filled with high-purity oxygen gas or N2O gas, or ultra-dry air (dew point is -40°C or lower, preferably -60°C or lower) and cooled. Also, the gas atmosphere that is lowered from the heating temperature T may be switched to a gas atmosphere different from the gas atmosphere that has been heated up to the heating temperature T. For example, without exposing to the atmosphere in the same furnace that has been dehydrated or dehydrogenated, the inside of the furnace is filled with high-purity oxygen gas or N2O gas, or ultra-dry air (dew point is -40°C or lower, preferably -60°C or lower) and cooled. After reducing the contained moisture in the film by heat treatment for dehydration or dehydrogenation, the electrical characteristics of the thin film transistor are improved using an oxide semiconductor film that has been slowly cooled (or cooled) under an atmosphere containing no moisture (dew point is -40°C or lower, preferably -60°C or lower), and a thin film transistor having both mass productivity and high performance is realized. After reducing the contained moisture in the film by heat treatment for dehydration or dehydrogenation, the electrical characteristics of the thin film transistor are improved using an oxide semiconductor film that has been slowly cooled (or cooled) under an atmosphere containing no moisture (dew point is -40°C or lower, preferably -60°C or lower), and a thin film transistor having both mass productivity and high performance is realized.

[0031] After reducing the contained moisture in the film by heat treatment for dehydration or dehydrogenation, the electrical characteristics of the thin film transistor are improved using an oxide semiconductor film that has been slowly cooled (or cooled) under an atmosphere containing no moisture (dew point is -40°C or lower, preferably -60°C or lower), and a thin film transistor having both mass productivity and high performance is realized. After reducing the contained moisture in the film by heat treatment for dehydration or dehydrogenation, the electrical characteristics of the thin film transistor are improved using an oxide semiconductor film that has been slowly cooled (or cooled) under an atmosphere containing no moisture (dew point is -40°C or lower, preferably -60°C or lower), and a thin film transistor having both mass productivity and high performance is realized. After reducing the contained moisture in the film by heat treatment for dehydration or dehydrogenation, the electrical characteristics of the thin film transistor are improved using an oxide semiconductor film that has been slowly cooled (or cooled) under an atmosphere containing no moisture (dew point is -40°C or lower, preferably -60°C or lower), and a thin film transistor having both mass productivity and high performance is realized. After reducing the contained moisture in the film by heat treatment for dehydration or dehydrogenation, the electrical characteristics of the thin film transistor are improved using an oxide semiconductor film that has been slowly cooled (or cooled) under an atmosphere containing no moisture (dew point is -40°C or lower, preferably -60°C or lower), and a thin film transistor having both mass productivity and high performance is realized.

[0032] In this specification, heat treatment under an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium) is called heat treatment for dehydration or dehydrogenation. In this specification, it is not only the desorption as H2 by this heat treatment that is called dehydrogenation, but also H In this specification, heat treatment under an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium) is called heat treatment for dehydration or dehydrogenation. In this specification, it is not only the desorption as H2 by this heat treatment that is called dehydrogenation, but also H In this specification, heat treatment under an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium) is called heat treatment for dehydration or dehydrogenation. In this specification, it is not only the desorption as H2 by this heat treatment that is called dehydrogenation, but also H Dehydration or dehydrogenation, including the elimination of OH and the like, shall be referred to as dehydration or dehydrogenation for convenience.

[0033] Heat treatment is performed in an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.). When this is done, the oxide semiconductor layer becomes oxygen-deficient by the heat treatment, resulting in a lower resistance, that is, it becomes N-type ( N - type conversion, etc.).

[0034] In addition, a high-resistance drain region (also referred to as an HRD (High Resistance Drain) region) that is oxygen-deficient and overlaps with the drain electrode layer is formed. Also, a source electrode layer and a high-resistance source region (also referred to as an HRS (High Resistance e Source) region) that is oxygen-deficient and overlaps with the source electrode layer is formed.

[0035] Specifically, the carrier concentration of the high-resistance drain region is within the range of 1×10 18 / cm 3 or higher, and is higher than at least the carrier concentration (less than 1×10 / cm 18 / cm 3 of the channel formation region). Note that the carrier concentration in this specification refers to the value of the carrier concentration obtained from Hall effect measurement at room temperature. By making at least a part of the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excess state, the resistance is further increased, that is, it is made into the I-type to form the channel formation region. Note that, as a treatment for making the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excess state, there are film formation of an oxide insulating film in contact with the dehydrated or dehydrogenated oxide semiconductor layer by sputtering, or heat treatment after film formation of the oxide insulating film, or heat treatment in an atmosphere containing oxygen, or in an inert gas atmosphere

[0036] And by making at least a part of the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excess state, the resistance is further increased, that is, it is made into the I-type to form the channel formation region. Note that, as a treatment for making the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excess state, there are film formation of an oxide insulating film in contact with the dehydrated or dehydrogenated oxide semiconductor layer by sputtering, or heat treatment after film formation of the oxide insulating film, or heat treatment in an atmosphere containing oxygen, or in an inert gas atmosphere By making at least a part of the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excess state, the resistance is further increased, that is, it is made into the I-type to form the channel formation region. Note that, as a treatment for making the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excess state, there are film formation of an oxide insulating film in contact with the dehydrated or dehydrogenated oxide semiconductor layer by sputtering, or heat treatment after film formation of the oxide insulating film, or heat treatment in an atmosphere containing oxygen, or in an inert gas atmosphere By making at least a part of the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excess state, the resistance is further increased, that is, it is made into the I-type to form the channel formation region. Note that, as a treatment for making the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excess state, there are film formation of an oxide insulating film in contact with the dehydrated or dehydrogenated oxide semiconductor layer by sputtering, or heat treatment after film formation of the oxide insulating film, or heat treatment in an atmosphere containing oxygen, or in an inert gas atmosphere By making at least a part of the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excess state, the resistance is further increased, that is, it is made into the I-type to form the channel formation region. Note that, as a treatment for making the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excess state, there are film formation of an oxide insulating film in contact with the dehydrated or dehydrogenated oxide semiconductor layer by sputtering, or heat treatment after film formation of the oxide insulating film, or heat treatment in an atmosphere containing oxygen, or in an inert gas atmosphere By making at least a part of the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excess state, the resistance is further increased, that is, it is made into the I-type to form the channel formation region. Note that, as a treatment for making the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excess state, there are film formation of an oxide insulating film in contact with the dehydrated or dehydrogenated oxide semiconductor layer by sputtering, or heat treatment after film formation of the oxide insulating film, or heat treatment in an atmosphere containing oxygen, or in an inert gas atmosphere After heating in an atmosphere, it is cooled in an oxygen atmosphere, or by a process of cooling with ultra-dry air (dew point of -40°C or lower, preferably -60°C or lower).

[0037] Also, at least a part of the dehydrated or dehydrogenated oxide semiconductor layer (the part overlapping with the gate electrode layer) is used as the channel formation region, and by selectively making it in an oxygen-excessive state, high resistance formation, that is, type-I conversion can also be achieved. As a result, it becomes possible to fabricate and provide a semiconductor device having a thin film transistor with good electrical characteristics and high reliability.

[0038]

[0039] In addition, by forming a high resistance drain region in the oxide semiconductor layer overlapping with the drain electrode layer, the reliability can be improved when forming a drive circuit. Specifically, by forming a high resistance drain region, a structure can be obtained in which the conductivity can be changed stepwise from the drain electrode layer to the high resistance drain region and the channel formation region. Therefore, when operating by connecting to a wiring for supplying a high power supply potential VDD to the drain electrode layer, even if a high electric field is applied between the gate electrode layer and the drain electrode layer, the high resistance drain region serves as a buffer and a local high electric field is not applied, and a configuration can be obtained in which the breakdown voltage of the transistor is improved.

[0040] Also, by forming a high resistance drain region in the oxide semiconductor layer overlapping with the drain electrode layer (and the source electrode layer), the leakage current in the channel formation region can be reduced when forming a drive circuit. Specifically, by forming a high resistance drain region, the drain ​​​​​​As a path of the leakage current of the transistor flowing between the rain electrode layer and the source electrode layer, the rain electrode layer, the high-resistance drain region on the drain electrode layer side, the channel formation region, the source electrode layer, and the high-resistance source region on the source electrode layer side are arranged in this order. At this time, in the channel formation region, the leakage current flowing from the high-resistance drain region on the rain electrode layer side to the channel region is concentrated near the interface between the gate insulating layer, which becomes high resistance when the transistor is off, and the channel formation region, so that the leakage current in the back channel portion (a part of the surface of the channel formation region away from the gate electrode layer) can be reduced.

[0041] Also, the high-resistance source region overlapping the source electrode layer and the high-resistance drain region overlapping the drain electrode layer overlap with a part of the gate electrode layer via the gate insulating layer, depending on the width of the gate electrode layer, and the electric field strength near the end of the drain electrode layer can be more effectively relaxed.

[0042] In addition, as a display device having a driving circuit, in addition to a liquid crystal display device, a light-emitting display device using a light-emitting element and a display device also referred to as an electronic paper using an electrophoretic display element can be mentioned.

[0043] In a light-emitting display device using a light-emitting element, a plurality of thin-film transistors are provided in a pixel portion, and there is a portion where the gate electrode of a thin-film transistor in the pixel portion is connected to the source wiring or the drain wiring of another transistor. Further, in the driving circuit of the light-emitting display device using a light-emitting element, there is a portion where the gate electrode of the thin-film transistor is connected to the source wiring or the drain wiring of the thin-film transistor.

[0044] ​​​​In addition, since thin film transistors are easily damaged by static electricity or the like, it is preferable to provide a protection circuit for protecting the thin film transistors in the pixel portion on the same substrate with respect to the gate line or the source line. The protection circuit is preferably configured using a non-linear element using an oxide semiconductor layer.

[0045] Note that the ordinal numbers attached as the first and second are used for convenience and do not indicate the process order or the stacking order. Also, the unique names used as matters for specifying the invention in this specification do not indicate anything.

Effects of the Invention

[0046] A semiconductor device including a thin film transistor having sufficiently reduced parasitic capacitance and stable electrical characteristics even with a short channel length is realized.

Brief Description of the Drawings

[0047]

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Mode for Carrying Out the Invention

[0048] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed. Also, the present invention is not construed as being limited to the description of the embodiments shown below. In the configurations described below, the same parts or parts having the same functions are commonly used with the same reference numerals among different drawings, and the repeated description thereof is omitted.

[0049] (Embodiment 1) In this embodiment, one form of a semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS. 1, 2, 3, and 4.

[0050] Further, FIG. 1(A) is a plan view of a channel protection type thin film transistor 448 disposed in a pixel and FIG. 1(B) is a cross-sectional view taken along line D1-D2 in FIG. 1(A) and a cross-sectional view taken along line D5 -D6 in FIG. 1(A). Also, FIG. 1(C) is a cross-sectional view taken along line D3-D4 in FIG. 1(A). Note that FIG. 2(E) is the same as FIG. 1(B).

[0051] The thin film transistor 448 disposed in the pixel is of a channel protection type (also referred to as a channel stop type)​​​​ is a thin film transistor, and on a substrate 400 having an insulating surface, a gate electrode layer 421 a, an oxide semiconductor layer 442 including a gate insulating layer 402 and a channel formation region 423, a channel oxide insulating layer 426a functioning as a protection layer, a source electrode layer 425a, and a drain electrode layer 425b. Further, a protection insulating layer 403 and a planarization insulating layer 404 are laminated and provided in contact with the oxide insulating layer 426a, the source electrode layer 425a, and the drain electrode layer 425b so as to cover the thin film transistor 448. A pixel electrode layer 427 in contact with the drain electrode layer 4 25b is provided on the planarization insulating layer 404, and is electrically connected to the thin film transistor 448. The thin film transistor 448 for a pixel has an oxide semiconductor layer 442 including a high-resistance source region 424a, a high-resistance drain region 4 24b, and a channel formation region 423, and a high-resistance source region 424a is formed in contact with the lower surface of the source electrode layer 425a. Further, a high-resistance drain region 424b is formed in contact with the lower surface of the drain electrode layer 425b. The thin film transistor 448 has a configuration in which the high-resistance drain region or the high-resistance source region serves as a buffer even when a high electric field is applied, so that a local high electric field is not applied, and the breakdown voltage of the transistor is improved.

[0052] The channel formation region of the thin film transistor 448 disposed in the pixel is a region of the oxide semiconductor layer 442 that is in contact with the oxide insulating layer 426a serving as a channel protection layer and overlaps with the gate electrode layer 421a. Since the thin film transistor 448 is protected by the oxide insulating layer 426a, in the etching process for forming the source electrode layer 425a and the drain electrode layer 425b

[0053] ​​​​​​​​​​​It is possible to prevent the oxide semiconductor layer 442 from being etched.

[0054] In addition, in order to realize a display device in which the thin film transistor 448 has a high aperture ratio as a thin film transistor having translucency, the source electrode layer 425a and the drain electrode layer 425b use a conductive film having translucency.

[0055] Also, the gate electrode layer 421a of the thin film transistor 448 also uses a conductive film having translucency.

[0056] In addition, for the pixel in which the thin film transistor 448 is disposed, a conductive film having translucency with respect to visible light is used for the pixel electrode layer 427, or other electrode layers (such as a capacitive electrode layer) and other wiring layers such as a capacitive wiring layer, and a display device having a high aperture ratio is realized. Of course, it is preferable to use a film having translucency with respect to visible light for the gate insulating layer 402 and the oxide insulating layer 426a.

[0057] In this specification, the film having translucency with respect to visible light refers to a film having a film thickness with a visible light transmittance of 75 to 100%, and when the film has conductivity, it is also called a transparent conductive film. In addition, as a metal oxide applied to the gate electrode layer, the source electrode layer, the drain electrode layer, the pixel electrode layer, or other electrode layers and other wiring layers, a semi-transparent conductive film with respect to visible light may be used. Semi-transparent with respect to visible light means that the visible light transmittance is 50 to 75%.

[0058] In addition, in order to reduce the parasitic capacitance, at the wiring intersection where the gate wiring and the source wiring intersect, the gate insulating layer 402 and the oxide insulating layer are provided between the gate electrode layer 421b and the source electrode layer 425a. ​​​​​​​​​​​426b is provided. Note that the oxide insulating layer in the region overlapping with the channel formation region 423 426a and the oxide insulating layer 426b in the region not overlapping with the channel formation region 423 are indicated by different symbols, but they are layers formed of the same material and by the same process.

[0059] Hereinafter, using FIGS. 2(A) to 2(E), the process of fabricating the thin film transistor 448 and the wiring intersection on the same substrate will be described. Also, not only the pixel portion but also the thin film transistors in the driving circuit may be formed, and they can be fabricated on the same substrate by the same process.

[0060] First, after forming a conductive film having translucency on a substrate 400 having an insulating surface, the gate electrode layers 421a and 421b are formed by the first photolithography process. Also, in the pixel portion a capacitive wiring layer is formed by the same material having the same translucency as the gate electrode layers 421a and 421b and by the same first photolithography process. Also, when forming not only the pixel portion but also the driving circuit, if a capacitor is required in the driving circuit, a capacitive wiring layer is also formed in the driving circuit. Note that the resist mask may be formed by an inkjet method. When the resist mask is formed by the inkjet method since a photomask is not used, the manufacturing cost can be reduced. There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface, but at least

[0061] it is necessary to have heat resistance to withstand the subsequent heat treatment. A glass substrate can be used for the substrate 400 having an insulating surface.

[0062]

[0062] Also, as the glass substrate, when the temperature of the subsequent heat treatment is high, the strain point is 730 °C or higher It is advisable to use such a material. For the glass substrate, for example, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used. Note that by incorporating more barium oxide (BaO) compared to boron oxide, a more practical heat-resistant glass can be obtained. Therefore, it is preferable to use a glass substrate containing more BaO than B2O3.

[0063] Note that instead of the above glass substrate, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. Additionally, crystallized glass or the like can be used.

[0064] Also, an insulating film serving as an underlayer film may be provided between the substrate 400 and the gate electrode layers 421a and 421b. The underlayer film has a function of preventing the diffusion of impurity elements from the substrate 400 and can be formed by a stacked structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film.

[0065] The materials of the gate electrode layers 421a and 421b are conductive materials having translucency to visible light. For example, metal oxides of In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al -Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-O system, Sn-O system, and Zn-O system can be applied, and the film thickness is appropriately selected within the range of 50 nm or more and 300 nm or less. The film formation method of the metal oxide used for the gate electrode layers 421 a and 421b uses a sputtering method, a vacuum evaporation method (such as an electron beam evaporation method), an arc discharge ion plating method, or a spraying method. Also, sp When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used to form a film, and SiOx (X>0) that inhibits crystallization is included in the conductive film having translucency, and crystallization during the heat treatment for dehydration or dehydrogenation performed in the subsequent process is suppressed. This is preferable. The oxide semiconductor is preferably an oxide semiconductor containing In, and more preferably an oxide semiconductor containing In and Ga. In order to make the oxide semiconductor layer of type I (intrinsic), it is effective to go through a dehydration or dehydrogenation process. Next, a gate insulating layer 402 is formed on the gate electrode layers 421a and 421b. The gate insulating layer 402 can be formed by using a plasma CVD method, a sputtering method, or the like, as a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer. For example, a silicon oxynitride layer can be formed by the plasma CVD method using SiH4, oxygen, and nitrogen as the film-forming gas. The film thickness of the gate insulating layer 402 is set to 100 nm or more and 500 nm or less. In the case of lamination, for example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less on the first gate insulating layer are laminated.

[0066] In this embodiment, the gate insulating layer 402 is a silicon nitride layer with a film thickness of 200 nm or less formed by the plasma CVD method. Next, an oxide semiconductor film 43 with a film thickness of 2 nm or more and 200 nm or less is formed on the gate insulating layer 402.

[0067]

[0068]

[0069]

[0070] ​​​​​​​​​​​​is formed (see Fig. 2(A)). Even if a heat treatment for dehydration or dehydrogenation is performed after the formation of the oxide semiconductor film 430, the oxide semiconductor film is kept in an amorphous state, so it is preferable to make the film thickness as thin as 50 nm or less. By making the film thickness of the oxide semiconductor film thin, crystallization can be suppressed when heat treatment is performed after the formation of the oxide semiconductor layer. The oxide semiconductor film 430 is an In-Ga-Zn-O-based polycrystalline film, an In-Sn-Zn-O-based , an In-Al-Zn-O-based, a Sn-Ga-Zn-O-based, an Al-Ga-Zn-O-based, a Sn-

[0071] , an Al-Zn-O-based, an In-Zn-O-based, a Sn-Zn-O-based, an Al-Zn-O-based, an In-O , a Sn-O-based, or a Zn-O-based oxide semiconductor film. In this embodiment, a film is formed by a sputtering method using an In-Ga -Zn-O-based oxide semiconductor target. Further, the oxide semiconductor film 430 can be formed by a sputtering method in an atmosphere of a rare gas (typically argon), an oxygen atmosphere, or an atmosphere of a rare gas (typically argon) and an oxygen atmosphere. Further, when using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used for film formation, and SiOx (X>0) that inhibits crystallization is included in the oxide semiconductor film 430, and crystallization during the heat treatment for dehydration or dehydrogenation performed in a later step is preferably suppressed. Here, an oxide semiconductor target containing In, Ga, and Zn (In2O3:Ga2O 3:ZnO = 1:1:1 [mole ratio]) is used, the distance between the substrate and the target is 1 00 mm, the pressure is 0.2 Pa, the DC power supply is 0.5 kW, argon and oxygen (argon

[0072] : Film formation is carried out in an atmosphere where the oxygen flow rate is 30 sccm: 20 sccm (oxygen flow rate ratio 40%). Note that , when using a pulsed direct current (DC) power supply, dust can be reduced and the film thickness distribution becomes uniform, which is preferable . The film thickness of the In-Ga-Zn-O-based non-single crystal film shall be 5 nm to 200 nm. In this embodiment, as the oxide semiconductor film, an In-Ga-Zn-O-based oxide semiconductor target is used to form an In-Ga-Zn-O-based non-single crystal film with a film thickness of 20 nm by sputtering. .

[0073] There are an RF sputtering method that uses a high-frequency power supply as the sputtering power supply and a DC sputtering method in sputtering methods, and there is also a pulsed DC sputtering method that applies a bias pulse. RF sputtering method is mainly used when forming an insulating film, and DC sputtering method is mainly used when forming a metal film .

[0074] There is also a multi-source sputtering apparatus that can install multiple targets with different materials. Multi-source sputtering apparatus can deposit different material films in the same chamber in a laminated manner, or can also discharge multiple types of materials simultaneously in the same chamber to form a film.

[0075] There is also a sputtering apparatus that uses a magnetron sputtering method equipped with a magnet mechanism inside the chamber , and an ECR sputtering apparatus that uses plasma generated using microwaves without using glow discharge.

[0076] In addition, as a film formation method using sputtering, there are a reactive sputtering method that chemically reacts the target substance and the sputtering gas component during film formation to form a compound thin film thereof, and a bias sputtering method that also applies a voltage to the substrate during film formation.

[0077] Next, the oxide semiconductor film 430 is processed into an island-shaped oxide semiconductor film by a second photolithography process. In addition, a resist mask for forming an island-shaped oxide semiconductor layer is applied to the ink. If the resist mask is formed by the inkjet method, the photomask Since no disks are used, manufacturing costs can be reduced.

[0078] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400° C. or higher and lower than the distortion point of the substrate, preferably 425° C. or higher. If the temperature is 425℃ or higher, the heat treatment time can be 1 hour or less. The heat treatment time is longer than one hour. The substrate is placed in an electric furnace, and the oxide semiconductor layer is subjected to a heat treatment in a nitrogen atmosphere. After that, the oxide semiconductor layer is not exposed to the air, and water and hydrogen are prevented from re-mixing into the oxide semiconductor layer. In this embodiment, the heating temperature for dehydrating or dehydrogenating the oxide semiconductor layer is The same furnace is used to heat the material from temperature T to a temperature that is high enough to prevent water from entering again. The temperature is gradually cooled in a nitrogen atmosphere until the temperature drops by 100°C or more below the temperature of the substrate. Dehydration or dehydrogenation is performed under a rare gas atmosphere such as helium, neon, or argon. .

[0079] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the concentration of impurities is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferably set to 0.1 ppm or less.

[0080] Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, crystallization may occur and it may become a microcrystalline film or a polycrystalline film. crystalline film or a polycrystalline film.

[0081] Also, the first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor film 430 before it is processed into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out from the heating device and a photolithography process is performed. substrate is taken out from the heating device and a photolithography process is performed. substrate is taken out from the heating device and a photolithography process is performed.

[0082] Also, before forming the oxide semiconductor film 430, a heat treatment (at 400 °C or higher and below the strain point of the substrate) may be performed in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) or in an oxygen atmosphere to remove impurities such as hydrogen and water contained in the gate insulating layer. atmosphere (nitrogen, or helium, neon, argon, etc.) or in an oxygen atmosphere to remove impurities such as hydrogen and water contained in the gate insulating layer. ) to remove impurities such as hydrogen and water contained in the gate insulating layer.

[0083] Next, after forming an oxide insulating film by sputtering on the gate insulating layer 402 and the oxide semiconductor layer, a resist mask is formed by a third photolithography process, and selective etching is performed to form the oxide insulating layers 426a and 426b, and then the resist mask is removed. Next, after forming an oxide insulating film by sputtering on the gate insulating layer 402 and the oxide semiconductor layer, a resist mask is formed by a third photolithography process, and selective etching is performed to form the oxide insulating layers 426a and 426b, and then the resist mask is removed. Next, after forming an oxide insulating film by sputtering on the gate insulating layer 402 and the oxide semiconductor layer, a resist mask is formed by a third photolithography process, and selective etching is performed to form the oxide insulating layers 426a and 426b, and then the resist mask is removed. At this stage, in the oxide semiconductor layer, a region in contact with the oxide insulating layer is formed, and among this region, a region that overlaps via the gate electrode layer and the gate insulating layer and also overlaps with the oxide insulating layer 426a becomes the channel formation region. Also, a region that overlaps with the oxide insulating layer 426b that covers the periphery and side surfaces of the oxide semiconductor layer is formed. a region that overlaps via the gate electrode layer and the gate insulating layer and also overlaps with the oxide insulating layer 426a becomes the channel formation region. Also, a region that overlaps with the oxide insulating layer 426b that covers the periphery and side surfaces of the oxide semiconductor layer is formed. a region that overlaps with the oxide insulating layer 426b that covers the periphery and side surfaces of the oxide semiconductor layer is formed.

[0084] The oxide insulating film should have a film thickness of at least 1 nm or more and can be formed by appropriately using a method such as sputtering that does not mix impurities such as water and hydrogen into the oxide insulating film. In this embodiment film should have a film thickness of at least 1 nm or more and can be formed by appropriately using a method such as sputtering that does not mix impurities such as water and hydrogen into the oxide insulating film. In this embodiment In this form, a silicon oxide film with a film thickness of 300 nm is formed as the oxide insulating film using a sputtering method. The substrate temperature during film formation may be from room temperature to 300 °C, and in this embodiment, it is set to room temperature. The film formation of the silicon oxide film by the sputtering method is carried out in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or an atmosphere of a rare gas (typically argon) and oxygen. Also, a silicon oxide target or a silicon target can be used as the target. For example, using a silicon target, a silicon oxide film can be formed by the sputtering method in an atmosphere of oxygen and nitrogen. The oxide insulating film formed in contact with the low-resistance oxide semiconductor layer blocks the intrusion of moisture, hydrogen ions, OH and other impurities from the outside. Typically, an inorganic insulating film such as a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is used. First, an inorganic insulating film that blocks these from entering from the outside is used. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is used. - including Next, a second heat treatment (preferably at 200 °C or higher and 400 °C or lower, for example, 250 °C or higher and 350 °C or lower) is performed in an inert gas atmosphere or a nitrogen gas atmosphere (see Fig. 2(B)). For example, a second heat treatment at 250 °C for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, the end of the oxide semiconductor layer 442 overlapping with the oxide insulating layer 426b and a part of the oxide semiconductor layer 442 overlapping with the oxide insulating layer 426a are heated in a state of being in contact with the oxide insulating layer. When the second heat treatment is performed, a part of the oxide semiconductor layer 442 that does not overlap with the oxide insulating layer is heated in an exposed state. With the oxide semiconductor layer 442 exposed, nitrogen, or

[0085] Next, a second heat treatment (preferably at 200 °C or higher and 400 °C or lower, for example, 250 °C or higher and 350 °C or lower) is performed in an inert gas atmosphere or a nitrogen gas atmosphere (see Fig. 2(B)). For example, a second heat treatment at 250 °C for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, the end of the oxide semiconductor layer 442 overlapping with the oxide insulating layer 426b and a part of the oxide semiconductor layer 442 overlapping with the oxide insulating layer 426a are heated in a state of being in contact with the oxide insulating layer. When the second heat treatment is performed, a part of the oxide semiconductor layer 442 that does not overlap with the oxide insulating layer is heated in an exposed state. With the oxide semiconductor layer 442 exposed, nitrogen, or Next, a second heat treatment (preferably at 200 °C or higher and 400 °C or lower, for example, 250 °C or higher and 350 °C or lower) is performed in an inert gas atmosphere or a nitrogen gas atmosphere (see Fig. 2(B)). For example, a second heat treatment at 250 °C for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, the end of the oxide semiconductor layer 442 overlapping with the oxide insulating layer 426b and a part of the oxide semiconductor layer 442 overlapping with the oxide insulating layer 426a are heated in a state of being in contact with the oxide insulating layer. When the second heat treatment is performed, a part of the oxide semiconductor layer 442 that does not overlap with the oxide insulating layer is heated in an exposed state. With the oxide semiconductor layer 442 exposed, nitrogen, or a part of the oxide semiconductor layer 442 is heated in an exposed state. With the oxide semiconductor layer 442 exposed, nitrogen, or When heat treatment is performed in an inert gas atmosphere or an inert gas atmosphere, the exposed portion of the oxide semiconductor layer 442 is The high resistance (I-type) region can be made low resistance. The layer 426a is provided over and in contact with a region that serves as a channel formation region of the oxide semiconductor layer 442. It functions as a channel protection layer.

[0086] Next, the gate insulating layer 402, the oxide insulating layers 426a and 426b, and the oxide semiconductor layer 4 After forming a light-transmitting conductive film on the insulating film 42, a fourth photolithography process is performed to form a resist pattern. A resist mask is formed and selectively etched to form the source electrode layer 425a and the drain electrode layer 425b. A conductive film having a light-transmitting property is formed by the following method. Sputtering, vacuum deposition (electron beam deposition, etc.), and arc discharge ion plating The conductive film is made of a conductive material that is transparent to visible light. Materials such as In-Sn-Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn -O, Al-Zn-O, In-O, Sn-O, and Zn-O metal oxides are applied. The thickness of the film can be appropriately selected within the range of 50 nm to 300 nm. When using the target deposition method, a target containing SiO2 of 2% by weight or more and 10% by weight or less is used. The conductive film is then coated with SiOx (X>0) which inhibits crystallization. Suppresses crystallization during the heat treatment for dehydration or dehydrogenation in the process. It is preferred.

[0087] Note that a resist mask for forming the source electrode layer 425a and the drain electrode layer 425b is used. It may be formed by an inkjet method. When a resist mask is formed by an inkjet method, Since a photomask is not used, the manufacturing cost can be reduced.

[0088] Next, a protective insulating layer 403 is formed on the oxide insulating layers 426a and 426b, the source electrode layer 425a, and the drain electrode layer 42 5b. In this embodiment, a silicon nitride film is formed using an RF sputtering method. Since the RF sputtering method has good mass productivity, it is preferable as a film forming method for the protective insulating layer 403. The protective insulating layer 403 contains moisture, hydrogen ions, OH - and other impurities First, an inorganic insulating film that blocks these from entering from the outside is used, such as a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, or an aluminum oxynitride film. Of course, the protective insulating layer 403 is a transparent insulating film.

[0089] Next, a planarizing insulating layer 404 is formed on the protective insulating layer 403. As the planarizing insulating layer 404, organic materials having heat resistance such as polyimide, acrylic, benzocyclobutene, polyamide, and epoxy can be used. In addition to the above organic materials, low dielectric constant materials (lo w-k materials), siloxane resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass ) etc. can be used. Note that the planarizing insulating layer 404 may be formed by laminating a plurality of insulating films formed of these materials.

[0090] The siloxane resin corresponds to a resin containing an Si-O-Si bond formed using a siloxane-based material as a starting material. The siloxane resin may use an organic group (for example, an alkyl group or an aryl group) or a fluoro group as a substituent. Also, the organic group may have a fluoro group. ​

[0091] The method for forming the planarization insulating layer 404 is not particularly limited. Depending on the material, it may be a sputtering method, a SO G method, spin coating, dip, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, A knife coater or the like can be used.

[0092] Next, a fifth photolithography step is performed to form a resist mask, and a planarization insulating layer 4 04, and the protective insulating layer 403 is etched to form a contact that reaches the drain electrode layer 425b. Then, a hole 441 is formed and the resist mask is removed (see FIG. 2(D)). As shown in FIG. 1, an oxide insulating layer 426b is provided below the contact hole. The amount of planarizing insulation removed is smaller than when there is no oxide insulating layer below the contact hole. The thickness of the edge layer can be made thin, and the etching time can be shortened. The depth of the contact hole 441 is smaller than that in the case where no oxide insulating layer is provided below the contact hole. In the region overlapping with the contact hole 441, In addition, the coverage of the light-transmitting conductive film can be improved. A contact hole reaching the gate electrode layer 421b is also formed by this etching. A resist mask for forming a contact hole reaching the drain electrode layer 425b is then applied. If the resist mask is formed by the inkjet method, the photoresist can be formed by the inkjet method. Since no mask is used, manufacturing costs can be reduced.

[0093] Next, a light-transmitting conductive film is formed. Indium (In2O3) or indium tin oxide alloy (In2O3 - SnO2, abbreviated as ITO etc.) is formed by using a sputtering method, a vacuum evaporation method, or the like. As other materials for the transparent conductive film, an Al-Zn-O-based non-crystalline film containing nitrogen, that is, an Al-Zn- O-N-based non-crystalline film, a Zn-O-N-based non-crystalline film, or a Sn-Zn-O-N-based non-crystalline film may be used. The zinc composition ratio (atomic%) of the Al-Zn-O-N-based non-crystalline film is 47 atomic% or less, greater than the aluminum composition ratio (atomic%) in the non-crystalline film, and the aluminum composition ratio (atomic%) in the non-crystalline film is greater than the nitrogen composition ratio (atomic%) in the non-crystalline film . The etching treatment of such materials is performed with a hydrochloric acid-based solution. However, especially in the etching of ITO, residues are likely to occur, so an indium zinc oxide alloy (In2O3 - ZnO) may be used to improve the etching processability .

[0094] Note that the unit of the composition ratio of the transparent conductive film is atomic%, and it is evaluated by analysis using an electron probe X-ray microanalyzer (EPMA: Electron Probe X-ray MicroAnalyzer ).

[0095] Next, a sixth photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form the pixel electrode layer 427, and the resist mask is removed (see Fig. 2( E)). ).

[0096] Through the above processes, using six masks, a thin film transistor 448 and a wiring intersection portion with reduced parasitic capacitance can be fabricated on the same substrate. The thin film transistor 44 for pixels ​​8 is a channel protection type thin film transistor including an oxide semiconductor layer 442 containing a high resistance source region 424a, a high resistance drain region 424b, and a channel formation region 423. Therefore, even when a high electric field is applied, the thin film transistor 448 has the high resistance drain region 424b or the high resistance source region 424a serving as a buffer, and a local high electric field is not applied, resulting in a structure that improves the breakdown voltage of the transistor.

[0097] In addition, a holding capacitor formed of a capacitor wiring layer and a capacitor electrode with the gate insulating layer 402 as a dielectric can also be formed on the same substrate. The thin film transistor 448 and the holding capacitor are arranged in a matrix corresponding to individual pixels to form a pixel portion, and can be used as one substrate for manufacturing an active matrix type display device. In this specification, for convenience, such a substrate is referred to as an active matrix substrate.

[0098] Further, thin film transistors of a driving circuit can also be provided on the same substrate. By forming the driving circuit and the pixel portion on the same substrate, the connection wiring between the driving circuit and an external signal can be shortened, and miniaturization and cost reduction of the semiconductor device are possible.

[0099] Also, the oxide semiconductor layer 442 of the thin film transistor 448 for pixels shown in FIG. 1(B) has a first region 424c and a second region 424d overlapping with the oxide insulating layer 426b at the peripheral portion. The first region 424c and the second region 424d, which are the peripheral portions of the oxide semiconductor layer 442, are in the same oxygen-excessive state as the channel formation region 423, and when wiring or an oxide semiconductor layer with different potentials is arranged nearby, reduction of leakage current and reduction of parasitic capacitance can be realized.

[0100] Especially in the driving circuit, for high integration, it is preferable to narrow the intervals between a plurality of wirings and a plurality of oxide semiconductor layers and arrange them, and by overlapping with the oxide insulating layer 426b, the first region 424c and the second region 424d are provided, and it is effective to reduce leakage current and parasitic capacitance. Also, when arranging a plurality of thin film transistors in series or in parallel, the oxide semiconductor layers of the plurality of thin film transistors are made into one island, and element isolation for each element is performed by overlapping with the oxide insulating layer 426b, and the region overlapping with the oxide insulating layer 426b can be used as the element isolation region. By doing so, since a plurality of thin film transistors can be arranged in a narrow area, high integration of the driving circuit can be achieved. By overlapping with the oxide insulating layer 426b, the region overlapping with the oxide insulating layer 426b is used as the element isolation region. In this way, a plurality of thin film transistors can be arranged in a narrow area, so that high integration of the driving circuit can be achieved. (Embodiment 2)

[0101] In this embodiment, an example of manufacturing an active matrix type liquid crystal display device by forming a pixel portion and a driving circuit on the same substrate using the thin film transistor shown in Embodiment 1 is shown. In this embodiment, although the thin film transistor and the wiring intersection portion in the pixel portion were shown in Embodiment 1, in this embodiment, in addition to the thin film transistor and the wiring intersection portion, the thin film transistor, the holding capacitance, and the terminal portions of the gate wiring, source wiring of the driving circuit are also shown and described. The capacitance, gate wiring, and terminal portions of the source wiring can be formed by the same process as the manufacturing process shown in Embodiment 1. Also,

[0102] An example of the cross-sectional structure of the active matrix substrate is shown in FIG. 3(A).

[0103] In Embodiment 1, the thin film transistor and the wiring intersection portion in the pixel portion were illustrated, but in this embodiment, in addition to the thin film transistor and the wiring intersection portion, the thin film transistor, the holding capacitance, and the terminal portions of the gate wiring, source wiring of the driving circuit are also illustrated and described. The capacitance, gate wiring, and terminal portions of the source wiring can be formed by the same process as the manufacturing process shown in Embodiment 1. Also, in the portion that becomes the display region of the pixel portion, the gate wiring, source wiring, and capacitance wiring layer are all formed of a conductive film having translucency, and a high aperture ratio is realized. The capacitance, gate wiring, and terminal portions of the source wiring can be formed by the same process as the manufacturing process shown in Embodiment 1. Also, in the portion that becomes the display region of the pixel portion, the gate wiring, source wiring, and capacitance wiring layer are all formed of a conductive film having translucency, and a high aperture ratio is realized. The capacitance, gate wiring, and terminal portions of the source wiring can be formed by the same process as the manufacturing process shown in Embodiment 1. Also,

[0104] In FIG. 3A, a thin film transistor 220 electrically connected to a pixel electrode layer 227 is A channel protection type thin film transistor is provided in a pixel portion. The thin film transistor 220 has the same structure as the thin film transistor 448 of the first embodiment. The width of the gate electrode layer in the channel length direction is equal to the width of the oxide semiconductor layer of the thin film transistor 220. Narrower than the width in the longitudinal direction of the panel.

[0105] A layer formed of the same material and process as the gate electrode layer of the thin film transistor 220. The capacitor wiring layer 230 is connected to the capacitor electrode 231 via the gate insulating layer 202 which serves as a dielectric. The capacitor electrode 231 is connected to the source of the thin film transistor 220. The second electrode layer is formed of the same light-transmitting material and in the same process as the source electrode layer or the drain electrode layer. Therefore, in addition to the thin film transistor 220 having a light transmitting property, each storage capacitor Since the transparent insulating film 10 also has light transmitting properties, the aperture ratio can be improved.

[0106] It is important for the storage capacitor to have light transmittance in order to improve the aperture ratio. In the following small LCD panels, the number of gate wirings is increased to improve the resolution of the displayed image. Even if the pixel size is reduced to achieve high resolution, a high aperture ratio can be achieved. By using a film having light transmitting properties as the constituent members of the thin film transistor 220 and the storage capacitor, To achieve a wide viewing angle, a high aperture ratio is achieved even when one pixel is divided into multiple sub-pixels. That is, even if a high density group of thin film transistors is arranged, a large aperture ratio can be obtained. For example, two to four pixels can be arranged in one pixel, and a sufficient area can be secured for the display area. When having four sub-pixels and a holding capacitance, the thin film transistor has light transmissivity. In addition to this, since each holding capacitance also has light transmissivity, the aperture ratio can be improved.

[0107] Note that the holding capacitance is provided below the pixel electrode layer 227, and the capacitance electrode 231 is electrically connected to the pixel electrode layer 2 27.

[0108] In this embodiment, an example of forming the holding capacitance using the capacitance electrode 231 and the capacitance wiring layer 230 is shown, but the structure for forming the holding capacitance is not particularly limited. For example, without providing the capacitance wiring layer, the holding capacitance may be formed by overlapping the pixel electrode layer with the gate wiring of adjacent pixels through the planarization insulating layer, the protective insulating layer, and the gate insulating layer.

[0109] Also, in FIG. 3(A), since the holding capacitance forms a large capacitance, only the gate insulating layer 202 is provided between the capacitance wiring layer and the capacitance electrode, and the wiring intersection portion is provided with the gate insulating layer 202 and the oxide insulating layer 266b between the gate electrode layer 421b and the wiring formed above it to reduce the parasitic capacitance. In the holding capacitance, when only the gate insulating layer 202 is provided between the capacitance wiring layer and the capacitance electrode, during the etching for removing the oxide insulating layer 266b, selectively select the etching conditions or the material of the gate insulating layer so that only the gate insulating layer 202 remains. In this embodiment, since the oxide insulating layer 266b is a silicon oxide film obtained by sputtering, and the gate insulating layer 202 is a silicon nitride film obtained by plasma CVD method, it can be selectively removed. Note that when using a material in which the oxide insulating layer 266b and the gate insulating layer 202 are removed under the same etching conditions, a part of the gate insulating layer is thinned by etching. ​​​​​​ However, it is preferable that at least a gate insulating layer remains and the film thickness is such that a capacitor can be formed. In order to increase the holding capacitance, it is preferable to reduce the film thickness of the gate insulating layer. Therefore, the gate insulating layer on the capacitor wiring may be thinned during the selective etching of the oxide insulating layer 266b.

[0110] Further, the thin film transistor 260 is a channel protection type thin film transistor provided in the drive circuit, and has a shorter channel length L than the thin film transistor 220, resulting in a higher operating speed. The channel length L of the channel protection type thin film transistor provided in the drive circuit is preferably 0.1 μm or more and 2 μm or less. The width of the gate electrode layer 261 of the thin film transistor 260 in the channel length direction is wider than the width of the oxide semiconductor layer of the thin film transistor 260 in the channel length direction, and the end face of the gate electrode layer 261 overlaps with the source electrode layer 265a or the drain electrode layer 265b via the gate insulating layer 202 and the oxide insulating layer 266b.

[0111] The thin film transistor 260 includes a gate electrode layer 261, a gate insulating layer 202, at least a channel formation region 263, an oxide semiconductor layer having a high resistance source region 264a and a high resistance drain region 264b, a source electrode layer 265a, and a drain electrode layer 265b on a substrate 200 having an insulating surface. Further, an oxide insulating layer 266a in contact with the channel formation region 263 is provided.

[0112] Further, the gate electrode layer of the thin film transistor 260 in the drive circuit may be electrically connected to a conductive layer 267 provided above the oxide semiconductor layer. In that case, the thin film transistor A contact for electrically connecting the drain electrode layer of the transistor 220 and the pixel electrode layer 227 Using the same photomask as the contact hole, the planarization insulating layer 204, the protective insulating layer 203, the oxide insulating layer 266b, and the gate insulating layer 202 are selectively etched to form a contact hole The conductive layer 267 and the gate electrode layer 261 of the thin-film transistor 260 in the driving circuit are electrically connected through this contact hole

[0113] The protective insulating layer 203 uses an inorganic insulating film, such as a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, or an aluminum oxynitride film. In this embodiment, a silicon nitride film is used

[0114] In addition, the thin-film transistor 260 has a structure in which the width of the gate electrode layer 261 is wider than the width of the oxide semiconductor layer. Further, the oxide insulating layer 266b overlaps with the peripheral portion of the oxide semiconductor layer and also overlaps with the gate electrode layer 261. The oxide insulating layer 266b functions to widen the distance between the drain electrode layer 265b and the gate electrode layer 261 and reduce the parasitic capacitance formed between the drain electrode layer 265b and the gate electrode layer 261. Further, the first region 264c and the second region 264d of the oxide semiconductor layer that overlap with the oxide insulating layer 266b are in the same oxygen-excessive state as the channel formation region 263, and also function to reduce leakage current and parasitic capacitance

[0115] In addition, when the size of the liquid crystal display panel exceeds 10 inches, 60 inches, and further 120 inches, there is a possibility that the wiring resistance of the wiring having translucency becomes a problem. Therefore, it is preferable to reduce the wiring resistance by using metal wiring for a part of the wiring. For example, the source electrode layer 265a ​​​​​​​​​​​And the drain electrode layer 265b is made of a metal wiring such as Ti. To form the metal wiring, compared with Embodiment 1, the number of photomasks increases by one. Compared with Embodiment 1, the number of photomasks increases by one.

[0116] In that case, a source electrode layer or a drain electrode layer made of a metal electrode such as Ti is formed in contact with the dehydrated or dehydrogenated oxide semiconductor layer, and a high-resistance source region overlapping the source electrode layer and a high-resistance drain region overlapping the drain electrode layer are formed, and a region between the high-resistance source region and the high-resistance drain region becomes a channel formation region. A region between the high-resistance source region and the high-resistance drain region becomes a channel formation region.

[0117] Also, in order to reduce the wiring resistance, as shown in FIG. 3(A), auxiliary electrode layers 268a and 268b using a lower-resistance metal electrode are formed on the source electrode layer 265a and the drain electrode layer 265b. Also in this case, to form the metal wiring (metal electrode), compared with Embodiment 1, further the number of photomasks increases by one. A structure with only the light-transmissive source electrode layer and drain electrode layer may be used, but providing auxiliary electrode layers using a metal electrode on the source electrode layer and the drain electrode layer can reduce the wiring resistance.

[0118] The source electrode layer 265a, the drain electrode layer 265b, the auxiliary electrode layers 268a and 268b, and the source electrode layer and the drain electrode layer of the thin-film transistor 220 are formed by laminating a light-transmissive conductive film and a metal conductive film and selectively etching them by a photolithography process. The metal conductive film on the source electrode layer and the drain electrode layer of the thin-film transistor 220 is removed.

[0119] Note that when etching the metal conductive film, the materials and etching conditions are appropriately adjusted so that the source electrode layer and the drain electrode layer of the thin-film transistor 220 are not removed.

[0120] For example, an alkaline etchant is used to selectively etch the metal conductive film. The material of the metal conductive film is selected from Al, Cr, Cu, Ta, Ti, Mo, and W. Elements, alloys containing the above-mentioned elements as components, or alloy films formed by combining the above-mentioned elements, etc. are mentioned. Further, the metal conductive film may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on the aluminum film. A three-layer structure in which a Ti film is laminated, an aluminum film is laminated on the Ti film, and a Ti film is further formed thereon. Examples include a film, an alloy film, or a nitride film in which a single or a plurality of elements selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc) are combined with Al. Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (N d), scandium (Sc) may be used. In this embodiment, a Ti film is used as the metal conductive film, an In-Sn-O-based oxide is used for the source electrode layer and the drain electrode layer, and aqueous ammonia peroxide (a mixture of ammonia, water, and hydrogen peroxide solution) is used as the etchant.

[0121] The drain electrode layer 265b provided between the oxide semiconductor layer and the auxiliary electrode layer 268b made of a metal material also functions as a low-resistance drain region (also referred to as an LRN (Low Resistance N-type conductivity) region or an LRD (Low Resistance Drain) region). By configuring the oxide semiconductor layer, the low-resistance drain region, and the auxiliary electrode layer 268b which is a metal electrode, the breakdown voltage of the transistor can be further improved. In-Sn-O-based oxide is used for the source electrode layer and the drain electrode layer, and aqueous ammonia peroxide (a mixture of ammonia, water, and hydrogen peroxide solution) is used as the etchant.

[0122] The drain electrode layer 265b provided between the oxide semiconductor layer and the auxiliary electrode layer 268b made of a metal material also functions as a low-resistance drain region (LRN (Low Resistance N-type conductivity) region, LRD (Low Resistance Drai n) region). By configuring the oxide semiconductor layer, the low-resistance drain region, and the auxiliary electrode layer 268b which is a metal electrode, the breakdown voltage of the transistor can be further improved. The breakdown voltage of the transistor can be further improved by configuring the oxide semiconductor layer, the low-resistance drain region, and the auxiliary electrode layer 268b which is a metal electrode. It can be done. Specifically, the carrier concentration in the low-resistance drain region is greater than that in the high-resistance drain region (HRD region), for example, 1×10 20 / cm 3 or more and 1×10 21 / cm 3 or less within the following range is preferable.

[0123] In addition, a plurality of gate wirings, source wirings, and capacitor wiring layers are provided according to the pixel density. In the terminal portion, a plurality of first terminal electrodes having the same potential as the gate wiring, second terminal electrodes having the same potential as the source wiring and third terminal electrodes having the same potential as the capacitor wiring layer are arranged side by side. The number of each terminal electrode can be arbitrarily set, and the implementer can appropriately determine it.

[0124] In the terminal portion, the first terminal electrode having the same potential as the gate wiring can be formed of a material having the same light transmissivity as the pixel electrode layer 227. The first terminal electrode is electrically connected to the gate wiring through a contact hole reaching the gate wiring. The contact hole reaching the gate wiring is formed using the same photomask as the contact hole for electrically connecting the drain electrode layer of the thin-film transistor 220 and the pixel electrode layer 227, and selectively etching the planarization insulating layer 204, the protective insulating layer 203, the oxide insulating layer 266b, and the gate insulating layer 202.

[0125] In addition, the second terminal electrode 255 having the same potential as the source wiring 254 in the terminal portion can be formed of a material having the same light transmissivity as the pixel electrode layer 227. The second terminal electrode 255 is electrically connected to the source wiring through a contact hole reaching the source wiring 254. The source wiring ​​​​​The line is a metal wiring, and is made of the same material as the source electrode layer 265a of the thin film transistor 260. They are formed in the process and have the same potential.

[0126] The third terminal electrode having the same potential as the capacitance wiring layer 230 has the same light-transmitting property as the pixel electrode layer 227. In addition, the contact hole reaching the capacitance wiring layer 230 can be formed of a material having the above-mentioned properties. The contact hole 231 is electrically connected to the pixel electrode layer 227. The same photomask and process can be used to form the insulating film.

[0127] In addition, when an active matrix type liquid crystal display device is manufactured, A liquid crystal layer is provided between the substrate and the opposing substrate on which the opposing electrode is provided, and an active matrix The substrate and the counter substrate are fixed together. The counter electrode is electrically connected to the counter substrate. A common electrode is provided on the active matrix substrate, and a fourth terminal is electrically connected to the common electrode. The fourth terminal electrode is provided on the terminal portion. The fourth terminal electrode is connected to the common electrode at a fixed potential, for example, GND, 0 The fourth terminal electrode is a terminal for setting the pixel electrode layer 227 and the like. The insulating layer may be made of a material having the following properties:

[0128] Also, a gate electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, or other electrodes If the same material is used for the layers and other wiring layers, common sputter targets and common manufacturing equipment can be used. The cost of the material and the etchant (or This reduces the cost of etching gas, resulting in reduced manufacturing costs. It is possible.

[0129] In addition, in the structure of FIG. 3(A), when a photosensitive resin material is used as the planarization insulating layer 204, the process of forming a resist mask can be omitted.

[0130] In addition, FIG. 3(B) shows a cross-sectional structure that is partially different from that of FIG. 3(A). FIG. 3(B) is the same as FIG. 3( A) except that the planarization insulating layer 204 does not exist at the terminal portion and the structure of the thin film transistor of the driving circuit is different. Therefore, the same reference numerals are used for the same locations, and detailed descriptions of the same locations are omitted. In FIG. 3(B), a thin film transistor 270 using a metal wiring is disposed. Also, the terminal electrode is formed of the same material and in the same process as the metal wiring.

[0131] In addition, in the structure of FIG. 3(B), a photosensitive resin material is used as the planarization insulating layer 204 and the process of forming a resist mask is omitted. Therefore, a configuration in which the planarization insulating layer 204 does not exist at the terminal portion can be achieved without using a resist mask. At the terminal portion, if there is no planarization insulating layer, it is easy to make good connection with the FPC.

[0132] The thin film transistor 270 includes a gate electrode layer 271, a gate insulating layer 202, at least a channel formation region 273, a high resistance source region 274a, and a high resistance drain region 274b, an oxide semiconductor layer, a source electrode layer 275a, and a drain electrode layer 275b on a substrate 200 having an insulating surface. Also, an oxide insulating layer 27 6a in contact with the channel formation region 273 is provided.

[0133] In addition, a first region 274c and a second region 274d of the oxide semiconductor layer overlapping with the oxide insulating layer 276b are in the same oxygen-excessive state as the channel formation region 273, for reducing leakage current and parasitic current, and parasitic It also serves the function of reducing the production capacity. Further, the oxide semiconductor layer in contact with the protective insulating layer 203 The third region 274e of is provided between the channel formation region 273 and the high-resistance source region 274a The fourth region 274f of the oxide semiconductor layer in contact with the protective insulating layer 203 is provided between the channel formation region 273 and the high-resistance drain region 274b. The third region 274e and the fourth region 274f of the oxide semiconductor layer in contact with the protective insulating layer 203 can reduce the off-current

[0134] Also, in the channel protection type thin film transistor, in order to shorten the channel length L of the channel formation region, the width of the oxide insulating layer is narrowed, and there is a risk of short circuit on the oxide insulating layer when the source electrode layer and the drain electrode layer are provided on the narrow oxide insulating layer. Therefore, the source electrode layer 275a and the drain electrode layer 275b are provided leaving the ends from the narrow oxide insulating layer 276a

[0135] Note that when etching the metal conductive film, the respective materials and etching conditions are appropriately adjusted so that the oxide semiconductor layer of the thin film transistor 270 is not removed

[0136] In this embodiment, a Ti film is used as the metal conductive film, an In-Ga- Zn-O based oxide is used for the oxide semiconductor layer, and an aqueous solution of hydrogen peroxide (a mixed solution of aqueous ammonia, water, hydrogen peroxide solution) is used as the etchant.

[0137] Also, the gate electrode layer of the thin film transistor 270 in the driving circuit may be structured to be electrically connected to the conductive layer 277 provided above the oxide semiconductor layer

[0138] ​​​​​​​Also, the second terminal electrode 257 at the same potential as the source wiring 256 of the terminal portion can be formed of a material having the same light transmittance as the pixel electrode layer 227. The source wiring is a metal wiring and is formed of the same material and in the same process as the source electrode layer 275a of the thin film transistor 270 and is at the same potential. Moreover, since thin film transistors are easily damaged by static electricity or the like, it is preferable to provide a protection circuit on the same substrate as the pixel portion or the drive circuit. The protection circuit is preferably configured using a non-linear element using an oxide semiconductor layer. For example, the protection circuit is disposed between the pixel portion and the scanning line input terminal and the signal line input terminal. In this embodiment, a plurality of protection circuits are provided so that a surge voltage is applied to the scanning line, the signal line, and the capacitance bus line by static electricity or the like, and the pixel transistor or the like is not damaged. Therefore, the protection circuit is configured to discharge the charge to the common wiring when a surge voltage is applied. Further, the protection circuit is composed of non-linear elements arranged in parallel with respect to the scanning line. The non-linear element is composed of a two-terminal element such as a diode or a three-terminal element such as a transistor. For example, it can also be formed in the same process as the thin film transistor 220 in the pixel portion, and for example, by connecting the gate terminal and the drain terminal, it can have characteristics similar to those of a diode. Moreover, since thin film transistors are easily damaged by static electricity or the like, it is preferable to provide a protection circuit on the same substrate as the pixel portion or the drive circuit. The protection circuit is preferably configured using a non-linear element using an oxide semiconductor layer. For example, the protection circuit is disposed between the pixel portion and the scanning line input terminal and the signal line input terminal. In this embodiment, a plurality of protection circuits are provided so that a surge voltage is applied to the scanning line, the signal line, and the capacitance bus line by static electricity or the like, and the pixel transistor or the like is not damaged. Therefore, the protection circuit is configured to discharge the charge to the common wiring when a surge voltage is applied. Further, the protection circuit is composed of non-linear elements arranged in parallel with respect to the scanning line. The non-linear element is composed of a two-terminal element such as a diode or a three-terminal element such as a transistor. For example, it can also be formed in the same process as the thin film transistor 220 in the pixel portion, and for example, by connecting the gate terminal and the drain terminal, it can have characteristics similar to those of a diode. Moreover, since thin film transistors are easily damaged by static electricity or the like, it is preferable to provide a protection circuit on the same substrate as the pixel portion or the drive circuit. The protection circuit is preferably configured using a non-linear element using an oxide semiconductor layer. For example, the protection circuit is disposed between the pixel portion and the scanning line input terminal and the signal line input terminal. In this embodiment, a plurality of protection circuits are provided so that a surge voltage is applied to the scanning line, the signal line, and the capacitance bus line by static electricity or the like, and the pixel transistor or the like is not damaged. Therefore, the protection circuit is configured to discharge the charge to the common wiring when a surge voltage is applied. Further, the protection circuit is composed of non-linear elements arranged in parallel with respect to the scanning line. The non-linear element is composed of a two-terminal element such as a diode or a three-terminal element such as a transistor. For example, it can also be formed in the same process as the thin film transistor 220 in the pixel portion, and for example, by connecting the gate terminal and the drain terminal, it can have characteristics similar to those of a diode.

[0139] Also, since thin film transistors are easily damaged by static electricity or the like, it is preferable to provide a protection circuit on the same substrate as the pixel portion or the drive circuit. The protection circuit is preferably configured using a non-linear element using an oxide semiconductor layer. For example, the protection circuit is disposed between the pixel portion and the scanning line input terminal and the signal line input terminal. In this embodiment, a plurality of protection circuits are provided so that a surge voltage is applied to the scanning line, the signal line, and the capacitance bus line by static electricity or the like, and the pixel transistor or the like is not damaged. Therefore, the protection circuit is configured to discharge the charge to the common wiring when a surge voltage is applied. Further, the protection circuit is composed of non-linear elements arranged in parallel with respect to the scanning line. The non-linear element is composed of a two-terminal element such as a diode or a three-terminal element such as a transistor. For example, it can also be formed in the same process as the thin film transistor 220 in the pixel portion, and for example, by connecting the gate terminal and the drain terminal, it can have characteristics similar to those of a diode. Therefore, the protection circuit is configured to discharge the charge to the common wiring when a surge voltage is applied. Further, the protection circuit is composed of non-linear elements arranged in parallel with respect to the scanning line. The non-linear element is composed of a two-terminal element such as a diode or a three-terminal element such as a transistor. For example, it can also be formed in the same process as the thin film transistor 220 in the pixel portion, and for example, by connecting the gate terminal and the drain terminal, it can have characteristics similar to those of a diode. For example, it can also be formed in the same process as the thin film transistor 220 in the pixel portion, and for example, by connecting the gate terminal and the drain terminal, it can have characteristics similar to those of a diode. For example, it can also be formed in the same process as the thin film transistor 220 in the pixel portion, and for example, by connecting the gate terminal and the drain terminal, it can have characteristics similar to those of a diode. For example, it can also be formed in the same process as the thin film transistor 220 in the pixel portion, and for example, by connecting the gate terminal and the drain terminal, it can have characteristics similar to those of a diode.

[0140] Note that the formation process of the planarization insulating layer 204 may be omitted, and a structure without the planarization insulating layer 204 may be adopted. In this case, the conductive layer 267, the conductive layer 277, the pixel electrode layer 227, and the second terminal electrodes 255 and 257 are provided in contact with the protection insulating layer 203. Note that the formation process of the planarization insulating layer 204 may be omitted, and a structure without the planarization insulating layer 204 may be adopted. In this case, the conductive layer 267, the conductive layer 277, the pixel electrode layer 227, and the second terminal electrodes 255 and 257 are provided in contact with the protection insulating layer 203. Note that the formation process of the planarization insulating layer 204 may be omitted, and a structure without the planarization insulating layer 204 may be adopted. In this case, the conductive layer 267, the conductive layer 277, the pixel electrode layer 227, and the second terminal electrodes 255 and 257 are provided in contact with the protection insulating layer 203.

[0141] This embodiment can be freely combined with Embodiment 1.

[0142] (Embodiment 3) In addition, in this embodiment, an example of the configuration of a terminal portion provided on the same substrate as the thin film transistor is shown. In Embodiment 2, an example of the terminal portion of the source wiring was shown, but in this embodiment, the terminal portion of the source wiring having a configuration different from that of Embodiment 2 and the terminal portion of the gate wiring are illustrated. In FIG. 4, the same reference numerals are used for the same portions as in FIG. 3(A) or FIG. 3(B) for explanation. In Embodiment 2, an example of the terminal portion of the source wiring was shown. In this embodiment, the terminal portion of the source wiring having a configuration different from that of Embodiment 2 and the terminal portion of the gate wiring are illustrated. In FIG. 4, the same reference numerals are used for the same portions as in FIG. 3(A) or FIG. 3(B) for explanation. Explanation will be made.

[0143] FIGS. 4(A1) and 4(A2) respectively show a top view and a cross-sectional view of the gate wiring terminal portion. FIG. 4(A1) corresponds to a cross-sectional view taken along line C1-C2 in FIG. 4(A2). In FIG. 4(A1), the conductive layer 225 formed on the protective insulating layer 203 is a terminal electrode for connection that functions as an input terminal. Also, in FIG. 4(A1), in the terminal portion, the first terminal 221 formed of the same material as the gate electrode layer 421b and the connection electrode layers 223 and 228 formed of the same material as the source wiring overlap via the gate insulating layer 202 and are electrically connected by the conductive layer 225. Also, when the first terminal 221 has the configuration shown in FIG. 3(B), a metal wiring material can be used. In FIG. 4, the same reference numerals are used for the same portions as in FIG. 3(A) or FIG. 3(B) for explanation. (A1), the conductive layer 225 formed on the protective insulating layer 203 is a terminal electrode for connection that functions as an input terminal. Also, in FIG. 4(A1), in the terminal portion, the first terminal 221 formed of the same material as the gate electrode layer 421b and the connection electrode layers 223 and 228 formed of the same material as the source wiring overlap via the gate insulating layer 202 and are electrically connected by the conductive layer 225. Also, in FIG. 4(A1), in the terminal portion, the first terminal 221 formed of the same material as the gate electrode layer 421b and the connection electrode layers 223 and 228 formed of the same material as the source wiring overlap via the gate insulating layer 202 and are electrically connected by the conductive layer 225. Also, in FIG. 4(A1), in the terminal portion, the first terminal 221 formed of the same material as the gate electrode layer 421b and the connection electrode layers 223 and 228 formed of the same material as the source wiring overlap via the gate insulating layer 202 and are electrically connected by the conductive layer 225. Also, in FIG. 4(A1), in the terminal portion, the first terminal 221 formed of the same material as the gate electrode layer 421b and the connection electrode layers 223 and 228 formed of the same material as the source wiring overlap via the gate insulating layer 202 and are electrically connected by the conductive layer 225. Also, when the first terminal 221 has the configuration shown in FIG. 3(B), a metal wiring material can be used.

[0144] Also, FIGS. 4(B1) and 4(B2) respectively show a top view and a cross-sectional view of a source wiring terminal portion different from the source wiring terminal portion shown in FIG. 3(B). Also, FIG. 4(B1) corresponds to a cross-sectional view taken along line C3-C4 in FIG. 4(B2). In FIG. 4(B1), the conductive layer 225 formed on the protective insulating layer 203 is a terminal electrode for connection that functions as an input terminal. In FIG. 4, the same reference numerals are used for the same portions as in FIG. 3(A) or FIG. 3(B) for explanation. In FIG. 4(B1), the conductive layer 225 formed on the protective insulating layer 203 is a terminal electrode for connection that functions as an input terminal. In FIG. 4(B1), the conductive layer 225 formed on the protective insulating layer 203 is a terminal electrode for connection that functions as an input terminal. That is, in FIG. 4(B1), in the terminal portion, it is formed of the same material as the gate wiring. The electrode layer 226 overlaps below the second terminals 222 and 229 that are electrically connected to the source wiring via the gate insulating layer 202. The electrode layer 226 is not electrically connected to the second terminals 222 and 229. If the electrode layer 226 is set to a potential different from that of the second terminals 222 and 229, for example, floating, GND, 0V, etc., a capacitor for noise countermeasure or a capacitor for electrostatic countermeasure can be formed. Further, the second terminals 222 and 229 are electrically connected to the conductive layer 225 via the protective insulating layer 203. Also, the second terminals 222 and 229, which are a stack of conductive materials, can be a single layer of a metal wiring material when configured as shown in FIG. 3(B). A plurality of gate wirings, source wirings, and capacitor wirings are provided according to the pixel density. Also, in the terminal portion, a plurality of first terminals having the same potential as the gate wiring, second terminals having the same potential as the source wiring, third terminals having the same potential as the capacitor wiring, etc. are arranged side by side. The number of each terminal may be set to any number, and the implementer may appropriately determine it. This embodiment can be freely combined with Embodiment 1 or Embodiment 2. (Embodiment 4)

[0145] Here, in a liquid crystal display device in which a liquid crystal layer is enclosed between a first substrate and a second substrate, an example of forming a common connection portion for electrically connecting to a counter electrode provided on the second substrate on the first substrate is shown. Note that a thin film transistor is formed as a switching element on the first substrate.

[0146]

[0147] and the manufacturing process of the common connection part is made common with the manufacturing process of the switching element in the pixel part to form it without complicating the process

[0148] The common connection part is arranged at a position overlapping with the sealing material for bonding the first substrate and the second substrate and electrical connection with the counter electrode is made through the conductive particles contained in the sealing material. Or a common connection part is provided at a location not overlapping with the sealing material (excluding the pixel part), and a paste containing conductive particles is separately provided so as to overlap with the common connection part to make electrical connection with the counter electrode

[0149] FIG. 5(A) is a cross-sectional structure diagram of a semiconductor device in which a thin film transistor and a common connection part are manufactured on the same substrate

[0150] In FIG. 5(A), the thin film transistor 220 electrically connected to the pixel electrode layer 227 is a channel protection type thin film transistor provided in the pixel part, and in this embodiment, the same structure as the thin film transistor 448 of Embodiment 1 is used

[0151] Also, FIG. 5(B) is a diagram showing an example of a top view of the common connection part, and a cross-sectional view of the common connection part along the chain line C5 - C6 in the figure corresponds to FIG. 5(A). In FIG. 5(B), the same parts as those in FIG. 5(A ) are described using the same reference numerals

[0152] The common potential lines 205 and 210 are provided on the gate insulating layer 202 and are manufactured using the same material and the same process as the source electrode layer and the drain electrode layer of the thin film transistor 22 0

[0153] Also, the common potential lines 205 and 210 are covered with the protective insulating layer 203, and the protective insulating layer 203 is ​​​​It has a plurality of openings at positions overlapping the common potential lines 205 and 210. These openings are thin contact holes that connect the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227 and are formed in the same process.

[0154] Here, since the area sizes are significantly different, the contact holes in the pixel portion and the openings in the common connection portion will be referred to separately. Also, in Fig. 5(A), the pixel portion and the common connection portion are not shown at the same scale. For example, the length of the chain line C5 - C6 in the common connection portion is about 500 μm, while the width of the thin film transistor is less than 50 μm, and actually the area size is more than 10 times larger. However, for clarity, in Fig. 5(A), the scales of the pixel portion and the common connection portion are shown with different scales respectively.

[0155] Also, the common electrode layer 206 is provided on the protective insulating layer 203 and is formed of the same material and in the same process as the pixel electrode layer 227 in the pixel portion.

[0156] In this way, the manufacturing process of the common connection portion is made common with the manufacturing process of the switching element in the pixel portion. Perform.

[0157] Then, the first substrate provided with the pixel portion and the common connection portion and the second substrate having a counter electrode are fixed using a sealing material.

[0158] When the sealing material contains conductive particles, alignment of the pair of substrates is performed so that the sealing material overlaps the common connection portion. For example, in a small liquid crystal panel, two common connection portions are arranged overlapping the sealing material at the diagonal of the pixel portion. Also, in a large liquid crystal panel, four or more common connection portions are arranged overlapping the sealing material. 4 or more common connection portions are arranged overlapping the sealing material.

[0159] Note that the common electrode layer 206 is an electrode that contacts the conductive particles contained in the sealing material and is electrically connected to the counter electrode of the second substrate.

[0160] When using the liquid crystal injection method, after fixing a pair of substrates with a sealing material, the liquid crystal is injected between the pair of substrates. When using the liquid crystal droplet method, a sealing material is drawn on the second substrate or the first substrate, the liquid crystal is dropped, and then the pair of substrates are bonded together under reduced pressure. Note that in this embodiment, an example of the common connection portion that is electrically connected to the counter electrode is shown, but it is not particularly

[0161] limited and can be used for a connection portion that connects to other wirings or a connection portion that connects to an external connection terminal or the like.

[0162] Further, FIG. 5(C) shows a cross-sectional structure that is partially different from that of FIG. 5(A). FIG. 5(C) is the same as FIG. 5( A) in that there are an oxide semiconductor layer that overlaps the common electrode layer 206 and an oxide insulating layer that covers the end portion, and the configuration other than the point of using a metal wiring as the common potential line is the same. Therefore, the same reference numerals are used for the same locations, and the detailed description of the same locations is omitted.

[0163] The oxide semiconductor layer 207 is provided on the gate insulating layer 202 and is formed of the same material and in the same process as the oxide semiconductor layer of the thin film transistor 220. Further, an oxide insulating layer 208 that covers the oxide semiconductor layer 207 is formed. Then, a common potential line 209 made of a metal wiring is formed on the oxide semiconductor layer 207. This common potential line 209 made of a metal wiring is formed in the same process as the source electrode layer or the drain electrode layer of the thin film transistor of the drive circuit, as shown in FIG. 3(B) of Embodiment 2.

[0164] ​​​Also, the common potential line 209 is covered with a protective insulating layer 203, and the protective insulating layer 203 has a plurality of openings at positions overlapping the common potential line 209. These openings are formed in the same process as the contact hole that connects the drain electrode layer of the thin film transistor 2 20 and the pixel electrode layer 227. Manufactured.

[0165] Also, the common electrode layer 206 is provided on the protective insulating layer 203 and is manufactured using the same material and in the same process as the pixel electrode layer 227 in the pixel portion.

[0166] In this way, the manufacturing process of the common connection portion may be made common with the manufacturing process of the switching element in the pixel portion, and a configuration may be adopted in which the common potential line is used as a metal wiring to reduce the wiring resistance. Perform, and it may be configured to reduce the wiring resistance by using the common potential line as a metal wiring.

[0167] This embodiment can be freely combined with any one of Embodiments 1 to 3.

[0168] (Embodiment 5) In Embodiment 1 or Embodiment 2, an example in which the gate insulating layer is single-layered was shown, but in this embodiment an example of a laminate is shown. In FIG. 6, the same parts as those in FIG. 3(A) or FIG. 3(B) will be described using the same reference numerals.

[0169] In FIG. 6(A), the thin film transistor 280 is a channel protection type thin film transistor provided in the pixel portion, and is an example in which the gate insulating layer has two layers.

[0170] In this embodiment, a first gate insulating layer 282a having a thickness of 50 nm or more and 200 nm or less, and a gate insulating layer formed by laminating a second gate insulating layer 282b having a thickness of 50 nm or more and 300 nm or less is used. As the first gate insulating layer 282a, a silicon nitride film or a silicon oxynitride film having a thickness of 100 nm A silicon film is used. Also, as the second gate insulating layer 282b, a silicon oxide film with a thickness of 100 nm is used. A silicon film is used.

[0171] Also, the thin film transistor 280 includes a gate electrode layer 281, a first gate insulating layer 282a, a second gate insulating layer 282b, at least a channel formation region 283, a high-resistance source region 284a, a high-resistance drain region 284b, a source region 284c, a drain region 284d, an oxide semiconductor layer having them, a source electrode layer 285a, and a drain electrode layer 285b on a substrate having an insulating surface. Also, an oxide insulating layer 286a in contact with the channel formation region 283 is provided. Further, the pixel electrode layer 227 is electrically connected to the drain electrode layer 285b. A silicon film is used. 283, a high-resistance source region 284a, and a high-resistance drain region 284b, a source region 284c, a drain region 284d, an oxide semiconductor layer having them, a source electrode layer 285a, and a drain electrode layer 285b. Also, an oxide insulating layer 286a in contact with the channel formation region 283 is provided. Further, the pixel electrode layer 227 is electrically connected to the drain electrode layer 285b. 4c, a drain region 284d, an oxide semiconductor layer having them, a source electrode layer 285a, and a drain electrode layer 285b. Also, an oxide insulating layer 286a in contact with the channel formation region 283 is provided. Further, the pixel electrode layer 227 is electrically connected to the drain electrode layer 285b. An oxide insulating layer 286a in contact with the channel formation region 283 is provided. Further, the pixel electrode layer 227 is electrically connected to the drain electrode layer 285b. An oxide insulating layer 286a in contact with the channel formation region 283 is provided. Further, the pixel electrode layer 227 is electrically connected to the drain electrode layer 285b. An oxide insulating layer 286a in contact with the channel formation region 283 is provided. Further, the pixel electrode layer 227 is electrically connected to the drain electrode layer 285b.

[0172] The holding capacitor is provided below the pixel electrode layer 227, and the capacitor electrode 231 is electrically connected to the pixel electrode layer 227. The holding capacitor is provided below the pixel electrode layer 227, and the capacitor electrode 231 is electrically connected to the pixel electrode layer 227.

[0173] In this embodiment, the holding capacitor is formed using the capacitor electrode 231 and the capacitor wiring layer 230. In this embodiment, the holding capacitor is formed using the capacitor electrode 231 and the capacitor wiring layer 230.

[0174] Also, in FIG. 6(A), since the holding capacitor forms a large capacitance, only the gate insulating layer is provided between the capacitor wiring and the capacitor electrode. Also, in FIG. 6(A), since the holding capacitor forms a large capacitance, only the gate insulating layer is provided between the capacitor wiring and the capacitor electrode.

[0175] In this embodiment, a silicon oxide film obtained by sputtering is used as the oxide insulating layer 286b. When removing the oxide insulating layer overlapping the capacitor wiring layer 230, the second gate insulating layer, which is a silicon oxide film, is also etched and thinned to form the third gate insulating layer 282c. Note that the first gate insulating layer 282a is a silicon nitride film or a silicon oxynitride film and has etching resistance. In this embodiment, a silicon oxide film obtained by sputtering is used as the oxide insulating layer 286b. When removing the oxide insulating layer overlapping the capacitor wiring layer 230, the second gate insulating layer, which is a silicon oxide film, is also etched and thinned to form the third gate insulating layer 282c. Note that the first gate insulating layer 282a is a silicon nitride film or a silicon oxynitride film and has etching resistance. In this embodiment, a silicon oxide film obtained by sputtering is used as the oxide insulating layer 286b. When removing the oxide insulating layer overlapping the capacitor wiring layer 230, the second gate insulating layer, which is a silicon oxide film, is also etched and thinned to form the third gate insulating layer 282c. Note that the first gate insulating layer 282a is a silicon nitride film or a silicon oxynitride film and has etching resistance. In this embodiment, a silicon oxide film obtained by sputtering is used as the oxide insulating layer 286b. When removing the oxide insulating layer overlapping the capacitor wiring layer 230, the second gate insulating layer, which is a silicon oxide film, is also etched and thinned to form the third gate insulating layer 282c. Note that the first gate insulating layer 282a is a silicon nitride film or a silicon oxynitride film and has etching resistance. Function as a stopper to prevent etching damage to the gate electrode layer and the substrate.

[0176] By making the third gate insulating layer 282c thin, the holding capacitance can be increased. be achieved.

[0177] Also, FIG. 6(B) shows a cross-sectional structure that is partially different from that of FIG. 6(A).

[0178] In the thin film transistor 290 shown in FIG. 6(B), the first gate insulating layer 292a with a film thickness of 50 nm or more and 200 nm or less, and the second gate insulating layer 292b with a film thickness of 1 nm or more and 50 nm or less are used as a laminated gate insulating layer. As the first gate insulating layer 292a, a silicon oxide film with a film thickness of 100 nm is used. Also, as the second gate insulating layer 292b, a silicon nitride film or a silicon oxynitride film with a film thickness of 10 nm is used. The first gate insulating layer 292a uses a silicon oxide film with a film thickness of 100 nm. Also, as the second gate insulating layer 292b, a silicon nitride film or a silicon oxynitride film with a film thickness of 10 nm is used. The first gate insulating layer 292a uses a silicon oxide film with a film thickness of 100 nm. Also, as the second gate insulating layer 292b, a silicon nitride film or a silicon oxynitride film with a film thickness of 10 nm is used. are used.

[0179] The thin film transistor 290 includes a gate electrode layer 291, a first gate insulating layer 292a, a second gate insulating layer 292b, an oxide semiconductor layer having at least a channel formation region 293, a high-resistance source region 294a, and a high-resistance drain region 294b, a source electrode layer 295a, and a drain electrode layer 295b on a substrate 200 having an insulating surface. Also, an oxide insulating layer 296a in contact with the channel formation region 293 is provided. 1, a second gate insulating layer 292b, at least a channel formation region 293, a high-resistance source region 294a, and a high-resistance drain region 294b, an oxide semiconductor layer having a channel formation region 293, a high-resistance source region 294a, and a high-resistance drain region 294b, a source electrode layer 295a, and a drain electrode layer 295b on a substrate 200 having an insulating surface. Also, an oxide insulating layer 296a in contact with the channel formation region 293 is provided. The thin film transistor 290 includes a gate electrode layer 291, a first gate insulating layer 292a, a second gate insulating layer 292b, an oxide semiconductor layer having at least a channel formation region 293, a high-resistance source region 294a, and a high-resistance drain region 294b, a source electrode layer 295a, and a drain electrode layer 295b on a substrate 200 having an insulating surface. Also, an oxide insulating layer 296a in contact with the channel formation region 293 is provided. formation region 293, a high-resistance source region 294a, and a high-resistance drain region 294b, a source electrode layer 295a, and a drain electrode layer 295b on a substrate 200 having an insulating surface. Also, an oxide insulating layer 296a in contact with the channel formation region 293 is provided.

[0180] Also, the first region 294c and the second region 29 4d of the oxide semiconductor layer overlapping with the oxide insulating layer 296b are in the same oxygen-excessive state as the channel formation region 293, and also function to reduce leakage current and parasitic capacitance. Also, the third region 294e of the oxide semiconductor layer in contact with the protective insulating layer 203 is provided between the channel formation region 293 and the high-resistance source region 294a. oxide semiconductor layer overlapping with the oxide insulating layer 296b are in the same oxygen-excessive state as the channel formation region 293, and also function to reduce leakage current and parasitic capacitance. Also, the third region 294e of the oxide semiconductor layer in contact with the protective insulating layer 203 is provided between the channel formation region 293 and the high-resistance source region 294a. oxide semiconductor layer overlapping with the oxide insulating layer 296b are in the same oxygen-excessive state as the channel formation region 293, and also function to reduce leakage current and parasitic capacitance. Also, the third region 294e of the oxide semiconductor layer in contact with the protective insulating layer 203 is provided between the channel formation region 293 and the high-resistance source region 294a. This is also the case. Further, the fourth region 294f of the oxide semiconductor layer in contact with the protective insulating layer 203 is provided between the channel formation region 293 and the high-resistance drain region 294b. The third region 294e and the fourth region 294f of the oxide semiconductor layer in contact with the protective insulating layer 203 can reduce the off-current.

[0181] Further, the third region 294e and the fourth region 294f of the oxide semiconductor layer are also in contact with the second gate insulating layer 292b which is a silicon nitride film or a silicon oxynitride film. The protective insulating layer 203 contains no impurities such as moisture, hydrogen ions, and OH - and uses an inorganic insulating film that blocks these from entering from the outside, such as a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, or an aluminum oxynitride film.

[0182] Further, in this embodiment, a silicon oxide film obtained by sputtering is used as the oxide insulating layer 296b. When removing the oxide insulating layer overlapping with the capacitive wiring layer 230, the second gate insulating layer which is a silicon nitride film or a silicon oxynitride film is used as an etching stopper to etch the oxide insulating layer. This is an example.

[0183] Further, for a channel-protected thin-film transistor, in order to shorten the channel length L of the channel formation region, the width of the oxide insulating layer is narrowed, and when a source electrode layer and a drain electrode layer are provided on the narrow oxide insulating layer, there is a risk of short-circuiting on the oxide insulating layer. Therefore, the source electrode layer 295a and the drain electrode layer 295b are provided leaving the ends from the narrow oxide insulating layer 296a. This is the configuration.

[0184] This embodiment can be freely combined with any one of Embodiments 1 to 4.

[0185] (Embodiment 6) In this embodiment, a manufacturing process of a thin film transistor is partially different from that in Embodiment 1, as shown in FIG. 7 and 8 are the same as FIG. 1 and FIG. 2 except for some steps. Therefore, the same reference numerals are used for the same parts, and detailed descriptions of the same parts are omitted.

[0186] First, according to the first embodiment, a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer are formed on a substrate. The film 430 is formed, and the process up to the step of FIG. 2(A) in the first embodiment is carried out. FIG. 2(A) is This is the same as FIG. 8(A).

[0187] Then, the oxide semiconductor film 430 is formed into an island-shaped oxide semiconductor film by a second photolithography process. Process into body layers.

[0188] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400° C. or higher and lower than the distortion point of the substrate, preferably 425° C. or higher. If the temperature is 425℃ or higher, the heat treatment time can be 1 hour or less. The heat treatment time is longer than one hour. The substrate is placed in an electric furnace, and the oxide semiconductor layer is subjected to a heat treatment in a nitrogen atmosphere. After that, the oxide semiconductor layer is not exposed to the air, and water and hydrogen are prevented from re-mixing into the oxide semiconductor layer. After that, high-purity oxygen gas, high-purity N2O gas, or ultra-dry air is used in the same furnace. Cooling is performed by introducing oxygen gas (dew point is -40℃ or less, preferably -60℃ or less). It is preferable that the N2O gas does not contain water, hydrogen, etc. The purity of the oxygen gas or N2O gas to be introduced is preferably 6N (99.9999%) or more. should be 7N (99.99999%) or higher, that is, the impurity concentration in oxygen gas or N2O gas is 1 ppm or less, preferably 0.1 ppm or less).

[0189] Also, after the first heat treatment for dehydration or dehydrogenation, heating treatment may be performed in an oxygen gas or N2O gas atmosphere at a temperature of 200°C or higher and 400°C or lower, preferably 200°C or higher and 300°C or lower.

[0190] Also, the first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor film 430 before processing it into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out of the heating device, and a photolithography process is performed.

[0191] By going through the above steps, the entire oxide semiconductor film is made in an oxygen-excess state, thereby achieving high resistance, that is, type I conversion.

[0192] Next, after forming an oxide insulating film by sputtering on the gate insulating layer 402 and the oxide semiconductor layer, a resist mask is formed by a third photolithography process, and selective etching is performed to form the oxide insulating layers 426a and 426b, and then the resist mask is removed (see FIG. 8(B)).

[0193] Next, after forming a conductive film having translucency on the gate insulating layer 402, the oxide insulating layers 426a and 426b, and the oxide semiconductor layer 4 22, a resist mask is formed by a fourth photolithography process, and selective etching is performed to form the source electrode layer 425a and the drain electrode layer 425b (see FIG. 8(C)).

[0194] ​​​​​​​​Next, in order to reduce the variation in the electrical characteristics of the thin film transistor, a heat treatment is performed in an inert gas atmosphere or in a nitrogen gas atmosphere (preferably at a temperature of 150 °C or higher and lower than 350 °C). For example, a heat treatment is performed at 250 °C for 1 hour in a nitrogen atmosphere.

[0195] Next, a protective insulating layer 403 is formed on the oxide insulating layers 426a and 426b, the source electrode layer 425a, and the drain electrode layer 42 5b.

[0196] Next, a planarizing insulating layer 404 is formed on the protective insulating layer 403.

[0197] Next, a fifth photolithography process is performed to form a resist mask, and a contact hole 441 that reaches the drain electrode layer 425b is formed by etching the planarizing insulating layer 4 04 and the protective insulating layer 403, and the resist mask is removed (see Fig. 8(D)).

[0198] Next, a conductive film having translucency is formed.

[0199] Next, a sixth photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form the pixel electrode layer 427, and the resist mask is removed (see Fig. 8( E)).

[0200] Through the above steps, using six masks, a thin film transistor 420 and a wiring intersection portion with reduced parasitic capacitance can be fabricated on the same substrate.

[0201]

[0202] The thin film transistor 420 for pixels is a channel protection type thin film transistor including an oxide semiconductor layer 422 including a channel formation region.

[0202] ​Further, FIG. 7(A) is a plan view of a channel protection type thin film transistor 420 disposed in a pixel FIG. FIG. 7(B) is a cross-sectional view taken along line D7-D8 in FIG. 7(A) and a cross-sectional view taken along line D 11-D12 in FIG. 7(A). FIG. 7(C) is a cross-sectional view taken along line D9-D10 in FIG. 7(A). Note that FIG. 8(E) is the same as FIG. 7(B).

[0203] This embodiment can be freely combined with any one of Embodiments 1 to 5.

[0204] (Embodiment 7) In this embodiment, an example different from Embodiment 2 is shown in FIGS. 9(A) and FIG. 9(B) for the configuration of the holding capacitor. FIG. 9(A) is the same as FIG. 3(A) except for the difference in the configuration of the holding capacitor Therefore, the same reference numerals are used for the same parts, and detailed descriptions of the same parts are omitted. Note that FIG. 9 (A) shows a cross-sectional structure of the thin film transistor 220 in the pixel portion and the holding capacitor.

[0205] In FIG. 9(A), the dielectric is the protective insulating layer 203 and the planarizing insulating layer 204, and the holding capacitor is formed by the pixel electrode layer 2 27 and the capacitor wiring layer 250 overlapping the pixel electrode layer 227 . The capacitor wiring layer 250 has the same light transmissivity as the source electrode layer of the thin film transistor 220 in the pixel portion and is formed in the same process, so it is laid out so as not to overlap the source wiring layer of the thin film transistor 220 .

[0206] The holding capacitor shown in FIG. 9(A) has a pair of electrodes and a dielectric having light transmissivity, and the entire holding capacitor has light transmissivity.

[0207] Further, FIG. 9(B) is an example of a configuration of a holding capacitor different from FIG. 9(A). FIG. 9(B) is also FIG Since this is the same as 3(A) except for the difference in the storage capacitance, the same symbols are used for the same parts. Detailed explanations of the same parts will be omitted.

[0208] FIG. 9B shows a structure in which the dielectric is a gate insulating layer 202, a capacitance wiring layer 230, and the capacitance wiring layer 2 In this example, a storage capacitor is formed by laminating an oxide semiconductor layer 251 and a capacitor electrode 231 that overlap with the oxide semiconductor layer 30. In addition, the capacitance electrode 231 is laminated on the oxide semiconductor layer 251 in contact therewith, and a storage capacitance The oxide semiconductor layer 251 functions as one electrode of the thin film transistor 22. The capacitor wiring layer is formed of the same material having a light-transmitting property as the oxide semiconductor layer of 0 in the same process. 230 is a layer made of the same material and process as the gate electrode layer of the thin film transistor 220. Therefore, the layout is designed so as not to overlap with the gate wiring layer of the thin film transistor 220. In addition, the capacitance electrode 231 is electrically connected to the pixel electrode layer 227.

[0209] The storage capacitor shown in FIG. 9B also has a pair of electrodes and a dielectric material that are transparent, and the entire storage capacitor The body is translucent.

[0210] The storage capacitor shown in FIG. 9(A) and FIG. 9(B) has a light-transmitting property, and the number of gate wirings is In order to increase the resolution of displayed images, it is necessary to increase the capacity of the display even if the pixel size is reduced. It is possible to obtain a high aperture ratio.

[0211] This embodiment mode can be freely combined with other embodiment modes.

[0212] (Embodiment 8) In this embodiment, at least a part of the driver circuit and a thin film transistor to be disposed in the pixel portion are formed on the same substrate. An example of fabricating a transistor will be described below.

[0213] The thin film transistors arranged in the pixel section are formed according to Embodiments 1, 2, 5, and 6. Also, since the thin film transistors shown in Embodiments 1, 2, 5, and 6 are n-channel type TFTs, a part of the drive circuit that can be composed of n-channel type TFTs among the drive circuits is formed on the same substrate as the thin film transistors in the pixel section.

[0214] An example of a block diagram of an active matrix type display device is shown in FIG. 14(A). On the substrate 5300 of the display device, there are a pixel section 5301, a first scan line drive circuit 5302, a second scan line drive circuit 5303, and a signal line drive circuit 5304. In the pixel section 5301, a plurality of signal lines extend from the signal line drive circuit 5304 and are arranged, and a plurality of scan lines extend from the first scan line drive circuit 5302 and the scan line drive circuit 5303 and are arranged. Note that pixels each having a display element are arranged in a matrix in the intersection region of the scan lines and the signal lines. Also, the substrate 5300 of the display device is connected to a timing control circuit 5305 (also referred to as a controller or a control IC) via a connection part such as an FPC (Flexible Printed Circu it).

[0215] In FIG. 14(A), the first scan line drive circuit 5302, the second scan line drive circuit 5303, and the signal line drive circuit 5304 are formed on the same substrate 5300 as the pixel section 5301. Therefore, the number of components such as drive circuits provided outside is reduced, so that cost reduction can be achieved. Also, when a drive circuit is provided outside the substrate 5300, the number of connections at the connection part due to extending the wiring can be reduced, and improvement in reliability or yield can be achieved.

[0216] Note that the timing control circuit 5305 supplies, as an example, a start signal for the first scanning line driving circuit (GSP1) and a clock signal for the scanning line driving circuit (GCK1) to the first scanning line driving circuit 5302. Further, the timing control circuit 5305 supplies, as an example, a start signal for the second scanning line driving circuit (GSP2) (also referred to as a start pulse) and a clock signal for the scanning line driving circuit (GCK2) to the second scanning line driving circuit 5303. The signal line driving circuit 5304 is supplied with a start signal for the signal line driving circuit (SSP), a clock signal for the signal line driving circuit (SCK), video signal data (simply referred to as a video signal) (DATA), and a latch signal (LAT). Each clock signal may be a plurality of clock signals with a phase shift, or may be supplied together with a signal (CKB) obtained by inverting the clock signal. Note that either the first scanning line driving circuit 5302 or the second scanning line driving circuit 53 03 can be omitted. (SCK), video signal data (simply referred to as a video signal) (DATA), and a latch signal (LAT). Each clock signal may be a plurality of clock signals with a phase shift, or may be supplied together with a signal (CKB) obtained by inverting the clock signal. Note that either the first scanning line driving circuit 5302 or the second scanning line driving circuit 53 03 can be omitted. clock signals with a phase shift, or may be supplied together with a signal (CKB) obtained by inverting the clock signal. Note that either the first scanning line driving circuit 5302 or the second scanning line driving circuit 53 03 can be omitted. 03 can be omitted.

[0217] In FIG. 14(B), a circuit with a low driving frequency (for example, the first scanning line driving circuit 5302 and the second scanning line driving circuit 5303) is formed on the same substrate 5300 as the pixel portion 5301, and a configuration in which the signal line driving circuit 5304 is formed on a substrate different from the pixel portion 5301 is shown. With this configuration, a driving circuit formed on the substrate 5300 can be configured by a thin film transistor having a smaller field effect mobility as compared with a transistor using a single crystal semiconductor. Therefore, it is possible to achieve an increase in the size of the display device, a reduction in cost, or an improvement in yield. In FIG. 14(B), a circuit with a low driving frequency (for example, the first scanning line driving circuit 5302 and the second scanning line driving circuit 5303) is formed on the same substrate 5300 as the pixel portion 5301, and a configuration in which the signal line driving circuit 5304 is formed on a substrate different from the pixel portion 5301 is shown. With this configuration, a driving circuit formed on the substrate 5300 can be configured by a thin film transistor having a smaller field effect mobility as compared with a transistor using a single crystal semiconductor. Therefore, it is possible to achieve an increase in the size of the display device, a reduction in cost, or an improvement in yield. 5303) is formed on the same substrate 5300 as the pixel portion 5301, and a configuration in which the signal line driving circuit 5304 is formed on a substrate different from the pixel portion 5301 is shown. With this configuration, a driving circuit formed on the substrate 5300 can be configured by a thin film transistor having a smaller field effect mobility as compared with a transistor using a single crystal semiconductor. Therefore, it is possible to achieve an increase in the size of the display device, a reduction in cost, or an improvement in yield. 5303) is formed on the same substrate 5300 as the pixel portion 5301, and a configuration in which the signal line driving circuit 5304 is formed on a substrate different from the pixel portion 5301 is shown. With this configuration, a driving circuit formed on the substrate 5300 can be configured by a thin film transistor having a smaller field effect mobility as compared with a transistor using a single crystal semiconductor. Therefore, it is possible to achieve an increase in the size of the display device, a reduction in cost, or an improvement in yield. Therefore, it is possible to achieve an increase in the size of the display device, a reduction in cost, or an improvement in yield.

[0218] In addition, the thin film transistors shown in Embodiments 1, 2, 5, and 6 are n-channel type TFTs. In FIGS. 15(A) and 15(B), a configuration of a signal line driving circuit composed of n-channel type TFTs and an example of its operation will be shown and described.

[0219] The signal line driving circuit includes a shift register 5601 and a switching circuit 5602. The switching circuit 5602 includes a plurality of circuits such as switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each include a plurality of transistors such as thin film transistors 5603_1 to 5603_k (k is a natural number). An example in which the thin film transistors 5603_1 to 5603_k are N-channel type TFTs will be described.

[0220] The connection relationship of the signal line driving circuit will be described by taking the switching circuit 5602_1 as an example. The first terminals of the thin film transistors 5603_1 to 5603_k are each connected to wirings 5604_1 to 5604_k. The second terminals of the thin film transistors 5603_1 to 5603_k are each connected to signal lines S1 to Sk. The gates of the thin film transistors 5603_1 to 5603_ k are connected to the wiring 5605_1.

[0221] The shift register 5601 outputs signals of H level (also referred to as H signal , high power supply potential level) to the wirings 5605_1 to 5605_N in order, and has a function of sequentially selecting the switching circuits 5602_1 to 56 02_N.

[0222] The switching circuit 5602_1 connects the wirings 5604_1 to 5604_k and the signal lines S1 to Sk ​to control the conduction state (conduction between the first terminal and the second terminal), that is, wiring 5604_ has a function of controlling whether to supply the potentials of 1 to 5604_k to the signal lines S1 to Sk. Thus, the switching circuit 5602_1 has a function as a selector. Also, the thin film transistors 5603_1 to 5603_k each have a function of controlling the conduction state between the wiring 5604_1 to 5604_k and the signal lines S1 to Sk, that is, a function of supplying the potentials of the wiring 5604_1 to 5604_k to the signal lines S1 to Sk. Thus, the thin film transistors 56 03_1 to 5603_k each have a function as a switch.

[0223] Note that video signal data (DATA) is input to each of the wirings 5604_1 to 5604_k. The video signal data (DATA) is often an analog signal corresponding to image information or an image signal.

[0224] Next, the operation of the signal line driving circuit in Fig. 15(A) will be described with reference to the timing chart in Fig. 15(B). In Fig. 15(B), examples of the signals Sout_1 to Sout_N and the signals Vdata_1 to Vdata_k are shown. The signals Sout_1 to Sout_N are each an example of the output signals of the shift register 5601, and the signals Vdata_1 to Vdata _k are each an example of the signals input to the wirings 5604_1 to 5604_k. Note that one operation period of the signal line driving circuit corresponds to one gate selection period in the display device. One gate selection period is divided into periods T1 to TN as an example. The periods T1 to TN are each a period for writing video signal data (DATA) to the pixels belonging to the selected row.

[0225] ​​​ Note that, in the drawings and the like of this embodiment, the signal waveform distortion and the like of each component shown may be exaggerated for clarity. Therefore, it is noted that it is not necessarily limited to that scale.

[0226] During periods T1 to TN, the shift register 5601 sequentially outputs a signal of H level to wirings 5605_1 to 5605_N. For example, during period T1, the shift register 5601 outputs a high-level signal to wiring 5605_1. Then, since the thin film transistors 5603_1 to 5603_k turn on, wirings 5604_1 to 5604_k and signal lines S1 to Sk are in a conductive state. At this time, Data(S1) to Data(Sk) are input to wirings 5604_1 to 5604_k. Data(S1) to Data(Sk) are written to the pixels in the first column to the k-th column among the pixels belonging to the selected row via the thin film transistors 5603_1 to 5603_k, respectively. Thus, during periods T1 to TN, video signal data (DATA) is written to the pixels belonging to the selected row, k columns at a time in order.

[0227] As described above, by writing video signal data (DATA) to pixels in multiple columns at a time, the number of video signal data (DATA) or the number of wirings can be reduced. Therefore, the number of connections to the external circuit can be reduced. Also, by writing the video signal to pixels in multiple columns at a time, the writing time can be lengthened, and insufficient writing of the video signal can be prevented.

[0228] Note that, as the shift register 5601 and the switching circuit 5602, in the first embodiment It is possible to use a circuit composed of the thin film transistors shown in 2, 5, and 6. In this case, all the transistors included in the shift register 5601 can be configured with only one of the polarities of N-channel type or P-channel type.

[0229] A form of the shift register used in part of the scanning line driving circuit and / or the signal line driving circuit will be described with reference to FIGS. 16 and 17.

[0230] The scanning line driving circuit has a shift register. In some cases, it may also have a level shifter, a buffer, etc. In the scanning line driving circuit, when a clock signal (CLK) and a start pulse signal (SP) are input to the shift register, a selection signal is generated. The generated selection signal is buffer-amplified in the buffer and supplied to the corresponding scanning line. To the scanning line, the gate electrodes of the transistors of one line of pixels are connected. And since the transistors of one line of pixels must be turned on all at once, a buffer that can pass a large current is used.

[0231] The shift registers of the scanning line driving circuit and the signal line driving circuit will be described with reference to FIGS. 16 and 17. The shift register has a first pulse output circuit 10_1 to an Nth pulse output circuit 10_N (N is a natural number of 3 or more) (see FIG. 16(A)). In the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N of the shift register shown in FIG. 16(A), a first clock signal CK1 from a first wiring 11, a second clock signal CK2 from a second wiring 12, a third clock signal CK3 from a third The clock signal CK4 is supplied. Also, in the first pulse output circuit 10_1, the start pulse SP1 (the first start pulse) from the fifth line 15 is input. Also, in the nth pulse output circuit 10_n (n is a natural number from 2 to N) after the second stage, the signal from the pulse output circuit one stage before (referred to as the previous stage signal OUT(n - 1)) is input. Also, in the first pulse output circuit 10_1, the signal from the third pulse output circuit 10_3 two stages after is input. Similarly, in the nth pulse output circuit 10_n after the second stage or later, the signal from the (n + 2)th pulse output circuit 10_(n + 2) two stages after (referred to as the subsequent stage signal OUT(n + 2)) is input. Therefore, also from each stage of the pulse output circuit, the first output signal (OUT(1)(SR) to OUT(N)(SR)) for input to the subsequent stage and / or the pulse output circuit two stages before and the second output signal (OUT(1) to OUT(N)) for input to another circuit or the like are output. Note that, as shown in FIG. 16(A), since the subsequent stage signal OUT(n + 2) is not input to the last two stages of the shift register, as an example, a configuration in which the second start pulse SP2 and the third start pulse SP3 are separately input may be adopted. The start pulse SP1 (the first start pulse) from the fifth line 15 is input. Also, in the second stage and after, in the nth pulse output circuit 10_n (n is a natural number from 2 to N), the signal from the pulse output circuit one stage before (referred to as the previous stage signal OUT(n - 1)) is input. Also, in the first pulse output circuit 10_1, the signal from the third pulse output circuit 10_3 two stages after is input. Similarly, in the nth pulse output circuit 10_n after the second stage or later, the signal from the (n + 2)th pulse output circuit 10_(n + 2) two stages after (referred to as the subsequent stage signal OUT(n + 2)) is input. Therefore, also from each stage of the pulse output circuit, the first output signal (OUT(1)(SR) to OUT(N)(SR)) for input to the subsequent stage and / or the pulse output circuit two stages before and the second output signal (OUT(1) to OUT(N)) for input to another circuit or the like are output. Note that, as shown in FIG. 16(A), since the subsequent stage signal OUT(n + 2) is not input to the last two stages of the shift register, as an example, a configuration in which the second start pulse SP2 and the third start pulse SP3 are separately input may be adopted. In the nth pulse output circuit 10_n (n is a natural number from 2 to N) after the second stage and later, the signal from the pulse output circuit one stage before (referred to as the previous stage signal OUT(n - 1)) is input. Also, in the first pulse output circuit 10_1, the signal from the third pulse output circuit 10_3 two stages after is input. Similarly, in the nth pulse output circuit 10_n after the second stage or later, the signal from the (n + 2)th pulse output circuit 10_(n + 2) two stages after (referred to as the subsequent stage signal OUT(n + 2)) is input. Therefore, also from each stage of the pulse output circuit, the first output signal (OUT(1)(SR) to OUT(N)(SR)) for input to the subsequent stage and / or the pulse output circuit two stages before and the second output signal (OUT(1) to OUT(N)) for input to another circuit or the like are output. Note that, as shown in FIG. 16(A), since the subsequent stage signal OUT(n + 2) is not input to the last two stages of the shift register, as an example, a configuration in which the second start pulse SP2 and the third start pulse SP3 are separately input may be adopted. In the nth pulse output circuit 10_n (n is a natural number from 2 to N) after the second stage and later, the signal from the pulse output circuit one stage before (referred to as the previous stage signal OUT(n - 1)) is input. Also, in the first pulse output circuit 10_1, the signal from the third pulse output circuit 10_3 two stages after is input. Similarly, in the nth pulse output circuit 10_n after the second stage or later, the signal from the (n + 2)th pulse output circuit 10_(n + 2) two stages after (referred to as the subsequent stage signal OUT(n + 2)) is input. Therefore, also from each stage of the pulse output circuit, the first output signal (OUT(1)(SR) to OUT(N)(SR)) for input to the subsequent stage and / or the pulse output circuit two stages before and the second output signal (OUT(1) to OUT(N)) for input to another circuit or the like are output. Note that, as shown in FIG. 16(A), since the subsequent stage signal OUT(n + 2) is not input to the last two stages of the shift register, as an example, a configuration in which the second start pulse SP2 and the third start pulse SP3 are separately input may be adopted. In the first pulse output circuit 10_1, the signal from the third pulse output circuit 10_3 two stages after is input. Similarly, in the nth pulse output circuit 10_n after the second stage or later, the signal from the (n + 2)th pulse output circuit 10_(n + 2) two stages after (referred to as the subsequent stage signal OUT(n + 2)) is input. Therefore, also from each stage of the pulse output circuit, the first output signal (OUT(1)(SR) to OUT(N)(SR)) for input to the subsequent stage and / or the pulse output circuit two stages before and the second output signal (OUT(1) to OUT(N)) for input to another circuit or the like are output. Note that, as shown in FIG. 16(A), since the subsequent stage signal OUT(n + 2) is not input to the last two stages of the shift register, as an example, a configuration in which the second start pulse SP2 and the third start pulse SP3 are separately input may be adopted. In the first pulse output circuit 10_1, the signal from the third pulse output circuit 10_3 two stages after is input. Similarly, in the nth pulse output circuit 10_n after the second stage or later, the signal from the (n + 2)th pulse output circuit 10_(n + 2) two stages after (referred to as the subsequent stage signal OUT(n + 2)) is input. Therefore, also from each stage of the pulse output circuit, the first output signal (OUT(1)(SR) to OUT(N)(SR)) for input to the subsequent stage and / or the pulse output circuit two stages before and the second output signal (OUT(1) to OUT(N)) for input to another circuit or the like are output. Note that, as shown in FIG. 16(A), since the subsequent stage signal OUT(n + 2) is not input to the last two stages of the shift register, as an example, a configuration in which the second start pulse SP2 and the third start pulse SP3 are separately input may be adopted. In the nth pulse output circuit 10_n after the second stage or later, the signal from the (n + 2)th pulse output circuit 10_(n + 2) two stages after (referred to as the subsequent stage signal OUT(n + 2)) is input. Therefore, also from each stage of the pulse output circuit, the first output signal (OUT(1)(SR) to OUT(N)(SR)) for input to the subsequent stage and / or the pulse output circuit two stages before and the second output signal (OUT(1) to OUT(N)) for input to another circuit or the like are output. Note that, as shown in FIG. 16(A), since the subsequent stage signal OUT(n + 2) is not input to the last two stages of the shift register, as an example, a configuration in which the second start pulse SP2 and the third start pulse SP3 are separately input may be adopted. In the nth pulse output circuit 10_n after the second stage or later, the signal from the (n + 2)th pulse output circuit 10_(n + 2) two stages after (referred to as the subsequent stage signal OUT(n + 2)) is input. Therefore, also from each stage of the pulse output circuit, the first output signal (OUT(1)(SR) to OUT(N)(SR)) for input to the subsequent stage and / or the pulse output circuit two stages before and the second output signal (OUT(1) to OUT(N)) for input to another circuit or the like are output. Note that, as shown in FIG. 16(A), since the subsequent stage signal OUT(n + 2) is not input to the last two stages of the shift register, as an example, a configuration in which the second start pulse SP2 and the third start pulse SP3 are separately input may be adopted. Therefore, also from each stage of the pulse output circuit, the first output signal (OUT(1)(SR) to OUT(N)(SR)) for input to the subsequent stage and / or the pulse output circuit two stages before and the second output signal (OUT(1) to OUT(N)) for input to another circuit or the like are output. Note that, as shown in FIG. 16(A), since the subsequent stage signal OUT(n + 2) is not input to the last two stages of the shift register, as an example, a configuration in which the second start pulse SP2 and the third start pulse SP3 are separately input may be adopted. Therefore, also from each stage of the pulse output circuit, the first output signal (OUT(1)(SR) to OUT(N)(SR)) for input to the subsequent stage and / or the pulse output circuit two stages before and the second output signal (OUT(1) to OUT(N)) for input to another circuit or the like are output. Note that, as shown in FIG. 16(A), since the subsequent stage signal OUT(n + 2) is not input to the last two stages of the shift register, as an example, a configuration in which the second start pulse SP2 and the third start pulse SP3 are separately input may be adopted. Therefore, also from each stage of the pulse output circuit, the first output signal (OUT(1)(SR) to OUT(N)(SR)) for input to the subsequent stage and / or the pulse output circuit two stages before and the second output signal (OUT(1) to OUT(N)) for input to another circuit or the like are output. Note that, as shown in FIG. 16(A), since the subsequent stage signal OUT(n + 2) is not input to the last two stages of the shift register, as an example, a configuration in which the second start pulse SP2 and the third start pulse SP3 are separately input may be adopted. Note that, as shown in FIG. 16(A), since the subsequent stage signal OUT(n + 2) is not input to the last two stages of the shift register, as an example, a configuration in which the second start pulse SP2 and the third start pulse SP3 are separately input may be adopted. Note that, as shown in FIG. 16(A), since the subsequent stage signal OUT(n + 2) is not input to the last two stages of the shift register, as an example, a configuration in which the second start pulse SP2 and the third start pulse SP3 are separately input may be adopted. Note that, as shown in FIG. 16(A), since the subsequent stage signal OUT(n + 2) is not input to the last two stages of the shift register, as an example, a configuration in which the second start pulse SP2 and the third start pulse SP3 are separately input may be adopted.

[0232] Note that the clock signal (CK) is a signal that repeats the H level and the L level (also referred to as the L signal, the low power supply potential level) at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal (CK4) are sequentially delayed by 1 / 4 cycle. In the present embodiment, the first clock signal (CK1) to the fourth clock signal (CK4) are used to control the driving of the pulse output circuit and the like. Note that the clock signal, depending on the input driving circuit, is GCK. Note that the clock signal (CK) is a signal that repeats the H level and the L level (also referred to as the L signal, the low power supply potential level) at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal (CK4) are sequentially delayed by 1 / 4 cycle. In the present embodiment, the first clock signal (CK1) to the fourth clock signal (CK4) are used to control the driving of the pulse output circuit and the like. Note that the clock signal, depending on the input driving circuit, is GCK. Here, the first clock signal (CK1) to the fourth clock signal (CK4) are sequentially delayed by 1 / 4 cycle. In the present embodiment, the first clock signal (CK1) to the fourth clock signal (CK4) are used to control the driving of the pulse output circuit and the like. Note that the clock signal, depending on the input driving circuit, is GCK. Here, the first clock signal (CK1) to the fourth clock signal (CK4) are sequentially delayed by 1 / 4 cycle. In the present embodiment, the first clock signal (CK1) to the fourth clock signal (CK4) are used to control the driving of the pulse output circuit and the like. Note that the clock signal, depending on the input driving circuit, is GCK. In the present embodiment, the first clock signal (CK1) to the fourth clock signal (CK4) are used to control the driving of the pulse output circuit and the like. Note that the clock signal, depending on the input driving circuit, is GCK. 、Although it may also be referred to as SCK, it will be described as CK here.

[0233] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first wiring 11 ~ the fourth wiring 14. For example, in FIG. 16(A) , in the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11 continued, the second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the third wiring 13. Also, in the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, the second input terminal 22 is the third wiring 13 is electrically connected, and the third input terminal 23 is electrically connected to the fourth wiring 14 is.

[0234] Each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N has a first input terminal 21, the second input terminal 22, the third input terminal 23, the fourth input terminal 24, the fifth input terminal 25, the first output terminal 26, and the second output terminal 27 (see FIG. 16(B)). In the first pulse output circuit 10_1, the first clock signal CK1 is input to the first input terminal 21, the second clock signal CK2 is input to the second input terminal 22, the third clock signal CK3 is input to the input terminal 23, the start pulse is input to the fourth input terminal 24, the subsequent stage signal OUT(3) is input to the fifth input terminal 25, and the first output signal OUT(1)(SR) is output from the first output terminal 26, and the second output signal OUT(1) is output from the second output terminal 27 . will be. is output. will be output.

[0235] Note that the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N can use, in addition to the three-terminal thin film transistor (also referred to as TFT: Thin Film Transistor), the four-terminal thin film transistor described in the above-described embodiments. FIG. 16(C) shows the symbol of the four-terminal thin film transistor 28 described in the above-described embodiments. The symbol of the thin film transistor 28 shown in FIG. 16(C) means the four-terminal thin film transistor described in any one of the above-described Embodiments 1, 2, 5, and 6, and will be used hereinafter in the drawings and the like. In this specification, when a thin film transistor has two gate electrodes via a semiconductor layer, the gate electrode below the semiconductor layer is called the lower gate electrode, and the gate electrode above the semiconductor layer is also called the upper gate electrode. The thin film transistor 28 is an element capable of electrically controlling between the In terminal and the Out terminal by the first control signal G1 input to the lower gate electrode and the second control signal G2 input to the upper gate electrode. When an oxide semiconductor is used for the semiconductor layer including the channel formation region of the thin film transistor, the threshold voltage may shift to the minus side or the plus side during the manufacturing process. Therefore, in a thin film transistor using an oxide semiconductor for the semiconductor layer including the channel formation region, a configuration capable of controlling the threshold voltage is preferable. The threshold voltage of the four-terminal thin film transistor 28 shown in FIG. 16(C) can be controlled to a desired value by providing gate electrodes via a gate insulating film above and below the channel formation region of the thin film transistor 28 and controlling the potentials of the upper and / or lower gate electrodes. The above-described embodiments have been described with reference to the drawings. The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. For example, in the above-described embodiments, the case where the oxide semiconductor is used for the semiconductor layer including the channel formation region of the thin film transistor has been described. However, the present invention is not limited to this, and other semiconductor materials can be used. In addition, in the above-described embodiments, the case where the thin film transistor has two gate electrodes via the semiconductor layer has been described. However, the present invention is not limited to this, and the thin film transistor may have one gate electrode or three or more gate electrodes. Furthermore, in the above-described embodiments, the case where the thin film transistor is used for the pulse output circuit has been described. However, the present invention is not limited to this, and the thin film transistor can be used for other circuits. In addition, in the above-described embodiments, the case where the oxide semiconductor is used for the semiconductor layer including the channel formation region of the thin film transistor has been described. However, the present invention is not limited to this, and other semiconductor materials can be used. Furthermore, in the above-described embodiments, the case where the thin film transistor has two gate electrodes via the semiconductor layer has been described. However, the present invention is not limited to this, and the thin film transistor may have one gate electrode or three or more gate electrodes. In addition, in the above-described embodiments, the case where the thin film transistor is used for the pulse output circuit has been described. However, the present invention is not limited to this, and the thin film transistor can be used for other circuits. In addition, in the above-described embodiments, the case where the oxide semiconductor is used for the semiconductor layer including the channel formation region of the thin film transistor has been described. However, the present invention is not limited to this, and other semiconductor materials can be used. Furthermore, in the above-described embodiments, the case where the thin film transistor has two gate electrodes via the semiconductor layer has been described. However, the present invention is not limited to this, and the thin film transistor may have one gate electrode or three or more gate electrodes.

[0236] When an oxide semiconductor is used for the semiconductor layer including the channel formation region of the thin film transistor, the manufacturing process may cause the threshold voltage to shift to the minus side or the plus side. Therefore, in a thin film transistor using an oxide semiconductor for the semiconductor layer including the channel formation region, a configuration capable of controlling the threshold voltage is preferable. The threshold voltage of the four-terminal thin film transistor 28 shown in FIG. 16(C) can be controlled to a desired value by providing gate electrodes via a gate insulating film above and below the channel formation region of the thin film transistor 28 and controlling the potentials of the upper and / or lower gate electrodes. In addition, in the above-described embodiments, the case where the oxide semiconductor is used for the semiconductor layer including the channel formation region of the thin film transistor has been described. However, the present invention is not limited to this, and other semiconductor materials can be used. Furthermore, in the above-described embodiments, the case where the thin film transistor has two gate electrodes via the semiconductor layer has been described. However, the present invention is not limited to this, and the thin film transistor may have one gate electrode or three or more gate electrodes. In addition, in the above-described embodiments, the case where the thin film transistor is used for the pulse output circuit has been described. However, the present invention is not limited to this, and the thin film transistor can be used for other circuits. In addition, in the above-described embodiments, the case where the oxide semiconductor is used for the semiconductor layer including the channel formation region of the thin film transistor has been described. However, the present invention is not limited to this, and other semiconductor materials can be used. Furthermore, in the above-described embodiments, the case where the thin film transistor has two gate electrodes via the semiconductor layer has been described. However, the present invention is not limited to this, and the thin film transistor may have one gate electrode or three or more gate electrodes.

[0237] Next, an example of the specific circuit configuration of the pulse output circuit shown in FIG. 16(B) will be described with reference to FIG. 16 (D).

[0238] The first pulse output circuit 10_1 shown in FIG. 16(D) includes first transistors 31 to 13th transistor 43. In addition to the first input terminal 21 to the fifth input terminal 25, and the first output terminal 26 and the second output terminal 27, a power supply line 51 to which the first high power supply potential VDD is supplied, a power supply line 52 to which the second high power supply potential VCC is supplied, and a power supply line 53 to which the low power supply potential VSS is supplied, signals or power supply potentials are supplied to the first transistor 31 to the 13th transistor 4 3. Here, the magnitude relationship of the power supply potentials of the respective power supply lines in FIG. 16(D) is such that the first power supply potential VDD is a potential equal to or higher than the second power supply potential VCC, and the second power supply potential VCC is a potential higher than the third power supply potential VSS. Note that the first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat the H level and the L level at regular intervals, and it is assumed that they are VDD when at the H level and VSS when at the L level. By making the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, the potential applied to the gate electrode of the transistor can be kept low without affecting the operation, the shift of the threshold value of the transistor can be reduced, and deterioration can be suppressed. As shown in FIG. 16(D), among the first transistor 31 to the 13th transistor 43, it is preferable to use the four-terminal thin film transistor 28 shown in FIG. 16(C) for the first transistor 31, the sixth transistor 36 to the ninth transistor 39. The operations of the first transistor 31, the sixth transistor 36 to the ninth transistor 39 are the source ​​​​​​A transistor is required to switch the potential of a node to which one of the electrodes serving as a source or a drain is connected by a control signal of a gate electrode. The transistor has a fast response to the control signal input to the gate electrode (the rise of the on-current is steep), so that the malfunction of the pulse output circuit can be reduced. Therefore, by using the thin film transistor 28 with four terminals shown in Fig. 16(C), the threshold voltage can be controlled, and a pulse output circuit with less malfunction can be obtained. In Fig. 16(D), the first control signal G1 and the second control signal G2 are the same control signal, but a configuration in which different control signals are input may also be used. A transistor is required to switch the potential of a node to which one of the electrodes serving as a source or a drain is connected by a control signal of a gate electrode. The transistor has a fast response to the control signal input to the gate electrode (the rise of the on-current is steep), so that the malfunction of the pulse output circuit can be reduced. Therefore, by using the thin film transistor 28 with four terminals shown in Fig. 16(C), the threshold voltage can be controlled, and a pulse output circuit with less malfunction can be obtained. In Fig. 16(D), the first control signal G1 and the second control signal G2 are the same control signal, but a configuration in which different control signals are input may also be used. A transistor is required to switch the potential of a node to which one of the electrodes serving as a source or a drain is connected by a control signal of a gate electrode. The transistor has a fast response to the control signal input to the gate electrode (the rise of the on-current is steep), so that the malfunction of the pulse output circuit can be reduced. Therefore, by using the thin film transistor 28 with four terminals shown in Fig. 16(C), the threshold voltage can be controlled, and a pulse output circuit with less malfunction can be obtained. In Fig. 16(D), the first control signal G1 and the second control signal G2 are the same control signal, but a configuration in which different control signals are input may also be used. A transistor is required to switch the potential of a node to which one of the electrodes serving as a source or a drain is connected by a control signal of a gate electrode. The transistor has a fast response to the control signal input to the gate electrode (the rise of the on-current is steep), so that the malfunction of the pulse output circuit can be reduced. Therefore, by using the thin film transistor 28 with four terminals shown in Fig. 16(C), the threshold voltage can be controlled, and a pulse output circuit with less malfunction can be obtained. In Fig. 16(D), the first control signal G1 and the second control signal G2 are the same control signal, but a configuration in which different control signals are input may also be used. A transistor is required to switch the potential of a node to which one of the electrodes serving as a source or a drain is connected by a control signal of a gate electrode. The transistor has a fast response to the control signal input to the gate electrode (the rise of the on-current is steep), so that the malfunction of the pulse output circuit can be reduced. Therefore, by using the thin film transistor 28 with four terminals shown in Fig. 16(C), the threshold voltage can be controlled, and a pulse output circuit with less malfunction can be obtained. In Fig. 16(D), the first control signal G1 and the second control signal G2 are the same control signal, but a configuration in which different control signals are input may also be used. A transistor is required to switch the potential of a node to which one of the electrodes serving as a source or a drain is connected by a control signal of a gate electrode. The transistor has a fast response to the control signal input to the gate electrode (the rise of the on-current is steep), so that the malfunction of the pulse output circuit can be reduced. Therefore, by using the thin film transistor 28 with four terminals shown in Fig. 16(C), the threshold voltage can be controlled, and a pulse output circuit with less malfunction can be obtained. In Fig. 16(D), the first control signal G1 and the second control signal G2 are the same control signal, but a configuration in which different control signals are input may also be used. A transistor is required to switch the potential of a node to which one of the electrodes serving as a source or a drain is connected by a control signal of a gate electrode. The transistor has a fast response to the control signal input to the gate electrode (the rise of the on-current is steep), so that the malfunction of the pulse output circuit can be reduced. Therefore, by using the thin film transistor 28 with four terminals shown in Fig. 16(C), the threshold voltage can be controlled, and a pulse output circuit with less malfunction can be obtained. In Fig. 16(D), the first control signal G1 and the second control signal G2 are the same control signal, but a configuration in which different control signals are input may also be used. A transistor is required to switch the potential of a node to which one of the electrodes serving as a source or a drain is connected by a control signal of a gate electrode. The transistor has a fast response to the control signal input to the gate electrode (the rise of the on-current is steep), so that the malfunction of the pulse output circuit can be reduced. Therefore, by using the thin film transistor 28 with four terminals shown in Fig. 16(C), the threshold voltage can be controlled, and a pulse output circuit with less malfunction can be obtained. In Fig. 16(D), the first control signal G1 and the second control signal G2 are the same control signal, but a configuration in which different control signals are input may also be used.

[0239] In Fig. 16(D), for the first transistor 31, the first terminal is electrically connected to the power supply line 51, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode (the lower gate electrode and the upper gate electrode) is electrically connected to the fourth input terminal 24. In Fig. 16(D), for the first transistor 31, the first terminal is electrically connected to the power supply line 51, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode (the lower gate electrode and the upper gate electrode) is electrically connected to the fourth input terminal 24. In Fig. 16(D), for the first transistor 31, the first terminal is electrically connected to the power supply line 51, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode (the lower gate electrode and the upper gate electrode) is electrically connected to the fourth input terminal 24. In Fig. 16(D), for the second transistor 32, the first terminal is electrically connected to the power supply line 53, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode is electrically connected to the gate electrode of the fourth transistor 34. In Fig. 16(D), for the second transistor 32, the first terminal is electrically connected to the power supply line 53, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode is electrically connected to the gate electrode of the fourth transistor 34. In Fig. 16(D), for the second transistor 32, the first terminal is electrically connected to the power supply line 53, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode is electrically connected to the gate electrode of the fourth transistor 34. In Fig. 16(D), for the third transistor 33, the first terminal is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the first output terminal 26. In Fig. 16(D), for the third transistor 33, the first terminal is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the first output terminal 26. In Fig. 16(D), for the fourth transistor 34, the first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first output terminal 26. In Fig. 16(D), for the fifth transistor 35, the first terminal is electrically connected to the power supply line 53, the second terminal is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate electrode is the fourth In Fig. 16(D), for the fifth transistor 35, the first terminal is electrically connected to the power supply line 53, the second terminal is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate electrode is the fourth is electrically connected to the input terminal 24. The sixth transistor 36 has its first terminal electrically connected to the power line 52, its second terminal electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and its gate electrode (the lower gate electrode and the upper gate electrode) electrically connected to the fifth input terminal 25. The seventh transistor 37 has its first terminal electrically connected to the power line 52, its second terminal electrically connected to the second terminal of the eighth transistor 38, and its gate electrode (the lower gate electrode and the upper gate electrode) electrically connected to the third input terminal 23. The eighth transistor 38 has its first terminal electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and its gate electrode (the lower gate electrode and the upper gate electrode) electrically connected to the second input terminal 22. The ninth transistor 39 has its first terminal electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32, its second terminal electrically connected to the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40, and its gate electrode (the lower gate electrode and the upper gate electrode) electrically connected to the power line 52 . The tenth transistor 40 has its first terminal electrically connected to the first input terminal 21, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the second terminal of the ninth transistor 39. The eleventh transistor 41 has its first terminal electrically connected to the power line 53, its second terminal electrically connected to the second output terminal 27, and its gate electrode connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. The twelfth transistor 42 has its first terminal electrically connected to the power line 53, its second terminal electrically connected to the second output terminal 27, and its gate electrode connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. The twelfth transistor 42 has its first terminal electrically connected to the power line 53, its second terminal electrically connected to the second output terminal 27, and its gate electrode connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. The twelfth transistor 42 has its first terminal electrically connected to the power line 53, its second terminal electrically connected to the second output terminal 27, and its gate electrode connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. The twelfth transistor 42 has its first terminal electrically connected to the power line 53, its second terminal electrically connected to the second output terminal 27, and its gate electrode connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor The first terminal is electrically connected to the power line 53, and the second terminal is electrically connected to the second output terminal 27 , and the gate electrode is electrically connected to the gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode). The thirteenth transistor 43 has the first terminal electrically connected to the power line 5 3, the second terminal is electrically connected to the first output terminal 26, and the gate electrode is electrically connected to the gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode).

[0240] In FIG. 16(D), the connection point of the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 40, and the second terminal of the ninth transistor 39 is defined as node A . Also, the connection point of the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the first terminal of the eighth transistor 38, and the gate electrode of the eleventh transistor 41 is defined as node B

[0241] In FIG. 17(A), when the pulse output circuit described in FIG. 16(D) is applied to the first pulse output circuit 10_ 1, the signals input or output to the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26 and the second output terminal 27 are shown

[0242] Specifically, the first clock signal CK1 is input to the first input terminal 21, the second input terminal 22 receives the second clock signal CK2, the third input terminal 23 receives the third clock signal CK3, the start pulse is input to the fourth input terminal 24, and the fifth input terminal ​​The subsequent stage signal OUT(3) is input to 25, and the first output signal OUT (1)(SR) is output from the first output terminal 26, and the second output signal OUT(1) is output from the second output terminal 27 .

[0243] Note that a thin film transistor is an element having at least three terminals including a gate, a drain, and a source. Further, it has a semiconductor body in which a channel region is formed in a region overlapping with the gate, and the current flowing between the drain and the source through the channel region can be controlled by controlling the potential of the gate. Here, since the source and the drain vary depending on the structure and operating conditions of the thin film transistor, etc., it is difficult to limit which one is the source or the drain. Therefore, the regions functioning as the source and the drain may not be called the source or the drain. In that case, as an example, they may be denoted as the first terminal and the second terminal, respectively.

[0244] Note that in FIGS. 16(D) and 17(A), a capacitive element may be separately provided for performing a bootstrap operation by making the node A in a floating state. Further, a capacitive element having one electrode electrically connected to the node B may be separately provided for holding the potential of the node B.

[0245] Here, the timing chart of a shift register including a plurality of pulse output circuits shown in FIG. 17(A) is shown in FIG. 17(B). When the shift register is a scanning line driving circuit, the period 61 in FIG. 17(B) is a vertical blanking period, and the period 62 corresponds to a gate selection period.

[0246] Note that, as shown in FIG. 17(A), a ninth transistor to which a second power supply potential VCC is applied to the gate​​​​​​​​​​ By providing the transistor 39, there are the following advantages before and after the bootstrap operation. There are advantages as follows.

[0247] When there is no ninth transistor 39 to which a second potential VCC is applied to the gate electrode, when the potential of node A rises due to the bootstrap operation, the potential of the source, which is the second terminal of the first transistor 31, rises and becomes larger than the first power supply potential VDD. Then, the source of the first transistor 31 switches to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, so a large stress is applied, which can be a factor in transistor degradation. Therefore, by providing the ninth transistor 39 to which the second power supply potential VCC is applied to the gate electrode, although the potential of node A rises due to the bootstrap operation, it is possible to prevent the potential of the second terminal of the first transistor 31 from rising. That is, by providing the ninth transistor 39, the value of the negative bias voltage applied between the gate and the source of the first transistor 31 can be reduced. Therefore, with the circuit configuration of this embodiment, the negative bias voltage applied between the gate and the source of the first transistor 31 can also be reduced, so that degradation of the first transistor 31 due to stress can be suppressed. When the potential of node A rises due to the bootstrap operation without the ninth transistor 39 having the second potential VCC applied to the gate electrode, the potential of the source, which is the second terminal of the first transistor 31, rises and becomes larger than the first power supply potential VDD. And the source of the first transistor 31 switches to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, so a large stress is applied, which can be a factor in transistor degradation. So, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, so a large stress is applied, which can be a factor in transistor degradation. Therefore, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, so a large stress is applied, which can be a factor in transistor degradation. Therefore, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, so a large stress is applied, which can be a factor in transistor degradation. Therefore, by providing the ninth transistor 39 to which the second power supply potential VCC is applied to the gate electrode, although the potential of node A rises due to the bootstrap operation, it is possible to prevent the potential of the second terminal of the first transistor 31 from rising. Therefore, by providing the ninth transistor 39 to which the second power supply potential VCC is applied to the gate electrode, although the potential of node A rises due to the bootstrap operation, it is possible to prevent the potential of the second terminal of the first transistor 31 from rising. Therefore, by providing the ninth transistor 39 to which the second power supply potential VCC is applied to the gate electrode, although the potential of node A rises due to the bootstrap operation, it is possible to prevent the potential of the second terminal of the first transistor 31 from rising. That is, by providing the ninth transistor 39, the value of the negative bias voltage applied between the gate and the source of the first transistor 31 can be reduced. That is, by providing the ninth transistor 39, the value of the negative bias voltage applied between the gate and the source of the first transistor 31 can be reduced. Therefore, with the circuit configuration of this embodiment, the negative bias voltage applied between the gate and the source of the first transistor 31 can also be reduced, so that degradation of the first transistor 31 due to stress can be suppressed. Therefore, with the circuit configuration of this embodiment, the negative bias voltage applied between the gate and the source of the first transistor 31 can also be reduced, so that degradation of the first transistor 31 due to stress can be suppressed. Therefore, with the circuit configuration of this embodiment, the negative bias voltage applied between the gate and the source of the first transistor 31 can also be reduced, so that degradation of the first transistor 31 due to stress can be suppressed.

[0248] Note that for the location where the ninth transistor 39 is provided, it is connected between the second terminal of the first transistor 31 and the gate of the third transistor 33 via the first terminal and the second terminal. Note that for the location where the ninth transistor 39 is provided, it is connected between the second terminal of the first transistor 31 and the gate of the third transistor 33 via the first terminal and the second terminal. Any configuration that provides it may be used. In the case of a shift register with a plurality of pulse output circuits in this embodiment, in the signal line driving circuit having more stages than the scanning line driving circuit, the ninth transistor 39 may be omitted, and the advantage is that the number of transistors can be reduced.

[0249] By using an oxide semiconductor as the semiconductor layer of the first transistor 31 to the thirteenth transistor 43, the off-current of the thin film transistor can be reduced, and the on-current and the field effect mobility can be increased, and the degree of deterioration can be reduced. Therefore, malfunctions in the circuit can be reduced. In addition, compared with a transistor using an oxide semiconductor and a transistor using amorphous silicon, the degree of deterioration of the transistor due to the application of a high potential to the gate electrode is small. Therefore, the same operation can be obtained by supplying the first power supply potential VDD to the power supply line that supplies the second power supply potential VCC, and since the number of power supply lines for routing between circuits can be reduced, the circuit can be miniaturized.

[0250] Note that the clock signal supplied to the gate electrode (lower gate electrode and upper gate electrode) of the seventh transistor 37 by the third input terminal 23, and the gate electrode (lower gate electrode and upper gate electrode) of the eighth transistor 38 supplied by the second input terminal 22 The clock signal is supplied to the gate electrode (lower gate electrode and upper gate electrode) of the seventh transistor 37 by the second input terminal 22, and the gate electrode (lower gate electrode and upper gate electrode) of the eighth transistor 38 supplied by the third input terminal 23 The same operation can be achieved by changing the connection relationship so that the clock signal supplied to the gate electrode (lower gate electrode and upper gate electrode) of the seventh transistor 37 by the second input terminal 22, and the gate electrode (lower gate electrode and upper gate electrode) of the eighth transistor 38 supplied by the third input terminal 23 becomes the clock signal supplied by the third input terminal 23. This occurs. At this time, in the shift register shown in FIG. 17(A), the seventh transistor 37 and the eighth transistor 38 both change from the on state to the state where the seventh transistor 37 is off and the eighth transistor 38 is on, then to the state where the seventh transistor 37 is off and the eighth transistor 38 is off. As a result, the potential drop of node B caused by the potential drops of the second input terminal 22 and the third input terminal 23 occurs twice due to the potential drop of the gate electrode of the seventh transistor 37 and the potential drop of the gate electrode of the eighth transistor 38. On the other hand, when the seventh transistor 37 and the eighth transistor 38 both change from the on state to the state where the seventh transistor 37 is on and the eighth transistor 38 is off, then to the state where the seventh transistor 37 is off and the eighth transistor 38 is off, the potential drop of node B caused by the potential drops of the second input terminal 22 and the third input terminal 23 can be reduced once by the potential drop of the gate electrode of the eighth transistor 38. Therefore, it is preferable that a clock signal is supplied from the third input terminal 23 to the gate electrode (the lower gate electrode and the upper gate electrode) of the seventh transistor 37, and a clock signal is supplied from the second input terminal 22 to the gate electrode (the lower gate electrode and the upper gate electrode) of the eighth transistor 38. This is because the number of fluctuations in the potential of node B is reduced and noise can also be reduced. That is, the potential drop of node B caused by the potential drops of the second input terminal 22 and the third input terminal 23 can be reduced once by the potential drop of the gate electrode of the eighth transistor 38. Therefore, it is preferable that a clock signal is supplied from the third input terminal 23 to the gate electrode (the lower gate electrode and the upper gate electrode) of the seventh transistor 37, and a clock signal is supplied from the second input terminal 22 to the gate electrode (the lower gate electrode and the upper gate electrode) of the eighth transistor 38. This is because the number of fluctuations in the potential of node B is reduced and noise can also be reduced. That is, the potential drop of node B caused by the potential drops of the second input terminal 22 and the third input terminal 23 can be reduced once by the potential drop of the gate electrode of the eighth transistor 38. Therefore, it is preferable that a clock signal is supplied from the third input terminal 23 to the gate electrode (the lower gate electrode and the upper gate electrode) of the seventh transistor 37, and a clock signal is supplied from the second input terminal 22 to the gate electrode (the lower gate electrode and the upper gate electrode) of the eighth transistor 38. This is because

[0251] In this way, by configuring such that a signal of H level is periodically supplied to node B during the period when the potentials of the first output terminal 26 and the second output terminal 27 are held at the L level, the pulse is It is possible to suppress malfunction of the output circuit.

[0252] (Embodiment 9) A thin film transistor is manufactured, and the thin film transistor is used in a pixel portion and further in a driver circuit. It is possible to manufacture a semiconductor device (also called a display device) having a display function. The transistors and part or the entire driver circuit are integrated on the same substrate as the pixel section, An on-panel can be formed.

[0253] The display device includes a display element. The display element may be a liquid crystal element (also called a liquid crystal display element), a light-emitting A light-emitting element (also called a light-emitting display element) can be used. A light-emitting element is a light-emitting element that emits light by applying a current or a voltage. This category includes elements whose brightness is controlled by a specific factor, such as inorganic EL (Electroluminescent) devices. These include organic EL elements, electronic inks, etc. A display medium whose contrast changes due to an electrical effect, such as a liquid crystal display, can also be used.

[0254] The display device includes a panel in which a display element is sealed, and a controller for the panel. and a module in which an IC or the like including the above is mounted. In the process, the element substrate corresponds to one form before the display element is completed, and the element substrate is The element substrate is provided with a means for supplying a current to the display element in each of the plurality of pixels. The display element may be in a state where only the pixel electrodes of the display element are formed, or a conductive film that becomes the pixel electrodes may be formed. may be in a state after the formation of a film and before etching to form a pixel electrode, All forms apply.

[0255] In this specification, the term "display device" refers to an image display device, a display device, or an optical Refers to the source (including the lighting device). Also, connectors such as FPC (Flexible Printed Circuit) or TAB (Tape Automated Bonding) tape or TCP (Tape Carrier Package) attached modules, modules with a printed wiring board provided at the end of the TAB tape or TCP, or modules with an IC (integrated circuit) directly mounted on the display element by the COG (Chip On Glass) method are all considered to be included in the display device. inted circuit) or TAB (Tape Automated Bon ding) tape or TCP (Tape Carrier Package) are attached, modules with a printed wiring board provided at the end of the TAB tape or TCP, or modules with an IC (integrated circuit) directly mounted on the display element by the COG (Chip On Glass) method are all considered to be included in the display device. ding) tape or TCP (Tape Carrier Package) are attached, modules with a printed wiring board provided at the end of the TAB tape or TCP, or modules with an IC (integrated circuit) directly mounted on the display element by the COG (Chip On Glass) method are all considered to be included in the display device. dule, or modules with an IC (integrated circuit) directly mounted on the display element by the COG (Chip On Glass) method are all considered to be included in the display device. circuit) directly mounted on the display element by the COG (Chip On Glass) method are all considered to be included in the display device.

[0256] Regarding the appearance and cross-section of a liquid crystal display panel corresponding to one form of the semiconductor device, it will be described with reference to FIG. 10. FIGS. 10(A1)(A2) are plan views of the panel in which thin film transistors 4010, 4011, and liquid crystal elements 4013 are sealed between the first substrate 4001 and the second substrate 4006 by a sealing material 4005, and FIG. 10(B) corresponds to a cross-sectional view taken along M -N of FIGS. 10(A1)(A2). elements 4013 are sealed between the first substrate 4001 and the second substrate 4006 by a sealing material 4005, and FIG. 10(B) corresponds to a cross-sectional view taken along M -N of FIGS. 10(A1)(A2).

[0257] A sealing material 4005 is provided so as to surround the pixel portion 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006. Also, in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001, a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate. 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006. Also, in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001, a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate. semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate. semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate.

[0258] Note that the method of connecting the separately formed drive circuit is not particularly limited, and a COG method, a wire bonding method, or a TAB method, etc. can be used. FIG. 10(A1) is an example of mounting the signal line drive circuit 4003 by the COG method, and FIG. 10(A2) is an example of mounting the signal line drive circuit 4003 by the TAB method.

[0259] Also, the pixel portion 4002 provided on the first substrate 4001 and the scanning line drive circuit 4004 each have a plurality of thin film transistors. In FIG. 10(B), the thin films transistor 4010 included in the pixel portion 4002 and the thin film transistor 4011 included in the scanning line drive circuit 4004 are illustrated. On the thin film transistors 4010 and 4011, insulating layers 4041a, 40 41b, 4042a, 4042b, 4020, and 4021 are provided.

[0260] The thin film transistors 4010 and 4011 can be applied with highly reliable thin film transistors including the oxide semiconductor layer shown in Embodiments 1, 2, 5, and 6. As the thin film transistor 4011 for the drive circuit, the thin film transistors 26 0 and 270 shown in Embodiments 1, 2, 5, and 6 can be used, and as the thin film transistor 4010 for the pixel, the thin film transistors 420, 4 48, 220, 280, and 290 can be used. In the present embodiment, the thin film transistors 4010 and 4011 are n-channel type thin film transistors. 0, 270, for the pixel, the thin film transistors 420, 4 48, 220, 280, 290 can be used. In this embodiment, the thin film transistors 4010 and 4011 are n-channel type thin film transistors. On the insulating layer 4021, a conductive layer 4040 is provided at a position overlapping the channel formation region of the oxide semiconductor layer of the thin film transistor 4011 for the drive circuit. The conductive layer 4040 is made of an acid

[0261] oxide semiconductor layer of the thin film transistor 4011 for the drive circuit. The conductive layer 4040 is made of an acid oxide semiconductor layer of the thin film transistor 4011 for the drive circuit. The conductive layer 4040 is made of an acid By providing it at a position overlapping with the channel formation region of the compound semiconductor layer, the amount of change in the threshold voltage of the thin film transistor 4011 before and after the BT test can be reduced. Also, the potential of the conductive layer 4040 may be the same as that of the gate electrode layer of the thin film transistor 4011, or it may be different, and it can also function as a second gate electrode layer. Also, the potential of the conductive layer 4040 may be GND, 0V, or in a floating state.

[0262] Also, the pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. And the counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 40 06. The portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013. Note that insulating layers 4032 and 4033 that function as alignment films are provided for the pixel electrode layer 4030 and the counter electrode layer 4031, respectively, and the liquid crystal layer 4008 is sandwiched via the insulating layers 4032 and 4033.

[0263] Note that as the first substrate 4001 and the second substrate 4006, a light-transmissive substrate can be used, and glass, ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PV F (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used.

[0264] Also, 4035 is a columnar spacer obtained by selectively etching an insulating film, and is used to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. ​​​It is provided therein. Note that a spherical spacer may be used. Also, the counter electrode layer 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010 through. Using a common connection portion, the counter electrode layer 40 31 and the common potential line can be electrically connected via conductive particles disposed between a pair of substrates. Note that the conductive particles are contained in the sealing material 40 05.

[0265] Also, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the cholesteric liquid crystal transitions from the cholesteric phase to the isotropic phase when the temperature is raised. Since the blue phase appears only in a narrow temperature range, in order to improve the temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer 4008 . A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a response speed as short as 1 msec or less, is optically isotropic, does not require alignment treatment, and has a small viewing angle dependence. Note that in addition to the transmissive liquid crystal display device, the present invention can also be applied to a transflective liquid crystal display device. Note that in addition to the transmissive liquid crystal display device, the present invention can also be applied to a transflective liquid crystal display device.

[0266] In addition to the transmissive liquid crystal display device, the present invention can also be applied to a transflective liquid crystal display device.

[0267] Also, in a liquid crystal display device, an example is shown in which a polarizing plate is provided on the outside (viewing side) of the substrate, and a coloring layer (color filter) and an electrode layer used for the display element are provided in this order. However, the polarizing plate may be provided inside the substrate . Also, the laminated structure of the polarizing plate and the coloring layer is not limited to the present embodiment, and may be appropriately set according to the materials and manufacturing process conditions of the polarizing plate and the coloring layer. Also, a light shielding film that functions as a black matrix may be provided outside the display portion.

[0268] The thin film transistor 4011 includes an insulating layer 4041a that functions as a channel protection layer and an oxide An insulating layer 4041b is formed to cover the peripheral portion (including the side surface) of the stack of the oxide semiconductor layers. Similarly, the thin film transistor 4010 includes an insulating layer 4042a that functions as a channel protection layer and an insulating layer 4042b that is formed to cover the peripheral portion (including the side surface) of the stack of the oxide semiconductor layers. are formed.

[0269] The insulating layers 4041b and 4042b, which are oxide insulating layers covering the peripheral portion (including the side surface) of the stack of the oxide semiconductor layers, can increase the distance between the gate electrode layer and the wiring layer (such as the source wiring layer or the capacitor wiring layer) formed above or around it, thereby reducing the parasitic capacitance. The insulating layers 4041a, 4041b, 4042a, and 4042b may be formed of the same materials and by the same method as the oxide insulating layers 426a and 426b shown in Embodiment 1. Further, the structure is such that it is covered with an insulating layer 4021 that functions as a planarization insulating film to reduce the surface unevenness of the thin film transistor. Here, as the insulating layers 4041a, 4041b, 4042a, and 4042b, a silicon oxide film is formed by sputtering using Embodiment 1. b, 4042b can increase the distance between the gate electrode layer and the wiring layer (such as the source wiring layer or the capacitor wiring layer) formed above or around it, thereby reducing the parasitic capacitance. The insulating layers 4041a, 4041b, 4042a, and 4042b may be formed of the same materials and by the same method as the oxide insulating layers 426a and 426b shown in Embodiment 1. Further, the structure is such that it is covered with an insulating layer 4021 that functions as a planarization insulating film to reduce the surface unevenness of the thin film transistor. Here, as the insulating layers 4041a, 4041b, 4042a, and 4042b, a silicon oxide film is formed by sputtering using Embodiment 1. b, 4042b can increase the distance between the gate electrode layer and the wiring layer (such as the source wiring layer or the capacitor wiring layer) formed above or around it, thereby reducing the parasitic capacitance. The insulating layers 4041a, 4041b, 4042a, and 4042b may be formed of the same materials and by the same method as the oxide insulating layers 426a and 426b shown in Embodiment 1. Further, the structure is such that it is covered with an insulating layer 4021 that functions as a planarization insulating film to reduce the surface unevenness of the thin film transistor. Here, as the insulating layers 4041a, 4041b, 4042a, and 4042b, a silicon oxide film is formed by sputtering using Embodiment 1. layers 4041a, 4041b, 4042a, and 4042b may be formed of the same materials and by the same method as the oxide insulating layers 426a and 426b shown in Embodiment 1. Further, the structure is such that it is covered with an insulating layer 4021 that functions as a planarization insulating film to reduce the surface unevenness of the thin film transistor. Here, as the insulating layers 4041a, 4041b, 4042a, and 4042b, a silicon oxide film is formed by sputtering using Embodiment 1. layers 4041a, 4041b, 4042a, and 4042b may be formed of the same materials and by the same method as the oxide insulating layers 426a and 426b shown in Embodiment 1. Further, the structure is such that it is covered with an insulating layer 4021 that functions as a planarization insulating film to reduce the surface unevenness of the thin film transistor. Here, as the insulating layers 4041a, 4041b, 4042a, and 4042b, a silicon oxide film is formed by sputtering using Embodiment 1. is covered with an insulating layer 4021 that functions as a planarization insulating film to reduce the surface unevenness of the thin film transistor. Here, as the insulating layers 4041a, 4041b, 4042a, and 4042b, a silicon oxide film is formed by sputtering using Embodiment 1. Here, as the insulating layers 4041a, 4041b, 4042a, and 4042b, a silicon oxide film is formed by sputtering using Embodiment 1. Here, as the insulating layers 4041a, 4041b, 4042a, and 4042b, a silicon oxide film is formed by sputtering using Embodiment 1.

[0270] Also, an insulating layer 4020 is formed on the insulating layers 4041a, 4041b, 4042a, and 4042b. The insulating layer 4020 may be formed of the same materials and by the same method as the protective insulating layer 403 shown in Embodiment 1. Here, as the insulating layer 4020, a silicon nitride film is formed by RF sputtering. Here, as the insulating layer 4020, a silicon nitride film is formed by RF sputtering. Here, as the insulating layer 4020, a silicon nitride film is formed by RF sputtering.

[0271] Also, an insulating layer 4021 is formed as a planarization insulating film. The insulating layer 4021 may be formed of the same materials and by the same method as the planarization insulating layer 404 shown in Embodiment 1, and polyimide is used. , organic materials with heat resistance such as acrylic, benzocyclobutene, polyamide, and epoxy can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. Note that the insulating layer 40 21 may be formed by laminating a plurality of insulating films formed of these materials.

[0272] In this embodiment, a configuration in which a plurality of thin film transistors in the pixel portion are collectively surrounded by a nitride insulating film may be adopted. Using a nitride insulating film for the insulating layer 4020 and the gate insulating layer, as shown in FIG. 10 a region where the insulating layer 4020 and the gate insulating layer are in contact with each other may be provided so as to surround at least the periphery of the pixel portion of the active matrix substrate. With such a configuration, invasion of moisture from the outside can be prevented. Also, even after the semiconductor device, for example, the device is completed as a display device, invasion of moisture from the outside can be prevented in the long term, and the long-term reliability of the device can be improved.

[0273] Note that the siloxane resin corresponds to a resin containing a Si-O-Si bond formed using a siloxane-based material as a starting material. The siloxane resin may use an organic group (for example, an alkyl group or an aryl group) or a fluoro group as a substituent. Also, the organic group may have a fluoro group.

[0274] The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, sputtering, SOG method , spin coating, dipping, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife A photoresist or the like can be used. By combining the firing process of the insulating layer 4021 and the annealing of the semiconductor layer, it becomes possible to efficiently fabricate a semiconductor device. It becomes possible to efficiently fabricate a semiconductor device by combining the firing process of the insulating layer 4021 and the annealing of the semiconductor layer.

[0275] The pixel electrode layer 4030 and the counter electrode layer 4031 can be made of a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, or the like. Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, or the like. Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, or the like. Indium zinc oxide, indium tin oxide added with silicon oxide, or the like. A light-transmitting conductive material can be used.

[0276] Further, the pixel electrode layer 4030 and the counter electrode layer 4031 can be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition preferably has a sheet resistance of 10,000 Ω / sq or less and a light transmittance of 70% or more at a wavelength of 550 nm. Further, the resistivity of the conductive polymer contained in the conductive composition is preferably 0.1 Ω·cm or less. A conductive composition containing a conductive polymer (also referred to as a conductive polymer) can be used. The pixel electrode formed using the conductive composition preferably has a sheet resistance of 10,000 Ω / sq or less and a light transmittance of 70% or more at a wavelength of 550 nm. Further, the resistivity of the conductive polymer contained in the conductive composition is preferably 0.1 Ω·cm or less. Preferably, the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω·cm or less.

[0277] As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers of two or more of these can be mentioned. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers of two or more of these can be mentioned. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers of two or more of these can be mentioned.

[0278] In addition, various signals and potentials supplied to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004, or the pixel portion 4002 are supplied from the FPC 4018. Various signals and potentials supplied to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004, or the pixel portion 4002 are supplied from the FPC 4018.

[0279] Is the connection terminal electrode 4015 made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013? and is formed, and the terminal electrode 4016 is formed of the same conductive film as the source electrode layer and the drain electrode layer of the thin film transistors 4010 and 4011.

[0280] The connection terminal electrode 4015 is electrically connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019.

[0281] Also, in FIG. 10, an example is shown in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001, but the present invention is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or only a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted.

[0282] FIG. 19 shows an example of configuring a liquid crystal display module as a semiconductor device using the TFT substrate 2600 manufactured by the manufacturing method disclosed in this specification.

[0283] FIG. 19 is an example of a liquid crystal display module, in which the TFT substrate 2600 and the counter substrate 2601 are fixed by a sealing material 2602, and a pixel portion 2603 including TFTs and the like, a display element 2604 including a liquid crystal layer, and a coloring layer 2605 are provided therebetween to form a display area. The coloring layer 2605 is necessary for performing color display. In the case of the RGB system, coloring layers corresponding to the respective colors of red, green, and blue are provided corresponding to each pixel. Polarizing plates 2606 and 2607 and a diffusion plate 2613 are disposed outside the TFT substrate 2600 and the counter substrate 2601. The light source is composed of a cold cathode tube 2610 and a reflector 2611, and the circuit board 2612 is a flexible circuit. is necessary for performing color display. In the case of the RGB system, coloring layers corresponding to the respective colors of red, green, and blue are provided corresponding to each pixel. Outside the TFT substrate 2600 and the counter substrate 2601, polarizing plates 2606, 2607, and a diffusion plate 2613 are disposed. The light source is composed of a cold cathode tube 2610 and a reflector 2611, and the circuit board 2612 is a flexible circuit. ​​​​​​​​​​​The wiring circuit portion 2608 of the TFT substrate 2600 is connected by the wiring substrate 2609, and external circuits such as a control circuit and a power supply circuit are incorporated. Also, it may be laminated in a state having a retardation plate between the polarizing plate and the liquid crystal layer. The liquid crystal display module may use a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Bend) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, etc. By the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device.

[0284] The liquid crystal display module may use a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Bend) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, etc. n-Plane-Switching) mode, an FFS (Fringe Field S witching) mode, an MVA (Multi-domain Vertical A lignment) mode, a PVA (Patterned Vertical Alig nment) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated B irefringence) mode, an FLC (Ferroelectric Liqui d Crystal) mode, an AFLC (AntiFerroelectric Liq uid Crystal) mode, etc.

[0285] By the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. Yes.

[0286] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. Yes.

[0287] (Embodiment 10) An example of electronic paper is shown as one form of the semiconductor device.

[0288] An electronic paper that drives electronic ink using an element electrically connected to a switching element Electronic paper is also called an electrophoretic display. It has the same readability as paper, consumes less power than other display devices, and is thin and light. This has the advantage that it is possible to

[0289] Electrophoretic displays can take a variety of forms, but the first particle has a positive charge. A microcapsule containing a negatively charged second particle and a negatively charged second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particles and the second particles are different in color (colorless). (including

[0290] Thus, electrophoretic displays operate in such a way that materials with high dielectric constants migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect.

[0291] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. A color display is also possible by using a color filter or particles having a pigment.

[0292] In addition, the above microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. Display can be achieved by applying an electric field to the cell. An active matrix substrate obtained by a thin film transistor can be used.

[0293] Note that the first particles and the second particles in the microcapsules are made of a conductor material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electro chromic material, a magnetophoretic material, a material selected from these, or a composite material thereof may be used.

[0294] FIG. 18 shows an active matrix type electronic paper as an example of a semiconductor device. As the thin film transistor 581 used in the semiconductor device, it can be manufactured in the same manner as the thin film transistor shown in Embodiment 1, and is a highly reliable thin film transistor including an oxide semiconductor layer. Also the thin film transistors shown in Embodiments 2, 5, and 6 can also be applied as the thin film transistor 581 of the present embodiment.

[0295] The electronic paper of FIG. 18 is an example of a display device using a twist ball display method. The twist ball display method is a method of performing display by disposing spherical particles painted white and black between a first electrode layer and a second electrode layer that are electrode layers used in a display element, and generating a potential difference between the first electrode layer and the second electrode layer to control the orientation of the spherical particles.

[0296] The thin film transistor 581 formed on the substrate 580 is a thin film transistor having a bottom gate structure and is covered with an insulating film 583 in contact with the semiconductor layer. The source electrode layer or the drain electrode layer of the thin film transistor 581 is in contact with and electrically connected to the first electrode layer 587 through an opening formed in the insulating layer 585. The first electrode layer 587 is formed on the substrate 596 Between it and the second electrode layer 588, there are provided spherical particles 589 having a black region 590a and a white region 590b, and a cavity 594 filled with liquid around them. The periphery of the spherical particles 589 is filled with a filler 595 such as resin. The first electrode layer 587 corresponds to the pixel electrode, and the second electrode layer 588 corresponds to the common electrode. The second electrode layer 588 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 581. Using a common connection portion, the second electrode layer 588 and the common potential line can be electrically connected through conductive particles disposed between a pair of substrates.

[0297] Also, instead of the twist ball, it is also possible to use an electrophoretic element. A transparent liquid and microcapsules having a diameter of about 10 μm to 200 μm encapsulating positively charged white fine particles and negatively charged black fine particles are used. When an electric field is applied to the microcapsules provided between the first electrode layer and the second electrode layer by the first electrode layer and the second electrode layer, the white fine particles and the black fine particles move in opposite directions, and white or black can be displayed. A display element applying this principle is an electrophoretic display element, which is generally called electronic paper. Since the electrophoretic display element has a higher reflectance than a liquid crystal display element, an auxiliary light is not required, the power consumption is small, and the display portion can be recognized even in a dim place. Also, even when no power is supplied to the display portion, the image once displayed can be held. Therefore, even when the semiconductor device with a display function (also simply called a display device or a semiconductor device having a display device) is separated from the radio wave transmission source, the displayed image can be saved.

[0298] ​​​​​​​​​​​​​​​ Through the above steps, electronic paper having high reliability as a semiconductor device can be manufactured. .

[0299] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0300] (Embodiment 11) An example of a light-emitting display device is shown as a semiconductor device. is shown using a light-emitting element that uses electroluminescence. The light-emitting element that uses the light-emitting material is classified into two types according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter an inorganic EL element.

[0301] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into layers containing light-emitting organic compounds, causing a current to flow. The rears (electrons and holes) recombine to form an excited state in the light-emitting organic compound. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0302] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. It is the localized light emission to be used. Here, the organic EL element is used as the light emitting element for explanation. to be continued.

[0303] FIG. 12 shows an example of a pixel configuration to which digital time gradation driving can be applied as an example of a semiconductor device. It is a figure showing.

[0304] The configuration and operation of a pixel to which digital time gradation driving can be applied will be described. Here is an example in which one pixel uses two n-channel transistors using an oxide semiconductor layer in a channel formation region. to be shown.

[0305] Pixel 6400 has a switching transistor 6401, a light emitting element driving transistor 6 402, a light emitting element 6404, and a capacitor element 6403. The switching transistor 6401 has its gate connected to the scanning line 6406, its first electrode (one of the source electrode and the drain electrode) connected to the signal line 6405, and its second electrode (the other of the source electrode and the drain electrode) connected to the gate of the light emitting element driving transistor 6402. The light emitting element driving transistor 6402 has its gate connected to the power supply line 6407 via the capacitor element 6403, its first electrode connected to the power supply line 6407, and its second electrode connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate. The first electrode of the light emitting element driving transistor 6402 is connected to the power supply line 6407, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate.

[0306] Note that a low power supply potential is set for the second electrode (common electrode 6408) of the light emitting element 6404. Note that the low power supply potential is a potential that satisfies the low power supply potential < high power supply potential with respect to the high power supply potential set for the power supply line 6407. Examples of the low power supply potential include GND, 0V, etc. It may be determined. Apply the potential difference between this high power supply potential and the low power supply potential to the light emitting element 6404 to cause a current to flow through the light emitting element 6404 and make the light emitting element 6404 emit light. Therefore, the high power supply potential and the low power supply potential are set so that the potential difference therebetween is equal to or greater than the forward threshold voltage of the light emitting element 6404 respectively.

[0307] Note that the capacitor element 6403 can also be omitted by substituting for the gate capacitance of the transistor 6402 for driving the light emitting element. Regarding the gate capacitance of the transistor 6402 for driving the light emitting element a capacitance may be formed between the channel region and the gate electrode.

[0308] Here, in the case of the voltage input voltage drive method, a video signal that causes the transistor 6402 for driving the light emitting element to be either fully on or off is input to the gate of the transistor 6402 for driving the light emitting element. That is, the transistor 6402 for driving the light emitting element operates in the linear region. Since the transistor 6402 for driving the light emitting element operates in the linear region a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the transistor 6402 for driving the light emitting element . Note that a voltage equal to or higher than (the power supply line voltage + the Vth of the transistor 6402 for driving the light emitting element) is applied to the signal line 6405.

[0309] Also, when performing analog gradation driving instead of digital time gradation driving, the same pixel configuration as in FIG. 12 can be used by changing the signal input differently.

[0310] When performing analog gradation driving, a voltage equal to or higher than the forward voltage of the light emitting element 6404 + the Vth of the transistor 6402 for driving the light emitting element is applied to the gate of the transistor 6402 for driving the light emitting element The forward voltage of the light-emitting element 6404 refers to the voltage when a desired luminance is set, and includes at least the forward threshold voltage. Note that by inputting a video signal such that the transistor 6402 for driving the light-emitting element operates in the saturation region, a current can be caused to flow through the light-emitting element 6404. In order to operate the transistor 6402 for driving the light-emitting element in the saturation region, the potential of the power supply line 6407 is made higher than the gate potential of the transistor 6402 for driving the light-emitting element. By using an analog video signal, a current corresponding to the video signal can be caused to flow through the light-emitting element 6404, and analog gradation driving can be performed. Note that the pixel configuration shown in FIG. 12 is not limited to this. For example, a new switch, resistor element, capacitor element, transistor, or logic circuit may be added to the pixel shown in FIG. 12. Next, the configuration of the light-emitting element will be described with reference to FIG. 13. Here, the case where the TFT for driving the light-emitting element is of the n-type will be taken as an example, and the cross-sectional structure of the pixel will be described. The TFTs 7001, 7011, and 7021, which are the TFTs for driving the light-emitting element used in the semiconductor devices of FIGS. 13(A), (B), and (C), can be manufactured in the same manner as the thin-film transistors disposed in the pixels shown in Embodiment 1, and are highly reliable thin-film transistors including an oxide semiconductor layer. Further, the thin-film transistors disposed in the pixels shown in Embodiments 2, 5, and 6 can also be applied by using the TFTs 7001, 7011, and 7021. At least one of the anode and the cathode of the light-emitting element may be transparent in order to extract light. Thus, a thin-film transistor and a light-emitting element are formed on the substrate, and light is extracted from the surface opposite to the substrate. The forward voltage of the light-emitting element 6404 refers to the voltage when a desired luminance is set, and includes at least the forward threshold voltage. Note that by inputting a video signal such that the transistor 6402 for driving the light-emitting element operates in the saturation region, a current can be caused to flow through the light-emitting element 6404. In order to operate the transistor 6402 for driving the light-emitting element in the saturation region, the potential of the power supply line 6407 is made higher than the gate potential of the transistor 6402 for driving the light-emitting element. By using an analog video signal, a current corresponding to the video signal can be caused to flow through the light-emitting element 6404, and analog gradation driving can be performed. Note that the pixel configuration shown in FIG. 12 is not limited to this. For example, a new switch, resistor element, capacitor element, transistor, or logic circuit may be added to the pixel shown in FIG. 12. Next, the configuration of the light-emitting element will be described with reference to FIG. 13. Here, the case where the TFT for driving the light-emitting element is of the n-type will be taken as an example, and the cross-sectional structure of the pixel will be described. The TFTs 7001, 7011, and 7021, which are the TFTs for driving the light-emitting element used in the semiconductor devices of FIGS. 13(A), (B), and (C), can be manufactured in the same manner as the thin-film transistors disposed in the pixels shown in Embodiment 1, and are highly reliable thin-film transistors including an oxide semiconductor layer. Further, the thin-film transistors disposed in the pixels shown in Embodiments 2, 5, and 6 can also be applied by using the TFTs 7001, 7011, and 7021.

[0311] Note that the pixel configuration shown in FIG. 12 is not limited to this. For example, a new switch, resistor element, capacitor element, transistor, or logic circuit may be added to the pixel shown in FIG. 12. Next, the configuration of the light-emitting element will be described with reference to FIG. 13. Here, the case where the TFT for driving the light-emitting element is of the n-type will be taken as an example, and the cross-sectional structure of the pixel will be described. The TFTs 7001, 7011, and 7021, which are the TFTs for driving the light-emitting element used in the semiconductor devices of FIGS. 13(A), (B), and (C), can be manufactured in the same manner as the thin-film transistors disposed in the pixels shown in Embodiment 1, and are highly reliable thin-film transistors including an oxide semiconductor layer. Further, the thin-film transistors disposed in the pixels shown in Embodiments 2, 5, and 6 can also be applied by using the TFTs 7001, 7011, and 7021.

[0312] Next, the configuration of the light-emitting element will be described with reference to FIG. 13. Here, the case where the TFT for driving the light-emitting element is of the n-type will be taken as an example, and the cross-sectional structure of the pixel will be described. The TFTs 7001, 7011, and 7021, which are the TFTs for driving the light-emitting element used in the semiconductor devices of FIGS. 13(A), (B), and (C), can be manufactured in the same manner as the thin-film transistors disposed in the pixels shown in Embodiment 1, and are highly reliable thin-film transistors including an oxide semiconductor layer. Further, the thin-film transistors disposed in the pixels shown in Embodiments 2, 5, and 6 can also be applied by using the TFTs 7001, 7011, and 7021. Next, the configuration of the light-emitting element will be described with reference to FIG. 13. Here, the case where the TFT for driving the light-emitting element is of the n-type will be taken as an example, and the cross-sectional structure of the pixel will be described. The TFTs 7001, 7011, and 7021, which are the TFTs for driving the light-emitting element used in the semiconductor devices of FIGS. 13(A), (B), and (C), can be manufactured in the same manner as the thin-film transistors disposed in the pixels shown in Embodiment 1, and are highly reliable thin-film transistors including an oxide semiconductor layer. Further, the thin-film transistors disposed in the pixels shown in Embodiments 2, 5, and 6 can also be applied by using the TFTs 7001, 7011, and 7021. The TFTs 7001, 7011, and 7021, which are the TFTs for driving the light-emitting element used in the semiconductor devices of FIGS. 13(A), (B), and (C), can be manufactured in the same manner as the thin-film transistors disposed in the pixels shown in Embodiment 1, and are highly reliable thin-film transistors including an oxide semiconductor layer. Further, the thin-film transistors disposed in the pixels shown in Embodiments 2, 5, and 6 can also be applied by using the TFTs 7001, 7011, and 7021. Next, the configuration of the light-emitting element will be described with reference to FIG. 13. Here, the case where the TFT for driving the light-emitting element is of the n-type will be taken as an example, and the cross-sectional structure of the pixel will be described. The TFTs 7001, 7011, and 7021, which are the TFTs for driving the light-emitting element used in the semiconductor devices of FIGS. 13(A), (B), and (C), can be manufactured in the same manner as the thin-film transistors disposed in the pixels shown in Embodiment 1, and are highly reliable thin-film transistors including an oxide semiconductor layer. Further, the thin-film transistors disposed in the pixels shown in Embodiments 2, 5, and 6 can also be applied by using the TFTs 7001, 7011, and 7021. Next, the configuration of the light-emitting element will be described with reference to FIG. 13. Here, the case where the TFT for driving the light-emitting element is of the n-type will be taken as an example, and the cross-sectional structure of the pixel will be described. The TFTs 7001, 7011, and 7021, which are the TFTs for driving the light-emitting element used in the semiconductor devices of FIGS. 13(A), (B), and (C), can be manufactured in the same manner as the thin-film transistors disposed in the pixels shown in Embodiment 1, and are highly reliable thin-film transistors including an oxide semiconductor layer. Further, the thin-film transistors disposed in the pixels shown in Embodiments 2, 5, and 6 can also be applied by using the TFTs 7001, 7011, and 7021. Next, the configuration of the light-emitting element will be described with reference to FIG. 13. Here, the case where the TFT for driving the light-emitting element is of the n-type will be taken as an example, and the cross-sectional structure of the pixel will be described. The TFTs 7001, 7011, and 7021, which are the TFTs for driving the light-emitting element used in the semiconductor devices of FIGS. 13(A), (B), and (C), can be manufactured in the same manner as the thin-film transistors disposed in the pixels shown in Embodiment 1, and are highly reliable thin-film transistors including an oxide semiconductor layer. Further, the thin-film transistors disposed in the pixels shown in Embodiments 2, 5, and 6 can also be applied by using the TFTs 7001, 7011, and 7021. Next, the configuration of the light-emitting element will be described with reference to FIG. 13. Here, the case where the TFT for driving the light-emitting element is of the n-type will be taken as an example, and the cross-sectional structure of the pixel will be described. The TFTs 7001, 7011, and 7021, which are the TFTs for driving the light-emitting element used in the semiconductor devices of FIGS. 13(A), (B), and (C), can be manufactured in the same manner as the thin-film transistors disposed in the pixels shown in Embodiment 1, and are highly reliable thin-film transistors including an oxide semiconductor layer. Further, the thin-film transistors disposed in the pixels shown in Embodiments 2, 5, and 6 can also be applied by using the TFTs 7001, 7011, and 7021.

[0313] At least one of the anode and the cathode of the light-emitting element may be transparent in order to extract light. Thus, a thin-film transistor and a light-emitting element are formed on the substrate, and light is extracted from the surface opposite to the substrate. At least one of the anode and the cathode of the light-emitting element may be transparent in order to extract light. Thus, a thin-film transistor and a light-emitting element are formed on the substrate, and light is extracted from the surface opposite to the substrate. There are top emission structures that extract light from the top surface, bottom emission structures that extract light from the surface on the substrate side, and double-sided emission structures that extract light from the surface on the substrate side and the side opposite to the substrate. The pixel configuration can be applied to light-emitting elements of any emission structure. The light-emitting element of the top emission structure will be described with reference to Fig. 13(A). Fig. 13(A) shows a cross-sectional view of a pixel when the TFT 7001, which is a TFT for driving a light-emitting element, is of the n-type and the light emitted from the light-emitting element 7002 escapes to the anode 7005 side. In Fig. 13(A), the cathode 7003 of the light-emitting element 7002 and the TFT 7001, which is a TFT for driving the light-emitting element, are electrically connected, and the light-emitting layer 7004 and the anode 7005 are sequentially laminated on the cathode 7003. The cathode 7003 can be made of various materials as long as it has a low work function and reflects light. For example, Ca, Al, MgAg, AlLi, etc. are desirable. The light-emitting layer 7004 can be composed of a single layer or a plurality of layers laminated. When composed of a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are laminated in this order on the cathode 7003. It is not necessary to provide all of these layers. The anode 7005 is formed using a conductive material having light-transmitting properties, and for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide (hereinafter referred to as ITO), indium zinc oxide, or a light-transmitting conductive film such as indium tin oxide added with silicon oxide may be used.

[0314] The light-emitting element of the top emission structure will be described with reference to Fig. 13(A).

[0315] Fig. 13(A) shows a cross-sectional view of a pixel when the TFT 7001, which is a TFT for driving a light-emitting element, is of the n-type and the light emitted from the light-emitting element 7002 escapes to the anode 7005 side. In Fig. 13(A), the cathode 7003 of the light-emitting element 7002 and the TFT 7001, which is a TFT for driving the light-emitting element, are electrically connected, and the light-emitting layer 7004 and the anode 7005 are sequentially laminated on the cathode 7003. The cathode 7003 can be made of various materials as long as it has a low work function and reflects light. For example, Ca, Al, MgAg, AlLi, etc. are desirable. The light-emitting layer 7004 can be composed of a single layer or a plurality of layers laminated. When composed of a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are laminated in this order on the cathode 7003. It is not necessary to provide all of these layers. The anode 7005 is formed using a conductive material having light-transmitting properties, and for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide (hereinafter referred to as ITO), indium zinc oxide, or a light-transmitting conductive film such as indium tin oxide added with silicon oxide may be used. Fig. 13(A) shows a cross-sectional view of a pixel when the TFT 7001, which is a TFT for driving a light-emitting element, is of the n-type and the light emitted from the light-emitting element 7002 escapes to the anode 7005 side. In Fig. 13(A), the cathode 7003 of the light-emitting element 7002 and the TFT 7001, which is a TFT for driving the light-emitting element, are electrically connected, and the light-emitting layer 7004 and the anode 7005 are sequentially laminated on the cathode 7003. The cathode 7003 can be made of various materials as long as it has a low work function and reflects light. For example, Ca, Al, MgAg, AlLi, etc. are desirable. The light-emitting layer 7004 can be composed of a single layer or a plurality of layers laminated. When composed of a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are laminated in this order on the cathode 7003. It is not necessary to provide all of these layers.

[0316] Also, between the cathode 7003 and the cathode 7008 of adjacent pixels, a partition wall 7009 is provided to cover each end. The partition wall 7009 is made of polyimide, acrylic, polyamide, epoxy, or the like, an organic resin film, an inorganic insulating film, or organic polysiloxane. The partition wall 7009 is formed using a particularly photosensitive resin material, and it is preferably formed such that the side surface of the partition wall 7009 becomes an inclined surface with a continuous curvature. When a photosensitive resin

[0317] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 corresponds to the light-emitting element 7002. In the case of the pixel shown in Fig. 13(A), the light emitted from the light-emitting element 7002 is emitted toward the anode 7005 as shown by the arrow.

[0318] Next, the light-emitting element with a bottom emission structure will be described with reference to Fig. 13(B). A cross-sectional view of a pixel is shown when the TFT 7011 for driving the light-emitting element is of the n-type and the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side. In Fig. 13(B), on a light-transmissive conductive film 7017 electrically connected to the TFT 7011 for driving the light-emitting element, the cathode 7013 of the light-emitting element 7012 is formed, and a light-emitting layer 7014 and an anode 7015 are sequentially laminated on the cathode 7013. When the anode 7015 has light-transmissivity, a shielding film 7016 for reflecting or shielding light may be formed so as to cover the anode. The cathode 7013 can be made of various materials as long as it is a conductive material with a small work function, similar to the case of Fig. 13(A). However, the film thickness should be such that light can pass through (preferably about 5 nm to 30 nm). For example, ​​For example, an aluminum film having a film thickness of 20 nm can be used as the cathode 7013. And the light-emitting layer 7014 may be composed of a single layer or a plurality of layers, similar to FIG. 13(A). The anode 7015 does not necessarily need to transmit light, but it can be formed using a conductive material having light-transmitting properties, similar to FIG. 13(A). And for the shielding film 7016, for example, a metal that reflects light can be used, but it is not limited to a metal film. For example, a resin added with a black pigment can also be used.

[0319] Also, between the conductive film 7017 of one pixel and the conductive film 7018 of an adjacent pixel, partition walls 7019 are provided to cover the respective ends. The partition walls 7019 are formed using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or an organic polysiloxane. The partition walls 7019 are preferably formed using a photosensitive resin material such that the side surfaces of the partition walls 7019 form inclined surfaces with continuous curvature. When a photosensitive resin material is used for the partition walls 7019, the step of forming a resist mask can be omitted.

[0320] The region sandwiching the light-emitting layer 7014 between the cathode 7013 and the anode 7015 corresponds to the light-emitting element 7012. In the case of the pixel shown in FIG. 13(B), the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side as indicated by the arrow.

[0321] Next, a light-emitting element with a double-sided emission structure will be described with reference to FIG. 13(C). In FIG. 13(C), on a light-transmitting conductive film 7027 electrically connected to the TFT 7021 for driving the light-emitting element, the cathode 7023 of the light-emitting element 7022 is formed, and on the cathode 7023, a light-emitting layer 7 024. The anode 7025 is laminated in sequence. The cathode 7023 can be made of various materials as long as they are conductive materials with a small work function, similar to the case of Fig. 13(A). However, the film thickness should be such that light can pass through. For example, Al with a film thickness of 20 nm can be used as the cathode 7023. And the light-emitting layer 7024 can be composed of a single layer or multiple laminated layers, either way is fine, similar to Fig. 13(A). The anode 7025 can be formed using a conductive material with light-transmitting properties, similar to Fig. 13(A). Moreover, between the conductive films 7027 and 7028 of adjacent pixels, partition walls 7029 are provided to cover their respective ends. The partition walls 7029 are formed using organic resin films such as polyimide, acrylic, polyamide, and epoxy, inorganic insulating films, or organic polysiloxanes. The partition walls 7029 are preferably formed using a photosensitive resin material so that the side surfaces of the partition walls 7029 form inclined surfaces with continuous curvature. When using a photosensitive resin material for the partition walls 7029, the process of forming a resist mask can be omitted. The overlapping part of the cathode 7023, the light-emitting layer 7024, and the anode 7025 corresponds to the light-emitting element 7022. In the case of the pixel shown in Fig. 13(C), the light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the arrows. Here, although the light-emitting element is described as an organic EL element, it is also possible to provide an inorganic EL element as the light-emitting element. 024. The anode 7025 is laminated in sequence. The cathode 7023 can be made of various materials as long as they are conductive materials with a small work function, similar to the case of Fig. 13(A). However, the film thickness should be such that light can pass through. For example, Al with a film thickness of 20 nm can be used as the cathode 7023. And the light-emitting layer 7024 can be composed of a single layer or multiple laminated layers, either way is fine, similar to Fig. 13(A). The anode 7025 can be formed using a conductive material with light-transmitting properties, similar to Fig. 13(A).

[0322] Moreover, between the conductive films 7027 and 7028 of adjacent pixels, partition walls 7029 are provided to cover their respective ends. The partition walls 7029 are formed using organic resin films such as polyimide, acrylic, polyamide, and epoxy, inorganic insulating films, or organic polysiloxanes. The partition walls 7029 are preferably formed using a photosensitive resin material so that the side surfaces of the partition walls 7029 form inclined surfaces with continuous curvature. When using a photosensitive resin material for the partition walls 7029, the process of forming a resist mask can be omitted. The overlapping part of the cathode 7023, the light-emitting layer 7024, and the anode 7025 corresponds to the light-emitting element 7022. In the case of the pixel shown in Fig. 13(C), the light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the arrows. Here, although the light-emitting element is described as an organic EL element, it is also possible to provide an inorganic EL element as the light-emitting element. Moreover, between the conductive films 7027 and 7028 of adjacent pixels, partition walls 7029 are provided to cover their respective ends. The partition walls 7029 are formed using organic resin films such as polyimide, acrylic, polyamide, and epoxy, inorganic insulating films, or organic polysiloxanes. The partition walls 7029 are preferably formed using a photosensitive resin material so that the side surfaces of the partition walls 7029 form inclined surfaces with continuous curvature. When using a photosensitive resin material for the partition walls 7029, the process of forming a resist mask can be omitted. The overlapping part of the cathode 7023, the light-emitting layer 7024, and the anode 7025 corresponds to the light-emitting element 7022. In the case of the pixel shown in Fig. 13(C), the light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the arrows. Here, although the light-emitting element is described as an organic EL element, it is also possible to provide an inorganic EL element as the light-emitting element.

[0323] The overlapping part of the cathode 7023, the light-emitting layer 7024, and the anode 7025 corresponds to the light-emitting element 7022. In the case of the pixel shown in Fig. 13(C), the light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the arrows. Here, although the light-emitting element is described as an organic EL element, it is also possible to provide an inorganic EL element as the light-emitting element. The overlapping part of the cathode 7023, the light-emitting layer 7024, and the anode 7025 corresponds to the light-emitting element 7022. In the case of the pixel shown in Fig. 13(C), the light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0324] Here, although the light-emitting element is described as an organic EL element, it is also possible to provide an inorganic EL element as the light-emitting element. The overlapping part of the cathode 7023, the light-emitting layer 7024, and the anode 7025 corresponds to the light-emitting element 7022. In the case of the pixel shown in Fig. 13(C), the light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0325] Note that, although an example in which a thin film transistor (TFT for driving a light-emitting element) that controls driving of the light-emitting element and the light-emitting element are electrically connected has been shown, a configuration in which a current control TFT is connected between the TFT for driving the light-emitting element and the light-emitting element may also be used. However, the semiconductor device is not limited to the configuration shown in FIG. 13, and various modifications based on the technical idea disclosed in this specification are possible. Next, the appearance and cross section of a light-emitting display panel (also referred to as a light-emitting panel) corresponding to one form of the semiconductor device will be described with reference to FIG. 11. FIG. 11(A) is a plan view of a panel in which thin film transistors and light-emitting elements formed on a first substrate are sealed with a sealing material between the first substrate and a second substrate, and FIG. 11(B) corresponds to a cross-sectional view taken along line H-I in FIG. 11(A).

[0326]

[0327]

[0328] A pixel portion 4502, signal line driver circuits 4503a and 4503b, and scan line driver circuits 4504a and 4504b provided on a first substrate 4501 are surrounded by a sealing material 4505. Further, a second substrate 4506 is provided on the pixel portion 4502, signal line driver circuits 4503a and 4503b, and scan line driver circuits 4504a and 4504b. Therefore, the pixel portion 4502, signal line driver circuits 4503a and 4503b, and scan line driver circuits 4504a and 4504b are sealed together with a filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. In this way, it is preferably packaged (encapsulated) with a highly airtight and low outgassing protective film (such as a bonding film or an ultraviolet curable resin film) or a cover material so as not to be exposed to the outside air.

[0329] ​​​​​​​​​​​​​​ A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of thin film transistors. In FIG. 11B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45, a thin film transistor 4509 included in a line driver circuit 4503a is illustrated.

[0330] The thin film transistors 4509 and 4510 are the oxide semiconductors shown in the first, second, fifth and sixth embodiments. A highly reliable thin film transistor including a dielectric layer can be applied. The thin film transistor 4509 may be the thin film transistor shown in any one of the first, second, fifth and sixth embodiments. The thin film transistor 4510 disposed in the pixel is a thin film transistor. The resistors 420, 448, 220, 280, and 290 can be used. In this embodiment, the thin film transistors 4509 and 4510 are n-channel thin film transistors.

[0331] The oxide semiconductor layer of the thin film transistor 4509 for the driver circuit is formed over the insulating layer 4544. A conductive layer 4540 is provided in a position overlapping with the channel forming region. By providing the MOSFET in a position overlapping the channel formation region of the semiconductor layer, It is possible to reduce the amount of change in the threshold voltage of the thin film transistor 4509. The potential of the gate electrode layer 4540 may be the same as that of the gate electrode layer of the thin film transistor 4509 or may be different. The conductive layer 4 may be formed of a conductive material and may function as a second gate electrode layer. The potential of 540 may be GND, 0V, or may be in a floating state.

[0332] On the thin film transistor 4509, an insulating layer 4541a that functions as a channel protection layer and an insulating layer 4541b that covers the peripheral portion (including the side surface) of the oxide semiconductor layer are formed. Similarly, the thin film transistor 4510 has an insulating layer 4542a that functions as a channel protection layer and an insulating layer 4542b that covers the peripheral portion (including the side surface) of the oxide semiconductor layer are formed.

[0333] The insulating layers 4541b and 4542b, which are oxide insulating layers that cover the peripheral portion (including the side surface) of the oxide semiconductor layer, can increase the distance between the gate electrode layer and the wiring layer (such as the source wiring layer and the capacitor wiring layer) formed above or around it, thereby reducing the parasitic capacitance. The insulating layers 4541a, 4541b, 4542a, and 4542b may be formed by the same materials and methods as the oxide insulating layers 426a and 426b shown in Embodiment 1. Further, it is configured to be covered with an insulating layer 4543 that functions as a planarization insulating film to reduce the surface unevenness of the thin film transistor. Here, as the insulating layers 4541a, 4541b, 4542a, and 4542b, a silicon oxide film is formed by sputtering using Embodiment 1.

[0334] Also, an insulating layer 4543 is formed on the insulating layers 4541a, 4541b, 4542a, and 4542b. The insulating layer 4543 may be formed by the same materials and methods as the protective insulating layer 403 shown in Embodiment 1. Here, as the insulating layer 4543, a silicon nitride film is formed by RF sputtering.

[0335] Also, an insulating layer 4544 is formed as a planarization insulating film. The insulating layer 4544 may be formed by the same materials and methods as the planarization insulating layer 404 shown in Embodiment 1. Here, Use acrylic as the insulating layer 4544.

[0336] In this embodiment, a configuration may be adopted in which a plurality of thin film transistors in the pixel portion are collectively surrounded by a nitride insulating film. A nitride insulating film may be used for the insulating layer 4543 and the gate insulating layer, and as shown in FIG. 11, a region where the insulating layer 4543 and the gate insulating layer are in contact with each other may be provided so as to surround at least the periphery of the pixel portion of the active matrix substrate. In this manufacturing process, invasion of moisture from the outside can be prevented. Also, even after the device, for example, a display device, is completed, invasion of moisture from the outside can be prevented for a long period of time, and the long-term reliability of the device can be improved.

[0337] Also, 4511 corresponds to a light-emitting element, and the first electrode layer 4517, which is a pixel electrode of the light-emitting element 4511, is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. Note that the configuration of the light-emitting element 4511 has a stacked structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513, but is not limited to the shown configuration. Depending on the direction of light extracted from the light-emitting element 4511 and the like, the configuration of the light-emitting element 4511 can be appropriately changed.

[0338] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. Particularly, a photosensitive material is used to form an opening on the first electrode layer 4517, and it is preferable to form the side wall of the opening so as to be an inclined surface formed with a continuous curvature.

[0339] The electroluminescent layer 4512 may be configured as a single layer or as a plurality of layers stacked.

[0340] A protective film may be formed on the second electrode layer 4513 and the partition wall 4520 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not penetrate into the light-emitting element 4511. As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC film, etc. can be formed.

[0341] In addition, various signals and potentials applied to the signal line driving circuits 4503a and 4503b, the scanning line driving circuits 4504a and 4504b , or the pixel portion 4502 are supplied from the FPCs 4518a and 4518 b.

[0342] The connection terminal electrode 4515 is formed of the same conductive film as the first electrode layer 4517 of the light-emitting element 4511, and the terminal electrode 4516 is formed of the same conductive film as the source electrode layer and the drain electrode layer of the thin film transistors 4509 and 4510.

[0343] The connection terminal electrode 4515 is electrically connected to the terminal of the FPC 4518a through the anisotropic conductive film 4519.

[0344] The second substrate positioned in the light extraction direction from the light-emitting element 4511 must be translucent. In that case, a translucent material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

[0345] In addition to inert gases such as nitrogen and argon, an ultraviolet curable resin or a thermosetting resin can be used as the filling material 4507, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. For example, nitrogen is used as the filling material​ That's all that is required.

[0346] Also, if necessary, a polarizing plate, or a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), an optical film such as a color filter, etc. may be appropriately provided on the light-emitting surface of the light-emitting element. Also, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, anti-glare processing can be performed to diffuse the reflected light due to the surface irregularities and reduce the reflection.

[0347] The signal line driver circuits 4503a, 4503b, and the scan line driver circuits 4504a, 4504b may be implemented by drive circuits formed of a single-crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate. Also, only the signal line driver circuit, or a part thereof, or only the scan line driver circuit, or a part thereof may be separately formed and implemented, and is not limited to the configuration of FIG. 11.

[0348] By the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device.

[0349] This embodiment can be implemented in appropriate combination with the configurations described in Embodiments 1 to 4, and 6 to 8.

[0350] (Embodiment 12) The semiconductor device disclosed in this specification can be applied as an electronic paper. The electronic paper can be used in electronic devices in any field as long as it can display information. For example, using the electronic paper, it can be applied to electronic books (e-books), posters, in-vehicle advertisements in vehicles such as trains, displays on various cards such as credit cards, etc. An example of an electronic device is shown in FIG. 20.

[0351] Figure 20 shows an example of the electronic book 2700. For example, the electronic book 2700 is composed of two housings, a housing 2 701 and a housing 2703. The housing 2701 and the housing 27 03 are integrated by a shaft portion 2711, and can perform an opening / closing operation around the shaft portion 2711 . With such a configuration, it becomes possible to perform operations similar to those of a paper book .

[0352] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703 . The display unit 2705 and the display unit 2707 may be configured to display a continuous screen , or may be configured to display different screens. With the configuration of displaying different screens , for example, text can be displayed on the right display unit (display unit 2705 in FIG. 20), and an image can be displayed on the left display unit (display unit 2707 in FIG. 20).

[0353] Also, FIG. 20 shows an example in which the housing 2701 is provided with an operation unit or the like. For example, in the housing 2 701, a power supply 2721, operation keys 2723, a speaker 2725, etc. are provided . The operation keys 2723 can be used to turn the page. Note that a key board or a pointing device may be provided on the same surface as the display unit of the housing . Also, on the back or side surface of the housing , external connection terminals (terminals that can be connected to various cables such as earphone terminals, USB terminals, or an AC adapter and a USB cable), a recording medium insertion portion, etc. may be provided . Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary . .

[0354] Also, the electronic book 2700 may be configured to be able to wirelessly transmit and receive information. By wireless means, it is possible to purchase and download desired book data and the like from an electronic book server. This is also possible.

[0355] (Embodiment 13) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). Examples of electronic devices include television devices (also referred to as TVs or television receivers), monitors for computers, digital cameras, digital video cameras, digital photo frames, mobile phones (also referred to as mobile phones or mobile phone devices), portable game machines, portable information terminals, audio playback devices, and large game machines such as pachinko machines. These are examples. These include large game machines such as pachinko machines. These are examples.

[0356] FIG. 21(A) shows an example of a television device 9600. The television device 96 00 has a display unit 9603 incorporated in a housing 9601. The display unit 9603 can display images. Here, a configuration in which the housing 9601 is supported by a stand 9605 is shown. The display unit 9603 can display images. Here, a configuration in which the housing 9601 is supported by a stand 9605 is shown. The display unit 9603 can display images. Here, a configuration in which the housing 9601 is supported by a stand 9605 is shown.

[0357] The operation of the television device 9600 can be performed by operation switches provided in the housing 9601 or by a separate remote control operation unit 9610. By operation keys 9609 provided in the remote control operation unit 9610, operations such as changing channels and adjusting volume can be performed, and the images displayed on the display unit 9603 can be operated. Also, the remote control operation unit 9610 may be configured to be provided with a display unit 9607 for displaying information output from the remote control operation unit 9610. The operation of the television device 9600 can be performed by operation switches provided in the housing 9601 or by a separate remote control operation unit 9610. By operation keys 9609 provided in the remote control operation unit 9610, operations such as changing channels and adjusting volume can be performed, and the images displayed on the display unit 9603 can be operated. Also, the remote control operation unit 9610 may be configured to be provided with a display unit 9607 for displaying information output from the remote control operation unit 9610. The operation of the television device 9600 can be performed by operation switches provided in the housing 9601 or by a separate remote control operation unit 9610. By operation keys 9609 provided in the remote control operation unit 9610, operations such as changing channels and adjusting volume can be performed, and the images displayed on the display unit 9603 can be operated. Also, the remote control operation unit 9610 may be configured to be provided with a display unit 9607 for displaying information output from the remote control operation unit 9610. The operation of the television device 9600 can be performed by operation switches provided in the housing 9601 or by a separate remote control operation unit 9610. By operation keys 9609 provided in the remote control operation unit 9610, operations such as changing channels and adjusting volume can be performed, and the images displayed on the display unit 9603 can be operated. Also, the remote control operation unit 9610 may be configured to be provided with a display unit 9607 for displaying information output from the remote control operation unit 9610. The operation of the television device 9600 can be performed by operation switches provided in the housing 9601 or by a separate remote control operation unit 9610. By operation keys 9609 provided in the remote control operation unit 9610, operations such as changing channels and adjusting volume can be performed, and the images displayed on the display unit 9603 can be operated. Also, the remote control operation unit 9610 may be configured to be provided with a display unit 9607 for displaying information output from the remote control operation unit 9610.

[0358] Note that the television device 9600 has a configuration including a receiver, a modem, etc. The receiver can receive more general television broadcasts, and can also be connected to a communication network by wire or wirelessly via a modem, enabling one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0359] FIG. 21(B) shows an example of the digital photo frame 9700. For example, the digital photo frame 9700 has a display unit 9703 incorporated in a housing 9701. The display unit 9703 can display various images, and by displaying, for example, image data taken with a digital camera, it can function in the same way as a normal photo stand.

[0360] Note that the digital photo frame 9700 has a configuration including an operation unit, external connection terminals (terminals connectable to various cables such as USB terminals, USB cables, etc.), a recording medium insertion unit, etc. These configurations may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side or back surface as it improves the design. For example, by inserting a memory storing image data taken with a digital camera into the recording medium

[0361] insertion unit of the digital photo frame, the image data can be captured and the captured image data can be displayed on the display unit 9703.

[0362] FIG. 22(A) shows a portable game machine, which is composed of two housings, They are connected so as to be openable and closable by a connecting portion 9893. A display unit 9882 is incorporated in the housing 9881, and a display unit 9883 is incorporated in the housing 9891. Also, as shown in FIG. 22(A), the portable gaming machine further includes a speaker unit 9884, a recording medium insertion unit 988 6, an LED lamp 9890, input means (operation keys 9885, connection terminals 9887, sensors 9 888 (including functions for measuring force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9889), etc. Of course, the configuration of the portable gaming machine is not limited to the above, and it may be a configuration including at least the semiconductor device disclosed in this specification and a configuration in which other accessory equipment is appropriately provided. The portable gaming machine shown in FIG. 22(A) has a function of reading a program or data recorded on a recording medium and displaying it on a display unit, and a function of sharing information by performing wireless communication with another portable gaming machine. Note that the functions of the portable gaming machine shown in FIG. 22(A) are not limited to these, and it can have various functions.

[0363] FIG. 22(B) shows an example of a slot machine 9900 which is a large gaming machine. The slot machine 9900 has a display unit 9903 incorporated in a housing 9901. Also, the slot machine 9900 further includes operation means such as a start lever and a stop switch, a coin insertion slot, a speaker, etc. Of course, the configuration of the slot machine 9900 is not limited to the above and may be a configuration including at least the semiconductor device disclosed in this specification and a configuration in which other accessory equipment is appropriately provided.

[0364] FIG. 23(A) is a perspective view showing an example of a portable computer.

[0365] The portable computer in FIG. 23(A) has an upper housing 9301 and a lower housing 9302, and can be in a state where the upper housing 9301 having a display unit 9303 and the lower housing 9302 having a keyboard 9304 are overlapped with the hinge unit connecting them in a closed state, which is convenient for carrying. When the user inputs using the keyboard, the hinge unit can be opened, and the input operation can be performed while looking at the display unit 9303. Moreover, the lower housing 9302 has a pointing device 9306 for performing an input operation in addition to the keyboard 9304. If the display unit 9303 is a touch input panel, the input operation can also be performed by touching a part of the display unit. Further, the lower housing 9302 has a computing function unit such as a CPU and a hard disk. Also, the lower housing 9302 has an external connection port 9305 into which a communication cable conforming to the communication standard of another device, for example, USB, is inserted.

[0366]

[0367] The upper housing 9301 further has a display unit 9307 that can be slid and stored inside the upper housing 9301, and a wide display screen can be realized. Also, the user can adjust the orientation of the screen of the retractable display unit 9307. If the retractable display unit 9307 is a touch input panel, the input operation can also be performed by touching a par...

Claims

[Claim 1] a gate electrode layer; a gate insulating layer on the gate electrode layer; an oxide semiconductor layer on the gate insulating layer; an oxide insulating layer on the oxide semiconductor layer; a source electrode layer or a drain electrode layer over the oxide insulating layer, the oxide semiconductor layer has a first region in contact with the oxide insulating layer and a second region in contact with the source electrode layer or the drain electrode layer, the first region has a channel formation region overlapping with the gate electrode layer with the gate insulating layer interposed therebetween, and a region overlapping with the oxide insulating layer covering a periphery and side surfaces of the oxide semiconductor layer, an end surface of the oxide semiconductor layer overlaps with the source electrode layer or the drain electrode layer via the oxide insulating layer;

Images