Semiconductor device and manufacturing method thereof

Abstract

To improve the performance of a semiconductor device and ensure the reliability of the semiconductor device.SOLUTION: A lower electrode BE is formed in a wiring layer WL4. Two wirings M5 having a thickness greater than that of the lower electrode BE are formed in the wiring layer WL5 located above the wiring layer WL4. An insulating film IF1 and an upper electrode UE are formed on the lower electrode BE between the wiring layer WL4 and the wiring layer WL5. A resistive element RS1 is formed on the two wirings M5. The lower electrode BE, the insulating film IF1, and the upper electrode UE function as a capacitive element MIM.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device including a capacitor element and a resistor element formed in a multilayer wiring layer and a method for manufacturing the same.

Background Art

[0002] In recent semiconductor devices, the number of wiring layers has been increasing. By providing capacitor elements, resistor elements, etc. between each wiring layer, an increase in the planar size of the semiconductor device is suppressed, and miniaturization of the semiconductor device is promoted.

[0003] Patent Document 1 discloses a capacitor element in which a capacitor insulating film and an upper electrode are sequentially stacked on a lower electrode. This lower electrode is formed in a wiring layer and is formed by the same manufacturing process as the manufacturing process for forming the wiring.

[0004] Patent Document 2 discloses a technique for forming a resistor element made of a material such as silicon chromium (SiCr) between a lower wiring layer and an upper wiring layer.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] A capacitive element such as that of Patent Document 1 is used, for example, in a high-precision analog circuit that requires high relative accuracy. When using a wiring in the same wiring layer as the lower electrode of the capacitive element, the relative accuracy varies depending on the configuration of the wiring, and the characteristics of the capacitive element fluctuate. Therefore, there are restrictions on the wiring that can be used for the lower electrode. Note that relative accuracy is the magnitude of variation in characteristics among a plurality of elements formed within the same semiconductor substrate. Good relative accuracy means that the variation in characteristics among a plurality of elements is small enough to meet the requirements in a high-precision analog circuit.

[0007] Also, as a resistive element such as that of Patent Document 2, for example, a conductive film having a thickness of about 10 nm is used. This resistive element is formed between an upper wiring layer and a lower wiring layer. When patterning the upper wiring formed within the upper wiring layer, overetching is performed, and the longer the thickness of the upper wiring, the longer the overetching time. Therefore, when the thickness of the upper wiring is large and the thickness of the interlayer insulating film formed on the resistive element is small, there is a risk that the overetching will reach the resistive element.

[0008] In that case, there is a risk that the characteristics of the resistive element will fluctuate due to a decrease in the thickness of the resistive element or the disappearance of a part of the resistive element. Therefore, there are restrictions on the arrangement position of the resistive element. In particular, the above problem is more likely to occur as the distance between a plurality of wiring layers becomes shorter.

[0009] Therefore, when a capacitive element and a resistive element are provided between each wiring layer, a technique is desired that can improve the performance of the semiconductor device and ensure the reliability of the semiconductor device by improving the relative accuracy of the capacitive element and maintaining the characteristics of the resistive element.

[0010] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0011] The outline of typical embodiments disclosed in the present application will be briefly described as follows.

[0012] In one embodiment, a semiconductor device includes a first wiring formed in a first wiring layer, a second wiring and a third wiring formed in a second wiring layer positioned above the first wiring layer and having a thickness greater than that of the first wiring, a first insulating film and a first conductive film formed between the first wiring layer and the second wiring layer and on the first wiring, and a second conductive film formed on the second wiring and the third wiring. The first wiring, the first insulating film, and the first conductive film function as a capacitor element, and the second conductive film functions as a first resistor element electrically connected to the second wiring and the third wiring.

[0013] In one embodiment, a method of manufacturing a semiconductor device includes a step of forming a first interlayer insulating film on the semiconductor substrate, a step of forming a first wiring, a first insulating film, and a first conductive film sequentially stacked on the first wiring on the first interlayer insulating film, a step of forming a second interlayer insulating film covering the first wiring, the first insulating film, and the first conductive film, a step of forming a second wiring and a third wiring on the second interlayer insulating film, a step of forming a third interlayer insulating film covering the second wiring and the third wiring, and a step of forming a second conductive film on the third interlayer insulating film. The thickness of the first wiring is smaller than the thickness of each of the second wiring and the third wiring. The first wiring, the first insulating film, and the first conductive film function as a capacitor element, and the second conductive film functions as a first resistor element electrically connected to the second wiring and the third wiring.

Advantages of the Invention

[0014] According to one embodiment, the performance of the semiconductor device can be improved, and the reliability of the semiconductor device can be ensured.

Brief Description of the Drawings

[0015]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Modes for Carrying Out the Invention

[0016] Hereinafter, embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are denoted by the same reference numerals, and repeated explanations thereof are omitted. In the following embodiments, explanations of the same or similar parts are not repeated in principle unless particularly necessary.

[0017] In addition, the X direction, Y direction, and Z direction described in the present application intersect each other and are orthogonal to each other. The Z direction is a direction perpendicular to the upper surface of the semiconductor substrate SUB. In the present application, the Z direction is described as the vertical direction, height direction, or thickness direction of a certain structure.

[0018] (Embodiment 1) <Structure of the semiconductor device> As shown in FIG. 1, the semiconductor device includes a semiconductor substrate SUB, a plurality of transistors 1Q, a multilayer wiring layer formed on the semiconductor substrate SUB, and a capacitor element MIM and a resistor element RS1 formed between the wiring layers.

[0019] The multilayer wiring layer has a plurality of wiring layers. In Embodiment 1, the plurality of wiring layers include a wiring layer WL1, a wiring layer WL2, a wiring layer WL3, a wiring layer WL4, a wiring layer WL5, and a wiring layer WL6. The wiring layer WL6 is the uppermost wiring layer of the multilayer wiring layer. The wiring layer WL1 includes a plurality of wirings M1. The wiring layer WL2 includes a plurality of wirings M2. The wiring layer WL3 includes a plurality of wirings M3. The wiring layer WL4 includes a plurality of wirings M4. The wiring layer WL5 includes a plurality of wirings M5. The wiring layer WL6 includes a plurality of wirings M6.

[0020] The semiconductor substrate SUB is made of, for example, p-type single-crystalline silicon. In the semiconductor substrate SUB, a plurality of element isolation parts are formed that define regions where a plurality of semiconductor elements are formed. Also, in the semiconductor substrate SUB, well regions into which p-type or n-type impurities are introduced are formed. In the well regions, source regions and drain regions into which p-type or n-type impurities are introduced are formed. On the well regions, gate electrodes are formed via gate insulating films. In FIG. 1, as the semiconductor element, a transistor 1Q which is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is formed. The transistor 1Q includes a gate insulating film, a gate electrode, a source region, and a drain region.

[0021] On the semiconductor substrate SUB, an interlayer insulating film IL0 is formed so as to cover the plurality of transistors 1Q. The interlayer insulating film IL0 includes, for example, a silicon oxide film. In the interlayer insulating film IL0, a plurality of plugs PG are formed so as to be connected to the semiconductor substrate SUB. Each of the plurality of plugs PG is embedded inside a hole formed in the interlayer insulating film IL0 and includes a laminated film including, for example, a titanium nitride film and a tungsten film. On the interlayer insulating film IL0, a plurality of wirings M1 are formed so as to be connected to the plurality of plugs PG.

[0022] On the interlayer insulating film IL0, an interlayer insulating film IL1 is formed so as to cover the plurality of wirings M1. The interlayer insulating film IL1 includes, for example, a silicon oxide film. In the interlayer insulating film IL1, a plurality of vias V1 are formed so as to be connected to the plurality of wirings M1. The via V1 is embedded inside a hole formed in the interlayer insulating film IL1 and includes a laminated film including, for example, a titanium nitride film and a tungsten film. On the interlayer insulating film IL1, a plurality of wirings M2 are formed so as to be connected to the plurality of vias V1.

[0023] On the interlayer insulating film IL1, an interlayer insulating film IL2 is formed so as to cover a plurality of wirings M2. The interlayer insulating film IL2 includes, for example, a silicon oxide film. In the interlayer insulating film IL2, a plurality of vias V2 are formed so as to connect to the plurality of wirings M2. The via V2 is embedded inside a hole formed in the interlayer insulating film IL2 and includes a laminated film including, for example, a titanium nitride film and a tungsten film. On the interlayer insulating film IL2, a plurality of wirings M3 are formed so as to connect to the plurality of vias V2.

[0024] On the interlayer insulating film IL2, an interlayer insulating film IL3 is formed so as to cover a plurality of wirings M3. The interlayer insulating film IL3 includes, for example, a silicon oxide film. In the interlayer insulating film IL3, a plurality of vias V3 are formed so as to connect to the plurality of wirings M3. The via V3 is embedded inside a hole formed in the interlayer insulating film IL3 and includes a laminated film including, for example, a titanium nitride film and a tungsten film. On the interlayer insulating film IL3, a plurality of wirings M4 are formed so as to connect to the plurality of vias V3.

[0025] The plurality of wirings M4 have a lower electrode BE of the capacitor element MIM. An insulating film IF1 is formed on the lower electrode BE. The insulating film IF1 is, for example, a silicon oxide film, a silicon oxynitride film, or a silicon nitride film, or a laminated film formed by appropriately laminating these films. An upper electrode UE is formed on the insulating film IF1. The upper electrode UE is a conductive film and includes, for example, a titanium nitride film. The insulating film IF1 and the upper electrode UE are formed between the wiring layer WL4 and the wiring layer WL5. The lower electrode BE, the insulating film IF1, and the upper electrode UE function as the capacitor element MIM.

[0026] On the interlayer insulating film IL3, an interlayer insulating film IL4 is formed so as to cover a plurality of wirings M4 and capacitor elements MIM. The interlayer insulating film IL4 includes, for example, a silicon oxide film. In the interlayer insulating film IL4, a plurality of vias V4 are formed so as to connect to the plurality of wirings M4. Also, in the interlayer insulating film IL4, a via V4 connecting to the upper electrode UE of the capacitor element MIM is also formed. The via V4 is embedded inside a hole formed in the interlayer insulating film IL4 and includes a laminated film including, for example, a titanium nitride film and a tungsten film. On the interlayer insulating film IL4, a plurality of wirings M5 are formed so as to connect to the plurality of vias V4.

[0027] On the interlayer insulating film IL4, an interlayer insulating film IL5a is formed so as to cover a plurality of wirings M5. The interlayer insulating film IL5a includes, for example, a silicon oxide film. In the interlayer insulating film IL5a, local vias LV1 and LV2 are formed so as to connect to different wirings M5 respectively. The local vias LV1 and LV2 are each embedded inside a hole formed in the interlayer insulating film IL5a and include a laminated film including, for example, a titanium nitride film and a tungsten film.

[0028] On the interlayer insulating film IL5a, a resistance element RS1 is formed so as to connect to the local vias LV1 and LV2. That is, the resistance element RS1 is electrically connected to two different wirings M5 via the local vias LV1 and LV2. The resistance element RS1 is a conductive film. The resistance element RS1 includes at least one of, for example, a silicon chromium film (SiCr film), a silicon chromium film with carbon introduced (SiCrC film), a nickel chromium film (NiCr film), a titanium nitride film (TiN film), and a tantalum nitride film (TaN film).

[0029] On the interlayer insulating film IL5a, an interlayer insulating film IL5b is formed so as to cover the resistance element RS1. The interlayer insulating film IL5b includes, for example, a silicon oxide film. In the interlayer insulating film IL5b and the interlayer insulating film IL5a, a plurality of vias V5 are formed so as to connect to the plurality of wirings M5. The via V5 is embedded inside a hole formed in the interlayer insulating film IL5b and the interlayer insulating film IL5a, and includes a laminated film including, for example, a titanium nitride film and a tungsten film. On the interlayer insulating film IL5b, a plurality of wirings M6 are formed so as to connect to the plurality of vias V5.

[0030] FIG. 2 is an enlarged cross-sectional view of a portion where the capacitor element MIM and the resistance element RS1 are formed in FIG. 1. FIG. 3 is a cross-sectional view showing the same portion as FIG. 2. In FIG. 3, some configurations and some hatchings are omitted in order to easily explain the thickness of each wiring.

[0031] As shown in FIG. 2, the wiring M4 has a lower barrier metal film BM4a, a conductive film CF4 formed on the lower barrier metal film BM4a, and an upper barrier metal film BM4b formed on the conductive film CF4. The wiring M5 has a lower barrier metal film BM5a, a conductive film CF5 formed on the lower barrier metal film BM5a, and an upper barrier metal film BM5b formed on the conductive film CF5. The wiring M6 has a lower barrier metal film BM6a, a conductive film CF6 formed on the lower barrier metal film BM6a, and an upper barrier metal film BM6b formed on the conductive film CF6.

[0032] Note that the configurations of the wirings M1, M2, and M3 are the same as those of the wiring M4. That is, the wirings M1, M2, and M3 have a barrier metal film similar to the lower barrier metal film BM4a, a conductive film similar to the conductive film CF4, and a barrier metal film similar to the upper barrier metal film BM4b.

[0033] The lower barrier metal films BM4a, BM5a, and BM6a each include a titanium film and a titanium nitride film formed on the titanium film. The conductive films CF4, CF5, and CF6 each include an aluminum film or an aluminum alloy film in which copper or silicon is added to the aluminum film. The upper barrier metal films BM4b, BM5b, and BM6b each include a titanium nitride film.

[0034] The thickness T5 of the wiring M5 is greater than the thickness T4 of the wiring M4. The thickness T6 of the wiring M6 is greater than the thickness T5 of the wiring M5. The wiring layer WL6 is often used for routing the power supply. In order to suppress the voltage drop, the thickness T6 of the wiring M6 is set to be greater than the thicknesses of other wirings such as the wiring M4.

[0035] The thickness T4 of the wiring M4 is, for example, 220 nm or more and 360 nm or less. The thickness of the upper barrier metal film BM4b is, for example, 50 nm or more and 70 nm or less. The thickness of the conductive film CF4 is, for example, 130 nm or more and 230 nm or less. The thickness of the lower barrier metal film BM4a is, for example, 40 nm or more and 60 nm or less.

[0036] The thickness T5 of the wiring M5 is, for example, 550 nm or more and 690 nm or less. The thickness of the upper barrier metal film BM5b is, for example, 60 nm or more and 80 nm or less. The thickness of the conductive film CF5 is, for example, 450 nm or more and 550 nm or less. The thickness of the lower barrier metal film BM5a is, for example, 40 nm or more and 60 nm or less.

[0037] The thickness T6 of the wiring M6 is, for example, 1000 nm or more and 1640 nm or less. The thickness of the upper barrier metal film BM6b is, for example, 60 nm or more and 80 nm or less. The thickness of the conductive film CF6 is, for example, 900 nm or more and 1500 nm or less. The thickness of the lower barrier metal film BM6a is, for example, 40 nm or more and 60 nm or less.

[0038] The thickness of the insulating film IF1 is, for example, 20 nm or more and 50 nm or less. The thickness of the upper electrode UE is, for example, 50 nm or more and 150 nm or less. The thickness of the resistance element RS1 is, for example, 5 nm or more and 20 nm or less.

[0039] The distance L56 between the wiring layer WL5 and the wiring layer WL6 is longer than the distance L45 between the wiring layer WL4 and the wiring layer WL5. Note that the distance between the wiring layer WL1 and the wiring layer WL2, the distance between the wiring layer WL2 and the wiring layer WL3, and the distance between the wiring layer WL3 and the wiring layer WL4 are the same as the distance L45.

[0040] The distance L45 is, for example, 250 nm or more and 350 nm or less. The distance L45 corresponds to the thickness of the portion of the interlayer insulating film IL4 located on the wiring M4 and corresponds to the height of the via V4 that electrically connects the wiring M4 and the wiring M5.

[0041] The distance L56 is, for example, 500 nm or more and 650 nm or less. The distance L56 corresponds to the sum of the thickness of the portion of the interlayer insulating film IL5a located on the wiring M5 and the thickness of the portion of the interlayer insulating film IL5b located on the wiring M5, and corresponds to the height of the via V5 that electrically connects the wiring M5 and the wiring M6.

[0042] The distance L5m between the upper electrode UE and the wiring layer WL5 (wiring M5) is, for example, 50 nm or more and 280 nm or less. The distance L5m corresponds to the thickness of the portion of the interlayer insulating film IL4 located on the upper electrode UE and corresponds to the height of the via V4 that electrically connects the upper electrode UE and the wiring M5.

[0043] The distance L5r between the resistance element RS1 and the wiring layer WL5 (wiring M5) is, for example, 200 nm or more and 230 nm or less. The distance L5r corresponds to the thickness of the portion of the interlayer insulating film IL5a located on the wiring M4 and corresponds to the height of the local via LV1 and the height of the local via LV2 that electrically connect the resistance element RS1 and the wiring M5.

[0044] The distance L6r between the resistive element RS1 and the wiring layer WL6 (wiring M6) is, for example, 250 nm or more and 445 nm or less. The distance L6r corresponds to the thickness of the portion of the interlayer insulating film IL5b that is located above the resistive element RS1.

[0045] Note that the distances L45, L56, L5m, L5r, and L6r are distances in the direction (Z direction) perpendicular to the upper surface of the semiconductor substrate SUB.

[0046] <Method of manufacturing a semiconductor device> As shown in FIG. 4, first, a semiconductor substrate SUB is prepared. Next, a plurality of element isolation parts are formed in the semiconductor substrate SUB. Each of the plurality of element isolation parts can be formed by forming a groove in the semiconductor substrate SUB and embedding an insulating film such as a silicon oxide film in this groove. Next, p-type or n-type impurities are introduced into the semiconductor substrate SUB to form a well region. Next, a transistor 1Q is formed as a semiconductor element on the semiconductor substrate. For example, a gate electrode is formed on the well region via a gate insulating film, and p-type or n-type impurities are introduced into the well region to form a source region and a drain region.

[0047] Next, an interlayer insulating film IL0 is formed on the semiconductor substrate SUB so as to cover the transistor 1Q, for example, by a CVD (Chemical Vapor Deposition) method. Next, a polishing process by a CMP (Chemical Mechanical Polishing) method is performed on the upper surface of the interlayer insulating film IL0. Next, a plurality of plugs PG are formed in the interlayer insulating film IL0.

[0048] To form the plug PG, first, a hole is formed in the interlayer insulating film IL0 by photolithography technology and anisotropic etching processing. Next, a titanium nitride film and a tungsten film are sequentially formed on the interlayer insulating film IL0 so as to fill the inside of the hole, for example, by a CVD method. Next, a polishing process by a CMP method is performed to remove the titanium nitride film and the tungsten film located outside the hole. In this way, the plug PG is formed.

[0049] As shown in FIG. 5, a wiring layer WL1, a wiring layer WL2, and a wiring layer WL3 are sequentially formed on the interlayer insulating film IL0. First, a lower barrier metal film is formed on the interlayer insulating film IL0. The lower barrier metal film is a laminated film including, for example, a titanium film formed by a sputtering method and a titanium nitride film formed on the titanium film by a sputtering method. Next, a conductive film such as an aluminum film or an aluminum alloy film is formed on the lower barrier metal film by, for example, a sputtering method. Next, an upper barrier metal film such as a titanium nitride film is formed on the conductive film by, for example, a sputtering method.

[0050] Next, a plurality of wirings M1 are formed by patterning the upper barrier metal film, the conductive film, and the lower barrier metal film by photolithography technology and anisotropic etching treatment.

[0051] Next, an interlayer insulating film IL1 is formed on the interlayer insulating film IL0 by, for example, a CVD method. Next, a polishing treatment by a CMP method is performed on the upper surface of the interlayer insulating film IL1. Next, a plurality of vias V1 are formed in the interlayer insulating film IL1.

[0052] To form the via V1, first, a hole is formed in the interlayer insulating film IL1 by photolithography technology and anisotropic etching treatment. Next, a titanium nitride film and a tungsten film are sequentially formed on the interlayer insulating film IL1 by, for example, a CVD method so as to fill the inside of the hole. Next, by performing a polishing treatment by a CMP method, the titanium nitride film and the tungsten film located outside the hole are removed. In this way, the via V1 is formed.

[0053] Thereafter, wirings M2, an interlayer insulating film IL2, vias V2, wirings M3, an interlayer insulating film IL3, and vias V3 are formed by a method similar to the method of forming the wiring M1, the interlayer insulating film IL1, and the via V1.

[0054] As shown in FIG. 6, first, a lower barrier metal film BM4a is formed on the interlayer insulating film IL3. The lower barrier metal film BM4a is a laminated film including, for example, a titanium film formed by a sputtering method and a titanium nitride film formed on the titanium film by, for example, a sputtering method. Next, a conductive film CF4 such as an aluminum film or an aluminum alloy film is formed on the lower barrier metal film BM4a by, for example, a sputtering method. Next, an upper barrier metal film BM4b such as a titanium nitride film is formed on the conductive film CF4 by, for example, a sputtering method. Next, an insulating film IF1 is formed on the upper barrier metal film BM4b by, for example, a CVD method. Next, a conductive film CFm such as a titanium nitride film is formed on the insulating film IF1 by, for example, a sputtering method.

[0055] As shown in FIG. 7, by selectively patterning the conductive film CFm and the insulating film IF1, a conductive film CFm patterned as the upper electrode UE of the capacitor element MIM is formed.

[0056] First, a resist pattern RP1 is formed on the conductive film CFm. The resist pattern RP1 has an opening pattern that selectively covers a part of the conductive film CFm. Next, by performing an anisotropic etching process using the resist pattern RP1 as a mask, the conductive film CFm and the insulating film IF1 exposed from the resist pattern RP1 are removed. The remaining conductive film CFm is formed as the upper electrode UE. Thereafter, the resist pattern RP1 is removed by an ashing process.

[0057] As shown in FIG. 8, a plurality of wirings M4 are formed by selectively patterning the upper barrier metal film BM4b, the conductive film CF4, and the lower barrier metal film BM4a so that the insulating film IF1 and the upper electrode UE remain on the upper barrier metal film BM4b. The plurality of wirings M4 include the lower electrode BE of the capacitor element MIM.

[0058] First, a resist pattern RP2 is formed on the upper barrier metal film BM4b. The resist pattern RP2 has an opening pattern that selectively covers the locations where the insulating film IF1 and the upper electrode UE are formed in the upper barrier metal film BM4b. Next, by performing an anisotropic etching process using the resist pattern RP2 as a mask, the upper barrier metal film BM4b, the conductive film CF4, and the lower barrier metal film BM4a that are exposed from the resist pattern RP2 are removed. The remaining upper barrier metal film BM4b, conductive film CF4, and lower barrier metal film BM4a are formed as a plurality of wirings M4. Thereafter, the resist pattern RP2 is removed by an ashing process.

[0059] Although not shown in the figure, patterning may be performed using a hard mask instead of the resist pattern RP2. First, an insulating film is formed on the upper barrier metal film BM4b, for example, by CVD method. The insulating film is, for example, a silicon nitride film. Next, a resist pattern RP2 is formed on the insulating film. Next, by performing an anisotropic etching process using the resist pattern RP2 as a mask, the insulating film that is exposed from the resist pattern RP2 is removed. The remaining insulating film is formed as the hard mask. Thereafter, the resist pattern RP2 is removed by an ashing process.

[0060] The hard mask has the same opening pattern as the resist pattern RP2. By performing an anisotropic etching process using the hard mask, the upper barrier metal film BM4b, the conductive film CF4, and the lower barrier metal film BM4a that are exposed from the hard mask are removed. The remaining upper barrier metal film BM4b, conductive film CF4, and lower barrier metal film BM4a are formed as a plurality of wirings M4.

[0061] The patterning using the resist pattern, or the hard mask processed using the resist pattern as a mask, is not limited to the formation of the wiring M4, and may be performed for the formation of each of the wirings M1, M2, M3, M5, or M6.

[0062] In this way, through the manufacturing processes shown in FIGS. 6 to 8, a plurality of wirings M4, an insulating film IF1 sequentially laminated on the lower electrode BE, and an upper electrode UE are formed on the interlayer insulating film IL3.

[0063] As shown in FIG. 9, an interlayer insulating film IL4 is formed on the interlayer insulating film IL3, for example, by CVD method, so as to cover a plurality of wirings M4 including the lower electrode BE, the insulating film IF1, and the upper electrode UE. Next, a polishing process by CMP method is performed on the upper surface of the interlayer insulating film IL4. Next, a plurality of vias V4 are formed in the interlayer insulating film IL4. The method of forming the via V4 is the same as the method of forming the via V1.

[0064] As shown in FIG. 10, first, a plurality of wirings M5 are formed on the interlayer insulating film IL4. The method of forming the wiring M5 is the same as the method of forming the wiring M4. However, the thickness of each of the upper barrier metal film BM5b, the conductive film CF5, and the lower barrier metal film BM5a is different from the thickness of each of the upper barrier metal film BM4b, the conductive film CF4, and the lower barrier metal film BM4a.

[0065] Next, an interlayer insulating film IL5a is formed on the interlayer insulating film IL4, for example, by CVD method, so as to cover the plurality of wirings M5. Next, a polishing process by CMP method is performed on the upper surface of the interlayer insulating film IL5a.

[0066] As shown in FIG. 11, first, local vias LV1 and LV2 are formed in the interlayer insulating film IL5a. The method of forming the local vias LV1 and LV2 is the same as the method of forming the via V1. Note that the local vias LV1 and LV2 are formed so as to be connected to different wirings M5, respectively. Next, a conductive film CFr is formed on the interlayer insulating film IL5a, for example, by sputtering method.

[0067] As shown in FIG. 12, by selectively patterning the conductive film CFr, a resistance element RS1 connected to the local vias LV1 and LV2 is formed.

[0068] First, a resist pattern RP3 is formed on the conductive film CFr. The resist pattern RP3 has an opening pattern that selectively covers a part of the conductive film CFr. Next, anisotropic etching treatment is performed using the resist pattern RP3 as a mask to remove the conductive film CFr exposed from the resist pattern RP3. The remaining conductive film CFr is formed as the resistance element RS1. Then, the resist pattern RP3 is removed by ashing treatment.

[0069] As shown in FIG. 13, first, an interlayer insulating film IL5b is formed on the interlayer insulating film IL5a by, for example, the CVD method so as to cover the resistance element RS1. Next, polishing treatment by the CMP method is performed on the upper surface of the interlayer insulating film IL5b.

[0070] Next, a plurality of vias V5 are formed in the interlayer insulating film IL5b and the interlayer insulating film IL5a. The method of forming the via V5 is the same as the method of forming the via V1. However, the aperture diameter, the thickness of the titanium nitride film, and the thickness of the tungsten film in the via V5 are different from the aperture diameter, the thickness of the titanium nitride film, and the thickness of the tungsten film in the via V1.

[0071] As shown in FIG. 14, first, a lower barrier metal film BM6a is formed on the interlayer insulating film IL5b. The lower barrier metal film BM6a is a laminated film including a titanium film formed on the interlayer insulating film IL5b by, for example, sputtering and a titanium nitride film formed on the titanium film by, for example, sputtering. Next, a conductive film CF6 such as an aluminum film or an aluminum alloy film is formed on the lower barrier metal film BM6a by, for example, sputtering. Next, an upper barrier metal film BM6b such as a titanium nitride film is formed on the conductive film CF6 by, for example, sputtering.

[0072] Thereafter, a plurality of wirings M6 are formed by selectively patterning the upper barrier metal film BM6b, the conductive film CF6, and the lower barrier metal film BM6a. As a result, the structures of FIGS. 1 and 2 are obtained.

[0073] To pattern the plurality of wirings M6, first, a resist pattern is formed on the upper barrier metal film BM6b. The resist pattern has an opening pattern that selectively covers a part of the upper barrier metal film BM6b. Next, anisotropic etching treatment is performed using the resist pattern as a mask to remove the upper barrier metal film BM6b, the conductive film CF6, and the lower barrier metal film BM6a exposed from the resist pattern. The remaining upper barrier metal film BM6b, conductive film CF6, and lower barrier metal film BM6a are formed as the plurality of wirings M6. Thereafter, the resist pattern is removed by ashing treatment.

[0074] <Main features of the semiconductor device> <<Formation position of the resistor element RS1>> The resistor element RS1 can theoretically be formed between each wiring layer. However, in Embodiment 1, the resistor element RS1 is formed between the wiring layer WL6 and the wiring layer WL5. The reason therefor will be described below with reference to FIGS. 15 and 16. To form the resistor element RS1 between each wiring layer, it is necessary to satisfy the following first condition, second condition, and third condition.

[0075] As shown in FIG. 15, the first condition is that the over-etching amount OE1 of the anisotropic etching treatment performed when forming the resistor element RS1 is less than the distance L5r. That is, the over-etching during patterning of the conductive film CFr does not reach the wiring M5.

[0076] Referring back to FIG. 12, the resistive element RS1 is formed by performing anisotropic etching on the conductive film CFr using the resist pattern RP3 as a mask. At this time, since the etching uniformity is different within the same semiconductor substrate SUB, over-etching is performed so that unnecessary conductive film CFr is not left. Therefore, a part of the interlayer insulating film IL5a exposed from the resistive element RS1 is also etched. The over-etching amount OE1 is, for example, 100 nm or more and 120 nm or less.

[0077] The second condition is that the over-etching amount OE2 of the anisotropic etching process performed when forming the wiring M6 is less than the distance L6r. That is, the over-etching during the patterning of the wiring M6 does not reach the conductive film CFr.

[0078] For example, the wiring M6 is formed by performing anisotropic etching using the resist pattern RP4 as a mask. Here, over-etching is performed so that unnecessary lower barrier metal film BM6a or the like is not left. Therefore, a part of the interlayer insulating film IL5b exposed from the wiring M6 is also etched. The over-etching amount OE2 is, for example, 60 nm or more and 80 nm or less.

[0079] As shown in FIG. 16, the third condition is that the variation in the polishing amount of the polishing process by the CMP method is taken into account. After forming the interlayer insulating film, a polishing process is performed on the upper surface of the interlayer insulating film, but the polishing uniformity is different within the same semiconductor substrate SUB. Therefore, it is necessary to consider the over-polishing amount when polished excessively more than the set value.

[0080] Note that in order to form the resistive element RS1 between each wiring layer, it is necessary to divide the formation of the interlayer insulating film into two times, such as the interlayer insulating film IL5a and the interlayer insulating film IL5b. Therefore, since the polishing process by the CMP method is performed twice, it is necessary to calculate the over-polishing amount for two times.

[0081] When performing a polishing process on the upper surfaces of the interlayer insulating film IL5a and the interlayer insulating film IL5b, the excessive polishing amount 1 and the excessive polishing amount 2 are calculated. For example, when the distance L5r is set to 230 nm, 15% of the distance L5r is calculated as the excessive polishing amount 1 (34.5 nm). Also, when the distance L6r is set to 250 nm, 15% of the distance L6r is calculated as the excessive polishing amount 2 (37.5 nm).

[0082] Thus, considering the first condition, the second condition, and the third condition, it is necessary to consider approximately 250 nm as the minimum manufacturing margin between the resistance element RS1 and the wiring layer WL6 and between the resistance element RS1 and the wiring layer WL5, respectively.

[0083] As a comparative example, consider the case where the resistance element RS1 is formed between the wiring layer WL4 and the wiring layer WL5. As the semiconductor device is miniaturized, the value of the distance L45 becomes smaller. Therefore, there may be a case where the resistance element RS1 cannot be formed between the wiring layer WL4 and the wiring layer WL5. Also, even if the resistance element RS1 could be formed, the distances between the resistance element RS1 and the wiring layer WL4 and between the resistance element RS1 and the wiring layer WL5 are short. Therefore, when unexpected defects other than the defects related to the first condition, the second condition, and the third condition occur, it is difficult to make design changes, etc., and it is difficult to take countermeasures. That is, in the comparative example, it is difficult to stably manufacture the resistance element RS1.

[0084] As described above, in the first embodiment, the resistance element RS1 is formed between the wiring layer WL5 and the wiring layer WL6, which have the longest distance L56 among the wiring layers. Since the resistance element RS1 can be formed while ensuring a sufficient manufacturing margin, the characteristics of the resistance element RS1 can be maintained, and the reliability of the semiconductor device can be ensured.

[0085] <<Formation position of the capacitive element MIM>> FIG. 17 shows data obtained by the inventors of the present application regarding the relative accuracy of a plurality of capacitor elements MIM formed on the same semiconductor substrate SUB. The vertical axis of the graph in FIG. 17 indicates the Pelgrom coefficient of the capacitor element MIM. The smaller the value of the Pelgrom coefficient, the better the relative accuracy and the smaller the variation in characteristics among the plurality of capacitor elements MIM. Note that the error range was calculated as 3σ of the variation occurring within the plurality of semiconductor substrates SUB.

[0086] The upper surface of the upper barrier metal film is not a completely flat surface, but has irregularities formed thereon. The generation of these irregularities is due not only to the accuracy of the film formation process of the upper barrier metal film but also to the irregular shape of the upper surface of the underlying film. Therefore, the fewer the irregularities generated in the underlying film, the less likely the irregularities will occur in the film that becomes the upper layer. Further, since the generation of irregularities in the upper barrier metal film is small, the generation of irregularities in the insulating film IF1 and the upper electrode UE formed on the upper barrier metal film is also reduced. Therefore, the relative accuracy of the capacitor element MIM can be improved.

[0087] When comparing Sample 5 and Sample 4, the thicknesses of the upper barrier metal films are the same as each other, and the thicknesses of the conductive films are the same as each other, but the thickness of the lower barrier metal film of Sample 4 is larger than the thickness of the lower barrier metal film of Sample 5. Therefore, the larger the thickness of the lower barrier metal film, the fewer the irregularities generated in the conductive film and the upper barrier metal film that become the upper layer, and the relative accuracy of the capacitor element MIM is improved.

[0088] Also, when comparing Sample 5 and Sample 3, the thicknesses of the upper barrier metal films are the same as each other, and the thicknesses of the lower barrier metal films are the same as each other, but the thickness of the conductive film of Sample 3 is smaller than the thickness of the conductive film of Sample 5. Therefore, the smaller the thickness of the conductive film, the fewer the irregularities generated in the upper barrier metal film, and the relative accuracy is improved. Note that the result of Sample 2 was almost the same as the result of Sample 3.

[0089] Therefore, as can be seen by comparing Sample 5 with Sample 1, the smaller the thickness of the conductive film and the larger the thickness of the lower barrier metal film, the more the relative accuracy of the capacitive element MIM can be improved. For example, by setting the thickness of the conductive film CF4 to 230 nm or less and the thickness of the lower barrier metal film BM4a to 40 nm or more, the relative accuracy of the capacitive element MIM can be improved more effectively.

[0090] The thickness of each wiring is mainly the thickness of a conductive film such as an aluminum film or an aluminum alloy film. Therefore, in Embodiment 1, a conductive film CF4 having a thickness smaller than the thickness of the conductive film CF5 and the thickness of the conductive film CF6 is applied. That is, among the wirings formed in the multilayer wiring layer, the wiring M4 having the smallest thickness is used as the lower electrode BE of the capacitive element MIM. Thereby, since the relative accuracy of the capacitive element MIM can be improved, the performance of the semiconductor device can be improved.

[0091] <<Other Features Regarding the Formation Positions of the Resistive Element RS1 and the Capacitive Element MIM>>

[0092] The resistive element RS1 and the capacitive element MIM are arranged so as not to overlap each other in plan view. In other words, the resistive element RS1 is arranged so as not to be formed directly above the capacitive element MIM.

[0093] When forming the interlayer insulating film IL4, the upper surface of the interlayer insulating film IL4 is planarized by a polishing process using the CMP method. However, directly above the capacitive element MIM, the upper surface of the interlayer insulating film IL4 bulges compared to directly above the other wiring M4 by the thickness of the insulating film IF1 and the thickness of the upper electrode UE. Therefore, even when a polishing process is performed, the upper surface of the interlayer insulating film IL4 located directly above the capacitive element MIM may not be completely planarized.

[0094] In that case, directly above the capacitive element MIM, the raised shape on the upper surface of the interlayer insulating film IL4 may be reflected in the interlayer insulating film IL5a, and the upper surface of the interlayer insulating film IL5a may also have a raised shape. When the resistive element RS1 is formed on the upper surface of the interlayer insulating film IL5a including such a raised shape, it becomes difficult to form the resistive element RS1 with a uniform thickness. Then, there is a possibility that the characteristics of the resistive element RS1 may vary. If the resistive element RS1 and the capacitive element MIM are formed so as not to overlap each other in plan view, such a possibility can be eliminated.

[0095] Note that the resistive element RS1 and the capacitive element MIM are preferably formed between different wiring layers. For example, consider the case where both the resistive element RS1 and the capacitive element MIM are formed in the wiring layer WL5. If the resistive element RS1 is formed first, since the wiring M4 that functions as the lower electrode BE of the capacitive element MIM is covered by the interlayer insulating film IL5a, additional processes such as partially opening a part of the wiring M4 are required, and the manufacturing process becomes complicated.

[0096] On the other hand, if the capacitive element MIM is formed first, it is necessary to completely cover the upper electrode UE of the capacitive element MIM with the interlayer insulating film IL5a. This is because if the upper electrode UE is exposed from the interlayer insulating film IL5a, the upper electrode UE will be scraped off during the patterning of the resistive element RS1. Then, it is necessary to increase the distance L5r, but as the distance L5r increases, the distance L6r decreases, so there is a possibility that the resistive element RS1 may be exposed to over-etching. In order to eliminate such a possibility, if the distance L6r is increased, the distance L56 between the wiring layer WL6 and the wiring layer WL5 becomes longer, so it is difficult to miniaturize the semiconductor device. Also, when forming the via V5, the depth of the hole becomes large and the aspect ratio becomes high, so it becomes difficult to normally embed a tungsten film or the like inside the hole.

[0097] (Embodiment 2) In the following description, the differences from Embodiment 1 will be mainly described, and the description of the points overlapping with Embodiment 1 will be omitted.

[0098] As shown in FIG. 18, in the second embodiment, the conductive film CFm that functioned as the upper electrode UE in the first embodiment is caused to function as a resistance element RS2 electrically connected to a different wiring M5. The resistance element RS2 is connected to one via V4, and one via V4 is connected to one wiring M5. Further, the resistance element RS2 is connected to the other via V4, and the other via V4 is connected to the other wiring M5.

[0099] As shown in FIG. 17, similar to the capacitor element MIM, the relative accuracy of the resistance element RS2 can be improved as the thickness of the conductive film is smaller and the thickness of the lower barrier metal film is larger. Therefore, in the second embodiment, the insulating film IF1 and the resistance element RS2 are formed on the wiring M4 having the smallest thickness among the wirings formed in the multilayer wiring layer. Thereby, the relative accuracy of the resistance element RS2 can be improved, and the performance of the semiconductor device can be improved.

[0100] The resistance element RS2 is also formed between the wiring layer WL5 and the wiring layer WL4, similar to the upper electrode UE. However, the wiring M4 on which the resistance element RS2 is formed is different from the wiring M4 on which the upper electrode UE is formed. In other words, the resistance element RS2 is positioned so as not to overlap the capacitor element MIM in plan view. Further, the resistance element RS2 and the upper electrode UE can be formed in the same manufacturing process. Therefore, an increase in manufacturing cost can be suppressed. Note that the thicknesses of the resistance element RS2 and the upper electrode UE are the same, but the lengths, planar shapes, and planar areas of the resistance element RS2 and the upper electrode UE are different from each other.

[0101] Also, in the first embodiment, the resistance element RS1 and the capacitor element MIM were formed so as not to overlap each other in plan view. For the same reason as in the first embodiment, the resistance element RS1 and the resistance element RS2 are formed so as not to overlap each other in plan view.

[0102] (Third Embodiment) In the following description, the differences from the first embodiment will be mainly described, and the description of the points overlapping with the first embodiment will be omitted.

[0103] In Embodiment 1, wiring M4 is used as the lower electrode BE, and the upper electrode UE and the insulating film IF1 are formed between the wiring layer WL5 and the wiring layer WL4. As shown in FIG. 19, in Embodiment 3, wiring M3 is used as the lower electrode BE, and the upper electrode UE and the insulating film IF1 are formed between the wiring layer WL4 and the wiring layer WL3.

[0104] In other words, the distance between the resistance element RS1 and the capacitance element MIM in Embodiment 3 is longer than the distance between the resistance element RS1 and the capacitance element MIM in Embodiment 1.

[0105] The heat generated in the resistance element RS1 may vary the characteristics of the capacitance element MIM. Also, the heat generated in the capacitance element MIM may vary the characteristics of the resistance element RS1. By increasing the distance between the resistance element RS1 and the capacitance element MIM, the variation of each characteristic can be suppressed.

[0106] Note that wiring M2 may be used as the lower electrode BE, and the upper electrode UE and the insulating film IF1 may be formed between the wiring layer WL3 and the wiring layer WL2. Also, wiring M1 may be used as the lower electrode BE, and the upper electrode UE and the insulating film IF1 may be formed between the wiring layer WL2 and the wiring layer WL1. That is, it is sufficient that there is one or more other wiring layers between the wiring layer in which the wiring to which the resistance element RS1 is electrically connected is formed and the wiring layer in which the lower electrode BE of the capacitance element MIM is formed.

[0107] Also, regarding the resistance element RS2 of Embodiment 2, the same concept as the capacitance element MIM of Embodiment 3 can be applied. That is, the resistance element RS2 may be formed between the wiring layer WL4 and the wiring layer WL3, between the wiring layer WL3 and the wiring layer WL2, or between the wiring layer WL2 and the wiring layer WL1.

[0108] As described above, the present invention has been specifically described based on the embodiments for carrying out the present invention. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist thereof.

Explanation of Symbols

[0109] 1Q transistor BE lower electrode BM4a, BM5a, BM6a lower barrier metal films BM4b, BM5b, BM6b upper barrier metal films CF4, CF5, CF6, CFm, CFr conductive films IF1 insulating film IL0, IL1, IL2, IL3, IL4, IL5a, IL5b, IL6 interlayer insulating films LV1, LV2 local vias M1, M2, M3, M4, M5, M6 wirings MIM capacitor element PG plug RP1, RP2, RP3, RP4 resist patterns RS1, RS2 resistance elements SUB semiconductor substrate UE upper electrode V1, V2, V3, V4, V5 vias WL1, WL2, WL3, WL4, WL5, WL6 wiring layers

Claims

1. A semiconductor substrate, A multilayer wiring layer formed on the semiconductor substrate and having a first wiring layer and a second wiring layer positioned above the first wiring layer, A first wiring formed in the first wiring layer, A second wiring formed in the second wiring layer and having a thickness greater than that of the first wiring, A third wiring formed in the second wiring layer and having a thickness greater than that of the first wiring, A first insulating film formed between the first wiring layer and the second wiring layer and formed on the first wiring, A first conductive film formed between the first wiring layer and the second wiring layer and formed on the first insulating film, A second conductive film formed on the second wiring and the third wiring, comprising The first wiring, the first insulating film, and the first conductive film function as a capacitive element, The second conductive film functions as a first resistive element electrically connected to the second wiring and the third wiring, a semiconductor device.

2. In the semiconductor device according to Claim 1, A first interlayer insulating film covering the second wiring and the third wiring, A first via formed in the first interlayer insulating film so as to be connected to the second wiring, A second via formed in the first interlayer insulating film so as to be connected to the third wiring, further comprising The second conductive film is formed on the first interlayer insulating film so as to be connected to the first via and the second via, a semiconductor device.

3. In the semiconductor device according to Claim 2, The multilayer wiring layer has a third wiring layer positioned above the second wiring layer, The semiconductor device is A second interlayer insulating film formed on the first interlayer insulating film so as to cover the second conductive film, A fourth wiring formed in the third wiring layer, formed on the second interlayer insulating film, and having a thickness greater than the thickness of the second wiring, Further comprising, A semiconductor device in which, in a direction perpendicular to the upper surface of the semiconductor substrate, the distance between the third wiring layer and the second wiring layer is longer than the distance between the second wiring layer and the first wiring layer.

4. In the semiconductor device according to claim 3, The distance between the third wiring layer and the second wiring layer is 500 nm or more, a semiconductor device.

5. In the semiconductor device according to claim 4, The second conductive film includes at least one of a SiCr film, a SiCrC film, a NiCr film, a TiN film, and a TaN film, a semiconductor device.

6. In the semiconductor device according to claim 1, The first wiring has a first barrier metal film, a third conductive film formed on the first barrier metal film, and a second barrier metal film formed on the third conductive film, The thickness of the first barrier metal film is 40 nm or more, The thickness of the third conductive film is 230 nm or less, The thickness of the second barrier metal film is 50 nm or more, a semiconductor device.

7. In the semiconductor device according to claim 6, The first barrier metal film includes a TiN film and a Ti film, The third conductive film includes an Al film or an Al alloy film, The second barrier metal film includes a TiN film, The first conductive film includes a TiN film, a semiconductor device.

8. In the semiconductor device according to claim 6, The fifth wiring and the sixth wiring, which are formed in the second wiring layer and have a thickness greater than the thickness of the first wiring, The fourth conductive film formed between the first wiring layer and the second wiring layer, and further comprising, The semiconductor device, wherein the fourth conductive film functions as a second resistance element electrically connected to the fifth wiring and the sixth wiring.

9. In the semiconductor device according to claim 1, The semiconductor device, wherein the first resistance element and the capacitive element are arranged so as not to overlap each other in plan view.

10. In the semiconductor device according to claim 1, The semiconductor device, wherein at least one wiring layer is arranged between the first wiring layer and the second wiring layer.

11. (a) A step of preparing a semiconductor substrate, (b) After the step (a), a step of forming a first interlayer insulating film on the semiconductor substrate, (c) After the step (b), a step of forming a first wiring, a first insulating film, and a first conductive film sequentially stacked on the first wiring on the first interlayer insulating film, (d) After the step (c), a step of forming a second interlayer insulating film on the first interlayer insulating film so as to cover the first wiring, the first insulating film, and the first conductive film, (e) After the step (d), a step of forming a second wiring and a third wiring on the second interlayer insulating film, (f) After the step (e), a step of forming a third interlayer insulating film on the second interlayer insulating film so as to cover the second wiring and the third wiring, (g) After the step (f), a step of forming a first via in the third interlayer insulating film so as to connect to the second wiring and a second via in the third interlayer insulating film so as to connect to the third wiring, (h) After the step (g), a step of forming a second conductive film on the third interlayer insulating film so as to connect to the first via and the second via, comprising the thickness of the first wiring is smaller than the thickness of the second wiring and the thickness of the third wiring, the first wiring, the first insulating film, and the first conductive film function as a capacitor element, the second conductive film functions as a first resistor element electrically connected to the second wiring and the third wiring, a method of manufacturing a semiconductor device.

12. In the method of manufacturing a semiconductor device according to claim 11, (i) After the step (h), a step of forming a fourth interlayer insulating film on the third interlayer insulating film so as to cover the second conductive film, (j) After the step (i), a step of forming a fourth wiring on the fourth interlayer insulating film, further comprising The sum of the thickness of the portion of the third interlayer insulating film located on the second wiring or the third wiring and the thickness of the portion of the fourth interlayer insulating film located on the second wiring or the third wiring is greater than the thickness of the portion of the second interlayer insulating film located on the first wiring, a method of manufacturing a semiconductor device.

13. In the method of manufacturing a semiconductor device according to claim 12, (k) A step of performing a first polishing process by CMP on the upper surface of the first interlayer insulating film between the step (b) and the step (c), (l) A step of performing a second polishing process by CMP on the upper surface of the second interlayer insulating film between the step (d) and the step (e), (m) A step of performing a third polishing process by CMP on the upper surface of the third interlayer insulating film between the step (f) and the step (g), (n) A step of performing a fourth polishing process by CMP on the upper surface of the fourth interlayer insulating film between the step (i) and the step (j), further comprising, a method of manufacturing a semiconductor device.

14. In the method of manufacturing a semiconductor device according to claim 13, In the method for manufacturing a semiconductor device, the sum of the thickness of the portion of the third interlayer insulating film located on the second wiring or the third wiring and the thickness of the portion of the fourth interlayer insulating film located on the second wiring or the third wiring is 500 nm or more.

15. In the method for manufacturing a semiconductor device according to claim 13, the step (j) is (j1) a step of sequentially forming a first barrier metal film, a third conductive film, and a second barrier metal film on the fourth interlayer insulating film; (j2) a step of forming the fourth wiring by selectively patterning the first barrier metal film, the third conductive film, and the second barrier metal film after the step (j1); and in the step (i2), an anisotropic etching process is used, and a part of the fourth interlayer insulating film exposed from the fourth wiring is also etched. The method for manufacturing a semiconductor device.

16. In the method for manufacturing a semiconductor device according to claim 13, the step (h) is (h1) a step of forming the second conductive film on the third interlayer insulating film; (h2) a step of forming the first resistor element connected to the first via and the second via by selectively patterning the second conductive film after the step (h1); and in the step (h2), an anisotropic etching process is used, and a part of the third interlayer insulating film exposed from the first resistor element is also etched. The method for manufacturing a semiconductor device.

17. In the method for manufacturing a semiconductor device according to claim 11, the step (c) is (c1) a step of sequentially forming a third barrier metal film, a fourth conductive film, a fourth barrier metal film, the first insulating film, and the first conductive film on the first interlayer insulating film; (c2) A step of selectively patterning the first insulating film and the first conductive film after the step (c1); (c3) A step of forming the first wiring by selectively patterning the third barrier metal film, the fourth conductive film, and the fourth barrier metal film so that the first insulating film and the first conductive film remain on the fourth barrier metal film after the step (c2); having The thickness of the third barrier metal film is 40 nm or more; The thickness of the fourth conductive film is 230 nm or less; A method of manufacturing a semiconductor device, wherein the thickness of the fourth barrier metal film is 50 nm or more.

18. In the method of manufacturing a semiconductor device according to claim 11, (o) A step of forming a third via and a fourth via in the second interlayer insulating film between the step (d) and the step (e); further comprising In the step (c), a fifth wiring, a second insulating film, and a fifth conductive film sequentially stacked on the fifth wiring are formed on the first interlayer insulating film; In the step (d), the second interlayer insulating film is formed so as to also cover the fifth wiring, the second insulating film, and the fifth conductive film; In the step (e), a sixth wiring connected to the third via and a seventh wiring connected to the fourth via are formed on the second interlayer insulating film; The third via and the fourth via are formed so as to be connected to the fifth conductive film; A method of manufacturing a semiconductor device, wherein the fifth conductive film functions as a second resistor element electrically connected to the sixth wiring and the seventh wiring.

19. In the method of manufacturing a semiconductor device according to claim 11, A method of manufacturing a semiconductor device, wherein the first resistor element and the capacitor element are arranged so as not to overlap each other in plan view.

20. In the method of manufacturing a semiconductor device according to claim 11, (p) A step of forming an eighth wiring on the second interlayer insulating film between the step (d) and the step (e); (q) A step of forming a fifth interlayer insulating film on the second interlayer insulating film so as to cover the eighth wiring between the step (p) and the step (e); further comprising: In the step (e), the second wiring and the third wiring are formed on the fifth interlayer insulating film; In the step (f), the third interlayer insulating film is formed on the fifth interlayer insulating film; A method of manufacturing a semiconductor device, wherein the thickness of the eighth wiring is smaller than the thicknesses of the second wiring and the third wiring.

Images