Delta-sigma a / d converter and battery monitoring device

Abstract

To provide a delta-sigma A / D converter and a battery monitoring device capable of reducing A / D conversion errors caused by chopping.SOLUTION: A delta-sigma A / D converter 5 uses an operational amplifier 11 of a differential configuration. A first integrator 1 has a differential configuration and includes a pair of feedback capacitors Cf1 feedback-connecting a differential input terminal and a differential output terminal of the operational amplifier 11. The first integrator 1 is provided with a switched capacitor that includes a chopping switch 14 capable of reversing the polarity between the differential input terminal of the operational amplifier 11 and the pair of feedback capacitors Cf1. A switch φ3 resets a potential of the differential input terminal of the operational amplifier 11 at a timing when the feedback capacitors Cf1 and the differential input terminal of the operational amplifier 11 are disconnected by the chopping switch 14.SELECTED DRAWING: Figure 1A

Description

Technical Field

[0001] The present invention relates to a delta-sigma A / D converter and a battery monitoring device using the A / D converter.

Background Art

[0002] For example, Patent Document 1 proposes a technique for reducing A / D conversion errors due to chopping by making chopping random.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The technique described in this Patent Document 1 modulates the A / D conversion error spectrum due to chopping but does not eliminate the error. Also, as the chopping frequency decreases, flicker noise does not reach the high-frequency region and affects the low-frequency region as random noise. Further, a separate circuit for generating pseudo-random numbers is required, increasing the area and current consumption.

[0005] The present invention has been made in view of the above circumstances, and an object thereof is to provide a delta-sigma A / D converter capable of reducing A / D conversion errors due to chopping and a battery monitoring device using the A / D converter.

Means for Solving the Problems

[0006] According to the delta-sigma A / D converter using the differential configuration operational amplifier described in claim 1, it includes a pair of feedback capacitors that are in a differential configuration and have the differential input and output terminals of the operational amplifier connected in feedback respectively, and a switched capacitor using a chopping switch with a polarity that can be reversed between the differential input terminal of the operational amplifier and the pair of feedback capacitors, which is used as a first integrator. Also, a switch is provided to reset the potential of the differential input terminal of the operational amplifier at the timing when the feedback capacitor and the differential input terminal of the operational amplifier are disconnected by the chopping switch in the first integrator.

[0007] According to the delta-sigma A / D converter described in claim 1, at the timing when the feedback capacitor and the differential input terminal of the operational amplifier are disconnected by the chopping switch, the switch resets the potential of the differential input terminal of the operational amplifier. Therefore, the A / D conversion error caused by chopping occurring at the differential input terminal of the operational amplifier can be cleared, and the A / D conversion error caused by chopping can be reduced.

Brief Description of the Drawings

[0008]

Figure 1A

Figure 1B

Figure 2

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Figure 20

Embodiments for Carrying Out the Invention

[0009] Hereinafter, several embodiments of the data generation device and the battery monitoring device will be described with reference to the drawings. For the embodiments described later, the same reference numerals or similar reference numerals may be assigned to the components of the previously described embodiments, and the description may be omitted

[0010] (First Embodiment) FIG. 1A shows a part of the second-order delta-sigma A / D converter 5 of the CIFF type according to this embodiment. FIG. 1B shows the switches φ3 around the input and output of the operational amplifier 11 shown in FIG. 1A, which are labeled as switches Sip, Sim, and So for distinction.

[0011] FIG. 1A extracts and shows a part of the block configuration of the delta-sigma A / D converter 5 shown in FIG. 2. The delta-sigma A / D converter 5 shown in FIG. 2 has a first integrator 1 and a second integrator 2 connected in series. The adder 3b shown in FIG. 2 adds the output of the first integrator 1 multiplied by a gain 3a by 2 and the output of the second integrator 2, and outputs it to the quantizer 4. The output of the quantizer 4 is fed back so as to be subtracted from the input signal via the feedback D / A converter 13.

[0012] The configuration shown in FIG. 2 includes a gain 3a of 2, an adder 3b, a delay element 3c, and a gain 3d of -2. However, the configuration of FIG. 2 is equivalent to that configured by arranging the pseudo-addition circuit 3 on the input side of the second integrator 2 as shown in FIG. 3. The pseudo-addition circuit 3 adds the output of the first integrator 1, the output of the first integrator 1 multiplied by a gain 3a by 2, and the output multiplied by a gain 3d of -2 via the delay element 3c.

[0013] The delta-sigma A / D converter 5 partially shown in FIG. 1A is circuitized in a differential configuration based on the block configuration shown in FIG. 3. The delta-sigma A / D converter 5 has a configuration as a switch capacitor that performs chopping on the input side of the first integrator 1 and charges and discharges each capacitor (not shown). The delta-sigma A / D converter 5 operates with 11 types of clock signals shown in FIG. 4. Note that, for ease of understanding the description, in the following description, the notations of the switches φ1, φ1c, φ1d, φ2, φ2a, φ2b, and φ3 shown in FIG. 1 may also be used as descriptions of the phases (clock signals) of the clocks as they are. φ1: Master clock signal φ1+: Output if the output of the quantizer 4 is L φ1-: If the output of the quantizer 4 is H, the output φ1c: The odd-numbered clock of φ1 φ1d: The even-numbered clock of φ1 φ2: The inverted-phase clock signal of φ1 φ2a, φ2c: The odd-numbered clocks of φ2 φ2b, φ2d: The even-numbered clocks of φ2 φ3: Reset signal (synchronized with the master clock) Note that regarding the odd-numbered and even-numbered, they are relative when the left end of φ1 of the master clock shown in FIG. 4 is, for example, set to "1". Also, for easier understanding of the explanation, note that the switches described below, which are turned on by the respective clock signals above, may be described with the type of clock as a symbol.

[0014] As shown in FIG. 1, the first integrator 1 includes an operational amplifier 11 with a fully differential configuration. A series circuit of a switch φ1, a capacitor Cs1 which is a sampling capacitance element, and a chopping switch 12 is connected between the nodes of the positive input voltage VINP and the negative input voltage VINM and the differential input terminals of the operational amplifier 11. The chopping switch 12 is composed of two switches φ2a and two switches φ2b. The two switches φ2a directly connect between the node of the positive input voltage VINP and the negative input terminal of the operational amplifier 11, and between the node of the negative input voltage VINM and the positive input terminal of the operational amplifier 11, respectively. The two switches φ2b are connected so as to cross between the nodes of the input voltages VINP and VINM and the differential input terminals of the operational amplifier 11.

[0015] At the common connection point of the capacitor Cs1 and the chopping switch 12, one end of the capacitor Cd1 that constitutes the D / A converter 13 and one end of the switch φ1 are connected. To the other end of the capacitor Cd1, one ends of the switches φ1-, φ1+ and φ2 that constitute the D / A converter 13 are commonly connected, and the other ends of these switches φ1-, φ1+ and φ2 and the switch φ1 are connected to the reference voltages Vr-, Vr+ and the reference potential VCMO, respectively. The reference potential VCMO is the output common-mode potential, and the magnitude relationship of these voltages is set to (Vr- < VCMO < Vr+).

[0016] The chopping switch 12 can invert the polarity between the nodes of the input voltages VINP and VINM and the differential input terminals of the operational amplifier 11. Also, the chopping switch 14 can invert the polarity between the differential input terminals of the input-side operational amplifier 11 and the pair of feedback capacitors Cf1. There is an input parasitic capacitance Ci between the common connection point between the common connection point of the switch φ2a that constitutes the chopping switches 12 and 14 and the differential input terminals of the operational amplifier 11 and the node of the reference potential VCMO. To suppress the influence of the A / D conversion error based on this parasitic capacitance Ci, as shown in FIG. 1B, switches Sim and Sip(φ3) are connected between the negative input terminal of the operational amplifier 11 and the node of the input common potential VCMI, and between the positive input terminal and the node of the input common potential VCMI, respectively.

[0017] As shown in FIG. 1A, a series circuit of a chopping switch 14, a feedback capacitor Cf1, and a chopping switch 15 is connected between the input side and the output side of the operational amplifier 11. These chopping switches 14 and 15 are also composed of two switches φ2a and two switches φ2b, similar to the chopping switch 12. The switch φ2a is directly connected between the negative input terminal and the positive output terminal, and between the positive input terminal and the negative output terminal. The switch φ2b is cross-connected so that the polarities of the input side and the output side are reversed. The chopping switch 15 corresponds to the output-side chopping switch. Either the positive-side or negative-side output signal of the first integrator 1 corresponds to the first output signal, and the other corresponds to the second output signal. A switch So(φ3) is connected between the differential output terminals of the operational amplifier 11, and it is provided to suppress the influence of the parasitic capacitance generated around the operational amplifier 11.

[0018] A second integrator 2 with a pseudo-addition circuit 3 arranged on the input side is configured at the subsequent stage of the first integrator 1. Between the output line 16 of the first integrator 1 and the negative input terminal of the operational amplifier 18 with a fully differential configuration that constitutes the second integrator 2, a parallel circuit of a switch φ2, a capacitor Cs2, and a Cas, and a series circuit of a switch φ1 that constitute one polarity side of the pseudo-addition circuit 3 are connected. The configuration between the output line 17 of the first integrator 1 and the positive input terminal of the operational amplifier 18 is the same.

[0019] A series circuit of a switch φ2c and a capacitor Caa, and a series circuit of a switch φ2d and a capacitor Cab are connected between the output line 17 and the common connection point of the capacitor Cs2, the Cas, and the switch φ1. Switches φ1c and φ1d are respectively connected between the common connection point of each series circuit and the reference voltage. The configuration on the side connected to the output line 16 is the same. The switch φ2 is connected between the common connection point of the capacitor Cs2, the Cas, and the switch φ1 and the reference voltage. The capacitances of the capacitors Cas, Caa, and Cab are set to be equal. The capacitors Cas, Caa, and Cab respectively correspond to the addition, odd subtraction, and even operation capacitance elements.

[0020] A feedback capacitor Cf2 is connected between the differential input terminal and the differential output terminal of the operational amplifier 18 that constitutes the second integrator 2, and the differential output terminal is connected to the input terminal of the quantizer 4. The pseudo-addition circuit 3 performs addition as follows while utilizing the configuration of the second integrator 2. Thus, the delta-sigma A / D converter 5 is configured.

[0021] Next, the operation of this embodiment will be described. First, the operation of the first integrator 1 will be described. In this embodiment, the operation when the input side of the operational amplifier 11 is chopped by the chopping switches 12 and 14 each time will be described. Hereinafter, for ease of understanding the operation, the illustration of each switch is appropriately omitted, and the part of the switch that turns on according to each clock is shown by a solid line. In this embodiment, four phases are repeatedly executed by generating a clock that cyclically turns on the switches φ1 → φ2a → φ1 → φ2b →....

[0022] <φ1: Sampling phase> In the sampling phase shown on the left side of FIG. 5, a sampling process is performed in which the capacitor Cs1 is charged by the input voltages VINP and VINM. Also, simultaneously with the on-timing of the switch φ1, the switches φ1- and φ1+ are alternately turned on and off according to the result of the output of the quantizer 4, and the capacitor Cd1 of the D / A converter 13 is charged and discharged. Also simultaneously, the feedback capacitor Cf1 and the input terminal of the operational amplifier 11 are disconnected by the chopping switch 14. Further, when the switches Sim and Sip are turned on, the differential input terminals of the operational amplifier 11 are short-circuited, and the differential input terminals are connected to the input common node, and the potentials of both input terminals are reset to the input common potential VCMI.

[0023] <φ2a: Integration phase a> Next, in the integration phase a shown in the upper right of FIG. 5, the feedback capacitor Cf1 and the differential input terminals of the operational amplifier 11 are directly connected by the chopping switch 14, and the charges of the capacitors Cs1 and Cd1 are integrated into the feedback capacitor Cf1.

[0024] <φ1: Sampling Phase> Next, return to the sampling phase shown on the left side of FIG. 5. At this time as well, similar to the above, the capacitor Cs1 is charged by the input voltages VINP and VINM and sampling is performed. Also, simultaneously with the on-timing of the switch φ1, according to the result of the output of the quantizer 4, the switches φ1- and φ1+ are alternately turned on and off and the capacitor Cd1 of the D / A converter 13 is charged and discharged. Also, the feedback capacitor Cf1 and the input terminals of the operational amplifier 11 are disconnected by the chopping switch 14. Further, by turning on the switches Sim and Sip, the differential input terminals of the operational amplifier 11 are short-circuited and the potentials of both of these input terminals are stabilized at the input common potential VCMI and the potentials of both of the differential input terminals are reset.

[0025] Since the switches Sim and Sip (φ3) shown in FIG. 1B are configured to set the differential input terminals of the operational amplifier 11 to the respective predetermined input common potential VCMI, the potentials of the positive input terminal and the negative input terminal can be stably determined when resetting. Also, since the switch So is configured to make the differential output terminals of the operational amplifier 11 have the same potential by connecting between the differential output terminals, the differential output terminals can be reset to stable potentials respectively.

[0026] <φ2b: Integration Phase b> Next, shift to the integration phase b shown in the lower right of FIG. 5. At this time, with the polarities of the input and output terminals of the operational amplifier 11 switched to cross-connection by the chopping switches 12, 14, and 15, the charges of the capacitors Cs1 and Cd1 are integrated into the feedback capacitor Cf1.

[0027] In this way, the four phases are periodically repeated. Each time the first integrator 1 passes through the integration phase a or b once, it resets the voltage at the input terminal of the operational amplifier 11 to the input common potential VCMI at φ1 of the sampling phase. As a result, the first integrator 1 can perform integration without accumulating errors as much as possible.

[0028] Next, the operations of the pseudo-addition circuit 3 and the second integrator 2 will be described. The operation of the second integrator 2 shown in FIGS. 6 to 9 is such that the four phases are repeatedly executed by the clock circulating as φ1c → φ2c → φ1d → φ2d → φ1c →.... Also, the explanation with positive and negative polarities is given for the upper side in the figure which is one side of the differential configuration.

[0029] <φ1c: First Phase> In the first phase shown in FIG. 6, the charges of the capacitors Caa, Cas, and Cs2 are added to the feedback capacitor Cf2.

[0030] <φ2c: Second Phase> In the second phase shown in FIG. 7, the capacitors Cas and Cs2 are charged and sampled by the positive output of the first integrator 1, and the capacitor Caa is charged and sampled by the negative output of the first integrator 1.

[0031] <φ1d: Third Phase> In the third phase shown in FIG. 8, the charges of the capacitors Cab, Cas, and Cs2 are added to the feedback capacitor Cf2.

[0032] <φ2d: Fourth Phase> In the fourth phase shown in FIG. 9, the capacitors Cas and Cs2 are charged and sampled by the positive output of the first integrator 1, and the capacitor Cab is charged and sampled by the negative output of the first integrator 1.

[0033] As a result of repeating the above operations, the outputs of the addition results in the first and third phases in time series are added with twice the value of the input at that time, and at the timing of the next addition, the twice value added previously is subtracted. In this way, the input voltage is sequentially accumulated and added.

[0034] <Comparative Example> The inventors originally developed a delta-sigma A / D converter 5 that performs A / D conversion processing without considering the parasitic capacitance Ci, but found that an A / D conversion error occurred. As a result of investigating the cause, the inventors found that a parasitic capacitance Ci was generated at the differential input terminals of the operational amplifier 11, and that charges were accumulated in this parasitic capacitance Ci. It was found that when the plus and minus terminals of the input terminal and the output terminal of the operational amplifier 11 were reversely connected by chopping, it would affect the integration value of the first integrator 1 in the first stage as error charges.

[0035] As a comparative example, FIG. 10 shows the configuration of a first integrator 101 that replaces the first integrator 1. This first integrator 101 shows a configuration example when the influence of the parasitic capacitance Ci generated at the input of the operational amplifier 11 is not considered. Compared with the first integrator 1 of this embodiment, the first integrator 101 does not have switches φ3 configured between the differential input terminals and between the differential output terminals of the operational amplifier 11.

[0036] Then, as shown in the left diagram of FIG. 11 for the operation of the first integrator 101, the parasitic capacitance Ci of the input of the operational amplifier 11 has charges C i V ima 、C i V ipa remaining according to the potentials Vima and Vipa generated at the differential input terminals of the operational amplifier 11 during the integration phase a. Therefore, the influence of the error will be integrated in the integration phase b.

[0037] This operation can be expressed by the following mathematical formula. Consider the output error of the first integrator 101 based on the error charge when the phase transitions from φ2a → φ1 → φ2b. When considering in terms of mathematical formulas, for simplicity, the influence of the sampling capacitor Cs1 and the capacitor Cd1 of the D / A converter 13 is omitted, and the initial charge of the feedback capacitor Cf1 is considered to be zero.

[0038] As shown in Fig. 10, when the switch φ3 is not provided and reset is not performed, when passing through the phases of φ2a → φ1 → φ2b, the values of the positive input voltage Vintp and the negative input voltage Vintm of the operational amplifier 11 can be derived as shown in the following formula (1). This value is defined based on the change in the charge storage state of the parasitic capacitance Ci, the capacitor Cs, and the feedback capacitor Cf1.

Equation

[0039] When deriving Vintp - Vintm in this formula (1), it can be derived as shown in formula (2).

Equation

[0040] In this way, the voltage “-Vipa + Vima” at the time of φ2a of the phase remains, and the integration of the error charge Ci / Cf1·(-Vipa + Vima) based on this voltage is repeatedly performed many times, resulting in an integration error and being accumulated. When an error occurs, as shown in Fig. 12, the input level dependency of the delta-sigma A / D converter 5 occurs significantly, and the integral non-linearity error (INL) becomes large.

[0041] Fig. 13 shows the first integrator 1 again when parasitic capacitances Ci and Co are considered for the input and output of the operational amplifier 11. According to the delta-sigma A / D converter 5 of the present embodiment, the differential input terminals and differential output terminals of the operational amplifier 11 can be reset in the sampling phase by using the switch φ3 newly provided at the input and output of the operational amplifier 11. Fig. 14 shows the change in the charge storage states of the parasitic capacitance Ci, the capacitor Cs, and the feedback capacitor Cf1 when the phase changes from φ2a → φ1 → φ2b.

[0042] When this operation is expressed by a mathematical formula, it can be represented as follows. Consider the output error of the first integrator 1 based on the error charge when the phase changes from φ2a → φ1 → φ2b.

[0043] As shown in Fig. 14, when the reset process is executed, the values of the positive input voltage Vintp and the negative input voltage Vintm of the operational amplifier 11 based on the change in the charge storage states of the parasitic capacitance Ci, the capacitor Cs, and the feedback capacitor Cf1 when passing through the phases of φ2a → φ1 → φ2b can be derived as in the following formula (3).

Equation

[0044] When deriving Vintp - Vintm in this formula (3), it can be derived as in the following formula (4). In formula (4), the element of the voltage Vcmi is canceled out, and the voltage "-Vipa + Vima" at the time of φ2a of the aforementioned phase does not remain. As a result, the A / D conversion error due to chopping can be reduced.

Equation

[0045] <Summary of the present embodiment> According to this embodiment, at the timing when the feedback capacitor Cf1 and the input terminal of the operational amplifier 11 are disconnected by the chopping switch 14, the switch φ3 resets the potential of the input terminal of the operational amplifier 11 in the sampling phase. In this embodiment, the positive input terminal and the negative input terminal of the operational amplifier 11 are short-circuited and the voltage is stabilized at the input common potential VCMI for resetting. Therefore, the A / D conversion error due to chopping generated at each terminal of the differential input terminal of the operational amplifier 11 can be cleared, and the A / D conversion error due to chopping can be reduced.

[0046] Also according to this embodiment, since the switches Sim and Sip(φ3) are configured to set the differential input terminals of the operational amplifier 11 to a predetermined input common potential VCMI respectively, the potentials of the positive input terminal and the negative input terminal can be stably determined when resetting. Also, since the switch So is configured to connect between the differential output terminals of the operational amplifier 11 to make the potential between the differential output terminals the same, without separately driving the reference potential VCMO, the differential output terminals can be reset to stable potentials respectively, and it can be configured without the need for a separate drive circuit.

[0047] (Second Embodiment) The second embodiment will be described with reference to FIG. 15. In the second embodiment, the operation in the case where the input side of the operational amplifier 11 is chopped by the chopping switches 12 and 14 every (3 clocks of φ1) will be described. As shown in FIG. 15, the clock is generated as (φ2a for 3 clocks of φ1) → φ3 → (φ2b for 3 clocks of φ1) → φ3 →... of φ1. Even in such a case, the potential of the input terminal of the operational amplifier 11 can be reset at the timing of the clock signal φ3, and the same operational effects as those of the foregoing embodiment can be obtained.

[0048] (Third Embodiment) The third embodiment will be described with reference to FIGS. 16 and 17. FIG. 16 shows a configuration in which the delta-sigma A / D converter 5 of the first embodiment is applied to a battery monitoring IC 21 having a lock-in amplifier type battery impedance measurement function.

[0049] The battery monitoring device 20 is composed of a battery monitoring IC 21 and an external RC filter 26. The battery monitoring IC 21 is configured using an integrated circuit, and measures the impedance of each of the n (for example, 24) unit cells Ce1 to Cen that make up the battery pack 22. A series circuit of a limiting resistor 24, an N-channel MOSFET 25, and a shunt resistor Rsh is connected in parallel to the battery pack 22. The limiting resistor 24 limits the magnitude of the intermittent current flowing by controlling the on / off of the MOSFET 25.

[0050] An RC filter 26 configured by a resistor Ra and a capacitor Ca in a low-pass type is connected to each of the unit cells Ce1 to Cen which are secondary batteries. Both ends of the capacitor Ca constituting the RC filter 26 are connected to the respective input terminals of the delta-sigma A / D converter 5 of the battery monitoring IC 21. Also, both ends of the shunt resistor Rsh are connected to the input terminal of another delta-sigma A / D converter 5 via an RC filter 26 composed of a resistor Rz and a capacitor Cz.

[0051] The battery monitoring IC 21 includes one delta-sigma A / D converter 5, decimation filter 27, multipliers 28I and 28Q, LPFs 29I and 29Q for each of the unit cells Ce1, Ce2... Cen + one for current measurement. In addition, the battery monitoring IC 21 includes a SIN / COS generation unit 31, a PWM / PDM modulator 33, an impedance calculation unit 30, and a register 32. The impedance calculation unit 30 is composed of a digital control circuit and a counter.

[0052] The register 32 is connected to an interface 34 for communicating with the outside. When a write operation is performed on the register 32 from an external host device or the like via the interface 34, the frequency of the SIN / COS generation unit 31 and the modulation method in the PWM / PDM modulator 33 are set. Also, when the register 32 receives a measurement start command via the interface 34, the SIN / COS generation unit 31 starts operating and the PWM / PDM modulator 33 starts operating.

[0053] The PWM / PDM modulator 33 outputs a PWM (Pulse Width Modulation) signal or a PDM (Pulse Density Modulation) signal based on the modulation method set in the register 32 from an external host control device or the like via the interface 34. The PWM / PDM modulator 33 is connected to the gate of the FET 25, and the aforementioned PWM signal or PDM signal is applied. When the FET 25 is turned on, the delta-sigma A / D converter 5 detects the terminal voltage corresponding to the excitation current flowing through the shunt resistor Rsh from the battery pack 22 via the limiting resistor 24.

[0054] The delta-sigma A / D converter 5 measures and A / D converts the terminal voltages of the unit cells Ce1, Ce2... Cen and the terminal voltage of the shunt resistor Rsh. The output data of the delta-sigma A / D converter 5 is input to the decimation filter 27. A CIC (Cascaded Integrator-Comb) filter is used for the decimation filter 27 to reduce the sampling frequency and convert it into a multi-bit digital value.

[0055] The output of the decimation filter 27 branches into two and is input to the multipliers 28I and 28Q. The multipliers 28I and 28Q input the SIN signal and COS signal generated by the SIN / COS generation unit 31 and perform quadrature conversion. The outputs of the multipliers 28I and 28Q are respectively input to the LPFs 29I and 29Q. The LPFs 29I and 29Q cut off the high-frequency components to obtain the desired DC data and output the real part and the imaginary part to the impedance calculation unit 30 respectively.

[0056] The impedance calculation unit 30 receives each input and outputs the impedances of the unit cells Ce1, Ce2... Cen calculated thereby to the register 32. The data of the impedance values stored in the register 32 is transmitted to an external upper control device or the like.

[0057] Generally, when measuring the impedance of the assembled battery 22, it is necessary to perform measurement in a low frequency band of about 0.1 Hz to 10 kHz, and the delta-sigma A / D converter 5 is also required to have low noise performance in the same frequency band. When the delta-sigma A / D converter 5 includes, for example, an operational amplifier 11 constituted by a MOSFET, the level of low frequency noise due to flicker noise is high. If such an operational amplifier 11 is directly used in the delta-sigma A / D converter 5, the low frequency noise will increase.

[0058] The upper diagram of FIG. 17 shows an example of the frequency noise spectrum distribution as a comparative example. When the signal band is about 0.1 to 10 kHz, if the chopping frequency is set to about 10 kHz, the flicker noise will be mapped to the signal band, resulting in a low noise reduction effect. The charges stored in the parasitic capacitances Ci and Co of the operational amplifier 11 and the wiring become noise, causing an error in the conversion characteristics of the delta-sigma A / D converter 5. When the integral non-linearity error (INL) deteriorates, the DC voltage cannot be measured normally, which is particularly fatal in battery monitoring applications.

[0059] In order to solve this problem, for example, the sampling frequency of the delta-sigma A / D converter 5 may be set to about 2 MHz, which is a relatively high frequency. By setting the sampling frequency in this way, the chopping frequency can be set to about 1 MHz, which is half of that. In the foregoing embodiment and the present embodiment, the chopping switches 12, 14, and 15 of the delta-sigma A / D converter 5 chop and switch, thereby periodically interchanging the positive and negative input terminals and the positive and negative output terminals of the operational amplifier 11 with each other. As a result, the flicker noise can be configured to move to the high-frequency side according to this interchanged chopping frequency. As a result, the flicker noise on the low-frequency side can be reduced. Thereby, the delta-sigma A / D converter 5 is suitable for the battery monitoring device 20 that measures the impedances of the unit cells Ce1 to Cen.

[0060] (Fourth Embodiment) The fourth embodiment will be described with reference to FIGS. 18 to 20. In the fourth embodiment, various modified examples of the reset method will be described. FIGS. 18 to 20 show the connection methods of the switches Si, So, Sim, Sip, Sop, Som, Sfmp, and Sfpm configured around the first integrator 1. As shown in FIGS. 18 to 20, the switches Si, So, Sim, Sip, Sop, Som, Sfmp, and Sfpm may be connected so as to reset the differential input terminals.

[0061] In the example shown in FIG. 18, the switch Si is configured to make the differential input terminals of the operational amplifier 11 have the same potential at the timing of reset, and the switch So is configured to make the differential output terminals have the same potential. In this case, for example, the differential input terminals may be made to have the same potential by connecting between the differential input terminals of the operational amplifier 11 with one switch Si, and the differential output terminals may be made to have the same potential by connecting between the differential output terminals of the operational amplifier 11 with one switch So. Even in this way, the same operational effects as those of the foregoing embodiment can be obtained.

[0062] Also, as shown in FIG. 19, at the timing of reset, switches Sim and Sip may be provided to connect each of the positive input terminal and the negative input terminal of the operational amplifier 11 to the input common potential VCMI, which is a predetermined potential, so that the differential input terminals have the same potential.

[0063] As shown in FIG. 19, switches Som and Sop may be provided to connect between the differential output terminals of the operational amplifier 11 so that the differential output terminals have the same potential. Switches Som and Sop may be provided to connect each of the positive output terminal and the negative output terminal of the operational amplifier 11 to the reference potential VCMO, which is a predetermined potential, so that the differential output terminals have the same potential. Even in this case, the same operational effects as those of the foregoing embodiment can be obtained.

[0064] Also, as shown in FIG. 20, switches Sfmp and Sfpm may be configured to connect the positive input terminal and the negative output terminal of the operational amplifier 11 and to connect the negative input terminal and the positive output terminal of the operational amplifier 11 when resetting. By configuring the switches Sfmp and Sfpm as shown in FIG. 20, since the output of the operational amplifier 11 is fed back at the timing of reset, the potential of the differential input terminals can be fixed to the potential of the output terminals of the operational amplifier 11. As a result, the differential input terminals of the operational amplifier 11 can be reset respectively.

[0065] (Other Embodiments) The present invention is not limited to the foregoing embodiments, and for example, the following modifications or expansions are possible. The delta-sigma A / D converter 5 may be applied to other devices than the battery monitoring device 20 having a battery impedance measurement function. Although the form in which the second integrator 2 is connected to the subsequent stage of the first integrator 1 has been described, it can also be applied to a form in which a differential amplifier is connected instead of the second integrator 2, and further, it can also be applied to a form in which the output of the first integrator 1 is directly input to the quantizer 4. Therefore, the pseudo-addition circuit 3 and the second integrator 2 may be provided as necessary.

[0066] The present disclosure includes the following inventions in addition to the invention described in the claims. [1] A delta-sigma A / D converter using an operational amplifier (11) having a differential configuration, comprising a pair of feedback capacitors (Cf1) having a differential configuration and each feedback-connecting between the differential input terminals and the differential output terminals of the operational amplifier, and a first integrator (1) using a switched capacitor having a chopping switch (14) whose polarity between the differential input terminals of the operational amplifier and the pair of feedback capacitors can be switched, a delta-sigma A / D converter provided with switches (Sim, Sip; Si; Sfmp, Sfpm) for resetting the potential of the differential input terminals of the operational amplifier at a timing when the feedback capacitor (Cf1) and the differential input terminals of the operational amplifier are disconnected by the chopping switch in the first integrator.

[0067] [2] The delta-sigma A / D converter according to [1], having a differential configuration and comprising a second integrator (2) connected to the subsequent stage of the first integrator.

[0068] [3] The switches (Sim, Sip) are configured to set the differential input terminals of the operational amplifier to a predetermined potential (VCMI) respectively when resetting, The delta-sigma A / D converter according to [1] or [2], comprising a switch (So) for making the same potential between the differential output terminals when resetting.

[0069] [4] The switch (Si) is configured to make the differential input terminals of the operational amplifier have the same potential when resetting, The delta-sigma A / D converter according to [1] or [2], comprising a switch (So) for making the same potential between the differential output terminals when resetting.

[0070] [5] The switch (Si) is a delta-sigma A / D converter of [1] or [2] which makes the differential input terminals of the operational amplifier have the same potential by connecting between the differential input terminals when resetting.

[0071] [6] The differential input terminals are composed of a positive input terminal and a negative input terminal. The switches (Sim, Sip) are delta-sigma A / D converters of any one of [1] to [5] which make the differential input terminals have the same potential by connecting each of the positive input terminal and the negative input terminal of the operational amplifier to a predetermined potential when resetting.

[0072] [7] The switch (So) is a delta-sigma A / D converter of any one of [3] to [6] which makes the differential output terminals have the same potential by connecting between the differential output terminals when resetting.

[0073] [8] The switches (Som, Sop) are delta-sigma A / D converters of any one of [3] to [6] which make the differential output terminals have the same potential by connecting each of the differential output terminals of the operational amplifier to a predetermined potential when resetting.

[0074] [9] The differential input terminals are composed of a positive input terminal and a negative input terminal. The switches (Sfmp, Sfpm) are delta-sigma A / D converters of any one of [1] to [8] which connect the positive input terminal and the negative output terminal of the operational amplifier and connect the negative input terminal and the positive output terminal of the operational amplifier when resetting.

[0075]

[10] A battery monitoring device comprising a delta-sigma A / D converter (5) of any one of [1] to [9].

[0076] Although the present disclosure has been described in accordance with embodiments, it is to be understood that the present disclosure is not limited to such embodiments or structures. The present disclosure includes various modifications and variations within the equivalent scope. In addition, various combinations and forms, as well as other combinations and forms including only one element, more, or less thereof, are within the scope and spirit of the present disclosure.

Explanation of Signs

[0077] In the drawings, 1 represents a first integrator, 2 represents a second integrator, 3 represents a pseudo-addition circuit, 4 represents a quantizer, 5 represents a delta-sigma A / D converter, and Cf1 represents a feedback capacitor.

Claims

1. A delta-sigma A / D converter using an operational amplifier (11) having a differential configuration, comprising a pair of feedback capacitors (Cf1) having a differential configuration and each feedback-connected between the differential input terminals and the differential output terminals of the operational amplifier, and a switched capacitor provided with a chopping switch (14) capable of inverting the polarity between the differential input terminals of the operational amplifier and the pair of feedback capacitors, the switched capacitor being a first integrator (1), A delta-sigma A / D converter provided with a switch (φ3, Sim, Sip; Si; Sfmp, Sfp) for resetting the potential of the differential input terminals of the operational amplifier at a timing when the feedback capacitor (Cf1) and the differential input terminals of the operational amplifier are disconnected by the chopping switch in the first integrator.

2. The delta-sigma A / D converter according to claim 1, having a differential configuration and comprising a second integrator (2) connected to the subsequent stage of the first integrator.

3. The switches (Sim, Sip) are configured to set the differential input terminals of the operational amplifier to a predetermined potential (VCMI) respectively when resetting, The delta-sigma A / D converter according to claim 1 or 2, further comprising a switch (So) for making the potential between the differential output terminals the same when resetting.

4. The switch (Si) is configured to make the differential input terminals of the operational amplifier have the same potential when resetting, The delta-sigma A / D converter according to claim 1 or 2, further comprising a switch (So) for making the potential between the differential output terminals the same when resetting.

5. The switch (Si) is configured to connect between the differential input terminals of the operational amplifier when resetting, so that the differential input terminals have the same potential with each other. The delta-sigma A / D converter according to claim 1 or 2.

6. The differential input terminals are composed of a positive input terminal and a negative input terminal, The switches (Sim, Sip) are configured to connect the positive input terminal and the negative input terminal of the operational amplifier to a predetermined potential respectively when resetting, so that the differential input terminals have the same potential. The delta-sigma A / D converter according to claim 1 or 2.

7. The switch (So) is configured to connect between the differential output terminals when resetting, so that the differential output terminals have the same potential with each other. The delta-sigma A / D converter according to claim 3.

8. The delta-sigma A / D converter according to claim 3, wherein the switches (Som, Sop) connect respective differential output terminals of the operational amplifier to a predetermined potential when resetting to make the differential output terminals have the same potential.

9. The differential input terminals are composed of a positive input terminal and a negative input terminal. The delta-sigma A / D converter according to claim 1, wherein the switches (Sfmp, Sfpm) connect the positive input terminal and the negative output terminal of the operational amplifier and connect the negative input terminal and the positive output terminal of the operational amplifier when resetting.

10. A battery monitoring device including the delta-sigma A / D converter (5) according to any one of claims 1 to 9.

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