Display device

Abstract

To provide a display device improved in display quality.SOLUTION: A display device includes a display panel including pixels, and the pixels include: a light emitting element that includes an anode and a cathode connected to a first power source line; a first transistor that is connected between the cathode and the second power source line and operates according to a potential of a first node; a second transistor that is connected between the first node and a data line and receives a first scan signal; a third transistor that is connected between the first node and a reference voltage line and receives a second scan signal; and a fourth transistor that is connected between the first transistor and the first power source line.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly to a display device with improved display quality.

Background Art

[0002] Among display devices, a light-emitting display device displays an image using a light-emitting element that generates light by recombination of electrons and holes. Such a light-emitting display device has the advantages of having a fast response speed and being driven with low power consumption.

[0003] A light-emitting display device includes pixels connected to data lines and scan lines. A pixel generally includes a light-emitting element and a pixel circuit for controlling the amount of current flowing through the light-emitting element. The pixel circuit controls the amount of current flowing through the light-emitting element corresponding to a data signal. At this time, light of a predetermined luminance is generated corresponding to the amount of current flowing through the light-emitting diode.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] One object of the present invention is to provide a display device with improved display quality.

[0006] Another object of the present invention is to provide a display device with reduced power consumption.

Means for Solving the Problems

[0007] The display device according to the present invention includes a display panel including pixels, and each of the pixels includes a light-emitting element including an anode and a cathode connected to a first power line, a first transistor connected between the cathode and a second power line and operating according to the potential of a first node, a second transistor connected between the first node and a data line and receiving a first scan signal, a third transistor connected between the first node and a reference voltage line and receiving a second scan signal, and a fourth transistor connected between the first transistor and the first power line.

[0008] During a first initialization period, the second scan signal has an activation level, the first scan signal has a deactivation level during the first initialization period, the second scan signal has an activation level during a compensation period, and the first scan signal has a deactivation level during the compensation period.

[0009] The fourth transistor receives a third scan signal, and the third scan signal has a deactivation level during the first initialization period and an activation level during the compensation period.

[0010] The fourth transistor can be characterized by receiving the second scan signal.

[0011] The first transistor includes a first electrode connected to the cathode, a second electrode connected to the second power line, and a gate connected to the first node. The fourth transistor includes a first electrode connected to the first power line, a second electrode connected to the first electrode of the first transistor, and a gate receiving the third scan signal.

[0012] The pixel may further include a first initialization transistor connected between the second electrode of the first transistor and a first initialization voltage line and receiving a fourth scan signal, and a first capacitor connected between a second node connected to the first transistor and the first initialization transistor and the first node.

[0013] The fourth scan signal is activated during a first initialization period, deactivated during a data writing period in which the first scan signal is activated, and the first initialization period may be located before the data writing period.

[0014] The fourth scan signal may be further activated during a second initialization period located after the data writing period.

[0015] The second to fourth transistors may be turned off during the second initialization period.

[0016] There are a plurality of the pixels, the plurality of pixels include a first light emitting element that emits light of a first color and a second light emitting element that emits light of a second color different from the first color, the first initialization voltage line is connected to the first light emitting element, and includes a first - 1 initialization voltage line that receives a first - 1 initialization voltage and a first - 2 initialization voltage line that is connected to the second light emitting element and receives a first - 2 initialization voltage different from the first - 1 initialization voltage.

[0017] The pixel may further include a second initialization transistor connected between the cathode of the light emitting element and a second initialization voltage line, and the first initialization voltage line and the second initialization voltage line receive different initialization voltages.

[0018] The fourth transistor receives the third scan signal, the second initialization transistor receives the fourth scan signal, and it can be characterized in that a section in which the third scan signal is activated and a section in which the fourth scan signal is activated do not overlap with each other.

[0019] The display panel displays an image among a plurality of frames, at least one frame among the plurality of frames includes a writing frame and a holding frame, the first to third scan signals have an activation level within the writing frame, are maintained in an inactive state between the holding frames, and the fourth scan signal can be characterized in that it has an activation level within the writing frame and the holding frame.

[0020] There are a plurality of the pixels, the plurality of pixels include a first light-emitting element that emits light of a first color and a second light-emitting element that emits light of a second color different from the first color, the second initialization voltage line is connected to the first light-emitting element, and includes a second-1 initialization voltage line that receives a second-1 initialization voltage and a second-2 initialization voltage line that is connected to the second light-emitting element and receives a second-2 initialization voltage different from the second-1 initialization voltage, and it can be characterized in that.

[0021] The second initialization transistor receives a fifth scan signal, the fourth scan signal is activated during a first initialization section, the fifth scan signal is activated during the first initialization section and a second initialization section, the fourth scan signal and the fifth scan signal are inactivated during a data writing section in which the first scan signal is activated, the first initialization section is located before the data writing section, and the second initialization section can be characterized in that it is located after the data writing section.

[0022] The fourth scan signal can be characterized in that it is further activated during the second initialization section.

[0023] The display panel displays an image between a plurality of frames, and at least one of the plurality of frames includes a writing frame and a holding frame. The fourth scan signal has an activation level within the writing frame and is maintained in an inactivated state between the holding frames. The fifth scan signal can be characterized as having an activation level within the holding frame.

[0024] The pixel can be further characterized as including a first light emission control transistor connected between the first electrode of the first transistor and the cathode and receiving a light emission control signal, and a second light emission control transistor connected between the second electrode of the first transistor and the second power supply line and receiving the light emission control signal.

[0025] The pixel can be further characterized as including a second capacitor connected between the second electrode of the first transistor and either one of the first and second power supply lines, and the first transistor further includes a back gate connected to the second electrode of the first transistor.

[0026] Each of the first to fourth transistors can be characterized as an N-type transistor.

[0027] The first drive voltage received by the first power supply line is higher than the second drive voltage received by the second power supply line, and the reference voltage received by the reference voltage line is between the first drive voltage and the second drive voltage. This can be a characteristic.

[0028] The light emitting element can be further characterized as including an electron control layer disposed on the cathode, a light emitting layer disposed on the electron control layer, and a hole control layer disposed on the light emitting layer, and the anode is disposed on the hole control layer.

[0029] The second power supply line can be characterized as including a Ti / Al / Ti structure.

[0030] The anode includes an MgAg alloy, and the cathode can be characterized by including an ITO / Ag / ITO structure.

[0031] The second power line can be characterized by being disposed on the same layer as the data line and including the same material.

[0032] The second power line can be characterized by being disposed on the same layer as the first power line and including the same material.

[0033] The anode can be characterized by being directly connected to the first power line.

[0034] It can further be characterized by further including a connecting conductive pattern connecting between the anode and the first power line.

[0035] The display panel includes a display area where the pixels are disposed and a non-display area surrounding at least a part of the display area. The pixels are provided in a plurality, the anodes are provided in a plurality and are separately disposed for each of the pixels, and each of the anodes can be characterized by being connected to the second power line within the display area.

[0036] The display panel includes a display area where the pixels are disposed and a non-display area surrounding at least a part of the display area. The pixels are provided in a plurality, the anodes are commonly disposed for the pixels, and the anodes can be characterized by being connected to the second power line within the non-display area.

[0037] The light-emitting element is disposed on the anode, and further includes an intermediate layer including at least a light-emitting layer, and the cathode can be characterized by being disposed on the intermediate layer.

[0038] The display panel further includes a separator having an obtuse taper angle, the pixels are plural, the plural pixels include a first light-emitting element that emits light of a first color and a second light-emitting element that emits light of a second color different from the first color, and the separator can be characterized by dividing the cathode of the first light-emitting element and the cathode of the second light-emitting element.

[0039] The display panel can be characterized by further including a connection wiring that electrically connects the first transistor and the cathode.

[0040] The connection wiring includes a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer, a side surface of the third layer protrudes outward from a side surface of the second layer, and the cathode can be characterized by being in contact with the side surface of the second layer.

[0041] The display panel further includes a pixel definition film in which an opening for exposing at least a part of the anode is defined, a connection electrode disposed on the pixel definition film and electrically connected to the first transistor and the cathode, and a separator disposed on the pixel definition film, and in a contact region adjacent to the separator, a lower surface of the cathode can be characterized by being in contact with an upper surface of the connection electrode.

[0042] The connection electrode can be characterized by having an annular shape surrounding the opening.

[0043] The separator can be characterized by including a first side surface and a second side surface having different taper angles with respect to an upper surface of the pixel definition film.

[0044] Each of the pixels and the connection electrodes is provided in plural, each of the plural connection electrodes electrically connects the first transistor and the cathode in a corresponding pixel among the plural pixels, and a gap between plural connection electrodes adjacent to each other among the plural connection electrodes can be characterized by overlapping with the separator.

[0045] The display device according to the present invention includes a display panel including pixels, and each pixel includes a light-emitting element including an anode and a cathode connected to a first power line, a first electrode connected to the cathode, a second electrode connected to a second power line, and a driving transistor including a gate connected to a first node, a switching transistor connected between the first node and a data line, a light-emitting control transistor connected between the first electrode of the driving transistor and the cathode, a compensation transistor connected between the first electrode of the driving transistor and the first power line, and an initialization transistor connected between the cathode and an initialization voltage line. The compensation transistor and the initialization transistor receive different scan signals from each other.

Advantages of the Invention

[0046] According to the present invention, it is possible to provide a display device in which at least one of display quality and power consumption is reduced.

Brief Description of the Drawings

[0047]

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Mode for Carrying Out the Invention

[0048] In this specification, when a predetermined component (or region, layer, part, etc.) is described as being "on", "connected to", or "coupled to" another component, it means that it can be directly disposed / connected / coupled on the other component, or a third component can also be disposed between them.

[0049] The same reference numerals denote the same components. Also, in the drawings, the thickness, ratio, and dimensions of the components are exaggerated for the purpose of efficient explanation of the technical content. "And / or" includes all one or more combinations that the associated components can define.

[0050] The terms "first", "second", etc. can be used to describe various components, but the components should not be limited by these terms. These terms are only used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component can be referred to as the second component, and similarly, the second component can be referred to as the first component. Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0051] Also, terms such as "below", "under", "above", "over", etc. are used to explain the association relationship of the configurations illustrated in the drawings. These terms are relative concepts and are explained based on the directions shown in the drawings.

[0052] Terms such as "comprising" or "having" are intended to specify the presence of the features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, and it should be understood that they do not preclude in advance the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used in this specification have the same meaning as commonly understood by those skilled in the technical field to which the present invention pertains. Also, terms such as those defined in commonly used dictionaries should be interpreted to have a meaning consistent with the meaning in the context of the related art, and here, unless explicitly defined, they should not be interpreted as being overly ideal or having an overly formal meaning.

[0054] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0055] FIG. 1 is a block diagram of a display device DD according to an embodiment of the present invention.

[0056] Referring to FIG. 1, the display device DD can include a display panel DP, a driving controller 100, and a panel driver. As an example of the present invention, the panel driver can include a data driving circuit 200 (or data driver), a scan driving circuit 300, a light emission driving circuit 350, and a voltage generator 400.

[0057] The display panel DP can include a display area DA and a non-display area NDA surrounding at least a part of the display area DA. The display panel DP can include a plurality of pixels PX arranged in the display area DA. The display panel DP can include a first scan line GWL1 to GWLn, a second scan line GRL1 to GRLn, a third scan line GCL1 to GCLn, a fourth scan line GIL1 to GILn, and a light emission control line EML1 to EMLn. The first scan lines GWL1 to GWLn can be referred to as write scan lines, the second scan lines GRL1 to GRLn can be referred to as reference scan lines, the third scan lines GCL1 to GCLn can be referred to as compensation scan lines, and the fourth scan lines GIL1 to GILn can be referred to as initialization scan lines.

[0058] The display panel DP can be driven at a predetermined driving frequency, for example, 60 Hz, 120 Hz, or 240 Hz. Alternatively, the display panel DP can be configured to operate in a first mode driven at the fixed driving frequency or a second mode driven at a variable driving frequency. For example, in the second mode, the driving frequency can be variably changed in the range of 1 Hz to 240 Hz, but it is not particularly limited thereto.

[0059] The driving controller 100 receives an image signal RGB and a control signal CTRL. The driving controller 100 generates a video data signal DATA by converting the data format of the image signal RGB to match the interface specification with the data driving circuit 200. The driving controller 100 outputs a scan control signal SCS, a data control signal DCS, and a light emission driving control signal ECS.

[0060] The data driving circuit 200 (or data driving unit) receives a data control signal DCS and a video data signal DATA from the driving controller 100. The data driving circuit 200 converts the video data signal DATA into a data signal and outputs the data signal to data lines DL1 to DLm. The data signal is an analog voltage corresponding to the gradation value of the video data signal DATA. The data lines DL1 to DLm can be arranged along the first direction DR1, and each of the data lines DL1 to DLm can be extended along the second direction DR2.

[0061] The scan driving circuit 300 (or scan driving unit) and the light emitting driving circuit 350 (or light emitting driving unit) can be arranged in the non-display area NDA of the display panel DP. As an example of the present invention, the scan driving circuit 300 can be adjacent to one side of the display area DA, and the light emitting driving circuit 350 can be arranged adjacent to the other side of the display area DA opposite to the one side. In the example illustrated in FIG. 1, the scan driving circuit 300 and the light emitting driving circuit 350 are respectively arranged on both sides of the display area DA, but the present invention is not limited thereto. For example, the scan driving circuit 300 and the light emitting driving circuit 350 can be arranged to be adjacent to one of the one side and the other side of the display panel DP. In one embodiment, the scan driving circuit 300 and the light emitting driving circuit 350 can be integrated into one circuit.

[0062] According to one embodiment of the present invention, each of the plurality of pixels PX includes a light emitting element ED (see FIG. 3) and a pixel circuit (also referred to as a pixel driving unit) PXC (see FIG. 3) that controls the light emission of the light emitting element ED.

[0063] The pixel circuit PXC (see FIG. 3) can include at least one or more transistors and at least one or more capacitors. The scan driving circuit 300 and the light emitting driving circuit 350 can include transistors formed through the same process as the pixel circuit PXC (see FIG. 3). The pixel circuit PXC (see FIG. 3) can be referred to as a pixel driving unit.

[0064] The scan driving circuit 300 receives a scan control signal SCS from the driving controller 100. In response to the scan control signal SCS, the scan driving circuit 300 can output a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal to the first scan lines GWL1 to GWLn, the second scan lines GRL1 to GRLn, the third scan lines GCL1 to GCLn, and the fourth scan lines GIL1 to GILn, respectively. The light emission driving circuit 350 can output a light emission control signal to the light emission control lines EML1 to EMLn in response to a light emission driving control signal ECS from the driving controller 100.

[0065] Each of the first scan lines GWL1 to GWLn, the second scan lines GRL1 to GRLn, the third scan lines GCL1 to GCLn, the fourth scan lines GIL1 to GILn, and the light emission control lines EML1 to EMLn can extend in a first direction DR1, and the first scan lines GWL1 to GWLn, the second scan lines GRL1 to GRLn, the third scan lines GCL1 to GCLn, the fourth scan lines GIL1 to GILn, and the light emission control lines EML1 to EMLn can be separated in a second direction DR2.

[0066] Each of the plurality of pixels PX can be electrically connected to four scan lines, one light emission control line, and one data line. For example, as shown in FIG. 1, the pixels in the first row can be connected to the scan lines GWL1, GRL1, GCL1, GIL1, and the light emission control line EML1. The pixels in the first column can be connected to the data line DL1. Also, the pixels in the i-th row can be connected to the scan lines GWLi, GRLi, GCLi, GILi, and the light emission control line EMLi. However, the embodiments are not limited thereto, and each of the pixels PX may be connected to less than four scan lines or more than four scan lines.

[0067] The voltage generator 400 (or the power supply unit) generates the voltages necessary for the operation of the display panel DP. In this embodiment, the voltage generator 400 can generate a first driving voltage ELVDD, a second driving voltage ELVSS, a reference voltage VREF, a first initialization voltage VINT, and a second initialization voltage VAINT.

[0068] FIGS. 2A and 2B are timing diagrams for explaining the operation of the display device DD (see FIG. 1) according to an embodiment of the present invention. FIG. 2A is a timing diagram for explaining the case where the display device DD (see FIG. 1) operates at a first driving frequency according to an embodiment of the present invention. FIG. 2B is a timing diagram for explaining the case where the display device DD (see FIG. 1) operates at a second driving frequency according to an embodiment of the present invention.

[0069] Referring to FIGS. 1 and 2A, the driving frequency of the display device DD can be variably set in various ways. As an example of the present invention, the first driving frequency can be the highest driving frequency at which the display device DD can operate. The first driving frequency can be referred to as the reference frequency or the maximum frequency.

[0070] When the display device DD operates at the first driving frequency, the scan driving circuit 300 can sequentially activate the scan signals (for example, the first scan signals GW1 to GWn) to the high level in each of the plurality of frames F11, F12, F13, F14. In FIGS. 2A and 2B, only the first scan signals GW1 to GWn are illustrated for simplicity of explanation, but the second scan signal, the third scan signal, and the fourth scan signal can also be activated in a similar manner according to the driving frequency.

[0071] When the first driving frequency is the maximum frequency, each of the frames F11, F12, F13, F14 can include only the writing frame WP. In this case, the duration of the writing frame WP can be the same as the duration of each of the frames F11, F12, F13, F14.

[0072] Referring to FIGS. 1 to 2B, the display device DD can operate at a second driving frequency lower than the first driving frequency.

[0073] If the display device DD operates at a second driving frequency lower than the first driving frequency, the duration of each of the frames F21, F22 can be increased compared to the duration of each of the frames F11, F12, F13, F14 illustrated in FIG. 2A. FIG. 2B exemplarily illustrates that the duration of each of the frames F21, F22 operating at the second driving frequency is twice the duration of each of the frames F11, F12, F13, F14. However, the duration of each of the frames F21, F22 operating at the second driving frequency is not limited to any one embodiment.

[0074] Each of the frames F21, F22 can include a write frame WP and a holding frame HP. FIG. 2B exemplarily illustrates that the write frame WP has the same duration as each of the frames F11, F12, F13, F14 illustrated in FIG. 2A.

[0075] As shown in FIGS. 2A and 2B, the scan driving circuit 300 can sequentially activate the first scan signals GW1 to GWn to an active level (e.g., high level) during the write frame WP. Although not illustrated in FIG. 2B, the scan driving circuit 300 and the light emission driving circuit 350 can sequentially activate the scan signal and the light emission control signal to an active level (e.g., high level) during the write frame WP. A detailed description thereof will be given later.

[0076] During the holding frame HP, the scan driving circuit 300 can hold the first scan signals GW1 to GWn at an inactive level (e.g., low level). During the holding frame HP, the scan driving circuit 300 can hold the second and third scan signals at an inactive level.

[0077] FIG. 3 is a circuit diagram of a pixel PXij according to an embodiment of the present invention. FIGS. 4A and 4B are timing diagrams for explaining the operation of the pixel PXij of FIG. 3 according to an embodiment of the present invention.

[0078] FIG. 3 typically shows a pixel PXij connected to the i-th first scan line GWLi among the first scan lines GWL1 to GWLn (see FIG. 1) and connected to the j-th data line DLj among the plurality of data lines DL1 to DLm (see FIG. 1). The pixel PXij is connected to the i-th second scan line GRLi among the second scan lines GRL1 to GRLn (see FIG. 1), connected to the i-th third scan line GCLi among the third scan lines GCL1 to GCLn (see FIG. 1), and connected to the i-th fourth scan line GILi among the fourth scan lines GIL1 to GILn (see FIG. 1). Also, the pixel PXij is connected to the i-th emission control line EMLi among the emission control lines EML1 to EMLn.

[0079] The pixel PXij can include a pixel circuit PXC (or a pixel driving circuit) and a light emitting element ED electrically connected to the pixel circuit PXC. In this embodiment, the pixel circuit PXC can include eight transistors (hereinafter, the first to eighth transistors T1 to T8) and two capacitors (hereinafter, the first capacitor C1 and the second capacitor C2). In an embodiment of the present invention, at least one of the first to eighth transistors T1 to T8 can be omitted from the pixel PXij, or additional transistors can be further included in the pixel PXij.

[0080] The i-th first scan line GWLi transmits the i-th first scan signal GWi to the pixel PXij, the i-th second scan line GRLi transmits the i-th second scan signal GRi to the pixel PXij, the i-th third scan line GCLi transmits the i-th third scan signal GCi to the pixel PXij, and the i-th fourth scan line GILi can transmit the i-th fourth scan signal GIi to the pixel PXij. The i-th emission control line EMLi can transmit the i-th emission control signal EMi to the pixel PXij. The j-th data line DLj can transmit the data signal DS to the pixel PXij. The data signal DS can have a voltage level corresponding to the gradation value of the video data signal DATA (see FIG. 1) output from the driving controller 100 (see FIG. 1).

[0081] Also, the pixel PXij can be connected to a first power line PL1 that receives the first driving voltage ELVDD, a second power line PL2 that receives the second driving voltage ELVSS, a reference voltage line VL1 that receives the reference voltage VREF, a first initialization voltage line VL2 that receives the first initialization voltage VINT, and a second initialization voltage line VL3 that receives the second initialization voltage VAINT. The first driving voltage ELVDD has a voltage level higher than that of the second driving voltage ELVSS, the reference voltage VREF is higher than the second driving voltage ELVSS and lower than the first driving voltage ELVDD. The first initialization voltage VINT can have a voltage level lower than that of the second initialization voltage VAINT.

[0082] In this embodiment, each of the first to eighth transistors T1 to T8 can be an N-type (N type) thin film transistor having an oxide semiconductor as a semiconductor layer. In particular, when an N-type thin film transistor is applied to the first transistor T1, which can be referred to as a driving transistor, fluctuations in element characteristics due to previous data can be reduced compared to the case where a P-type thin film transistor is applied. Therefore, the characteristics of overcoming instantaneous afterimages can be improved.

[0083] The light-emitting element ED can include an anode AE and a cathode CE. When the light-emitting element ED is an organic light-emitting element, the light-emitting element ED can further include an organic layer disposed between the anode AE and the cathode CE. The anode AE of the light-emitting element ED can be connected to the first power line PL1. In the present embodiment, the anode AE of the light-emitting element ED can be directly connected to the first power line PL1. The cathode CE of the light-emitting element ED can be connected to the pixel circuit PXC. The light-emitting element ED can emit light corresponding to the amount of current flowing through the first transistor T1 of the pixel circuit PXC.

[0084] The first transistor T1 is connected between the cathode CE of the light-emitting element ED and the second power line PL2 that receives the second driving voltage ELVSS. The first transistor T1 can be referred to as a driving transistor. The first transistor T1 can include a first electrode D1, a second electrode S1, and a gate electrode G1_1. The gate electrode G1_1 can be connected to the first node N1, the second electrode S1 can be connected to the second node N2, and the first electrode D1 can be connected to the third node N3. The first electrode D1 can be referred to as the drain of the first transistor T1, and the second electrode S1 can be referred to as the source of the first transistor T1. The first transistor T1 can operate according to the potential of the first node N1. In the present embodiment, the first transistor T1 can further include a back gate electrode G1_2. The back gate electrode G1_2 can be connected to the second electrode S1 of the first transistor T1.

[0085] According to an embodiment of the present invention, the first transistor T1 is an N-type thin-film transistor, and the cathode CE of the light-emitting element ED can be connected to the drain (or the first electrode D1) of the first transistor T1 via the sixth transistor T6.

[0086] The second transistor T2 is connected between the j-th data line DLj and the first node N1, and receives the i-th first scan signal GWi. The second transistor T2 can be referred to as a switching transistor. The second transistor T2 can include a first electrode D2 connected to the j-th data line DLj, a second electrode S2 connected to the first node N1, and a gate electrode G2 connected to the i-th first scan line GWLi. The second transistor T2 can transmit the data signal DS received through the j-th data line DLj to the first node N1 in response to the i-th first scan signal GWi received through the i-th first scan line GWLi.

[0087] The third transistor T3 is connected between the reference voltage line VL1 and the first node N1, and receives the i-th second scan signal GRi. The third transistor T3 can be referred to as a first compensation transistor. The third transistor T3 can include a first electrode D3 connected to the reference voltage line VL1, a second electrode S3 connected to the first node N1, and a gate electrode G3 connected to the i-th second scan line GRLi. The third transistor T3 can be turned on by the i-th second scan signal GRi received through the i-th second scan line GRLi to transmit the reference voltage VREF to the first node N1. In this embodiment, the reference voltage VREF can have a voltage level between the first driving voltage ELVDD and the second driving voltage ELVSS. For example, when the first driving voltage ELVDD is 13V and the second driving voltage ELVSS is 0V, the reference voltage VREF can be 1.3V.

[0088] The fourth transistor T4 is connected between the first power line PL1 and the third node N3 and receives the i-th third scan signal GCi. The fourth transistor T4 can be referred to as a second compensation transistor. The fourth transistor T4 includes a first electrode D4 connected to the first power line PL1, a second electrode S4 connected to the first electrode D1 of the first transistor T1 (i.e., the third node N3), and a gate electrode G4 connected to the i-th third scan line GCLi. The fourth transistor T4 can be turned on by the i-th third scan signal GCi received through the i-th third scan line GCLi to transmit the first driving voltage ELVDD to the third node N3.

[0089] When the fourth transistor T4 is not connected to the first power line PL1 and receives a voltage using another power line, the number of power lines connected to the pixel PXij increases. However, by using the first driving voltage ELVDD supplied through the first power line PL1 for the fourth transistor T4 according to this embodiment, the voltage generator 400 (see FIG. 1) can further not include another power line. Through this, the area of the non-display area NDA (see FIG. 1) can be reduced. Also, the number of power lines connected to the pixel PXij can be reduced. Through this, the interval between the wirings connected to the pixel PXij can be increased, so that the signal interference between the wirings can be reduced. Therefore, a pixel PXij and a display device DD (see FIG. 1) with improved display quality can be provided.

[0090] The fifth transistor T5 is connected between the first initialization voltage line VL2 and the second node N2 and can receive the i-th fourth scan signal GIi. The fifth transistor T5 can be referred to as the first initialization transistor. The fifth transistor T5 can include a first electrode D5 connected to the second electrode S1 of the first transistor T1, a second electrode S5 connected to the first initialization voltage line VL2, and a gate electrode G3 connected to the i-th fourth scan line GILi. The fifth transistor T5 can be turned on by the i-th fourth scan signal GIi received through the i-th fourth scan line GILi to transmit the first initialization voltage VINT to the second node N2.

[0091] The sixth transistor T6 is connected between the first transistor T1 and the cathode CE of the light-emitting element ED and can receive the i-th light emission control signal EMi. The sixth transistor T6 can be referred to as the first light emission control transistor. The sixth transistor T6 can include a first electrode D6 connected to the cathode CE of the light-emitting element ED, a second electrode S6 connected to the first electrode D1 of the first transistor T1, and a gate electrode G6 connected to the i-th light emission control line EMLi. The sixth transistor T6 can be turned on by the i-th light emission control signal EMi received through the i-th light emission control line EMLi to electrically connect the cathode CE of the light-emitting element ED to the first electrode D1 of the first transistor T1.

[0092] The seventh transistor T7 is connected between the first transistor T1 and the second power line PL2 and can receive the i-th light emission control signal EMi. The seventh transistor T7 can be referred to as the second light emission control transistor. The seventh transistor T7 can include a first electrode D7 connected to the second electrode S1 of the first transistor T1, a second electrode S7 connected to the second power line PL2, and a gate electrode G7 connected to the i-th light emission control line EMLi. The seventh transistor T7 can be turned on by the i-th light emission control signal EMi received through the i-th light emission control line EMLi to electrically connect the second power line PL2 to the second electrode S1 of the first transistor T1.

[0093] The eighth transistor T8 is connected between the second initialization voltage line VL3 and the cathode CE of the light emitting element ED and can receive the i-th fourth scan signal GIi. The eighth transistor T8 can be referred to as the second initialization transistor. The eighth transistor T8 can include a first electrode D8 connected to the fourth node N4, a second electrode S8 connected to the second initialization voltage line VL3, and a gate electrode G8 connected to the i-th fourth scan line GILi. The cathode CE of the light emitting element ED and the first electrode D6 of the sixth transistor T6 can be connected to the fourth node N4. The eighth transistor T8 can be turned on by the i-th fourth scan signal GIi received through the i-th fourth scan line GILi to transmit the second initialization voltage VAINT to the cathode CE of the light emitting element ED.

[0094] In this embodiment, the fourth transistor T4 and the eighth transistor T8 can receive different scan signals. Also, the fourth transistor T4 and the eighth transistor T8 can be connected to different voltage lines. Through this, the initialization operation of the cathode CE through the eighth transistor T8 and the compensation operation of the first transistor T1 through the fourth transistor T4 can proceed independently. Also, during the compensation operation, the third node N3 to which the drain of the first transistor T1 is connected and the fourth node N4 to which the cathode CE of the light-emitting element ED is connected can be separated. Through this, during the compensation operation, the influence of the parasitic capacitance formed at the fourth node N4 can be reduced. Therefore, the compensation stability can be improved.

[0095] On the contrary, different from this embodiment, when the fourth transistor T4 and the eighth transistor T8 receive the same scan signal and are connected to the same voltage line, during the compensation operation, the third node N3 and the fourth node N4 are not separated, and the parasitic capacitance formed at the fourth node N4 affects the compensation amount.

[0096] The first capacitor C1 can be connected between the first node N1 and the second node N2. The first capacitor C1 can include a first electrode E1 connected to the first node N1 and a second electrode E2 connected to the second node N2. The first capacitor C1 can store the differential voltage between the first node N1 and the second node N2. The first capacitor C1 can be referred to as a storage capacitor.

[0097] The second capacitor C2 can be connected between the first power supply line PL1 and the second node N2. The second capacitor C2 can include a first electrode E3 connected to the first power supply line PL1 and a second electrode E4 connected to the second node N2. The second capacitor C2 can store the differential voltage between the first driving voltage ELVDD and the second node N2. The second capacitor C2 can be referred to as a hold capacitor.

[0098] The operation of pixel PXij will be described in more detail with reference to FIGS. 3 to 4C.

[0099] The display device DD (see FIG. 1) displays an image for each frame. Each of the first scan lines GWL1 to GWLn (see FIG. 1), the second scan lines GBL1 to GBLn (see FIG. 1), the third scan lines GCL1 to GCLn (see FIG. 1), the fourth scan lines GIL1 to GILn (see FIG. 1), and the emission control lines EML1 to EMLn can sequentially receive a scan signal or an emission control signal between frames. Each of FIGS. 4A and 4B illustratively shows the operation of pixel PXij between the writing frame WP in any one of the frames F11 to F14 shown in FIG. 2A and the writing frame WP in the frames F21 and F22 shown in FIG. 2B. FIG. 4C illustratively shows the operation of pixel PXij between the holding frames HP in the frames F21 and F22 shown in FIG. 2B.

[0100] As shown in FIGS. 4A to 4C, each of the scan signals GRi, GWi, GCi, GIi and the emission control signal EMi can have an activation level (or high level) during a partial section and an inactivation level (or low level) during a partial section. The N-type first to eighth transistors T1 to T8 described above are turned on when the corresponding scan signal or emission control signal has a high level.

[0101] First, referring to FIGS. 3 to 4B, the writing frame WP can include a first initialization section t1, a compensation section t2, a data writing section t3, a second initialization section t4, and an emission section t5. In the present embodiment, the first initialization section t1 can be located before the data writing section t3, and the second initialization section t4 can be located after the data writing section t3.

[0102] First, during the first initialization period t1, the second scan signal GRi and the fourth scan signal GIi can have an activation level. In this embodiment, the first initialization period t1 can correspond to the first intervals AP1_I, AP1_I' (or the first - 1 activation intervals) in which the fourth scan signal GIi has an activation level. During the first initialization period t1, the first scan signal GWi, the third scan signal GCi, and the emission control signal EMi can have a non - activation level.

[0103] During the first initialization period t1, the third transistor T3, the fifth transistor T5, and the eighth transistor T8 can be turned on. During the first initialization period t1, the first node N1 can be initialized to the reference voltage VREF, the second node N2 can be initialized to the first initialization voltage VINT, and the cathode CE of the light - emitting element ED can be initialized to the second initialization voltage VAINT.

[0104] A part of the intervals AP_R, AP_R' (or the second activation intervals) in which the second scan signal GRi has an activation level overlaps with the first intervals AP1_I, AP1_I' in which the fourth scan signal GIi has an activation level. Therefore, by simultaneously initializing the first node N1 and the second node N2 during the first initialization period t1, the first capacitor C1 can be initialized to the differential voltage value between the reference voltage VREF and the first initialization voltage VINT. The second capacitor C2 can be initialized to the differential voltage value between the first driving voltage ELVDD and the first initialization voltage VINT. The first initialization period t1 can be a period in which the gate electrode G1_1 and the source S1 of the first transistor T1 are initialized and the cathode CE of the light - emitting element ED is initialized.

[0105] In one embodiment, as shown in FIG. 4A, the start time of the second activation period AP_R of the second scan signal GRi can be after the start time of the first - 1 activation period AP1_I of the fourth scan signal GIi. However, the embodiment is not limited to this. The start time of the first - 1 activation period AP1_I may be after the start time of the second activation period AP_R, or these times may be the same. For example, as shown in FIG. 4B, the start time of the first - 1 activation period AP1_I' of the fourth scan signal GIi can be after the start time of the second activation period AP_R' of the second scan signal GRi. At this time, the entire first - 1 activation period AP1_I' of the fourth scan signal GIi can overlap with the second activation period AP_R' of the second scan signal GRi. Or, the first - 1 activation period AP1_I' and the second activation period AP_R' may start simultaneously.

[0106] Thereafter, during the compensation period t2, the second scan signal GRi and the third scan signal GCi can have an activation level. In this embodiment, the second scan signal GRi can maintain an activation level substantially during the first initialization period t1 and the compensation period t2. During the compensation period t2, the first scan signal GWi, the fourth scan signal GIi, and the emission control signal EMi can have a non - activation level.

[0107] During the compensation period t2, the third transistor T3 and the fourth transistor T4 are turned on in response to the second scan signal GRi and the third scan signal GCi, respectively, and the first driving voltage ELVDD can be supplied to the third node N3. A part of the sections AP_R and AP_R' where the second scan signal GRi has an activation level overlaps with the sections AP_C and AP_C' (or the third activation section) where the third scan signal GCi has an activation level. That is, a part of the sections AP_R and AP_R' overlaps with the sections AP1_I and AP1_I', and another part of the sections AP_R and AP_R' overlaps with the sections AP_C and AP_C'. During the compensation period t2, the threshold voltage Vth of the first transistor T1 can be compensated by the coupling of the first capacitor C1. A voltage "(VREF - Vth)" that is approximately equal to the threshold voltage Vth of the first transistor T1 lower than the reference voltage VREF provided to the gate electrode G1_1 of the first transistor T1 can be provided to the second node N2.

[0108] In one embodiment, as illustrated in FIG. 4A, the time point when the third activation section AP_C of the third scan signal GCi ends can be located after the time point when the second activation section AP_R of the second scan signal GRi ends. However, the embodiment is not limited thereto, and the time point when the second activation section AP_R ends may be after the time point when the third activation section AP_C ends, or these time points may be simultaneous. For example, as illustrated in FIG. 4B, the time point when the second activation section AP_R' of the second scan signal GRi ends can be located after the time point when the third activation section AP_C' of the third scan signal GCi ends. At this time, the entire third activation section AP_C' of the third scan signal GCi can overlap with the second activation section AP_R' of the second scan signal GRi. Alternatively, the second activation section AP_R' and the third activation section AP_C' may end simultaneously.

[0109] In this embodiment, the section in which the third scan signal GCi is activated and the section in which the fourth scan signal GIi is activated can be non-overlapping with each other. Therefore, the compensation section t2 can be non-overlapping with the first initialization section t1. That is, the compensation section t2 and the first initialization section t1 do not proceed simultaneously and can proceed independently. That is, as shown in the examples of FIGS. 4A and 4B, between the end point of the first initialization section t1 and the start point of the compensation section t2, the fourth scan signal GIi is at the non-activated level, the second scan signal GRi remains at the activated level, and the first scan signal GWi, the third scan signal GCi, and the light emission control signal EMi remain at the non-activated level. Through this, during the compensation section t2, the third node N3 to which the drain of the first transistor T1 is connected and the fourth node N4 to which the cathode CE of the light emitting element ED is connected are maintained in a separated state, and the influence of the parasitic capacitance formed at the fourth node N4 on the third node N3 during the compensation operation can be reduced. Therefore, the compensation stability can be improved.

[0110] Thereafter, during the data writing section t3, the first scan signal GWi can have an activated level. During the data writing section t3, the second scan signal GRi, the third scan signal GCi, the fourth scan signal GIi, and the light emission control signal EMi can have non-activated levels. In the examples of FIGS. 4A and 4B, between the end points of the sections AP_C’, AP_C or the end points of the sections AP_R, AP_R’ and the start point of the data writing section t3, the first to fourth scan signals GWi, GRi, GCi, GIi and the light emission control signal EMi are at non-activated levels. Also, between the end point of the compensation section t2 and the end points of the sections AP_C’, AP_C or the end points of the sections AP_R, AP_R’, the third scan signal GCi is at the activated level, and the first, second, and fourth scan signals GWi, GRi, GIi and the light emission control signal EMi are at non-activated levels.

[0111] During the data writing period t3, the second transistor T2 can be turned on. The second transistor T2 can output a voltage corresponding to the data signal DS, and the data signal DS can be provided to the first node N1. The potential of the first node N1 can be changed from the reference voltage VREF to the data signal DS. For example, corresponding to a predetermined gradation, the voltage of the first node N1 can be increased from the reference voltage VREF to the data signal DS. Or, corresponding to a black gradation or the like, the voltage of the first node N1 can be decreased from the reference voltage VREF to the data signal DS.

[0112] The data signal DS can be charged to the first capacitor C1. Although the threshold voltage Vth of the first transistor T1 may be different for each pixel PX (see FIG. 1), the pixel PXij illustrated in FIG. 3 can supply a current proportional to the data signal DS to the light emitting element ED regardless of the deviation of the threshold voltage Vth of the first transistor T1.

[0113] Thereafter, during the second initialization period t4, the fourth scan signal GIi can have an activation level. In the present embodiment, the second initialization period t4 can correspond to a second section AP2_I (or, a first - 2 activation section) in which the fourth scan signal GIi has an activation level. During the second initialization period t4, the first scan signal GWi, the second scan signal GRi, the third scan signal GCi, and the light emission control signal EMi can have an inactivation level. Different from the first initialization period t1, in the second initialization period t4, the second scan signal GRi has an inactivation level, and only the fourth scan signal GIi can have an activation level. Note that in the examples of FIGS. 4A and 4B, between the end point of the data writing period t3 and the start point of the second initialization period t4, the first to fourth scan signals GWi, GRi, GCi, GIi, and the light emission control signal EMi are at an inactivation level.

[0114] During the second initialization period t4, the fifth transistor T5 and the eighth transistor T8 can be turned on. During the second initialization period t4, the second node N2 can be initialized to the first initialization voltage VINT, and the cathode CE of the light-emitting element ED can be initialized to the second initialization voltage VAINT.

[0115] In this embodiment, by initializing the cathode CE of the light-emitting element ED by the eighth transistor T8, it is possible to prevent the light-emitting element ED from instantaneously emitting light at a high luminance due to the residual voltage remaining at the cathode CE of the light-emitting element ED at the initial stage of driving the light-emitting element ED. It is possible to prevent the characteristic degradation of the black gradation, and it is possible to prevent display unevenness from being visually recognized in the display area DA (see FIG. 1) due to the initialization voltage provided to the light-emitting element ED at a low gradation. Therefore, it is possible to provide a pixel PX (see FIG. 1) and a display device DD (see FIG. 1) with improved display quality. In one embodiment, the second initialization voltage VAINT can have the same voltage level (for example, 13V) as the first driving voltage ELVDD. However, it is not limited thereto.

[0116] In this embodiment, the fourth scan signal GIi can control the fifth transistor T5 and the eighth transistor T8 simultaneously. Since the fifth transistor T5 and the eighth transistor T8 are turned on by the same scan signal, the source initialization operation of the first transistor T1 and the cathode CE initialization operation of the light-emitting element ED through the fifth transistor T5 can proceed simultaneously. Therefore, compared with the case of using another scan line for controlling each of the fifth transistor T5 and the eighth transistor T8, the number of scan lines connected to the pixel PXij can be reduced, so that the configuration of the pixel circuit PXC and the configuration of the scan drive circuit 300 (see FIG. 1) for panel driving can be simplified. Through this, the area of the non-display area NDA (see FIG. 1) can be reduced, and the interval between wirings included in the pixel PXij can be increased, so that the signal interference between the wirings can be reduced.

[0117] In this embodiment, in response to the second section AP2_I proceeding after the data writing section t3, the second section AP2_I proceeds with the data signal DS charged in the first capacitor C1. At this time, even if the first initialization voltage VINT is provided to the second node N2 by the turn-on operation of the fifth transistor T5, the first node N1 is set to the floating state, so that the differential voltage between the first node N1 and the second node N2 stored in the first capacitor C1 can be made not to vary. Therefore, the drive current of the light-emitting element ED in the light-emitting section t5 is determined by the gate-source voltage of the first transistor T1 corresponding to the differential voltage stored in the first capacitor C1, and the drive current of the light-emitting element ED can also be made not to vary.

[0118] On the other hand, in one embodiment of the present invention, the second section AP2_I can have a shorter duration than the first section AP1_I. For example, the duration of the second section AP2_I can be set short enough so that the differential voltage stored in the first capacitor C1 does not vary. Through this, the differential voltage stored in the first capacitor C1 corresponding to the data signal DS can be kept constant even after the second initialization section t4 has elapsed. Thereafter, during the light-emitting section t5, the light-emitting control signal EMi can have an active level. During the light-emitting section t5, the first scan signal GWi, the second scan signal GRi, the third scan signal GCi, and the fourth scan signal GIi can have an inactive level.

[0119] During the light emission period t5, the sixth transistor T6 can be turned on so that the cathode CE of the light emitting element ED and the first transistor T1 can be electrically connected. Also, during the light emission period t5, the seventh transistor T7 can be turned on so that the first transistor T1 can be electrically connected to the second power supply line PL2. If the sixth transistor T6 and the seventh transistor T7 are turned on, a drive current can flow from the first drive voltage ELVDD through the light emitting element ED, the sixth transistor T6, the first transistor T1, and the seventh transistor T7 to the second drive voltage ELVSS. In the examples of FIGS. 4A and 4B, between the end of the second initialization period t4 and the start of the light emission period t5, the first to fourth scan signals GWi, GRi, GCi, GIi and the light emission control signal EMi are at the inactive level.

[0120] The drive current flowing through the light emitting element ED can be proportional to the square of the difference between the gate-source voltage (referred to as Vgs) of the first transistor T1 and the threshold voltage (referred to as Vth) of the first transistor T1, which is “(Vgs - Vth) 2 ”. Since the gate voltage level of the first transistor T1 is “(DS + (ELVSS - (VREF - Vth)))” and the source voltage level of the first transistor T1 is the second drive voltage ELVSS, the current flowing through the light emitting element ED can be proportional to the square of the difference between the data signal DS and the reference voltage VREF, which is “(DS - VREF) 2 ”.

[0121] According to the present invention, the threshold voltage Vth of the first transistor T1 can have no influence on the current flowing through the light emitting element ED. The threshold voltage of each of the first transistors T1 included in each of the pixels PX (see FIG. 1) can be different according to the characteristics of the first transistor T1. However, regardless of the characteristics of the first transistors T1 included in each of the pixels PX (see FIG. 1), the current flowing through the light emitting element ED in the subsequent light emission period t5 can be constant. That is, the current flowing through the light emitting element ED is “(DS - VREF) 2By being proportional to “, it is possible to provide a pixel PX (see FIG. 1) and a display device DD (see FIG. 1) with improved display quality.

[0122] On the other hand, according to another embodiment of the present invention, the fourth scan signal GIi can be activated only between the first intervals AP1_I and AP1_I', and only the first initialization interval t1 can be provided. That is, the second initialization interval t4 can be omitted. After the data writing interval t3, the light emitting interval t5 can be advanced without proceeding to another initialization interval.

[0123] Referring to FIGS. 3 to 4C, the holding frame HP can include a first initialization interval t1_h, a second initialization interval t4_h, and a light emitting interval t5_h. The first initialization interval t1_h, the second initialization interval t4_h, and the light emitting interval t5_h in the holding frame HP can be located at corresponding times to the first initialization interval t1, the second initialization interval t4, and the light emitting interval t5 in the writing frame WP described above in FIG. 4A.

[0124] Within the holding frame HP, the fourth scan signal GIi can have an activation level between the first interval AP1_Ih and the second interval AP2_Ih. Within the holding frame HP, in the remaining intervals except for the light emitting interval t5_h, the first scan signal GWi, the second scan signal GRi, the third scan signal GCi, and the light emission control signal EMi can all have non-activation levels. That is, within the holding frame HP, only the fourth scan signal GIi can have an activation level in the remaining intervals except for the light emitting interval t5_h.

[0125] The first section AP1_Ih and the second section AP2_Ih within the holding frame HP can be positioned at corresponding times to the first section AP1_I and the second section AP2_I within the writing frame WP described above in FIG. 4A. That is, according to this embodiment, the fourth scan signal GIi can be activated at a fixed period even during low-frequency driving, and the cathode CE of the light-emitting element ED can also be initialized at a fixed period. That is, within the duration of the writing frame WP, the correspondence relationship between the start time to the end time and the duration of the first section AP1_I, the correspondence relationship between the start time to the end time and the duration of the second section AP2_I, and within the duration of the holding frame HP, the correspondence relationship between the start time to the end time and the duration of the first section AP1_Ih, the correspondence relationship between the start time to the end time and the duration of the second section AP2_Ih can generally coincide. Through this, the change in the driving current within the holding frame HP can be minimized, so that the flicker phenomenon can be prevented from appearing due to the luminance deviation caused by the current deviation. Also, for example, the duration of the writing frame WP and the duration of the holding frame HP are generally of the same degree. Also, for example, the durations of each of the first and second sections where the fourth scan signal GIi is activated in the writing frame WP and the holding frame HP are of the same degree.

[0126] The light-emitting section t5_h within the holding frame HP can be driven in the same manner as the light-emitting section t5 within the writing frame WP. During the light-emitting section t5_h within the holding frame HP, the sixth transistor T6 and the seventh transistor T7 can be turned on, and a driving current can flow from the first driving voltage ELVDD through the light-emitting element ED, the sixth transistor T6, the first transistor T1, and the seventh transistor T7 to the second driving voltage ELVSS.

[0127] On the other hand, according to another embodiment of the present invention, the first initialization period t1_h and the second initialization period t4_h can be omitted within the holding frame HP. That is, all scan signals may have an inactive state in the remaining periods within the holding frame HP except for the light emission period t5_h.

[0128] FIG. 5A is a circuit diagram of a pixel PXij_a according to an embodiment of the present invention. FIGS. 5B and 5C are timing diagrams for explaining the operation of the pixel PXij_a of FIG. 5A according to an embodiment of the present invention. For the components illustrated in FIG. 5A that are the same as the components illustrated in FIG. 3, the same reference numerals are used and their specific descriptions are omitted.

[0129] Referring to FIGS. 5A to 5C, a pixel PXij_a according to an embodiment of the present invention includes a pixel circuit PXCa and a light emitting element ED. In this embodiment, the pixel circuit PXCa can include eight transistors T1 to T4, T5a, T6, T7, and T8a and two capacitors C1 and C2.

[0130] In this embodiment, the display panel DP (see FIG. 1) can further include a fifth scan line that outputs a fifth scan signal. FIG. 5A exemplarily shows that the pixel PXij_a is connected to an i-th fifth scan line GBLi that outputs an i-th fifth scan signal GBi among the fifth scan lines.

[0131] The eighth transistor T8a is connected between the second initialization voltage line VL3 and the cathode CE of the light emitting element ED and can receive the i-th fifth scan signal GBi. The gate electrode G8 of the eighth transistor T8a can be connected to the i-th fifth scan line GBLi. That is, the eighth transistor T8a can receive a scan signal different from that of the fifth transistor T5a, and the fifth transistor T5a and the eighth transistor T8a can be independently controlled.

[0132] As illustrated in FIG. 5B, the write frame WPa can include a first initialization section t1a, a compensation section t2a, a data writing section t3a, a second initialization section t4a, and a light emission section t5a.

[0133] According to the present embodiment, the fifth scan signal GBi can have an activation level between the first section AP1_B and the second section AP2_B in the write frame WPa. The first section AP1_B can be located before the data writing section t3a, and the second section AP2_B can be located after the data writing section t3a. In the present embodiment, the first initialization section t1a can correspond to the first section AP1_B where the fifth scan signal GBi has an activation level, and the second initialization section t4a can correspond to the second section AP2_B where the fifth scan signal GBi has an activation level. The fifth scan signal GBi can have a deactivation level between the compensation section t2a, the data writing section t3a, and the light emission section t5a. The initialization operation of the cathode CE can be performed between the first initialization section t1a and the second initialization section t4a.

[0134] As shown in FIG. 5C, the fifth scan signal GBi can have an activation level between the first section AP1_Bh and the second section AP2_Bh in the holding frame HPa. The first section AP1_Ih and the second section AP2_Ih in the holding frame HPa can be located at corresponding times to the first section AP1_I and the second section AP2_I in the write frame WPa. That is, according to the present embodiment, the fifth scan signal GBi can be activated at a fixed period even during low-frequency driving, and the cathode CE of the light-emitting element ED can also be initialized at a fixed period. That is, the correspondence relationship between the start time to the end time and the duration of the first section AP1_B, the correspondence relationship between the start time to the end time and the duration of the second section AP2_B, and the correspondence relationship between the start time to the end time and the duration of the first section AP1_Bh, the correspondence relationship between the start time to the end time and the duration of the second section AP2_Bh within the duration of the write frame WPa and within the duration of the holding frame HPa can be generally the same. Through this, the change in the drive current within the holding frame HPa can be minimized, so that the flicker phenomenon can be prevented from appearing due to the current deviation. Also, for example, the duration of the write frame WPa and the duration of the holding frame HPa are generally of the same degree. Also, for example, the durations of each of the first and second sections in which the fifth scan signal GBi is activated in the write frame WPa and the holding frame HPa are of the same degree.

[0135] According to the present embodiment, in the write frame WPa, the fourth scan signal GIi_a can be activated between the first section AP1_Ia and the second section AP2_Ia, and the first section AP1_Ia and the second section AP2_Ia in which the fourth scan signal GIi_a is activated can overlap with the first section AP1_B and the second section AP2_B in which the fifth scan signal GBi is activated, respectively. That is, the fourth scan signal GIi_a can have an activation level in the first initialization section t1a and the second initialization section t4a.

[0136] On the other hand, according to another embodiment of the present invention, the section where the fourth scan signal GIi_a is activated in the write frame WPa may overlap only with the first section AP1_B where the fifth scan signal GBi is activated, and may not overlap with the second section AP2_B where the fifth scan signal GBi is activated. That is, the fourth scan signal GIi_a may be activated only during the first initialization section t1a, and may be deactivated during the second initialization section t4a. Therefore, only the cathode CE initialization operation of the light-emitting element ED can proceed during the second initialization section t4a. Therefore, before the data writing section t3a, the source S1 initialization operation of the first transistor T1 proceeds during the first initialization section t1a, and it is not necessary to proceed with the source S1 initialization operation of the first transistor T1 after the data writing section t3a. That is, by independently controlling the fifth transistor T5a and the eighth transistor T8a, another initialization voltage can be prevented from being provided to the first node N1 after the data writing section t3a, so that the differential voltage stored in the first capacitor C1 corresponding to the data signal DS can be kept constant even after the second initialization section t4a has elapsed.

[0137] The fourth scan signal GIi_a can be deactivated in the holding frame HPa. That is, in this embodiment, only the cathode CE initialization operation of the light-emitting element ED can proceed during the first initialization section t1a_h and the second initialization section t4a_h in the holding frame HPa. By performing only the initialization operation of the cathode CE in the holding frame HPa, the change in the drive current can be minimized and the occurrence of the flicker phenomenon can be prevented. Therefore, the power consumption can be reduced by maintaining the fourth scan signal GIi_a at the deactivated level in the holding frame HPa.

[0138] FIG. 6A is a circuit diagram of a pixel PXij_b according to an embodiment of the present invention. Among the components shown in FIG. 6A, the same reference numerals are assigned to the components that are the same as those shown in FIG. 3, and the specific description thereof is omitted.

[0139] Referring to FIG. 6A, a pixel PXij_b according to an embodiment of the present invention includes a pixel circuit PXCb and a light-emitting element ED. In this embodiment, the pixel circuit PXCb can include seven transistors T1 to T7 and two capacitors C1 and C2. That is, in this embodiment, a transistor (i.e., the eighth transistor T8 (see FIG. 3)) that provides an initialization voltage to the cathode CE of the light-emitting element ED can be omitted compared to the embodiment described above with reference to FIG. 3. Through this, the configuration of the pixel circuit PXCb can be simplified and the design freedom of the pixel circuit PXCb can be increased. Also, another initialization voltage line (i.e., the second initialization voltage line VL3 (see FIG. 3)) for providing an initialization voltage to the cathode CE can be omitted. Through this, the area of the non-display region NDA (see FIG. 1) can be reduced, and the interval between wirings connected to the pixel PXij_b can be increased, so that signal interference between the wirings can be reduced.

[0140] In an embodiment of the present invention, the fourth scan signal GIi (the fourth scan signal GIi_a in FIGS. 5B and 5C) can operate as described above with reference to FIGS. 5B and 5C. That is, the fourth scan signal GIi can have an activation level between the first initialization section t1a (see FIG. 5B) and the second initialization section t4a (see FIG. 5B) within the write frame WPa (see FIG. 5B), and can have a non-activation level within the holding frame HPa (see FIG. 5C). Alternatively, the fourth scan signal GIi can have an activation level only during the first initialization section t1a (see FIG. 5B) within the write frame WPa (see FIG. 5B).

[0141] FIG. 6B is a circuit diagram of a pixel PXij_c according to an embodiment of the present invention. For the components illustrated in FIG. 6B that are the same as the components illustrated in FIG. 3, the same reference numerals are used and the specific description thereof is omitted.

[0142] Referring to FIG. 6B, a pixel PXij_c according to an embodiment of the present invention includes a pixel circuit PXCc and a light emitting element ED. In this embodiment, the pixel circuit PXCc can include eight transistors T1 to T3, T4c, and T5 to T8, and two capacitors C1, C2. In this embodiment, the third scan lines GCL1 to GCLn (see FIG. 1) that output the third scan signal can be omitted. As shown in FIG. 6B, the fourth transistor T4c can receive the i-th second scan signal GRi. The gate electrode G4 of the fourth transistor T4c can be connected to the i-th second scan line GRLi. That is, the fourth transistor T4c can receive the same scan signal as the third transistor T3, and the third transistor T3 and the fourth transistor T4c can be controlled simultaneously.

[0143] According to this embodiment, compared with the case of using another scan line for controlling each of the third transistor T3 and the fourth transistor T4c, the number of scan lines can be reduced, so that the configuration of the pixel circuit PXCc and the configuration of the scan drive circuit 300 (see FIG. 1) for panel driving can be simplified. Through this, the area of the non-display region NDA (see FIG. 1) can be reduced, and the interval between the wirings connected to the pixel PXij_c can be increased, so that the signal interference between the wirings can be reduced.

[0144] In an embodiment of the present invention, the second scan signal GRi can operate as described above with reference to FIGS. 4A to 4C. That is, the second scan signal GRi can have an activation level within the first initialization section t1 (see FIG. 4A) and the compensation section t2 (see FIG. 4A) within the write frame WPa (see FIG. 5B), and can have a non-activation level within the holding frame HP (see FIG. 4B).

[0145] FIG. 6C is a circuit diagram of a pixel PXij_d according to an embodiment of the present invention. Among the components shown in FIG. 6C, the same reference numerals are also given to the components that are the same as the components shown in FIG. 3, and the specific description thereof is omitted.

[0146] Referring to FIG. 6C, a pixel PXij_d according to an embodiment of the present invention includes a pixel circuit PXCd and a light-emitting element ED. In this embodiment, the pixel circuit PXCd can include eight transistors T1 to T8 and two capacitors C1 and C2d.

[0147] According to this embodiment, the second capacitor C2d can be connected between the second power line PL2 and the second node N2. The second capacitor C2d can include a first electrode E3d connected to the second power line PL2 and a second electrode E4 connected to the second node N2. Therefore, in this embodiment, the second capacitor C2d can store the differential voltage between the second driving voltage ELVSS and the second node N2.

[0148] FIGS. 7A and 7B are circuit diagrams of pixels PX1a and PX2a according to an embodiment of the present invention.

[0149] FIG. 7A exemplarily shows a pixel PX1a (hereinafter referred to as the first pixel PX1a) connected to the i-th first scan line GWLi and the j-th data line DLj, and FIG. 7B exemplarily shows a pixel PX2a (hereinafter referred to as the second pixel PX2a) connected to the i-th first scan line GWLi and the (j + 1)-th data line DLj+1. This exemplarily shows that the first pixel PX1a and the second pixel PX2a are arranged in the same row, and the first pixel PX1a and the second pixel PX2a can be commonly connected to the i-th first scan line GWLi, the i-th second scan line GRLi, the i-th third scan line GCLi, the i-th fourth scan line GILi, and the i-th light emission control line EMLi.

[0150] The first pixel PX1a can include a first pixel circuit PXC1a and a first light-emitting element ED1a electrically connected to the first pixel circuit PXC1a. The second pixel PX2a can include a second pixel circuit PXC2a and a second light-emitting element ED2a electrically connected to the second pixel circuit PXC2a. The first light-emitting element ED1a and the second light-emitting element ED2a can provide lights of different colors. For example, the first light-emitting element ED1a can provide light of a first color among red light, blue light, and green light, and the second light-emitting element ED2a can provide light of a second color different from the first color among red light, blue light, and green light.

[0151] The fifth transistor T5_1 included in the first pixel circuit PXC1a can be connected to a first-1 initialization voltage line VL2_1. The first-1 initialization voltage line VL2_1 can receive a first-1 initialization voltage VINT_1. The fifth transistor T5_2 included in the second pixel circuit PXC2a can be connected to a first-2 initialization voltage line VL2_2. The first-2 initialization voltage line VL2_2 can receive a first-2 initialization voltage VINT_2. The first-2 initialization voltage VINT_2 can have a voltage level different from that of the first-1 initialization voltage VINT_1. That is, according to this embodiment, the initialization voltage VINT_1 provided to the source S1 of the first transistor T1 in the first pixel circuit PXC1a and the initialization voltage VINT_2 provided to the source S1 of the first transistor T1 in the second pixel circuit PXC2 can be independently provided according to the characteristics of the respective light-emitting elements ED1a and ED2a.

[0152] FIG. 8A and FIG. 8B are circuit diagrams of pixels PX1b and PX2b according to an embodiment of the present invention.

[0153] FIG. 8A exemplarily shows a pixel PX1b (hereinafter referred to as the first pixel PX1b) connected to the i-th first scan line GWLi and the j-th data line DLj, and FIG. 8B exemplarily shows a pixel PX2b (hereinafter referred to as the second pixel PX2b) connected to the i-th first scan line GWLi and the (j + 1)-th data line DLj+1. It is exemplarily shown that the first pixel PX1b and the second pixel PX2b are arranged in the same row, and the first pixel PX1b and the second pixel PX2b can be commonly connected to the i-th first scan line GWLi, the i-th second scan line GRLi, the i-th third scan line GCLi, the i-th fourth scan line GILi, and the i-th emission control line EMLi.

[0154] The first pixel PX1b can include a first pixel circuit PXC1b and a first light-emitting element ED1b electrically connected to the first pixel circuit PXC1b. The second pixel PX2b can include a second pixel circuit PXC2b and a second light-emitting element ED2b electrically connected to the second pixel circuit PXC2b. The first light-emitting element ED1b and the second light-emitting element ED2b can provide lights of different colors. For example, the first light-emitting element ED1b can provide light of a first color which is any one of red light, blue light, and green light, and the second light-emitting element ED2b can provide light of a second color which is one of the red light, blue light, and green light other than the first color.

[0155] The eighth transistor T8_1 included in the first pixel circuit PXC1b can be connected to the second-1 initialization voltage line VL3_1. The second-1 initialization voltage line VL3_1 can receive the second-1 initialization voltage VAINT_1. The eighth transistor T8_2 included in the second pixel circuit PXC2b can be connected to the second-2 initialization voltage line VL3_2. The second-2 initialization voltage line VL3_2 can receive the second-2 initialization voltage VAINT_2. The second-2 initialization voltage VAINT_2 can have a voltage level different from that of the second-1 initialization voltage VAINT_1. That is, according to the present embodiment, the initialization voltage VAINT_1 provided to the cathode CE of the light-emitting element ED1b in the first pixel circuit PXC1b and the initialization voltage VAINT_2 provided to the cathode CE of the light-emitting element ED2b in the second pixel circuit PXC2b can be independently provided according to the characteristics of the respective light-emitting elements ED1b and ED2b.

[0156] For example, different amounts of parasitic capacitance can be formed in the light-emitting elements ED1b and ED2b that provide lights of different colors. According to an embodiment, in reflection of the parasitic capacitance formed in each of the first light-emitting element ED1b that provides the first color light and the second light-emitting element ED2b that provides the second color light, different levels of the second-1 and second-2 initialization voltages VAINT_1 and VAINT_2 can be provided to the cathode CE of the first light-emitting element ED1b and the cathode CE of the second light-emitting element ED2b, respectively. Through this, since the gradation can be improved and the color expression ability to be changed can also be improved, a display device DD (see FIG. 1) with improved display quality can be provided.

[0157] FIGS. 9A and 9B are cross-sectional views of display panels DP and DPa according to an embodiment of the present invention. FIG. 10 is a cross-sectional view of a display panel DPb according to an embodiment of the present invention. FIG. 11 is a cross-sectional view of a display panel DPc according to an embodiment of the present invention. In FIGS. 9A to 10, a part of the display area DA is enlarged and illustrated, and in FIG. 11, a part of the display area DA and a part of the non-display area NDA are enlarged and illustrated.

[0158] Referring to FIG. 9A, the display panel DP can include a base layer BL, a circuit element layer DP-CL disposed on the base layer BL, a display element layer DP-ED, and a sealing layer ESL. The circuit element layer DP-CL includes at least a plurality of insulating layers and circuit elements. The insulating layers described below can include organic layers and / or inorganic layers.

[0159] Insulating layers, semiconductor layers, and conductive layers are formed through processes such as coating and vapor deposition. Thereafter, the insulating layers, semiconductor layers, and conductive layers can be selectively patterned through photolithography and etching processes. Semiconductor patterns, conductive patterns, signal lines, etc. are formed through such processes. Patterns disposed on the same layer are formed through the same process.

[0160] The base layer BL can include a synthetic resin layer. The synthetic resin layer can include a thermosetting resin. In particular, the synthetic resin layer is a polyimide-based resin layer, and its material is not particularly limited. The synthetic resin layer can include at least any one of an acrylic resin, a methacrylic resin, polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin. In addition, the base layer BL can include a glass substrate, a metal substrate, or an organic / inorganic composite material substrate, etc. The base layer BL can include a first polyimide layer, a second polyimide layer, and an inorganic layer disposed therebetween.

[0161] Form at least one inorganic layer on the upper surface of the base layer BL. The inorganic layer can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer can be formed in multiple layers. The multi-layer inorganic layer can constitute the barrier layer BRL described later. The barrier layer BRL prevents foreign substances from flowing in from the outside. The barrier layer BRL can include a silicon oxide layer and a silicon nitride layer. Each of these can be provided in plurality, and the silicon oxide layer and the silicon nitride layer can be alternately laminated. For example, the base layer BL can include a first synthetic resin layer, a silicon oxide (SiOx) layer disposed on the first synthetic resin layer, an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, and a second synthetic resin layer disposed on the amorphous silicon layer. The silicon oxide layer and the amorphous silicon layer can be referred to as a base barrier layer.

[0162] The lower conductive layer BML can be disposed on the barrier layer BRL. The lower conductive layer BML can be provided in a pattern form and can be disposed to overlap each transistor. The lower conductive layer BML can block the electrical potential due to the polarization development of the base layer BL from affecting the transistor. Also, the lower conductive layer BML can block the light incident on the transistor from below.

[0163] The lower conductive layer BML can include a reflective metal. For example, the lower conductive layer BML can include titanium (Ti), molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), and copper (Cu), etc.

[0164] The lower conductive layer BML can be provided in an isolated form. Or, the lower conductive layer BML can be synchronized with the source or gate of the transistor. Or, the lower conductive layer BML can be connected to other electrodes and a constant voltage or a pulse signal can be applied independently. The lower conductive layer BML according to an embodiment of the present invention can be provided in various forms and is not limited to any one embodiment.

[0165] A first insulating layer 10 can be disposed on the barrier layer BRL. The first insulating layer 10 can be referred to as a buffer layer. The first insulating layer 10 can improve the bonding force between the barrier layer BRL and the semiconductor pattern and / or the conductive pattern. The first insulating layer 10 can include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer can be alternately laminated.

[0166] A semiconductor layer can be disposed on the first insulating layer 10. The semiconductor layer can include a plurality of oxide semiconductor patterns SP1, SP2. Each of the oxide semiconductor patterns SP1, SP2 can include a crystalline or amorphous oxide semiconductor. For example, each of the oxide semiconductor patterns SP1, SP2 can include a metal oxide such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), or a mixture of these metals and their oxides. Each of the oxide semiconductor patterns SP1, SP2 can include indium-tin oxide (ITO), indium-gallium-zinc oxide (IGZO), zinc oxide (ZnO), indium-zinc oxide (IZnO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-zinc-tin oxide (IZTO), zinc-tin oxide (ZTO), etc.

[0167] Each of the oxide semiconductor patterns SP1 and SP2 can include a plurality of regions classified according to whether the metal oxide is reduced. A region where the metal oxide is reduced (hereinafter, reduction region) has higher conductivity than a region where it is not (hereinafter, non-reduction region). The reduction region substantially serves as a source region, a drain region, or a signal transmission region of a transistor. The non-reduction region substantially corresponds to the channel region (or semiconductor region, or non-reduction region) of the transistor. In other words, a part of the semiconductor pattern is the channel region of the transistor, another part is the source region or drain region of the transistor, and still another part can be the signal transmission region.

[0168] The source region or drain region itself can be the source S1 to S8 or drain D1 to D8 of the transistors T1 to T8 described in FIG. 3. The source S1 to S8 or drain D1 to D8 of the transistors T1 to T8 may include the source region or drain region of the oxide semiconductor patterns SP1 and SP2 described above and a conductive pattern connected thereto. Hereinafter, for simplicity of explanation, the source region or drain region of the oxide semiconductor patterns SP1 and SP2 is referred to as a source or a drain.

[0169] FIG. 9A exemplarily shows the second transistor T2 and the fourth transistor T4 among the transistors T1 to T8 in FIG. 3. The second transistor T2 can include a first oxide semiconductor pattern SP1 including a source S2, a first channel portion CH1, and a drain D2. The source S2 and the drain D2 of the second transistor T2 can extend in opposite directions from the first channel portion CH1. The fourth transistor T4 can include a second oxide semiconductor pattern SP2 including a source S4, a second channel portion CH2, and a drain D4. The source S4 and the drain D4 of the fourth transistor T4 can extend in opposite directions from the second channel portion CH2. The description regarding the first and second oxide semiconductor patterns SP1 and SP2 can be similarly applied to the oxide semiconductor patterns of the remaining transistors not shown in FIG. 9A.

[0170] A second insulating layer 20 covering the oxide semiconductor patterns SP1 and SP2 can be disposed on the first insulating layer 10. The second insulating layer 20 is an inorganic layer and / or an organic layer and can have a single-layer or multi-layer structure. The second insulating layer 20 can contain at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0171] Gate electrodes G2 and G4 can be disposed on the second insulating layer 20. The gate electrodes G2 and G4 can be disposed above the oxide semiconductor patterns SP1 and SP2, respectively. However, this is shown by way of example, and the gate electrodes G2 and G4 can be disposed below the semiconductor patterns SP1 and SP2, respectively.

[0172] FIG. 9A exemplarily illustrates the gate electrode G2 of the second transistor T2 and the gate electrode G4 of the fourth transistor T4. The gate electrode G2 of the second transistor T2 can be disposed on the channel portion CH1 of the first oxide semiconductor pattern SP1, and the gate electrode G4 of the fourth transistor T4 can be disposed on the channel portion CH2 of the second oxide semiconductor pattern SP2. The description regarding the gate electrodes G2 and G4 of the second and fourth transistors T2 and T4 can be similarly applied to the gate electrodes of the remaining transistors not shown in FIG. 9A.

[0173] The gate electrodes G2 and G4 can contain titanium (Ti), silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), or an alloy thereof, etc., but are not particularly limited thereto.

[0174] On the second insulating layer 20, a third insulating layer 30 covering the gate electrodes G2 and G4 can be disposed. A fourth insulating layer 40 can be disposed on the third insulating layer 30. Each of the third insulating layer 30 and the fourth insulating layer 40 is an inorganic layer and / or an organic layer, and can have a single-layer or multi-layer structure. In one embodiment, each of the third insulating layer 30 and the fourth insulating layer 40 can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0175] A number of conductive patterns can be disposed on the fourth insulating layer 40. In the present embodiment, the conductive patterns disposed on the fourth insulating layer 40 can include a connection electrode CNE, a data line DLj, a first power line PL1, and a second power line PL2.

[0176] FIG. 9A exemplarily shows a connection electrode CNE to which a cathode CE is connected. Although not shown in FIG. 9A, the connection electrode CNE to which the cathode CE is connected can be connected to the source S6 of the sixth transistor T6 described above in FIG. 2 through a contact hole penetrating the second to fourth insulating layers 20, 30, 40. Although FIG. 9A exemplarily shows only the connection electrode CNE to which the cathode CE is connected, a plurality of connection electrodes connected to the drain and source of each transistor can be disposed on the second insulating layer 20.

[0177] FIG. 9A exemplarily shows a part of the first power line PL1. The first power line PL1 can be connected to the drain D4 of the fourth transistor T4 through a contact hole penetrating the second to fourth insulating layers 20, 30, 40. On the other hand, a connection electrode connected to the drain D4 of the fourth transistor T4 among the connection electrodes can be provided integrally with the first power line PL1. In the present embodiment, the first power line PL1 can include a Ti / Al / Ti structure.

[0178] FIG. 9A exemplarily illustrates a part of the data line DLj. The data line DLj can be connected to the source S2 of the second transistor T2 through a contact hole penetrating the second to fourth insulating layers 20, 30, 40. On the other hand, among the connection electrodes, the connection electrode connected to the source S2 of the second transistor T2 can be provided integrally with the data line DLj.

[0179] FIG. 9A exemplarily illustrates a part of the second power line PL2. In the present embodiment, the second power line PL2 can be arranged on the same layer as the first power line PL1. Also, the first and second power lines PL1, PL2 can be arranged on the same layer as the data line DLj.

[0180] The second power line PL2 can contain the same material as the first power line PL1. According to the present embodiment, the second power line PL2 can include a Ti / Al / Ti structure. Since the second power line PL2 has a low specific resistance, the amount of noise due to the voltage drop and ripple generation of the second power line PL2 can be reduced. The source S1 (see FIG. 3) of the first transistor T1 (see FIG. 3), which is called a driving transistor, is electrically connected to the second power line PL2 with reduced noise, and it is possible to prevent the voltage level of the source S1 (see FIG. 3) of the first transistor T1 (see FIG. 3) from fluctuating. Also, the light-emitting element ED is connected between the drain D1 (see FIG. 3) of the first transistor T1 (see FIG. 3) and the first power line PL1, and the voltage level of the source S1 (see FIG. 3) of the first transistor T1 (see FIG. 3) can be prevented from being affected by the specific resistance of the material included in one electrode of the light-emitting element ED. Through this, it is possible to prevent the driving current of the light-emitting element ED from fluctuating. Therefore, the display quality of the display device DD (see FIG. 1) can be improved.

[0181] The fifth insulating layer 50 can be disposed on the fourth insulating layer 40. The fifth insulating layer 50 can cover the connection electrode CNE, the data line DLj, the first power line PL1, and the second power line PL2 disposed on the fourth insulating layer 40. In this embodiment, the fifth insulating layer 50 is an organic layer and can have a single-layer structure, but is not particularly limited.

[0182] The cathode CE of the light-emitting element ED can be disposed on the fifth insulating layer 50. The cathode CE can be connected to the connection electrode CNE through a contact hole penetrating the fifth insulating layer 50. In this embodiment, the cathode CE can include a structure of ITO / Ag / ITO.

[0183] The pixel definition film PDL can be disposed on the fifth insulating layer 50. The opening OP-PDL of the pixel definition film PDL (hereinafter, the light-emitting opening) can expose at least a part of the cathode CE. The light-emitting opening OP-PDL of the pixel definition film PDL can define a light-emitting region. For example, a plurality of pixels PX (see FIG. 1) can be arranged in a certain rule on the plane of the display panel DP. The region where the plurality of pixels PX (see FIG. 1) are arranged can be defined as a pixel region, and one pixel region can include a light-emitting region and a non-light-emitting region adjacent to the light-emitting region. The non-light-emitting region can surround the light-emitting region.

[0184] The pixel definition film PDL can be an organic layer. For example, the pixel definition film PDL can include general-purpose polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), PMMA (Polymethylmethacrylate), and PS (Polystyrene), polymer derivatives having a phenolic group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0185] In one embodiment, the pixel definition layer PDL can have the property of absorbing light and can, for example, have a black color. The pixel definition layer PDL can include a black coloring agent. The black coloring agent can include a black dye and a black pigment. The black coloring agent can include carbon black, a metal such as chromium, or an oxide thereof. The pixel definition layer PDL can correspond to a light-shielding pattern having light-shielding characteristics.

[0186] An intermediate layer IML can be disposed on the cathode CE. The intermediate layer IML can include at least an emission layer EML. In one embodiment, the intermediate layer IML can include a functional layer FNL and an emission layer EML. The functional layer FNL can control the movement of charges between the cathode CE and the anode AE. For example, the functional layer FNL can be provided by a plurality of layers or can be provided by two or more layers separated via the emission layer EML. FIG. 9A exemplarily illustrates that the functional layer FNL includes an electron control layer ECL and a hole control layer HCL.

[0187] The electron control layer ECL can be disposed on the cathode CE. The electron control layer ECL can include at least one of an electron injection layer and an electron transport layer. In one embodiment, the electron control layer can further include a hole blocking layer.

[0188] The emission layer EML can be disposed on the electron control layer ECL. The emission layer EML can be disposed only in a region corresponding to the emission opening OP-PDL. The emission layer EML can be formed separately for each of a plurality of pixels PX (see FIG. 1). Although the patterned emission layer EML in this embodiment is exemplarily illustrated, the emission layer EML can be disposed commonly for a plurality of pixels PX. The commonly disposed emission layer EML can generate white light or blue light. Also, the emission layer EML can have a multilayer structure.

[0189] A hole control layer HCL can be disposed on the light-emitting layer EML. The hole control layer HCL can include at least one of a hole injection layer and a hole transport layer. The hole transport layer can include at least one of a hole buffer layer and an electron blocking layer.

[0190] An anode AE can be disposed on the hole control layer HCL. That is, according to this embodiment, within the light-emitting aperture OP-PDL, the light-emitting layer EML is disposed on the cathode CE, and the anode AE can be disposed on the light-emitting layer EML. In this embodiment, a plurality of anodes AE are provided, and the anodes AE can be separately arranged in a pattern form for each of a plurality of pixels PX (see FIG. 1). Each of the anodes AE can be connected to a second power line PL2 through a contact hole penetrating the pixel defining film PDL and the fifth insulating layer 50 in a non-light-emitting region within the display area DA. In this embodiment, the anode AE can be directly in contact and connected to the first power line PL1.

[0191] By separately providing the anode AE for each of the pixels PX (see FIG. 1), voltage drop can be reduced or prevented as compared with the case where the anode AE is provided as a common layer. Through this, it is not necessary to provide the anode AE thickly corresponding to the degree of voltage drop, and it is possible to prevent the display efficiency from decreasing. In this embodiment, the anode AE can include an MgAg alloy.

[0192] The display panel DP can further include a sealing layer ESL disposed on the display element layer DP-ED to seal the display element layer DP-ED. The sealing layer ESL can include at least an inorganic layer or an organic layer, and in one embodiment, the sealing layer ESL can include two inorganic layers IL1, IL2 and an organic layer OL disposed therebetween. Also, the display panel DP can further include a functional layer such as an anti-reflection layer or a refractive index adjustment layer.

[0193] Referring to FIG. 9B, the display panel DPa according to the present embodiment can include a base layer BL, a circuit element layer DP-CLa, and a display element layer DP-ED. For the components identical to those illustrated in FIG. 9A among the components illustrated in FIG. 9B, the same reference numerals are used in combination, and the specific description thereof is omitted.

[0194] The circuit element layer DP-CLa according to the present embodiment can further include a sixth insulating layer 60 disposed on the fifth insulating layer 50 as compared with the embodiment illustrated in FIG. 9A.

[0195] A first connection electrode CNE1 and a data line DLj can be disposed on the fourth insulating layer 40. Although only the first connection electrode CNE1 connected to the drain D4 of the fourth transistor T4 is exemplarily illustrated in FIG. 9B, a plurality of first connection electrodes connected to the drain and source of each transistor can be disposed on the fourth insulating layer 40.

[0196] A second connection electrode CNE2 to which a cathode CE is connected, a first power line PL1a, and a second power line PL2a can be disposed on the fourth insulating layer 40. Although not illustrated in FIG. 9B, the second connection electrode CNE2 can be connected to the first connection electrode CNE1 connected to the source S6 of the sixth transistor T6, and can be electrically connected to the sixth transistor T6 by the first connection electrode CNE1. The first power line PL1a can be connected to the first connection electrode CNE1 connected to the drain D4 of the fourth transistor T4 through a contact hole penetrating the fifth insulating layer 50. The first power line PL1a can be electrically connected to the drain D4 of the fourth transistor T4 through the first connection electrode CNE1.

[0197] In this embodiment, the first power line PL1a and the second power line PL2a can be arranged on a layer different from the data line DLj. However, the arrangement of the data line DLj, the first power line PL1a, and the second power line PL2a is not limited to any one embodiment. For example, the first power line PL1a and the second power line PL2a may be arranged on different layers from each other. One of the first power line PL1a and the second power line PL2a can be arranged on the fourth insulating layer 40, and the other one can be arranged on the fifth insulating layer 50.

[0198] Referring to FIG. 10, the display panel DPb according to this embodiment can include a base layer BL, a circuit element layer DP-CLb, and a display element layer DP-ED. For the components that are the same as the components shown in FIG. 9A among the components shown in FIG. 10, the same reference numerals are used together, and the specific description thereof is omitted.

[0199] The circuit element layer DP-CLb according to this embodiment can further include a connection conductive pattern CNP that connects the anode AE and the first power line PL1 compared to the embodiments shown in FIGS. 9A and 9B. The connection conductive pattern CNP is arranged on the fourth insulating layer 40 and can cover the first power line PL1. Therefore, the anode AE can be connected to the connection conductive pattern CNP through a contact hole that penetrates the fifth insulating layer 50 and the pixel definition film PDL, and can be electrically connected to the first power line PL1 through the connection conductive pattern CNP.

[0200] In this embodiment, the connection conductive pattern CNP can include indium tin oxide (ITO). The connection conductive pattern CNP can include the same material as the material arranged on the uppermost layer of the first power line PL1. However, the material of the connection conductive pattern CNP is not limited thereto.

[0201] According to the present embodiment, by providing a connecting conductive pattern CNP that covers the first power line PL1, damage to the first power line PL1 can be prevented in subsequent processes, for example, in the process of forming contact holes penetrating the fifth insulating layer 50.

[0202] Referring to FIG. 11, the display panel DPc according to the present embodiment can include a base layer BL, a circuit element layer DP-CLc, and a display element layer DP-EDc. For components that are the same as those illustrated in FIG. 9A among the components illustrated in FIG. 11, the same reference numerals are used in combination, and their specific descriptions are omitted.

[0203] The anode AEc according to the present embodiment can be commonly arranged for a plurality of pixels PX (see FIG. 1) as compared with the embodiments illustrated in FIGS. 9A to 11. The anode AEc commonly arranged for the pixels PX (see FIG. 1) can be connected to the first power line PL1c in the non-display area NDA. FIG. 11 exemplarily illustrates that the anode AEc is connected to the first power line PL1c through a contact hole penetrating the pixel definition film PDLc and the fifth insulating layer 50c in the non-display area NDA, but it is not limited thereto. For example, the first power line may be arranged outside the pixel definition film and the fifth insulating layer. At this time, the anode can be extended along the edges of the pixel definition film and the fifth insulating layer and connected to the first power line outside the pixel definition film and the fifth insulating layer.

[0204] According to the present embodiment, since contact holes for connecting the anode AEc and the first power line PL1c to the fifth insulating layer 50c and the pixel definition film PDLc for each pixel PX (see FIG. 1) do not need to be formed within the display area DA, the process can be relatively simplified.

[0205] FIG. 12 is a cross-sectional view of a display panel according to an embodiment of the present invention.

[0206] Referring to FIG. 12, the display panel DP can include a base layer BL, a circuit element layer DP-CL' disposed on the base layer BL, an upper insulating layer UIL, a connection wiring CN, a display element layer DP-ED', and a sealing layer ESL.

[0207] FIG. 12 illustrates one transistor TR and two capacitors C1 and C2 in the pixel driving unit PXC. The transistor TR is a transistor connected to the light emitting element ED' through the connection wiring CN, that is, corresponding to a node (for example, the fourth node N4 in FIG. 3) corresponding to the cathode CE' of the light emitting element ED', and specifically can correspond to the sixth transistor T6 in FIG. 3. On the other hand, although not shown, other transistors constituting the pixel driving unit PXC can have the same structure as the transistor TR (hereinafter, the connection transistor) shown in FIG. 12. However, this is an illustrative explanation, and other transistors constituting the pixel driving unit PXC can also have a structure different from the connection transistor TR and are not limited to any one embodiment.

[0208] The lower conductive layer BML is disposed to overlap the connection transistor TR and can be covered by the first insulating layer 10. At least one of an inorganic barrier layer and a buffer layer can be further disposed between the lower conductive layer BML and the base layer BL.

[0209] In this embodiment, the lower conductive layer BML can be connected to the source of the connection transistor TR (or, the transistor) through the source electrode pattern W1. In this case, the lower conductive layer BML can be synchronized with the source of the transistor TR. However, this is an illustrative example, and the lower conductive layer BML can be connected to the gate of the transistor TR and synchronized with the gate. Or, the lower conductive layer BML can be connected to other electrodes and a constant voltage or a pulse signal can be independently applied. Or, the lower conductive layer BML can be provided in an isolated form from other conductive patterns. The lower conductive layer BML according to an embodiment of the present invention can be provided in various forms and is not limited to any one embodiment.

[0210] A connection transistor TR can be arranged on the first insulating layer 10. The connection transistor TR can include a semiconductor pattern SP and a gate electrode GE. The semiconductor pattern SP can be arranged on the first insulating layer 10. The semiconductor pattern SP can include a source region SR, a drain region DR, and a channel region CHR that are classified according to the degree of conductivity.

[0211] The display panel according to the present embodiment may further include another source electrode pattern W1 and drain electrode pattern W2 respectively connected to the source region SR and the drain region DR. Specifically, the other source electrode pattern W1 and drain electrode pattern W2 can be integrally formed with one of the lines constituting the pixel driving unit, and are not limited to any one embodiment.

[0212] The second insulating layer 20 can commonly overlap a plurality of pixels and cover the semiconductor pattern SP. The gate electrode GE can be arranged on the second insulating layer 20. The gate electrode GE can correspond to the gate of the connection transistor TR.

[0213] A third insulating layer 30 is arranged on the gate electrode GE, and a fourth insulating layer 40 can be arranged on the third insulating layer 30. The plurality of conductive patterns can include a first capacitor electrode CPE1, a second capacitor electrode CPE2, and a third capacitor electrode CPE3.

[0214] The first capacitor electrode CPE1 and the second capacitor electrode CPE2 constitute a first capacitor C1. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 can be separated via the first insulating layer 10 and the second insulating layer 20.

[0215] In one embodiment of the present invention, the first capacitor electrode CPE1 and the lower conductive layer BML may have an integral shape. Also, the second capacitor electrode CPE2 and the gate electrode GE may have an integral shape.

[0216] The third capacitor electrode CPE3 can be disposed on the third insulating layer 30. The third capacitor electrode CPE3 is separated from the second capacitor electrode CPE2 via the third insulating layer 30 and can overlap in a plane. The third capacitor electrode CPE3 and the second capacitor electrode CPE2 can form the second capacitor C2.

[0217] A fourth insulating layer 40 can be disposed on the third insulating layer 30 and / or the third capacitor electrode CPE3. A source electrode pattern W1 and a drain electrode pattern W2 can be disposed on the fourth insulating layer 40. The source electrode pattern W1 can be connected to the source region SR of the connection transistor TR through the first contact hole CNT1, and the source electrode pattern W1 and the source region SR of the semiconductor pattern SP can function as the source of the connection transistor TR. The drain electrode pattern W2 can be connected to the drain region DR of the connection transistor TR through the second contact hole CNT2, and the drain electrode pattern W2 and the drain region DR of the semiconductor pattern SP can function as the drain of the connection transistor TR. On the other hand, the source electrode pattern W1 and the drain electrode pattern W2 can also be disposed in the display panels DP, DPa, DPb, DPc described above in FIGS. 9A to 11. A fifth insulating layer 50 can be disposed on the source electrode pattern W1 and the drain electrode pattern W2.

[0218] A connection wiring CN can be disposed on the fifth insulating layer 50. The connection wiring CN can electrically connect the pixel driving unit PXC and the light emitting element ED'. That is, the connection wiring CN can electrically connect the connection transistor TR and the light emitting element ED'. The connection wiring CN can be a connection node that connects the pixel driving unit PXC and the light emitting element ED'. That is, the connection wiring CN can correspond to the fourth node N4 (see FIG. 3) shown in FIG. 3. On the other hand, this is an illustrative explanation, and as long as the connection wiring CN can be connected to the light emitting element ED', it can be defined as a connection node with various elements among the elements constituting the pixel driving unit PXC according to the design of the pixel driving unit PXC, and is not limited to any one embodiment.

[0219] An upper insulating layer UIL can be disposed on the connection wiring CN. The upper insulating layer UIL can be disposed on the fifth insulating layer 50 to cover the connection wiring CN. The upper insulating layer UIL can be an organic layer. For example, the upper insulating layer UIL can include general-purpose polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), PMMA (Polymethylmethacrylate), and PS (Polystyrene), polymer derivatives having a phenolic group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0220] The upper insulating layer UIL can be provided with an opening that exposes at least a part of the connection wiring CN. The connection wiring CN can be electrically connected to the light emitting element ED' through a part exposed from the upper insulating layer UIL. That is, the connection wiring CN can electrically connect the connection transistor TR and the light emitting element ED'. A detailed explanation thereof will be described later. On the other hand, in the display panel DP according to an embodiment of the present invention, the upper insulating layer UIL may be omitted, may be provided in plurality, and is not limited to any one embodiment.

[0221] On the upper insulating layer UIL, a display element layer DP-ED' can be arranged. The display element layer DP-ED' can include a pixel definition layer PDL, a light-emitting element ED', and a separator SPR. The light-emitting element ED' can include an anode AE', an intermediate layer IML', and a cathode CE'.

[0222] In this embodiment, the anode AE' can be arranged on the upper insulating layer UIL. The anode AE' can be a semi-transmissive, transmissive, or reflective electrode. According to an embodiment of the present invention, the anode AE' can include a reflective layer formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof, etc., and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer can include at least one or more selected from the group including indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3), and aluminum-doped zinc oxide (AZO). For example, the anode AE' can include a laminated structure of ITO / Ag / ITO. The anode AE' can be connected to a first power line PL1 (see FIG. 3), and a first driving voltage ELVDD (see FIG. 3) can be applied.

[0223] In the pixel definition layer PDL, a light-emitting opening OP-PDL that exposes at least a part of the anode AE' can be defined. The light-emitting openings OP-PDL can be provided in a plurality and arranged corresponding to each light-emitting element. All components of the light-emitting element ED' can be superposed and arranged in the light-emitting opening OP-PDL, and it can be a region where the light substantially emitted by the light-emitting element ED' is displayed.

[0224] The intermediate layer IML’ can be disposed between the anode AE’ and the cathode CE’. The intermediate layer IML’ can include a light-emitting layer EML and a functional layer FNL’. The light-emitting element ED’ can include intermediate layers IML’ of various structures and is not limited to any one embodiment. For example, the functional layer FNL’ can be provided by a plurality of layers, or can be provided by two or more layers separated via the light-emitting layer EML. Alternatively, in one embodiment, the functional layer FNL’ may be omitted. In FIG. 12, an embodiment is illustrated in which the light-emitting layer EML and the functional layer FNL’ have different shapes from each other, but is not limited thereto, and the light-emitting layer EML and the functional layer FNL’ may be arranged in the same planar shape.

[0225] The functional layer FNL’ can be disposed between the anode AE’ and the cathode CE’. Specifically, the functional layer FNL’ can be disposed between the anode AE’ and the light-emitting layer EML, or can be disposed between the cathode CE’ and the light-emitting layer EML. Alternatively, the functional layer FNL’ can be disposed between the anode AE’ and the light-emitting layer EML and between the cathode CE’ and the light-emitting layer EML. In this embodiment, the light-emitting layer EML is shown as being inserted into the functional layer FNL’. However, this is shown by way of example, and the functional layer FNL’ can include a layer disposed between the light-emitting layer EML and the anode AE’ and / or a layer disposed between the light-emitting layer EML and the cathode CE’, each of which may be provided in plurality and is not limited to any one embodiment. The functional layer FNL’ can include a hole control layer and an electron control layer, and at least a part of the hole control layer can be disposed between the anode AE’ and the light-emitting layer EML, and at least a part of the electron control layer can be disposed between the light-emitting layer EML and the cathode CE’.

[0226] The cathode CE’ can be disposed on the intermediate layer IML’. As described above, the cathode CE’ can be connected to the connection wiring CN and electrically connected to the pixel driving unit PXC. That is, the cathode CE’ can be electrically connected to the connection transistor TR through the connection wiring CN.

[0227] As described above, the connection wiring CN can include a drive connection part CDP and a light-emitting connection part CEP. The drive connection part CDP is a part of the connection wiring CN that is connected to the pixel drive part PXC, and can be a part that is substantially connected to the connection transistor TR. In this embodiment, the drive connection part CDP can penetrate the fifth insulating layer 50 and be electrically connected to the drain region DR of the semiconductor pattern SP through the drain electrode pattern W2. The light-emitting connection part CEP can be a part of the connection wiring CN that is connected to the light-emitting element ED'. The light-emitting connection part CEP is defined in the region exposed from the upper insulating layer UIL and can be a part to which the cathode CE' is connected. At this time, a chip part TP can be defined in the light-emitting connection part CEP.

[0228] Referring to FIGS. 12 and 13A, the light-emitting connection part CEP of the connection wiring CN will be described in more detail. As shown in FIGS. 12 and 13A, the connection wiring CN can have a three-layer structure. Specifically, the connection wiring CN can include a first layer L1, a second layer L2, and a third layer L3 that are sequentially stacked along the third direction DR3. The second layer L2 can include a different material from the first layer L1. Also, the second layer L2 can include a different material from the third layer L3. The second layer L2 can have a relatively thick thickness compared to the first layer L1. Also, the second layer L2 can have a relatively thick thickness compared to the third layer L3. The second layer L2 can include a material with high conductivity. In one embodiment, the second layer L2 can include aluminum (Al).

[0229] On the one hand, the first layer L1 can contain a material with a lower etching rate than the second layer L2. That is, the second layer L2 can be composed of a material with a high etching selectivity with respect to the first layer L1. In one embodiment, the first layer L1 can contain titanium (Ti), and the second layer L2 can contain aluminum (Al). In this case, the side surface L1_W of the first layer L1 can be defined outside the side surface L2_W of the second layer L2. That is, the light-emitting connection portion CEP of the connection wiring CN can have a shape in which the side surface L1_W of the first layer L1 protrudes outside from the side surface L2_W of the second layer L2. That is, the light-emitting connection portion CEP of the connection wiring CN can have a shape in which the side surface L2_W of the second layer L2 is recessed inward from the side surface L1_W of the first layer L1.

[0230] Also, the third layer L3 can contain a material with a lower etching rate than the second layer L2. That is, the third layer L3 and the second layer L2 can be composed of materials with a high etching selectivity with respect to each other. In one embodiment, the third layer L3 can contain titanium (Ti), and the second layer L2 can contain aluminum (Al). In this case, the side surface L3_W of the third layer L3 can be defined outside the side surface L2_W of the second layer L2. That is, the light-emitting connection portion CEP of the connection wiring CN can have a shape in which the side surface L3_W of the third layer L3 protrudes outside from the side surface L2_W of the second layer L2. That is, the light-emitting connection portion CEP of the connection wiring CN can have an undercut shape or an overhang structure, and the chip portion TP of the light-emitting connection portion CEP can be defined by a portion of the third layer L3 that protrudes compared to the second layer L2.

[0231] The upper insulating layer UIL and the pixel definition film PDL can expose at least a part of the chip portion TP and at least a part of the second side surface L2_W. Specifically, a first opening OP1 that exposes one side of the connection wiring CN can be defined in the upper insulating layer UIL, and a second opening OP2 that overlaps the first opening OP1 can be defined in the pixel definition film PDL. The planar area of the second opening OP2 can be larger than the planar area of the first opening OP1. However, the present invention is not limited thereto. As long as at least a part of the chip portion TP and at least a part of the second side surface L2_W can be exposed, the planar area of the second opening OP2 may be smaller than the planar area of the first opening OP1, or may be the same.

[0232] An intermediate layer IML' can be disposed on the pixel definition film PDL. The intermediate layer IML' can also be disposed on a partial region of the upper insulating layer UIL exposed by the second opening OP2 of the pixel definition film PDL. Further, the intermediate layer IML' can also be disposed on a partial region of the connection wiring CN exposed by the first opening OP1 of the upper insulating layer UIL. As shown in FIG. 13A, the intermediate layer IML' can include one end IN1 disposed along the upper surface of the fifth insulating layer 50 and the other end IN2 disposed along the upper surfaces of the connection wiring CN and the chip portion TP. That is, when viewed in cross section, the intermediate layer IML' can have a shape in which the connection is partially broken with respect to the chip portion TP in the region where the light-emitting connection portion CEP is defined. However, when viewed in plan, the intermediate layer IML' can have an integral shape that is entirely connected within the region defined by the closed line by the separator SPR (see FIG. 15A).

[0233] A cathode CE' can be disposed on the intermediate layer IML'. The cathode CE' can also be disposed on a partial region of the upper insulating layer UIL exposed by the second opening OP2 of the pixel definition layer PDL. Further, the cathode CE' can also be disposed on a partial region of the connection wiring CN exposed by the first opening OP1 of the upper insulating layer UIL. As shown in FIG. 13A, the cathode CE' can include one end EN1 of the cathode CE' disposed along the upper surface of the fifth insulating layer 50 and the other end EN2 disposed along the upper surfaces of the connection wiring CN and the chip portion TP. That is, when viewed in cross section, the cathode CE' can have a shape in which the connection is partially broken with respect to the chip portion TP in a region where the light-emitting connection portion CEP is defined. However, when viewed in plan, the cathode CE' can have an integral shape that is entirely connected within a region defined by a closed curve by the separator SPR (see FIG. 15A).

[0234] On the other hand, one end EN1 of the cathode CE' can be disposed along the side surface of the second layer L2 and can contact the side surface L2_W of the second layer L2. Specifically, through the difference in the deposition angle between the cathode CE' and the intermediate layer IML', the cathode CE' can be formed to contact the side surface L2_W of the second layer L2 exposed from the intermediate layer IML' by the chip portion TP. That is, the cathode CE' can be connected to the connection wiring CN without a separate patterning process for the intermediate layer IML', and thus the light-emitting element ED' can be electrically connected to the pixel driving portion PXC through the connection wiring CN.

[0235] Also, in the present embodiment, the other end IN2 of the intermediate layer IML' and the other end EN2 of the cathode CE' are shown covering the side surface L3_W of the third layer L3, but this is shown by way of example, and at least a part of the side surface L3_W of the third layer L3 may be exposed from the other end IN2 of the intermediate layer IML' and / or the other end EN2 of the cathode CE'.

[0236] The display panel DP' according to this embodiment can include a separator SPR. The separator SPR can be disposed on the pixel definition layer PDL. In one embodiment, the cathode CE' and the intermediate layer IML' can be formed by co-evaporating a plurality of pixels through an open mask. At this time, the cathode CE' and the intermediate layer IML' can be divided by the separator SPR. As described above, the separator SPR can have a closed line shape for each light emitting unit, and thus the cathode CE' and the intermediate layer IML' can have a shape divided for each light emitting unit. That is, the cathode CE' and the intermediate layer IML' can be electrically independent for each adjacent pixel.

[0237] Referring to FIGS. 12 and 13B, the separator SPR will be described in more detail. As illustrated in FIG. 13B, the separator SPR can have an inverted taper shape. That is, the angle θ (hereinafter, the taper angle) formed by the side surface SPR_W of the separator SPR with respect to the upper surface of the pixel definition layer PDL can be an obtuse angle. However, this is merely an exemplary illustration, and the taper angle θ can be variously set as long as the separator SPR can electrically disconnect the cathode CE' for each pixel. In addition, the separator SPR can also have a structure such as a chip portion TP and is not limited to any one embodiment.

[0238] In one embodiment, the separator SPR can include a material having insulating properties, and particularly can include an organic insulating material. The separator SPR may include an inorganic insulating material, and an organic insulating substance and an inorganic insulating substance may be formed in multiple layers, and a conductive substance may also be included according to the embodiment. That is, as long as the cathode CE' can be electrically disconnected for each pixel, the separator SPR is not particularly limited with respect to the type of material.

[0239] A dummy layer UP can be disposed on the upper part of the separator SPR. The dummy layer UP can include a first dummy layer UP1 disposed on the separator SPR and a second dummy layer UP2 disposed on the first dummy layer UP1. The first dummy layer UP1 can be formed in the same process as the intermediate layer IML' and can include the same substances as each other. The second dummy layer UP2 can be formed in the same process as the cathode CE' and can include the same substances as each other. That is, the first dummy layer UP1 and the second dummy layer UP2 can be formed simultaneously in the formation process of the intermediate layer IML' and the cathode CE'. In another embodiment, the display panel DP' may not include the dummy layer UP.

[0240] As illustrated in FIG. 13B, in one embodiment, the cathode CE' can include a first end EN1a, and the second dummy layer UP2 can include a second end EN2a. The first end EN1a can be separated from the separator SPR and located on the pixel definition film PDL, and the second end EN2a can be separated from the first end EN1a and located on the side surface SPR_W of the separator SPR. However, in FIG. 13B, the first end EN1a is illustrated as being separated from the side surface SPR_W of the separator SPR by a predetermined distance, but the present invention is not limited thereto, and if the second end EN2a is electrically disconnected, the first end EN1a can also be in contact with the side surface SPR_W of the separator SPR. Further, even if the first end EN1a and the second end EN2a are not distinguished from each other and are connected, since the thickness of the portion formed along the side surface SPR_W of the separator SPR is thin, the electrical resistance is large, and when the cathode CE' is electrically disconnected between adjacent pixels, the cathode CE' is regarded as being divided by the separator SPR.

[0241] According to the present invention, even without another patterning process for the cathode CE' or the intermediate layer IML', the cathode CE' or the intermediate layer IML' can be prevented from being formed on the side surface SPR_W of the separator SPR or formed thinly, so that the cathode CE' or the intermediate layer IML' can be divided for each pixel. Further, if the cathode CE' or the intermediate layer IML' can be electrically disconnected between adjacent pixels, the shape of the separator SPR can be variously deformed and is not limited to any one embodiment.

[0242] FIG. 14 is a cross-sectional view of a display panel according to an embodiment of the present invention. For ease of explanation, FIG. 14 shows a cross-sectional view of a region corresponding to FIG. 13. Hereinafter, the same reference numerals are given to the same configurations as those described with reference to FIG. 13, and redundant descriptions are omitted.

[0243] The display panel DP'-1 shown in FIG. 14 can further include a capping pattern CPP as compared with the display panel DP' shown in FIG. 13. The capping pattern CPP can be disposed on the upper insulating layer UIL. Further, the capping pattern CPP can also be disposed on a partial region of the connection wiring CN exposed by the first opening OP1 of the upper insulating layer UIL. The capping pattern CPP can be disposed so as to overlap the connection wiring CN, and specifically, can be disposed so as to overlap the light-emitting connection portion CEP and / or the chip portion TP.

[0244] Further, as shown in FIG. 14, in cross-section, the capping pattern CPP can have a shape in which the connection is partially broken with reference to the chip portion TP in the region where the light-emitting connection portion CEP is defined. However, when viewed in plan, the capping pattern CPP can have an integral shape that is entirely connected within the region defined by the closed line by the separator SPR (see FIG. 15A). On the other hand, one end of the capping pattern CPP with a partially broken connection can contact the side surface of the second connection wiring layer L2, and the other end of the capping pattern CPP can be disposed on the upper portion of the third connection wiring layer L3 to cover the chip portion TP.

[0245] The capping pattern CPP can contain a conductive substance. Therefore, the cathode CE' can be electrically connected to the connection wiring CN through the capping pattern CPP. That is, the capping pattern CPP contacts the side surface of the second layer L2 of the connection wiring, and then the cathode CE' contacts the capping pattern CPP and can all be electrically connected. The capping pattern CPP is disposed relatively outward compared to the second layer L2 of the connection wiring, and the cathode CE' is connected to the capping pattern CPP instead of the side surface of the second layer L2 and can be electrically connected to the second layer L2, so the connection between the connection wiring CN and the cathode CE' can be made more easily.

[0246] Also, the capping pattern CPP can contain a substance having a relatively low reactivity compared to the second layer L2 of the connection wiring. For example, the capping pattern CPP can contain copper (Cu), silver (Ag), a transparent conductive oxide, etc. Since the side surface of the second layer L2 of the connection wiring is protected by the capping pattern CPP having a relatively low reactivity, oxidation of the substances contained in the second layer L2 can be prevented. Also, it is possible to prevent the phenomenon that the silver (Ag) component contained in the anode AE' layer is reduced and remains as particles that induce defects during the etching process of patterning the anode AE'. For example, since the residue of the particles can be suppressed on the capping pattern CPP having a relatively low reactivity, it becomes possible to favorably perform the connection between the connection wiring CN and the cathode CE' through the capping pattern CPP.

[0247] In one embodiment, the capping pattern CPP is formed through the same process as the anode AE' and can contain the same substance as the anode AE'. However, this is only an illustrative explanation, and the capping pattern CPP can also be formed through a process different from the anode AE', can contain other substances, and is not limited to any one embodiment.

[0248] FIGS. 15A to 15C are plan views showing an enlarged partial area of a display panel according to an embodiment. FIGS. 15A to 15C can correspond to enlarged plan views of the display panels DP’ and DP’-1 according to the embodiment described above with reference to FIGS. 12 to 14. FIG. 15A shows an area where a total of four light-emitting units arranged in two rows and two columns are arranged. FIG. 15B shows an enlarged view of a partial area shown in FIG. 15A. FIG. 15C shows a partial configuration of the configuration shown in FIG. 15A with some configurations omitted or emphasized. Hereinafter, the present invention will be described with reference to FIGS. 15A to 15C.

[0249] FIG. 15A shows light-emitting units UT11, UT12, UT21, and UT22 arranged in two rows and two columns. The first row Rk light-emitting part includes light-emitting parts constituting the first row first column light-emitting unit UT11 and the first row second column light-emitting unit UT12, and the second row Rk+1 light-emitting part includes light-emitting parts constituting the second row first column light-emitting unit UT21 and the second row second column light-emitting unit UT22. FIG. 15B shows the first row Rk light-emitting part. FIGS. 15A to 15C show a separator SPR, a plurality of light-emitting parts EP1, EP2, EP3 arranged in a region partitioned by the separator SPR, connection wirings CN1, CN2, CN3, an anode AE’, and a cathode CE’ in the configuration of the display panel.

[0250] As described above, each of the light-emitting parts EP1, EP2, and EP3 can correspond to a light-emitting opening OP-PDL (see FIG. 12). That is, each of the light-emitting parts EP1, EP2, and EP3 is a region where light is emitted by a light-emitting element and can correspond to a unit constituting an image displayed on the display panel DP’ (see FIG. 12). More specifically, the unit constituting the image can correspond to the region defined by the light-emitting opening OP-PDL (see FIG. 12), particularly the region defined by the lower surface of the light-emitting opening OP-PDL.

[0251] The light emitting parts EP1, EP2, and EP3 can include a first light emitting part EP1, a second light emitting part EP2, and a third light emitting part EP3. The first light emitting part EP1, the second light emitting part EP2, and the third light emitting part EP3 can each emit a first color light, a second color light, and a third color light, and the first to third color lights can be lights of different colors from each other. For example, the first light emitting part EP1 can emit red light, the second light emitting part EP2 can emit green light, and the third light emitting part EP3 can emit blue light, but the color combination is not limited to this. Also, at least two or more of each of the light emitting parts EP1, EP2, and EP3 can emit light of the same color. For example, all of the first to third light emitting parts EP1, EP2, and EP3 can emit blue light, or all can emit white light.

[0252] On the other hand, the third light emitting part EP3 that emits the third color light among the light emitting parts EP1, EP2, and EP3 can include two sub-light emitting parts EP31 and EP32 that are separated from each other in the second direction DR2. However, this is shown by way of example, and the third light emitting part EP3 may be provided in one pattern having an integral shape like the other light emitting parts EP1 and EP2, and at least one of the other light emitting parts EP1 and EP2 can also include separated sub-light emitting parts, and it is not limited to any one embodiment.

[0253] The Rk light-emitting unit in the first row includes light-emitting parts EP1, EP2, and EP3 that constitute the light-emitting unit UT11 in the first row and first column and the light-emitting unit UT12 in the first row and second column. The Rk+1 light-emitting unit in the second row can include light-emitting parts EP1, EP2, and EP3 that constitute the light-emitting unit UT21 in the second row and first column and the light-emitting unit UT22 in the second row and second column. A part of the Rk light-emitting unit in the first row and a part of the Rk+1 light-emitting unit in the second row can have a symmetrical shape. For example, the first light-emitting part EP1 and the second light-emitting part EP2 of the light-emitting unit UT21 in the second row and first column and the first light-emitting part EP1 and the second light-emitting part EP2 of the light-emitting unit UT11 in the first row and first column can have a shape and an arrangement shape that are line-symmetrical with respect to the axis arranged in the first direction DR1, and the third light-emitting part EP3 of the light-emitting unit UT21 in the second row and first column and the third light-emitting part EP3 of the light-emitting unit UT11 in the first row and first column can have a shape and an arrangement shape that are line-symmetrical with respect to the axis along the first direction DR1. However, this is exemplary and not limited thereto.

[0254] Hereinafter, the light-emitting unit UT11 in the first row and first column will be described. For easy explanation, FIG. 15B shows a plurality of cathodes CE’_1, CE’_2, CE’_3, a plurality of pixel driving parts PXC1, PXC2, PXC3, and a plurality of connection wirings CN1, CN2, CN3. The cathodes CE’_1, CE’_2, CE’_3 can be separated from each other by a separator SPR and electrically disconnected. In this embodiment, one light-emitting unit can include three light-emitting parts EP1, EP2, and EP3. Therefore, the light-emitting unit can include three cathodes CE’_1, CE’_2, CE’_3 (hereinafter, the first to third cathodes), three pixel driving parts PXC1, PXC2, PXC3, and three connection wirings CN1, CN2, CN3. However, this is shown by way of example, and the number and arrangement of the light-emitting units can be designed in various ways and are not limited to any one embodiment.

[0255] Each of the first to third pixel driving units PXC1, PXC2, and PXC3 is electrically connected to the light-emitting elements that constitute the first to third light-emitting units EP1, EP2, and EP3. In this specification, "connected" includes not only the case of being physically directly connected but also the case of being electrically connected.

[0256] Also, as shown in FIG. 15B, each region where the pixel driving units PXC1, PXC2, and PXC3 are defined on the plane can correspond to a unit in which transistors and capacitor elements that constitute a pixel circuit PXC (see FIG. 3) for driving the light-emitting elements of the pixel are repeatedly arranged.

[0257] The first to third pixel driving units PXC1, PXC2, and PXC3 can be sequentially arranged along the first direction DR1. On the other hand, the arrangement positions of the first to third pixel driving units PXC1, PXC2, and PXC3 can be independently designed regardless of the positions and shapes of the first to third light-emitting units EP1, EP2, and EP3.

[0258] For example, the first to third pixel driving units PXC1, PXC2, and PXC3 are arranged at positions different from the positions where the first to third cathodes CE'_1, CE'_2, and CE'_3 are arranged, that is, at positions defined by being partitioned by a separator SPR, or are designed to have shapes and areas different from the shapes of the first to third cathodes CE'_1, CE'_2, and CE'_3. Or, the first to third pixel driving units PXC1, PXC2, and PXC3 are arranged so as to overlap the positions where the first to third light-emitting units EP1, EP2, and EP3 are present, and may be designed to have a shape having an area similar to that of the first to third cathodes CE'_1, CE'_2, and CE'_3, which is a region defined by being partitioned by a separator SPR.

[0259] In this embodiment, each of the first to third pixel driving units PXC1, PXC2, and PXC3 is illustrated in a rectangular shape, each of the first to third light emitting units EP1, EP2, and EP3 is arranged in a form with a smaller area and a different shape, and the first to third cathodes CE'_1, CE'_2, and CE'_3 are arranged at positions overlapping the first to third light emitting units EP1, EP2, and EP3 and are illustrated in an irregular shape.

[0260] Therefore, as illustrated in FIG. 15B, the first pixel driving unit PXC1 can be arranged at a position partially overlapping with the first light emitting unit EP1, the second light emitting unit EP2, and other adjacent light emitting units. The second pixel driving unit PXC2 can be arranged at a position overlapping with the first light emitting unit EP1, the second light emitting unit EP2, and the third light emitting unit EP3. The third pixel driving unit PXC3 can be arranged at a position overlapping with the third light emitting unit EP3. On the other hand, this is shown by way of example, and the positions of the first to third pixel driving units PXC1, PXC2, and PXC3 can be designed in various forms and arrangements independently of the light emitting units EP1, EP2, and EP3 and are not limited to any one embodiment. Although not limited thereto, in the example of FIG. 15B, the first pixel driving unit PXC1 overlaps with a part of the first light emitting unit EP1, a part of the second light emitting unit EP2, a part of the first cathode CE'_1, a part of the second cathode CE'_2, a part of the connection wiring CN1, a part of the connection wiring CN2, the second light emitting connection part CEP2, etc. in the first row and first column light emitting unit UT11, and can also be arranged at a position overlapping with a part of other light emitting units adjacent to the first row and first column light emitting unit UT11. In addition, the second pixel driving unit PXC2 overlaps with the remaining part of the first light emitting unit EP1, the remaining part of the second light emitting unit EP2, the remaining part of the first cathode CE'_1, the remaining part of the second cathode CE'_2, the remaining part of the connection wiring CN1 including the first light emitting connection part CEP1, the remaining part of the connection wiring CN2, etc. in the first row and first column light emitting unit UT11, and can also be arranged at a position overlapping with a part of the third cathode CE'_3. Further, the third pixel driving unit PXC3 can be disposed at a position overlapping with a part of the remaining portion of the third cathode CE'_3, the connection wiring CN including the third light emitting unit EP3, the third light emitting connection unit CEP3, and the driving connection unit CDP3 in the first row and first column light emitting unit UT11.

[0261] A plurality of connection wirings CN can be provided and arranged to be spaced apart from each other. One connection wiring CN can electrically connect any one of the pixel driving units PXC1, PXC2, PXC3 to a corresponding light emitting element. Specifically, the connection wiring CN can correspond to a node (refer to the fourth node N4 in FIG. 3) where the light emitting element ED' (refer to FIGS. 12 and 14) is connected to the pixel driving unit PXC (refer to FIG. 3).

[0262] As shown in FIGS. 12, 14, etc., the connection wiring CN can include a first connection part (or, light emitting connection part CEP) and a second connection part (or, driving connection part CDP). The light emitting connection part CEP can be provided on one side of the connection wiring CN, and the driving connection part CDP can be provided on the other side of the connection wiring CN.

[0263] The driving connection part CDP can be a part of the connection wiring CN that is connected to the pixel driving unit PXC. In this embodiment, the driving connection part CDP can be connected to one electrode of the transistor constituting the pixel driving unit PXC. Specifically, the driving connection part CDP can be connected to the drain of the sixth transistor T6 shown in FIG. 3. Therefore, the position of the driving connection part CDP can correspond to the position of the transistor (refer to the transistor TR in FIGS. 12 and 14) physically connected to the connection wiring CN in the pixel driving unit PXC. The light emitting connection part CEP can be a part of the connection wiring CN that is connected to the light emitting element. In this embodiment, the light emitting connection part CEP can be connected to the cathode CE' of the light emitting element (refer to FIGS. 12 and 14).

[0264] The light-emitting unit can include first to third connection wirings CN1, CN2, and CN3. The first connection wiring CN1 connects the light-emitting element forming the first light-emitting part EP1 and the first pixel driving part PXC1, the second connection wiring CN2 connects the light-emitting element forming the second light-emitting part EP2 and the second pixel driving part PXC2, and the third connection wiring CN3 can connect the light-emitting element forming the third light-emitting part EP3 and the third pixel driving part PXC3.

[0265] Specifically, the first to third connection wirings CN1, CN2, and CN3 can each connect the first to third cathodes CE’_1, CE’_2, and CE’_3 and the first to third pixel driving parts PXC1, PXC2, and PXC3. The first connection wiring CN1 can include a first driving connection part CDP1 connected to the first pixel driving part PXC1 and a first light-emitting connection part CEP1 connected to the first cathode CE’_1. The second connection wiring CN2 can include a second driving connection part CDP2 connected to the second pixel driving part PXC2 and a second light-emitting connection part CEP2 connected to the second cathode CE’_2. The third connection wiring CN3 can include a third driving connection part CDP3 connected to the third pixel driving part PXC3 and a third light-emitting connection part CEP3 connected to the third cathode CE’_3.

[0266] The first to third driving connection parts CDP1, CDP2, and CDP3 can be aligned along the first direction DR1. As described above, the first to third driving connection parts CDP1, CDP2, and CDP3 can each correspond to the positions of the connection transistors constituting the first to third pixel driving parts PXC1, PXC2, and PXC3. The connection transistor is a transistor that includes a connection node where the pixel driving part and the light-emitting element are connected to one electrode in one pixel, and can correspond to, for example, the sixth transistor T6 in FIG. 3. According to the present invention, regardless of the shape, size, and emission color of the light-emitting part, the shapes, positions, and arrangements of the pixel driving parts of all pixels can be easily configured and designed.

[0267] In this embodiment, the first to third light-emitting connection parts CEP1, CEP2, and CEP3 can be arranged at positions that do not overlap with the light-emitting parts EP1, EP2, and EP3 on a plane. As will be described later, each of the light-emitting connection parts CEP1, CEP2, and CEP3 of the connection wiring CN is a part to which a light-emitting element ED’ (see FIG. 12) is connected and is a part where a chip part TP (see FIG. 12) is defined, so it can be provided at a position that does not overlap with the light-emitting opening OP-PDL (see FIGS. 12 and 14). That is, the light-emitting connection parts CEP1, CEP2, and CEP3 can be arranged at positions separated from the light-emitting parts EP1, EP2, and EP3 at each of the cathodes CE’_1, CE’_2, and CE’_3, and the cathodes CE’_1, CE’_2, and CE’_3 can include a partial region protruding from the light-emitting parts EP1, EP2, and EP3 on a plane in order to connect to the connection wirings CN1, CN2, and CN3 at the positions where the light-emitting connection parts CEP1, CEP2, and CEP3 are arranged.

[0268] For example, the first cathode CE’_1 can include a protruding part shaped to protrude from the first light-emitting part EP1 at a position that does not overlap with the first light-emitting part EP1 in order to connect to the first connection wiring CN1 at the position where the first light-emitting connection part CEP1 is arranged, and the first light-emitting connection part CEP1 can be provided on the protruding part.

[0269] Also, the first pixel driving part PXC1, particularly the first driving connection part CDP1, which is the position where the first connection wiring CN1 is connected to the transistor TR (see FIGS. 12 and 14), can be defined at a position that does not overlap with the first light-emitting part EP1 on a plane. According to this embodiment, by arranging the first connection wiring CN1 on the first light-emitting part EP1, the separated first cathode CE’_1 and the first pixel driving part PXC1 can be easily connected.

[0270] On one hand, the third pixel driving unit PXC3, particularly the third driving connection part CDP3 where the third connection wiring CN3 is connected to the transistor TR, is defined at a position non-overlapping with the third light-emitting connection part CEP3 on the plane and can be arranged at a position overlapping with the third light-emitting part EP3. According to this embodiment, by connecting the third cathode CE'_3 and the pixel driving unit PXC3 through the third connection wiring CN3, in the design of the pixel driving unit PXC3, the constraints according to the position and shape of the third light-emitting part EP3 are reduced, and the design freedom can be improved.

[0271] Referring to FIG. 15A again, the light-emitting parts in the second row Rk+1 can be composed of light-emitting parts having a shape and arrangement that are line-symmetric with respect to an axis along the first direction DR1 or the second direction DR2 of the light-emitting units UT11 and UT12 in the first row. At this time, due to the characteristics of the shape and arrangement of the light-emitting units UT11 and UT12 in the first row, the light-emitting units UT21 and UT22 in the second row can be composed of light-emitting parts in a form where the light-emitting units UT11 and UT12 in the first row are shifted in the first direction DR1 or the second direction DR2. That is, the light-emitting unit UT21 in the second row and the first column can be composed of a light-emitting part having the same shape as the light-emitting unit UT12 in the first row and the second column, and the light-emitting unit UT22 in the second row and the second column can be composed of a light-emitting part having the same shape as the light-emitting unit UT11 in the first row and the first column.

[0272] Therefore, the shape and arrangement form of the connection wiring CN-c arranged in the light-emitting unit UT21 in the second row and the first column can be the same as those of the connection wirings CN1, CN2, and CN3 arranged in the light-emitting unit UT12 in the first row and the second column. Similarly, the shape and arrangement form of the connection wiring CN-d arranged in the light-emitting unit UT22 in the second row and the second column can be the same as those of the connection wirings CN1, CN2, and CN3 arranged in the light-emitting unit UT11 in the first row and the first column.

[0273] On the one hand, referring to FIG. 15C, the anode AE' of the light-emitting element according to an embodiment of the present invention can be commonly provided to a plurality of light-emitting portions EP1, EP2, and EP3. That is, the anode AE' can be formed of one layer that is integral throughout the display area DA. Therefore, the anode AE' layer can be arranged to overlap with the separator SPR. Or, each anode AE' of the light-emitting element can be formed of independent conductive patterns separated from each other and can be electrically connected to each other through other conductive layers. Therefore, the anode AE' may or may not be arranged to overlap with the separator SPR.

[0274] As described above, a first driving voltage ELVDD (see FIG. 3) is applied to the anode AE', and a voltage common to all the light-emitting portions can be provided. The anode AE' is connected to a first power line PL1 (see FIG. 3) that provides the first driving voltage ELVDD (see FIG. 3) in the non-display area NDA (see FIG. 1), or can also be connected to the first power line PL1 (see FIG. 3) in the display area DA, and is not limited to any one embodiment. In the latter case, the first power line PL1 (see FIG. 3) is arranged in the non-display area NDA (see FIG. 1), and the anode AE' can have a shape extended to the non-display area NDA (see FIG. 1).

[0275] In the cross-sectional views of FIGS. 12 and 14, an example is shown in which the anode AE' overlaps with the light-emitting aperture OP-PDL and does not overlap with the separator SPR. However, as shown in FIG. 15C, the anode AE' of the light-emitting element has an integral shape and can have a mesh or lattice shape in which an opening is defined in a partial region. That is, as long as the same first driving voltage ELVDD (see FIG. 3) can be applied to each anode AE' of the plurality of light-emitting elements, the shape of the anode AE' can be provided in various ways and is not limited to any one embodiment.

[0276] On the one hand, a plurality of openings OP-AE' can be defined in the anode AE' according to this embodiment, and the opening OP-AE' can penetrate the anode AE' layer. The opening OP-AE' of the anode AE' layer can be arranged at a position non-overlapping with the light-emitting part EP, and can be defined at a position generally overlapping with the separator SPR. The opening can facilitate the discharge of gas generated from an organic layer arranged below the anode AE', for example, the upper insulating layer UIL (see FIG. 12) described later. Therefore, the gas of the organic layer arranged below the light-emitting element during the display panel manufacturing process can be sufficiently discharged, and the rate at which the gas discharged from the organic layer after manufacturing deteriorates the light-emitting element can be reduced.

[0277] According to this embodiment, by including a connection wiring between the light-emitting element and the pixel driving part, the arrangement and shape of the light-emitting part are not changed, and even if only the cathode shape is changed, the light-emitting element can be easily connected to the pixel driving part. Therefore, the degree of freedom in design with respect to the arrangement of the pixel driving part can be improved, and the area or resolution of the light-emitting part of the display panel can be easily increased.

[0278] FIGS. 16A to 16D are enlarged plan views of a partial region of a display panel according to an embodiment of the present invention. In FIG. 16A, light-emitting units UT11, UT12, UT21, UT22 arranged in two rows and two columns are exemplarily illustrated. FIG. 16B illustrates light-emitting parts arranged in a single row. For easy explanation, FIG. 16B illustrates a plurality of cathodes CE'_1, CE'_2, CE'_3, a plurality of pixel driving parts PXC1, PXC2, PXC3, first to third connection electrodes CNE1', CNE2', CNE3', and a separator SPR. FIG. 16C illustrates a separator SPR and a plurality of light-emitting parts EP1, EP2, EP3 and a plurality of connection electrodes CNE1', CNE2', CNE3' arranged in a region partitioned by the separator SPR in the configuration of the display panel. In explaining FIGS. 16A to 16D, the same reference numerals are also given to the components identical to those described in FIGS. 12 to 15C, and the description thereof is omitted, and the differences will be mainly described.

[0279] One light-emitting unit UT11 can include three cathodes CE'_1, CE'_2, CE'_3 (hereinafter, the first to third cathodes), three pixel driving units PXC1, PXC2, PXC3, and three connection electrodes CNE1', CNE2', CNE3'. However, this is only an exemplary illustration, and the number and arrangement of the light-emitting parts included in the light-emitting unit UT11 can be designed in various ways and are not limited to any one embodiment.

[0280] The light-emitting unit UT11 can include the first to third connection electrodes CNE1', CNE2', CNE3'. The first connection electrode CNE1' electrically connects the first light-emitting element ED1' forming the first light-emitting part EP1 (or, the first light-emitting part EP1 is defined) and the first pixel driving unit PXC1, the second connection electrode CNE2' electrically connects the second light-emitting element ED2' forming the second light-emitting part EP2 and the second pixel driving unit PDC2, and the third connection electrode CNE3' can electrically connect the third light-emitting element ED3' forming the third light-emitting part EP3 and the third pixel driving unit PXC3.

[0281] Specifically, the first to third connection electrodes CNE1', CNE2', CNE3' can be electrically connected to the first to third cathodes CE'_1, CE'_2, CE'_3 and the first to third pixel driving units PXC1, PXC2, PXC3 in a one-to-one correspondence respectively.

[0282] Each of the first to third connection electrodes CNE1', CNE2', CNE3' can be disposed on the pixel definition film PDL (see FIG. 17). The first to third connection electrodes CNE1', CNE2', CNE3' can have an annular shape surrounding the corresponding first to third light-emitting parts EP1, EP2, EP3. In one embodiment of the present invention, an example is illustrated in which each of the first to third connection electrodes CNE1', CNE2', CNE3' has a closed-line annular shape, but it is not limited thereto. For example, at least a part of the first to third connection electrodes CNE1', CNE2', CNE3' may have an open annular shape with a part cut off.

[0283] Since the first to third connection electrodes CNE1’, CNE2’, and CNE3’ have an annular shape, the degree of freedom in the positions where the first to third connection electrodes CNE1’, CNE2’, and CNE3’ are connected to the first to third pixel driving units PXC1, PXC2, and PXC3 can be improved. That is, since the first to third light-emitting connection parts CEP1 to CEP3 can be arranged corresponding to arbitrary positions of the annular first to third connection electrodes CNE1’, CNE2’, and CNE3’ respectively, the degree of freedom in the connection between the first to third connection electrodes CNE1’, CNE2’, and CNE3’ and the first to third pixel driving units PXC1, PXC2, and PXC3 is improved. For example, the first connection electrode CNE1’ is connected to the first pixel driving unit PXC1 through the first light-emitting connection part CEP1 (or the first connection part), the second connection electrode CNE2 is connected to the second pixel driving unit PXC2 through the second light-emitting connection part CEP2 (or the second connection part), and the third connection electrode CNE3’ can be connected to the third pixel driving unit PXC3 through the connection wiring CN3 (the third light-emitting connection part CEP3 and the third driving connection part CDP3). That is, the connection wiring additionally connected to the first and second connection electrodes CNE1’ and CNE2’ can be omitted.

[0284] One connection wiring CN3 can electrically connect the third pixel driving unit PXC3 and the third light-emitting element ED3’ constituting the third light-emitting part EP3. The connection wiring CN3 can include the third light-emitting connection part CEP3 (or the third connection part) and the driving connection part CDP3. The third light-emitting connection part CEP3 can be provided on one side of the connection wiring CN3, and the driving connection part CDP3 can be provided on the other side of the connection wiring CN3.

[0285] The drive connection part CDP3 can be the part of the connection wiring CN3 that is connected to the pixel drive part PXC3. In this embodiment, the drive connection part CDP3 can be connected to one electrode of the transistor that constitutes the pixel drive part PXC3. The position of the drive connection part CDP3 can correspond to the position of the transistor that is physically connected to the connection wiring CN3 within the pixel drive part. The third light-emitting connection part CEP3 can be the part of the connection wiring CN3 that is connected to the third light-emitting element ED3'. In this embodiment, the third light-emitting connection part CEP3 can be connected to the third connection electrode CNE3'.

[0286] The first connection electrode CNE1' can include a first edge EG11 that surrounds at least a part of the first light-emitting part EP1 and a second edge EG12 that surrounds the first edge EG11. The second connection electrode CNE2' can include a first edge EG21 that surrounds at least a part of the second light-emitting part EP2 and a second edge EG22 that surrounds the first edge EG21. The third connection electrode CNE3' can include a first edge EG31 that surrounds at least a part of the third light-emitting part EP3 and a second edge EG32 that surrounds the first edge EG31.

[0287] The first to third connection electrodes CNE1', CNE2', CNE3' can be arranged to be separated from each other. For example, the gaps GP1, GP2, GP3 between a plurality of adjacent connection electrodes among the first to third connection electrodes CNE1', CNE2', CNE3' can overlap with the separator SPR. For example, the first edges EG11, EG21, EG31 (EG1c) of the first to third connection electrodes CNE1', CNE2', CNE3' are not covered by the separator SPR, and the second edges EG12, EG22, EG32 (EG2c) of the first to third connection electrodes CNE1', CNE2', CNE3' can overlap with the separator SPR. Or, the second edges EG12, EG22, EG32 of the first to third connection electrodes CNE1', CNE2', CNE3' can be covered by the separator SPR. The gap GP (GP1, GP2, GP3) can be said to be formed between adjacent connecting electrodes CNE. The gap GP1 can be said to be formed between the first connecting electrode CNE1’ and the second connecting electrode CNE2’. More specifically, the gap GP1 can be said to be formed between the second edge EG12 of the first connecting electrode CNE1’ and the second edge EG22 of the second connecting electrode CNE2’. Also, the gap GP2 can be said to be formed between the first connecting electrode CNE1’ and the third connecting electrode CNE3’. More specifically, the gap GP2 can be said to be formed between the second edge EG12 of the first connecting electrode CNE1’ and the second edge EG32 of the third connecting electrode CNE3’. Also, the gap GP3 can be said to be formed between the second connecting electrode CNE2’ and the third connecting electrode CNE3’. More specifically, the gap GP3 can be said to be formed between the second edge EG22 of the second connecting electrode CNE2’ and the second edge EG32 of the third connecting electrode CNE3’. As described above, the gaps GP (GP1, GP2, GP3) can overlap with the separator SPR. For example, focusing on the first connection electrode CNE1’, as shown in FIGS. 17 and 18, the first edge EG11 of the first connection electrode CNE1’ is not covered by the separator SPR, and the second edge EG12 of the first connection electrode CNE1’ can overlap with the separator SPR or may be covered by the separator SPR. Also, focusing on the second connection electrode CNE2’, as shown in FIGS. 17 and 18, the first edge EG21 of the second connection electrode CNE2’ is not covered by the separator SPR, and the second edge EG22 of the second connection electrode CNE2’ can overlap with the separator SPR or may be covered by the separator SPR. Further, focusing on the third connection electrode CNE3’, the first edge EG31 of the third connection electrode CNE3’ is not covered by the separator SPR, and the second edge EG32 of the third connection electrode CNE3’ can overlap with the separator SPR or may be covered by the separator SPR. Thus, as shown in FIGS. 17 and 18, the second edge EG12 of the adjacent first connection electrode CNE1’ and the second edge EG22 of the second connection electrode CNE2’ can overlap with the separator SPR or may be covered by the separator SPR. Also, the second edge EG22 of the adjacent second connection electrode CNE2’ and the second edge EG32 of the third connection electrode CNE3’ can overlap with the separator SPR or may be covered by the separator SPR. The second edge EG12 of the adjacent first connection electrode CNE1’ and the second edge EG32 of the third connection electrode CNE3’ can overlap with the separator SPR or may be covered by the separator SPR.

[0288] In one embodiment of the present invention, the first to third light-emitting connection portions CEP1, CEP2, CEP3 can be arranged at positions non-overlapping with the first to third light-emitting portions EP1, EP2, EP3 on a plane. For example, in the pixel definition film PDL (see FIG. 17), a light-emitting opening OP-PDL and a through hole OP-P separated from the light-emitting opening OP-PDL can be defined.

[0289] The through hole OP-P can include a first through hole OP-P1, a second through hole OP-P2, and a third through hole OP-P3. The first to third light-emitting connection parts CEP1, CEP2, CEP3 can be arranged corresponding to each of the first to third through holes OP-P1, OP-P2, OP-P3. The light-emitting opening OP-PDL can include a first light-emitting opening OP-PDL1, a second light-emitting opening OP-PDL2, and a third light-emitting opening OP-PDL3. The first to third light-emitting parts EP1, EP2, EP3 can be defined corresponding to each of the first to third light-emitting openings OP-PDL1, OP-PDL2, OP-PDL3. Therefore, the first to third light-emitting connection parts CEP1, CEP2, CEP3 can be arranged at positions separated from the first to third light-emitting parts EP1, EP2, EP3.

[0290] The first to third connection electrodes CNE1’, CNE2’, CNE3’ can be arranged on the pixel definition film PDL (see FIG. 17). When viewed in a plane, the first connection electrode CNE1’ can surround the first light-emitting opening OP-PDL1, the second connection electrode CNE2’ can surround the second light-emitting opening OP-PDL2, and the third connection electrode CNE3’ can surround the third light-emitting opening OP-PDL3.

[0291] According to an embodiment of the present invention, a drive connection part CDP3, which is a position where the connection wiring CN3 is connected to the transistor TR (see FIG. 17) of the third pixel driving part PXC3, is defined at a position non-overlapping with the third light-emitting connection part CEP3 in a plane and can be arranged at a position overlapping with the third light-emitting part EP3. For example, the connection wiring CN3 (FIG. 16A, etc.) corresponds to the connection wiring CN-ad shown in FIG. 19, the drive connection part CDP3 (FIG. 16A, etc.) corresponds to a part in contact with the intermediate connection electrode CN’ shown in FIG. 19, and the third light-emitting connection part CEP3 (FIG. 16A, etc.) can correspond to a part in contact with the connection electrode CNEa’ shown in FIG. 19. By connecting the third cathode CE’_3 and the pixel driving part PXC3 through the connection wiring CN3, in the design of the pixel driving part PXC3, the constraints according to the position and shape of the third light-emitting part EP3 are reduced, and the degree of freedom in design can be improved.

[0292] The first to third cathodes CE'_1, CE'_2, CE'_3 can be connected to the first to third connection electrodes CNE1', CNE2', CNE3. For example, the lower surfaces of the first to third cathodes CE'_1, CE'_2, CE'_3 can be respectively connected (or in contact) with the upper surfaces of the first to third connection electrodes CNE1', CNE2', CNE3. That is, it can be said that the first to third cathodes CE'_1, CE'_2, CE'_3 and the first to third connection electrodes CNE1', CNE2', CNE3 are in surface contact. Therefore, the contact reliability (or connection stability) between the first to third cathodes CE'_1, CE'_2, CE'_3 and the first to third connection electrodes CNE1', CNE2', CNE3 can be further improved.

[0293] In addition, the connection regions where the first to third cathodes CE'_1, CE'_2, CE'_3 and the first to third connection electrodes CNE1', CNE2', CNE3 are connected can surround at least a part of each of the first to third light-emitting openings OP-PDL1, OP-PDL2, OP-PDL3. The first to third cathodes CE'_1, CE'_2, CE'_3 and the first to third connection electrodes CNE1', CNE2', CNE3 can be connected in a region adjacent to the separator SPR, and each of the connection regions can be defined adjacent to the separator SPR. That is, the first to third cathodes CE'_1, CE'_2, CE'_3 and the first to third connection electrodes CNE1', CNE2', CNE3 are not partially connected at specific points, but can be connected over a relatively wide region, for example, a region similar to the shape of each of the first to third connection electrodes CNE1', CNE2', CNE3. That is, the area of the connection region can be increased, and the connection can proceed stably. That is, as shown in FIGS. 16A to 16C, etc., the first to third connection electrodes CNE1', CNE2', CNE3 are formed longer in an annular shape, and the area of the connection region between the first to third cathodes CE'_1, CE'_2, CE'_3 and the annular first to third connection electrodes CNE1', CNE2', CNE3 can be ensured.

[0294] FIG. 16D shows a separator SPR, light emitting portions EP1, EP2, EP3, and a first electrode EL1. Referring to FIG. 16D, the anode AE' of a light emitting element ED' (see FIG. 17) according to an embodiment of the present invention can be commonly provided to the first to third light emitting portions EP1, EP2, EP3. That is, the anode AE' can be formed of a single layer that is integral throughout the display area DA, and thus the anode AE' layer can be disposed to overlap with the separator SPR. Alternatively, each anode AE' of the light emitting element can be formed of independent conductive patterns spaced apart from each other and can be electrically connected to each other through other conductive layers. Thus, the anode AE' pattern may be disposed to overlap with the separator SPR or may be disposed without overlapping.

[0295] On the other hand, a plurality of openings can be defined in the anode AE' according to this embodiment, and the openings can penetrate the anode AE' layer. The openings in the anode AE' layer can be disposed at positions non-overlapping with the light emitting portions EP1, EP2, EP3, and can be defined at positions generally overlapping with the separator SPR.

[0296] FIG. 17 is a cross-sectional view of a display panel according to an embodiment of the present invention. FIG. 18 is a cross-sectional view showing an enlarged partial region of the display panel according to an embodiment of the present invention. FIG. 17 shows a cross-sectional view showing a portion corresponding to the line I-I' of FIG. 16A. FIG. 18 shows a cross-sectional view of the enlarged CC region of FIG. 17. In explaining FIGS. 17 and 18, the same reference numerals are assigned to the same components as those described in FIGS. 12 to 16D, and the description thereof is omitted, and the differences will be mainly described.

[0297] Referring to FIGS. 17 and 18, the display panel DP'-2 of one embodiment can include a base layer BL, a circuit element layer DP-CL', an intermediate connection electrode CN', a connection electrode CNE', a display element layer DP-ED', a sealing layer ECL, and a sensing layer ISL. However, this is only an example, and in one embodiment of the present invention, the display panel DP'-2 may not include the sensing layer ISL. The circuit element layer DP-CL' can include a plurality of conductive patterns and semiconductor patterns disposed between a plurality of insulating layers 10, 20, 30, 40, 50, 60 disposed on the base layer BL.

[0298] The intermediate connection electrode CN' can be disposed on the fifth insulating layer 50. The intermediate connection electrode CN' can electrically connect the pixel driving unit PXC and the light emitting element ED'. That is, the intermediate connection electrode CN' can electrically connect the connection transistor TR and the light emitting element ED'. The intermediate connection electrode CN' can be a connection node that connects the pixel driving unit PXC and the light emitting element ED'. For example, the intermediate connection electrode CN' can correspond to the fourth node N4 illustrated in FIG. 3.

[0299] The sixth insulating layer 60 can be disposed on the intermediate connection electrode CN'. The sixth insulating layer 60 can be disposed on the fifth insulating layer 50 to cover at least a part of the intermediate connection electrode CN'. Each of the fifth insulating layer 50 and the sixth insulating layer 60 can be an organic layer. For example, each of the fifth insulating layer 50 and the sixth insulating layer 60 can include general-purpose polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), PMMA (Polymethylmethacrylate), and PS (Polystyrene), polymer derivatives having a phenolic group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0300] The sixth insulating layer 60 may be provided with a through hole OP-60 that exposes at least a part of the intermediate connection electrode CN'. The intermediate connection electrode CN' can be connected to the connection electrode CNE' through a part exposed from the sixth insulating layer 60 and can be electrically connected to the light emitting element ED'. That is, the intermediate connection electrode CN' can electrically connect the connection transistor TR and the light emitting element ED' together with the connection electrode CNE'. On the other hand, in the display panel DP'-2 according to an embodiment of the present invention, the sixth insulating layer 60 may be omitted, may be provided in plural, and is not limited to any one embodiment. When the sixth insulating layer 60 is omitted, the intermediate connection electrode CN' can also be omitted.

[0301] The intermediate connection electrode CN' can include a first layer L1', a second layer L2', and a third layer L3' sequentially stacked along the third direction DR3. The second layer L2' can include a substance different from that of the first layer L1'. Also, the second layer L2' can include a substance different from that of the third layer L3'. The second layer L2' can have a relatively thicker thickness compared to the first layer L1'. Also, the second layer L2' can have a relatively thicker thickness compared to the third layer L3'. The second layer L2' can include a substance with high conductivity. In one embodiment, the second layer L2' can include aluminum (Al).

[0302] The connection electrode CNE' can be disposed on the pixel definition film PDL. The connection electrode CNE' can electrically connect the pixel driving unit PXC and the light emitting element ED'. That is, the pixel driving unit PXC can be electrically connected to the light emitting element ED' through the intermediate connection electrode CN' and the connection electrode CNE'. The connection electrode CNE' can correspond to the first connection electrode CNE1' shown in FIG. 16A. The second connection electrode CNE2' (see FIG. 16A) and the third connection electrode CNE3' (see FIG. 16A) can also have a structure similar to that of the connection electrode CNE'.

[0303] The connecting electrode CNE’ can include a first edge EG1c adjacent to the light-emitting opening OP-PDL and a second edge EG2c surrounding the first edge EG1c. The cathode CE’ of the light-emitting element ED’ can be in contact with the connecting electrode CNE’ in a region adjacent to the second edge EG2c.

[0304] The connecting electrode CNE’ can include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3). However, the material constituting the connecting electrode CNE’ is not limited to the above examples.

[0305] A display element layer DP-ED’ can be disposed on the circuit element layer DP-CL’. The display element layer DP-ED’ can include a pixel definition film PDL, a light-emitting element ED’, and a separator SPR.

[0306] A through hole OP-P spaced apart from the light-emitting opening OP-PDL can be defined in the pixel definition film PDL. A plurality of through holes OP-P can be provided and arranged corresponding to each light-emitting element. The size of the through hole OP-P defined in the pixel definition film PDL can be larger than the size of the through hole OP-60 defined in the sixth insulating layer 60. The connecting electrode CNE’ can be disposed in the through hole OP-P and the through hole OP-60 and can be connected to the intermediate connecting electrode CN’.

[0307] The light-emitting element ED’ can include an anode AE’, an intermediate layer IML’, and a cathode CE’. The intermediate layer IML’ can include a light-emitting layer EML and a functional layer FNL’. The functional layer FNL’ can include a first intermediate functional layer FNLa disposed between the anode AE’ and the light-emitting layer EML and a second intermediate functional layer FNLb disposed between the cathode CE’ and the light-emitting layer EML. In one embodiment of the present invention, one of the first intermediate functional layer FNLa and the second intermediate functional layer FNLb can be omitted. In this embodiment, the light-emitting layer EML shown is inserted into the functional layer FNL’. That is, it can be understood that the light-emitting layer EML is disposed between the first intermediate functional layer FNLa and the second intermediate functional layer FNLb.

[0308] The functional layer FNL’ can control the movement of charges between the anode AE’ and the cathode CE’. For example, the first intermediate functional layer FNLa can include a hole injection / transport material and / or an electron injection / transport material. The second intermediate functional layer FNLb can include at least one of an electron blocking layer, a hole transport layer, a hole injection layer, a hole blocking layer, an electron transport layer, an electron injection layer, and a charge generation layer.

[0309] The separator SPR can be disposed on the pixel definition film PDL. Also, the separator SPR can be disposed on the connection electrode CNE’ disposed on the pixel definition film PDL and on the gap GP between the connection electrode CNE’ and an adjacent connection electrode adjacent thereto.

[0310] In one embodiment, the cathode CE’ and the intermediate layer IML’ can be formed by being commonly deposited on a plurality of pixels through an open mask. At this time, the cathode CE’ and the intermediate layer IML’ can be divided by a separator SPR. As described above, the separator SPR can have a closed line shape for each light-emitting unit, and thus the cathode CE’ and the intermediate layer IML’ can have a shape divided for each light-emitting unit. That is, the cathode CE’ and the intermediate layer IML’ can be electrically independent for each adjacent pixel. However, this is only an exemplary description, and in the intermediate layer IML’, the functional layer FNL’ can be formed through an open mask, and the light-emitting layer EML can also be formed through a fine metal mask, and it is not limited to any one embodiment.

[0311] Referring to FIGS. 17 and 18, the separator SPR can have a double reverse taper shape. That is, the taper angle formed by the first side surface SPR_W1 of the separator SPR with respect to the upper surface of the pixel definition film PDL and the taper angle formed by the second side surface SPR_W2 can be different from each other. The taper angle can be an obtuse angle. For example, referring to FIG. 18, the taper angle formed by the first side surface SPR_W1 with respect to the upper surface of the pixel definition film PDL can be smaller than the taper angle formed by the second side surface SPR_W2 with respect to the upper surface of the pixel definition film PDL. However, this is only an exemplary illustration, and if the separator SPR can electrically disconnect the cathode CE’ for each pixel, the taper angle can be set in various ways. Also, the separator SPR can have a structure such as a chip portion and is not limited to any one embodiment.

[0312] A dummy layer UP can be disposed on the upper part of the separator SPR. The dummy layer UP can include a first dummy layer UP1 disposed on the separator SPR and a second dummy layer UP2 disposed on the first dummy layer UP1. In one embodiment, the first dummy layer UP1 can include a first - 1 dummy layer UP1a and a first - 2 dummy layer UP1b. The first - 1 dummy layer UP1a can be formed in the same process as the first intermediate functional layer FNLa and can include the same substance as each other. The first - 2 dummy layer UP1b can be formed in the same process as the second intermediate functional layer FNLb and can include the same substance as each other.

[0313] The dummy layer UP can be formed so as not to be in contact with the connection electrode CNE’ and the cathode CE’. The second dummy layer UP2 included in the dummy layer UP can be formed so as not to be in contact with the connection electrode CNE’ and the cathode CE’. In one embodiment, the dummy layer UP can be formed not only on the upper surface of the separator SPR but also partially on the side surfaces SPR_W1, SPR_W2. In one embodiment, the display panel DP may not include the dummy layer UP.

[0314] The cathode CE’ can be brought into contact with the connection electrode CNE’ through the contact region CA. The contact region CA can be provided adjacent to the separator SPR. In the contact region CA, the upper surface CNE - us of the connection electrode CNE’ is in contact with the lower surface CE - bs of the cathode CE’. On the other hand, since the separator SPR has an inverted taper shape and the contact region CA is provided adjacent to the separator SPR, at least a part of the contact region CA where the cathode CE’ and the connection electrode CNE’ are in contact can be disposed under the side surfaces SPR_W1, SPR_W2 of the separator SPR.

[0315] On the one hand, in one embodiment, at least a part of the connection electrode CNE' can be disposed below the separator SPR. The separator SPR can be disposed on the connection electrode CNE' and the gap GP between the connection electrode CNE' and the adjacent connection electrode adjacent thereto, and the second edge EG2c of the connection electrode CNE' can be covered by the separator SPR.

[0316] The display panel DP'-2 of one embodiment can include an intermediate region MA disposed between the light-emitting region EA where the light-emitting element ED' is disposed and the contact region CA. The intermediate region MA can be a region where at least a part of the intermediate layer IML' (the intermediate layer IML' can include the light-emitting layer EML and the functional layer FNL') is disposed. In the intermediate region MA, the functional layer FNL' included in the intermediate layer IML' can be disposed between the connection electrode CNE' and the cathode CE'. That is, in the intermediate region MA, the connection electrode CNE' and the cathode CE' can be separated via the functional layer FNL'.

[0317] The intermediate region MA can be adjacent to the contact region CA. The functional layer FNL' disposed in the intermediate region MA can include the first intermediate functional layer FNLa and the second intermediate functional layer FNLb described above. The first intermediate functional layer FNLa can be disposed between the anode AE' and the light-emitting layer EML in the light-emitting region EA, and the second intermediate functional layer FNLb can be disposed between the cathode CE' and the light-emitting layer EML in the light-emitting region EA.

[0318] In the display panel DP'-2 of one embodiment, the functional layer FNL' and the cathode CE' can be formed through other vapor deposition process methods. The cathode CE' can be formed by a vapor deposition method that can deposit the vapor deposition material at a lower incident angle compared to the vapor deposition method for forming the functional layer FNL'. The functional layer FNL' can be formed, for example, by a thermal evaporation method, and the cathode CE' can be covered by a sputtering method. Therefore, since the material for forming the functional layer FNL' cannot enter the lower part of the side surface of the separator SPR during the formation process of the functional layer FNL', a part of the connection electrode CNE' can be exposed, and the cathode CE' is formed adjacent to the separator SPR compared to the functional layer FNL', and the cathode CE' can contact the upper surface CNE-us of the exposed connection electrode CNE'. That is, a contact region CA where the cathode CE' and the connection electrode CNE' contact can be formed through the difference in the vapor deposition process method in the formation processes of the functional layer FNL' and the cathode CE'.

[0319] On the other hand, the connection region CNA where the connection electrode CNE' is connected to the intermediate connection electrode CN' can be arranged between the light-emitting region EA and the contact region CA. The connection region CNA can overlap with the intermediate region MA. At least a part of the intermediate layer IML' can be arranged to overlap with the connection region CNA. In the display panel DP'-2 of one embodiment, the functional layer FNL' included in the intermediate layer IML' can be arranged to overlap with the connection region CNA.

[0320] According to one embodiment of the present invention, the connection electrode CNE' has an annular shape surrounding at least a part of the light-emitting region EA where the light-emitting element ED' is arranged. Therefore, the degrees of freedom of the position where the connection electrode CNE' and the light-emitting element ED' are connected and the position where the connection electrode CNE' and the pixel driving unit PXC are connected can be improved. That is, the connection electrode CNE' has an annular shape surrounding at least a part of the light-emitting region EA. Therefore, the cathode CE' of the light-emitting element ED' can be connected at any position of the annular connection electrode CNE'.

[0321] Also, the upper surface CNE-us of the connection electrode CNE' can be brought into contact with the lower surface CE-bs of the cathode CE' of the light-emitting element ED' through the contact region CA defined so as to be adjacent to the separator SPR. It can be said that the connection electrode CNE' and the cathode CE' are in surface contact. Therefore, the contact reliability between the connection electrode CNE' and the cathode CE' can be improved. Since the lower surface of the connection electrode CNE' and the upper surface of the intermediate connection electrode CN' are in contact, the contact reliability can be improved. By adopting the described structure for the display panel DP'-2 according to one embodiment, the sizes of the through holes OP-P and OP-60 for connecting the connection electrode CNE' and the intermediate connection electrode CN' can be reduced or minimized. Therefore, the area or resolution of the light-emitting portion of the display panel DP'-2 can be easily increased. That is, since the lower surface of the connection electrode CNE' and the upper surface of the intermediate connection electrode CN' are in contact, the contact reliability is improved. Therefore, the sizes of the through holes OP-P and OP-60 for connecting the connection electrode CNE' and the intermediate connection electrode CN' can be reduced or minimized. Thus, the area or resolution of the light-emitting portion of the display panel DP'-2 can be easily increased.

[0322] The sensing layer ISL can sense an external input. In this embodiment, the sensing layer ISL can be formed on the encapsulation layer ECL through a continuous process. At this time, it can be expressed that the sensing layer ISL is directly disposed on the encapsulation layer ECL. Being directly disposed can mean that no other components are disposed between the sensing layer ISL and the encapsulation layer ECL. That is, it is possible that no other adhesive member is disposed between the sensing layer ISL and the encapsulation layer ECL. However, this is shown by way of example. In the display panel DP according to one embodiment of the present invention, the sensing layer ISL can also be formed separately and then coupled to the display panel DP through an adhesive member, and is not limited to any one embodiment.

[0323] The sensing layer ISL can include a plurality of conductive layers and a plurality of insulating layers. The plurality of conductive layers can include a first sensing conductive layer MTL1 and a second sensing conductive layer MTL2, and the plurality of insulating layers can include first to third sensing insulating layers 71, 72, and 73. However, this is shown by way of example, and the number of conductive layers and insulating layers is not limited to any one embodiment.

[0324] Each of the first to third sensing insulating layers 71, 72, and 73 can have a single-layer structure or a multilayer structure laminated along the third direction DR3. The first to third sensing insulating layers 71, 72, and 73 can include an inorganic film. The inorganic film can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first to third sensing insulating layers 71, 72, and 73 can include an organic film. The organic film can include at least one of an acrylic resin, a methacrylic resin, polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyimide resin, a polyamide resin, and a perylene resin.

[0325] The first sensing conductive layer MTL1 can be disposed between the first sensing insulating layer 71 and the second sensing insulating layer 72, and the second sensing conductive layer MTL2 can be disposed between the second sensing insulating layer 72 and the third sensing insulating layer 73. A part of the second sensing conductive layer MTL2 can be connected to the first sensing conductive layer MTL1 through a contact hole CNT formed in the second sensing insulating layer 72. Each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 can have a single-layer structure or a multilayer structure laminated along the third direction DR3.

[0326] The single-layer sensing conductive layer can include a metal layer or a transparent conductive layer. The metal layer can include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer can include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (IZTO). Alternatively, the transparent conductive layer can include a conductive polymer such as PEDOT, metal nanowires, graphene, or the like.

[0327] The multi-layer sensing conductive layer can include a metal layer. The metal layer can have, for example, a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti). Alternatively, the multi-layer sensing conductive layer can include at least one metal layer and at least one transparent conductive layer.

[0328] The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 can form a sensor in the sensing layer ISL to sense an external input. The sensor can be driven in a capacitance method and can be driven by either a mutual-capacitance method or a self-capacitance method. However, this is only an illustrative explanation, and the sensor can also be driven by a resistance film method, an ultrasonic method, or an infrared method in addition to the capacitance method and is not limited to any one embodiment.

[0329] Each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may include a transparent conductive oxide and may have a metal mesh shape formed of an opaque conductive material. The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 can have various materials and various shapes as long as the visibility of the video displayed by the display panel DP is not reduced, and is not limited to any one embodiment.

[0330] FIG. 19 is a cross-sectional view of a display panel according to an embodiment of the present invention. In explaining FIG. 19, the same reference numerals are used for the same components as those described in FIGS. 17 and 18, and the description thereof is omitted.

[0331] Referring to FIG. 19, the display panel DP'-3 can further include a connection wiring CN-ad disposed between the sixth insulating layer 60 and the pixel definition film PDL. The connection wiring CN-ad can be connected to the intermediate connection electrode CN' through a through hole OP-60 that exposes at least a part of the intermediate connection electrode CN'.

[0332] In an embodiment of the present invention, the connection wiring CN-ad can be disposed on the same layer as the anode AE'. For example, the connection wiring CN-ad can have the same material and the same layer structure as the anode AE'. Also, the connection wiring CN-ad can be formed by the same process as the anode AE'. However, this is only an example and is not limited thereto. For example, the connection wiring CN-ad may include a different material and may be formed by a different process from the anode AE'.

[0333] A through hole OP-Pa can be defined in the pixel definition film PDL. The through hole OP-Pa and the through hole OP-60 can be non-overlapping with each other, but are not particularly limited thereto. For example, the through hole OP-Pa and the through hole OP-60 may overlap with each other. The connection electrode CNEa' can be disposed in the through hole OP-Pa. The connection electrode CNEa' can be connected to a part of the connection wiring CN-ad exposed by the through hole OP-Pa.

[0334] According to the present invention, it is possible to prevent the driving current of the light-emitting element from fluctuating. Also, in the compensation operation, it is possible to reduce or eliminate the influence of the parasitic capacitance of the node connected to the cathode, and it is possible to provide a pixel circuit with improved compensation stability.

[0335] According to the present invention, the gradation can be improved and the expression ability of the changing colors can be enhanced. According to the present invention, the amount of noise caused by the voltage drop and ripple generation in the power line can be reduced. Therefore, the display quality of the display device can be improved.

[0336] According to the present invention, a display device with reduced power consumption can be provided.

[0337] The preferred embodiments of the invention have been described above with reference thereto. However, those skilled in the relevant technical field or those with ordinary knowledge in the relevant technical field can understand that the present invention can be variously modified and changed without departing from the spirit and scope of the present invention described in the claims to be described later. Therefore, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

Explanation of Reference Numerals

[0338] DD Display device PXC Pixel circuit ED Light-emitting element T1 First transistor T2 Second transistor T3 Third transistor T4 Fourth transistor T5 First initialization transistor T8 Second initialization transistor

Claims

1. a display panel including pixels; The pixel is a light emitting device including an anode and a cathode connected to a first power line; a first transistor connected between the cathode and a second power line and operated in response to a potential of a first node; a second transistor connected between the first node and a data line to receive a first scan signal; a third transistor connected between the first node and a reference voltage line to receive a second scan signal; a fourth transistor coupled between the first transistor and the first power line.

2. The second scan signal has an activation level during a first initialization period, and the first scan signal has a deactivation level during the first initialization period; The display device of claim 1 , wherein the second scan signal has an active level during a compensation period, and the first scan signal has a deactivated level during the compensation period.

3. the fourth transistor receives a third scan signal; The display device of claim 2 , wherein the third scan signal has a deactivated level during the first initialization period and an activated level during the compensation period.

4. The display device of claim 2 , wherein the fourth transistor receives the second scan signal.

5. the first transistor includes a first electrode connected to the cathode, a second electrode connected to the second power line, and a gate connected to the first node; 4. The display device of claim 3, wherein the fourth transistor includes a first electrode connected to the first power line, a second electrode connected to the first electrode of the first transistor, and a gate receiving the third scan signal.

6. The pixel is a first initialization transistor connected between the second electrode of the first transistor and a first initialization voltage line to receive a fourth scan signal; The display device of claim 5 , further comprising: a first capacitor connected between the first node and a second node connected to the first transistor and the first initialization transistor.

7. the fourth scan signal is activated during a first initialization period and is inactivated during a data write period in which the first scan signal is activated; The display device of claim 6 , wherein the first initialization period is located before the data writing period.

8. The display device of claim 7 , wherein the fourth scan signal is further activated during a second initialization period that follows the data write period.

9. The display device of claim 8, wherein the second, third, and fourth transistors are turned off during the second initialization period.

10. The pixel is a plurality of pixels, and the plurality of pixels each include a first light-emitting element that emits light of a first color and a second light-emitting element that emits light of a second color different from the first color; 7. The display device of claim 6, wherein the first initialization voltage line includes a 1-1 initialization voltage line connected to the first light emitting element and receiving a 1-1 initialization voltage, and a 1-2 initialization voltage line connected to the second light emitting element and receiving a 1-2 initialization voltage different from the 1-1 initialization voltage.

11. The pixel is a second initialization transistor connected between the cathode of the light emitting device and a second initialization voltage line, The display device of claim 6 , wherein the first initialization voltage line and the second initialization voltage line receive different initialization voltages.

12. the fourth transistor receives the third scan signal; the second initialization transistor receives the fourth scan signal; The display device of claim 11 , wherein a period during which the third scan signal is activated and a period during which the fourth scan signal is activated do not overlap each other.

13. The display panel displays an image during a plurality of frames, at least one of the plurality of frames including a write frame and a holding frame; the first, second, and third scan signals have an active level during the write frame and are maintained in an inactive state during the holding frame; The display device of claim 11 , wherein the fourth scan signal has an activation level in the write frame and the holding frame.

14. The pixel is a plurality of pixels, and the plurality of pixels each include a first light-emitting element that emits light of a first color and a second light-emitting element that emits light of a second color different from the first color; 12. The display device of claim 11, wherein the second initialization voltage line includes a 2-1 initialization voltage line connected to the first light emitting element and receiving a 2-1 initialization voltage, and a 2-2 initialization voltage line connected to the second light emitting element and receiving a 2-2 initialization voltage different from the 2-1 initialization voltage.

15. the second initialization transistor receives a fifth scan signal; the fourth scan signal is activated during a first initialization period, and the fifth scan signal is activated during the first initialization period and the second initialization period; the fourth scan signal and the fifth scan signal are inactivated during a data write period during which the first scan signal is activated; The display device of claim 11 , wherein the first initialization period is located before the data writing period, and the second initialization period is located after the data writing period.

16. The display device of claim 15, wherein the fourth scan signal is further activated during the second initialization period.

17. The display panel displays an image during a plurality of frames, at least one of the plurality of frames including a write frame and a holding frame; the fourth scan signal has an active level in the write frame and is maintained in an inactive state during the holding frame; The display device of claim 15 , wherein the fifth scan signal has an activation level in the holding frame.

18. The pixel is a first light emission control transistor connected between the first electrode and the cathode of the first transistor and configured to receive a light emission control signal; The display device of claim 5 , further comprising: a second light emission control transistor connected between the second electrode of the first transistor and the second power line, the second light emission control transistor receiving the light emission control signal.

19. The pixel is a second capacitor connected between the second electrode of the first transistor and one of the first and second power supply lines, The display device of claim 5 , wherein the first transistor further comprises a back gate connected to the second electrode of the first transistor.

20. The display device according to claim 1 , wherein each of the first to fourth transistors is an N-type transistor.

21. a first driving voltage received by the first power line is higher than a second driving voltage received by the second power line; The display device of claim 1 , wherein the reference voltage received by the reference voltage line is between the first driving voltage and the second driving voltage.

22. The light-emitting element is an electronic control layer disposed on the cathode; a light-emitting layer disposed on the electronic control layer; a hole control layer disposed on the light emitting layer, The display device of claim 1 , wherein the anode is disposed on the hole control layer.

23. The display device of claim 1 , wherein the second power line comprises a Ti / Al / Ti structure.

24. the anode comprises a MgAg alloy; The display of claim 1 , wherein the cathode comprises an ITO / Ag / ITO structure.

25. The display device of claim 1 , wherein the second power line is disposed on the same layer as the data line and contains the same material.

26. The display device according to claim 1 , wherein the second power line is disposed on the same layer as the first power line and contains the same material as the first power line.

27. The display device of claim 1 , wherein the anode is directly connected to the first power line.

28. The display device of claim 1 , further comprising a connecting conductive pattern connecting the anode and the first power line.

29. the display panel includes a display area in which the pixels are arranged and a non-display area surrounding at least a portion of the display area, 2. The display device according to claim 1, wherein a plurality of the pixels are provided, a plurality of the anodes are provided and arranged separately for each of the pixels, and each of the anodes is connected to the first power supply line within the display area.

30. the display panel includes a display area in which the pixels are arranged and a non-display area surrounding at least a portion of the display area, The display device according to claim 1 , wherein a plurality of the pixels are provided, the anode is disposed in common to the pixels, and the anode is connected to the first power line within the non-display area.

31. The light-emitting element is an intermediate layer disposed on the anode and including at least a light-emitting layer; The display device according to claim 1 , wherein the cathode is disposed on the intermediate layer.

32. the display panel further includes a separator having an obtuse taper angle; The pixel is a plurality of pixels, and the plurality of pixels each include a first light-emitting element that emits light of a first color and a second light-emitting element that emits light of a second color different from the first color; 32. The display device of claim 31, wherein the separator divides the cathode of the first light emitting element and the cathode of the second light emitting element.

33. The display device of claim 31, wherein the display panel further comprises a connection line electrically connecting the first transistor and the cathode.

34. the interconnection wiring includes a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer; 34. The display device of claim 33, wherein a side surface of the third layer protrudes outward from a side surface of the second layer, and the cathode is in contact with the side surface of the second layer.

35. The display panel includes: a pixel defining membrane having an opening defined therein exposing at least a portion of the anode; a connecting electrode disposed on the pixel defining layer and electrically connected to the first transistor and the cathode; a separator disposed on the pixel defining film, The display device of claim 31 , wherein the lower surface of the cathode contacts the upper surface of the connecting electrode in a contact region adjacent to the separator.

36. The display device according to claim 35 , wherein the connecting electrode has a ring shape surrounding the opening.

37. The display device of claim 35, wherein the separator includes a first side and a second side that are tapered at different angles relative to an upper surface of the pixel defining layer.

38. The pixels and the connecting electrodes are each provided in a plurality of parts, Each of the plurality of connecting electrodes electrically connects the first transistor and the cathode in a corresponding pixel among the plurality of pixels; The display device of claim 35 , wherein gaps between adjacent ones of the plurality of connecting electrodes overlap the separator.

39. a display panel including pixels; The pixel is a light emitting device including an anode and a cathode connected to a first power line; a driving transistor including a first electrode connected to the cathode, a second electrode connected to a second power line, and a gate connected to a first node; a switching transistor connected between the first node and a data line; a light emitting control transistor connected between the first electrode and the cathode of the driving transistor; a compensation transistor connected between the first electrode of the driving transistor and the first power line; an initialization transistor coupled between the cathode and an initialization voltage line; The compensation transistor and the initialization transistor receive different scan signals.

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