Semiconductor device

Abstract

To provide a semiconductor device that reduces the contact resistance between a terminal and a bus bar while easing restrictions on bus bar design.SOLUTION: A semiconductor device includes a substrate 100, three P input terminals 4a, 4b, and 4c provided on the substrate, three N input terminals 5a, 5b, and 5c provided on the substrate, and output terminals 6a, 6b, and 6c provided on the substrate. The P input terminal, the N input terminal, and the output terminal are arranged in that order on a straight line (on axis Y1, axis Y2, and axis Y3) in the longitudinal direction of the substrate.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The technology disclosed in this specification relates to semiconductor technology.

Background Art

[0002] Generally, in power semiconductor modules typified by insulated gate bipolar transistors (IGBTs), intelligent power modules (IPMs), or transfer-molded power modules (TPMs), current density has been increasing due to miniaturization of packages, and the amount of current flowing through each module tends to increase.

[0003] Therefore, heat generation due to the contact resistance between terminals and busbars, which had little impact in the past, can no longer be ignored due to the increase in the amount of high current, and there are situations where operating conditions of inverters and the like have to be relaxed due to terminal heat generation.

[0004] On the other hand, for example, in Patent Document 1 (Japanese Patent Application Laid-Open No. 2023-29342), by providing the P terminal and the N terminal in consideration of the height of the busbar, the busbar can be connected to the module while remaining flat, and as a result, a structure that can sufficiently secure the contact area with the terminals is shown.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In Patent Document 1 (Japanese Patent Application Laid-Open No. 2023-29342), a configuration having PN terminals with different heights is shown in consideration of the thickness of the bus bar. However, in this configuration, there is a problem that the design of the bus bar is restricted by the relationship with the height of the PN terminals.

[0007] The technology disclosed in the specification of the present application has been made in view of the problems as described above, and is a technology for reducing the contact resistance between the terminals and the bus bar and relaxing the restrictions on the design of the bus bar.

Means for Solving the Problems

[0008] A semiconductor device according to a first aspect of the technology disclosed in the specification of the present application includes a base material, three P input terminals provided on the base material, three N input terminals provided on the base material, and an output terminal provided on the base material. In the longitudinal direction of the base material, the P input terminals, the N input terminals, and the output terminal are arranged in a straight line in that order.

Effects of the Invention

[0009] According to at least the first aspect of the technology disclosed in the specification of the present application, by increasing the number of input terminals to increase and disperse the current paths on the input side, it is possible to suppress the concentration of heat without imposing restrictions on the design of the bus bar.

[0010] Also, the objects, features, aspects, and advantages related to the technology disclosed in the specification of the present application will become more apparent from the following detailed description and the accompanying drawings.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

Figure 4

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Figure 6

Embodiments for Carrying Out the Invention

[0012] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following embodiments, detailed features and the like are also shown for the purpose of explaining the technology, but these are examples, and not all of them are necessarily essential features for the embodiments to be practicable.

[0013] Note that the drawings are shown schematically, and for convenience of explanation, omissions of configurations or simplifications of configurations are made in the drawings as appropriate. Also, the mutual relationships of the sizes and positions of the configurations shown in different drawings are not necessarily accurately described and can be changed as appropriate. Also, in drawings such as a plan view that is not a cross-sectional view, hatching may be added to facilitate understanding of the content of the embodiment.

[0014] Also, in the descriptions shown below, the same reference numerals are given to and illustrated for the same components, and their names and functions are also considered the same. Therefore, detailed descriptions thereof may be omitted to avoid duplication.

[0015] Also, in the descriptions described in the present specification, when a component is described as "comprising", "including", or "having", etc., it is not an exclusive expression excluding the existence of other components unless otherwise specified.

[0016] In addition, in the descriptions set forth in the specification of the present application, even when ordinal numbers such as "first" or "second" are used, these terms are used for convenience in order to facilitate understanding of the content of the embodiments, and the content of the embodiments is not limited to the order or the like that may be caused by these ordinal numbers.

[0017] In addition, in the descriptions set forth in the specification of the present application, expressions such as “… axis positive direction” or “… axis negative direction” mean that the direction along the arrow of the illustrated … axis is the positive direction, and the direction opposite to the arrow of the illustrated … axis is the negative direction.

[0018] In addition, in the descriptions set forth in the specification of the present application, even when terms that mean specific positions or directions such as "up", "down", "left", "right", "side", "bottom", "front" or "back" are used, these terms are used for convenience in order to facilitate understanding of the content of the embodiments, and are not related to the position or direction when the embodiments are actually implemented.

[0019] In addition, in the descriptions set forth in the specification of the present application, when described as “… upper surface” or “… lower surface”, in addition to the upper surface itself or the lower surface itself of the target component, a state in which other components are formed on the upper surface or the lower surface of the target component is also included. That is, for example, when described as "B provided on the upper surface of A", it does not prevent another component "C" from intervening between A and B.

[0020] <First Embodiment> Hereinafter, a semiconductor device according to the present embodiment will be described.

[0021] <Regarding the Configuration of the Semiconductor Device> FIG. 1 is a plan view showing an example of the configuration of a semiconductor device according to the present embodiment. As shown in the example of FIG. 1, a power semiconductor module 3a, a power semiconductor module 3b, and a power semiconductor module 3c are respectively connected to a P bus bar 2a and an N bus bar 2b. The P bus bar 2a and the N bus bar 2b are arranged such that a part of them overlaps in a plan view while being separated from each other.

[0022] In addition, a plurality of capacitors 1 connected in parallel with each other are provided on the P bus bar 2a and the N bus bar 2b. Each capacitor 1 has a positive electrode connected to the P bus bar 2a and a negative electrode connected to the N bus bar 2b.

[0023] FIG. 2 is a plan view showing an example of the terminal arrangement of the power semiconductor module 3a shown in FIG. 1. As shown in the example of FIG. 2, the power semiconductor module 3a includes a P input terminal 4a, a P input terminal 4b, a P input terminal 4c, an N input terminal 5a, an N input terminal 5b, an N input terminal 5c, an AC output terminal 6a, an AC output terminal 6b, and an AC output terminal 6c provided on a base material 100. The P input terminal 4a, the P input terminal 4b, and the P input terminal 4c are provided independently of each other. Similarly, the N input terminal 5a, the N input terminal 5b, and the N input terminal 5c are provided independently of each other. Similarly, the AC output terminal 6a, the AC output terminal 6b, and the AC output terminal 6c are provided independently of each other.

[0024] The base material 100 includes a semiconductor substrate having an element structure and a wiring structure on its upper surface.

[0025] In the present embodiment, by providing the P input terminal 4b and the N input terminal 5b that were not provided on the base material 100 in the conventional configuration, the current near the input terminals can be dispersed, and the heat generation amount at that location can be suppressed.

[0026] The P input terminal 4a, the P input terminal 4b, and the P input terminal 4c are connected to the laminated P bus bar 2a. The N input terminal 5a, the N input terminal 5b, and the N input terminal 5c are connected to the laminated N bus bar 2b.

[0027] Further, the P input terminal 4a, the N input terminal 5a, and the AC output terminal 6a are arranged in that order linearly along the longitudinal direction of the module (the Y-axis direction in FIG. 2) (arranged on the axis Y1). Similarly, the P input terminal 4b, the N input terminal 5b, and the AC output terminal 6b are arranged in that order linearly along the longitudinal direction of the module (arranged on the axis Y2). Similarly, the P input terminal 4c, the N input terminal 5c, and the AC output terminal 6c are arranged in that order linearly along the longitudinal direction of the module (arranged on the axis Y3).

[0028] Here, it is desirable that the P input terminal, the N input terminal, and the AC output terminal be provided at opposite ends in the longitudinal direction of the base material 100.

[0029] <Second Embodiment> A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above-described embodiment are denoted by the same reference numerals in the drawings, and detailed descriptions thereof will be omitted as appropriate.

[0030] <Regarding the Configuration of the Semiconductor Device> FIG. 3 is a plan view showing another example of the terminal arrangement of the power semiconductor module shown in FIG. 1. As shown in the example of FIG. 3, the power semiconductor module 30a includes a P input terminal 40a, a P input terminal 40b, a P input terminal 40c, an N input terminal 50a, an N input terminal 50b, an N input terminal 50c, an AC output terminal 6a, an AC output terminal 6b, and an AC output terminal 6c. The P input terminal 40a, the P input terminal 40b, and the P input terminal 40c are integrally provided via a plate material 40 on the module surface (that is, provided by being electrically connected). Similarly, the N input terminal 50a, the N input terminal 50b, and the N input terminal 50c are integrally provided via a plate material 50 on the module surface (that is, provided by being electrically connected).

[0031] By electrically connecting each of the terminals on the surface of the module, it is possible to prevent deterioration of the current balance for each terminal. As a result, it is possible to suppress the temperature rise caused by terminal heating.

[0032] <Third Embodiment> A semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the above-described embodiments will be denoted by the same reference numerals and illustrated, and detailed descriptions thereof will be omitted as appropriate.

[0033] <Regarding the Configuration of the Semiconductor Device> FIG. 4 is a perspective view showing an example of the terminal structure of the power semiconductor module 30a shown in FIG. 3. As shown in the example of FIG. 4, the N input terminals 50a, 50b, and 50c have an upper surface 50d and a side surface 50e that are integrally formed via a plate material 50. Here, the side surface 50e is the surface farthest from the P bus bar 2a, that is, the surface on the opposite side of the N input terminals 50a, 50b, and 50c from the surface facing the P input terminals 40a, 40b, and 40c.

[0034] In the example shown in FIG. 3, the N bus bar 2b is provided in contact with only the upper surface 50d, but in the example of FIG. 4, the N bus bar is provided in contact with both the upper surface 50d and the side surface 50e.

[0035] FIG. 5 is a side view showing an example of the configuration of the N bus bar provided in contact with the upper surface 50d and the side surface 50e. As shown in the example of FIG. 5, the N bus bar 20b has a bent portion 200b that bends 90° so as to be in contact with the upper surface 50d and the side surface 50e. Note that an opening (not shown here) is formed in the N bus bar 2b at the location where the P bus bar 2a and the P input terminal 40a are in contact, and the P bus bar 2a can be in contact with the P input terminal 40a without contacting the N bus bar 2b.

[0036] <Fourth Embodiment> A semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the above-described embodiment will be denoted by the same reference numerals and illustrated, and detailed descriptions thereof will be omitted as appropriate.

[0037] <Regarding the configuration of the semiconductor device> FIG. 6 is a perspective view showing an example of the configuration of a power semiconductor module according to this embodiment. As shown in the example of FIG. 6, the power semiconductor module 31a includes a P input terminal 4a, a P input terminal 41b, a P input terminal 4c, an N input terminal 5a, an N input terminal 51b, an N input terminal 5c, an AC output terminal 6a, an AC output terminal 6b, and an AC output terminal 6c. The P input terminal 4a, the P input terminal 41b, and the P input terminal 4c are provided independently of each other. Similarly, the N input terminal 5a, the N input terminal 51b, and the N input terminal 5c are provided independently of each other.

[0038] The height of the upper surface of the P input terminal 41b is set higher than the height of the upper surface of the P input terminal 4a and the height of the upper surface of the P input terminal 4c, with an upper limit of, for example, 10 mm. Similarly, the height of the upper surface of the N input terminal 51b is set higher than the height of the upper surface of the N input terminal 5a and the height of the upper surface of the N input terminal 5c, with an upper limit of, for example, 10 mm.

[0039] As shown in FIGS. 3 and 4, the P input terminal 4a, the P input terminal 41b, and the P input terminal 4c may be integrally formed via a plate material. Similarly, the N input terminal 5a, the N input terminal 51b, and the N input terminal 5c may be integrally formed via a plate material.

[0040] By setting the height of the upper surface of the P input terminal 41b and the height of the upper surface of the N input terminal 51b to be higher than the height of the upper surfaces of the other terminals, even without tightening the P input terminal 41b and the N input terminal 51b with screws, they are fixed while sufficient pressure is applied by the bus bars that contact from the upper surface. Therefore, even when only the P input terminal 4a, the P input terminal 4c, the N input terminal 5a, and the N input terminal 5c are tightened and fixed with screws, sufficient pressure is applied to the contact surfaces between the P input terminal 41b and the N input terminal 51b and the corresponding bus bars respectively. As a result, current can flow appropriately from the P input terminal 41b and the N input terminal 51b, and heat generation of the terminals can be suppressed.

[0041] <Effects caused by the plurality of embodiments described above> Next, examples of the effects caused by the plurality of embodiments described above are shown. In the following description, although the effects are described based on the specific configurations shown in the examples in the plurality of embodiments described above, within the range where the same effects occur, they may be replaced with other specific configurations shown in the present specification. That is, for the sake of convenience, in the following, only one of the corresponding specific configurations may be described representatively, but the specifically described representative configuration may be replaced with other corresponding specific configurations.

[0042] Also, such replacement may be made across a plurality of embodiments. That is, even when the respective configurations shown in different embodiments are combined to produce the same effects, it may be the case.

[0043] According to the embodiments described above, the semiconductor device includes a base material 100, three P input terminals (P input terminal 4a, P input terminal 4b, P input terminal 4c, P input terminal 40a, P input terminal 40b, P input terminal 40c, or P input terminal 41b) provided on the base material 100, three N input terminals (N input terminal 5a, N input terminal 5b, N input terminal 5c, N input terminal 50a, N input terminal 50b, N input terminal 50c, or N input terminal 51b) provided on the base material 100, and output terminals (AC output terminal 6a, AC output terminal 6b, or AC output terminal 6c) provided on the base material 100. In the longitudinal direction of the base material 100, the P input terminals, N input terminals, and output terminals are arranged in a straight line in that order.

[0044] According to such a configuration, by increasing the number of input terminals and increasing and dispersing the current paths on the input side, it is possible to suppress the concentration of heat quantity without imposing restrictions on the design of the bus bar (without considering the shape of the bus bar so as to improve heat dissipation).

[0045] In addition, the contact resistance value between the input terminal and the bus bar can be reduced to suppress heat generation.

[0046] Moreover, by arranging each pair of P input terminals, N input terminals, and AC output terminals in a straight line along the Y-axis direction, the current path flowing in the Y-axis direction can be extended to the terminal portion (that is, it can be extended from the location where the P input terminal or N input terminal is arranged to the location where the AC output terminal is arranged).

[0047] As a result, the range in which the magnetic field generated by di / dt can be canceled between the first current in the negative Y-axis direction flowing from the P input terminal to the AC output terminal and the second current in the positive Y-axis direction flowing from the AC output terminal to the N input terminal is extended. Therefore, the surge voltage can be suppressed.

[0048] In addition, when other configurations exemplified in the specification of the present application are appropriately added to the above configuration, that is, even when other configurations in the specification of the present application that are not mentioned as the above configuration are appropriately added, the same effects can be achieved.

[0049] Also, according to the embodiments described above, the P input terminal 40a, the P input terminal 40b, and the P input terminal 40c are electrically connected to each other via the plate member 40 and provided integrally. Further, the N input terminal 50a, the N input terminal 50b, and the N input terminal 50c are electrically connected to each other via the plate member 50 and provided integrally. According to such a configuration, by electrically connecting each input terminal on the surface of the semiconductor module, it is possible to suppress deterioration of the current balance for each input terminal. In addition, by making the input terminals integral, resin can be prevented from remaining between the input terminals, and electrical connection between the bus bar and the input terminals can be promoted, so that the contact resistance between the bus bar and the input terminals can be reduced.

[0050] Also, according to the embodiments described above, the integrally provided N input terminal has an upper surface 50d and a side surface 50e. The side surface 50e of the N input terminal is a surface opposite to the surface facing the integrally provided P input terminal. And the semiconductor device includes an N bus bar 20b provided in contact with the upper surface 50d and the side surface 50e of the integrally provided N input terminal. According to such a configuration, since the contact area between the N bus bar 20b and the N input terminals N input terminal 50a, the N input terminal 50b, and the N input terminal 50c can be increased, terminal heat generation can be suppressed.

[0051] Also, according to the embodiments described above, each P input terminal is a first P input terminal, a second P input terminal, and a third P input terminal. Here, the first P input terminal corresponds to, for example, P input terminal 4a or the like. Also, the second P input terminal corresponds to, for example, P input terminal 41b or the like. Also, the third P input terminal corresponds to, for example, P input terminal 4c or the like. The P input terminal 4a, the P input terminal 41b, and the P input terminal 4c are arranged in a straight line in that order. Also, the height of the upper surface of the P input terminal 41b is higher than the height of the upper surface of the P input terminal 4a and the height of the upper surface of the P input terminal 4c, and the difference between the height of the upper surface of the P input terminal 41b and the height of the upper surface of the P input terminal 4a and the height of the upper surface of the P input terminal 4c is 10 mm or less. Also, each N input terminal is a first N input terminal, a second N input terminal, and a third N input terminal. Here, the first N input terminal corresponds to, for example, N input terminal 5a or the like. Also, the second N input terminal corresponds to, for example, N input terminal 51b or the like. Also, the third N input terminal corresponds to, for example, N input terminal 5c or the like. The N input terminal 5a, the N input terminal 51b, and the N input terminal 5c are arranged in a straight line in that order. Also, the height of the upper surface of the N input terminal 51b is higher than the height of the upper surface of the N input terminal 5a and the height of the upper surface of the N input terminal 5c, and the difference between the height of the upper surface of the N input terminal 51b and the height of the upper surface of the N input terminal 5a and the height of the upper surface of the N input terminal 5c is 10 mm or less. According to such a configuration, by setting the upper surfaces of the input terminals (P input terminal 41b and N input terminal 51b) in the central portion higher than the upper surfaces of the other input terminals (P input terminal 4a, P input terminal 4c, N input terminal 5a, and N input terminal 5c), sufficient pressure is applied to fix the P input terminal 41b and the N input terminal 51b without tightening them with screws. Therefore, current can flow appropriately from the P input terminal 41b and the N input terminal 51b, suppressing heat generation of the terminals.

[0052] <Regarding the modifications of the above-described multiple embodiments> In the above-described multiple embodiments, the materials, materials, dimensions, shapes, relative arrangement relationships, or implementation conditions of each component may also be described, but these are all examples in all aspects and are not limiting.

[0053] Therefore, numerous variations and equivalents that are not shown are envisioned within the scope of the technology disclosed in this specification. For example, when at least one component is deformed, added, or omitted, or when at least one component in at least one embodiment is extracted and combined with components in other embodiments.

[0054] Also, in at least one of the above-described embodiments, when the material name or the like is described without specific designation, as long as there is no contradiction, it is assumed that the material contains other additives, such as alloys.

[0055] Also, as long as there is no contradiction, when it is described in the above-described embodiments that "one" component is provided, the component may be provided with "one or more".

[0056] Furthermore, each component in the above-described embodiments is a conceptual unit, and within the scope of the technology disclosed in this specification, it includes the case where one component consists of multiple structures, the case where one component corresponds to a part of a certain structure, and further, the case where multiple components are provided in one structure.

[0057] Also, each component in the above-described embodiments includes structures having other structures or shapes as long as they perform the same function.

[0058] Also, the descriptions in this specification are referenced for all purposes related to this technology, and none of them are considered to be prior art.

[0059] Hereinafter, aspects of the present disclosure will be collectively described as appendices.

[0060] (Appendix 1) A base material, Three P input terminals provided on the base material, Three N input terminals provided on the base material, An output terminal provided on the base material, and In the longitudinal direction of the base material, the P input terminals, the N input terminals, and the output terminal are arranged in a straight line in that order. A semiconductor device.

[0061] (Appendix 2) The semiconductor device according to Appendix 1, The three P input terminals are electrically connected to each other via a first plate material and provided integrally, The three N input terminals are electrically connected to each other via a second plate material and provided integrally. A semiconductor device.

[0062] (Appendix 3) The semiconductor device according to Appendix 2, The integrally provided N input terminals have an upper surface and a side surface, The side surface of the N input terminal is the surface opposite to the surface facing the integrally provided P input terminal, The semiconductor device further includes an N bus bar provided in contact with the upper surface and the side surface of the integrally provided N input terminal. A semiconductor device.

[0063] (Appendix 4) The semiconductor device according to any one of Appendices 1 to 3, Each of the P input terminals is designated as the first P input terminal, the second P input terminal, and the third P input terminal, The first P input terminal, the second P input terminal, and the third P input terminal are arranged in a straight line in that order. The height of the upper surface of the second P input terminal is higher than the height of the upper surface of the first P input terminal and the height of the upper surface of the third P input terminal. The difference between the height of the upper surface of the second P input terminal and the height of the upper surface of the first P input terminal and the height of the upper surface of the third P input terminal is 10 mm or less. Each of the N input terminals is defined as a first N input terminal, a second N input terminal, and a third N input terminal. The first N input terminal, the second N input terminal, and the third N input terminal are arranged in a straight line in that order. The height of the upper surface of the second N input terminal is higher than the height of the upper surface of the first N input terminal and the height of the upper surface of the third N input terminal. The difference between the height of the upper surface of the second N input terminal and the height of the upper surface of the first N input terminal and the height of the upper surface of the third N input terminal is 10 mm or less. Semiconductor device.

Description of Signs

[0064] 1 Capacitor, 2 Left and right, 2a P bus bar, 2b N bus bar, 3a Power semiconductor module, 3b Power semiconductor module, 3c Power semiconductor module, 4a P input terminal, 4b P input terminal, 4c P input terminal, 5a N input terminal, 5b N input terminal, 5c N input terminal, 6a AC output terminal, 6b AC output terminal, 6c AC output terminal, 20b N bus bar, 30a Power semiconductor module, 31a Power semiconductor module, 40 Plate material, 40a P input terminal, 40b P input terminal, 40c P input terminal, 41b P input terminal, 50 Plate material, 50a N input terminal, 50b N input terminal, 50c N input terminal, 50d Upper surface, 50e Side surface, 51b N input terminal, 100 Substrate, 200b Bending portion.

Claims

1. A base material, Three P input terminals provided on the base material, Three N input terminals provided on the base material, An output terminal provided on the base material, and In the longitudinal direction of the base material, the P input terminals, the N input terminals, and the output terminal are arranged in a straight line in that order. A semiconductor device.

2. The semiconductor device according to Claim 1, The three P input terminals are electrically connected to each other via a first plate material and provided integrally, The three N input terminals are electrically connected to each other via a second plate material and provided integrally. A semiconductor device.

3. The semiconductor device according to Claim 2, The integrally provided N input terminal has an upper surface and a side surface, The side surface of the N input terminal is the surface opposite to the surface facing the integrally provided P input terminal, The semiconductor device further includes an N bus bar provided in contact with the upper surface and the side surface of the integrally provided N input terminal. A semiconductor device.

4. The semiconductor device according to any one of Claims 1 to 3, Each of the P input terminals is defined as a first P input terminal, a second P input terminal, and a third P input terminal, The first P input terminal, the second P input terminal, and the third P input terminal are arranged in a straight line in that order, The height of the upper surface of the second P input terminal is higher than the height of the upper surface of the first P input terminal and the height of the upper surface of the third P input terminal, The difference between the height of the upper surface of the second P input terminal, the height of the upper surface of the first P input terminal, and the height of the upper surface of the third P input terminal is 10 mm or less, Each of the N input terminals is defined as a first N input terminal, a second N input terminal, and a third N input terminal, The first N input terminal, the second N input terminal, and the third N input terminal are arranged in a straight line in that order, The height of the upper surface of the second N input terminal is higher than the height of the upper surface of the first N input terminal and the height of the upper surface of the third N input terminal, The difference between the height of the upper surface of the second N input terminal, the height of the upper surface of the first N input terminal, and the height of the upper surface of the third N input terminal is 10 mm or less. A semiconductor device.

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