Semiconductor device

Abstract

To provide a semiconductor device which can suppress concentration of currents in the lower part of an active cell region.SOLUTION: An insulated gate bipolar transistor (IGBT) 100 includes a first trench gate electrode 16a extending in a first width direction; and a second trench gate electrode 16b facing the first trench gate electrode 16a. A first positional range of a first channel region in a first width direction formed by the first trench gate electrode 16a and a second positional range of a second channel region in a first width direction formed by a second trench gate electrode 16b are different from each other.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor) having a plurality of trench gate electrodes.

Background Art

[0002] Patent Document 1 discloses a technique related to an IE-type trench gate IGBT that utilizes the IE (Injection Enhancement) effect. The IE-type trench gate IGBT includes an active cell region and a hole collector cell region.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The IE-type trench gate IGBT has a problem that current tends to concentrate at the lower part of the active cell region.

[0005] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] A semiconductor device according to an embodiment includes a first trench gate electrode extending in a first width direction, and a second trench gate electrode facing the first trench gate electrode. A first position range in the first width direction of a first channel region formed by the first trench gate electrode and a second position range in the first width direction of a second channel region formed by the second trench gate electrode are different from each other.

Advantages of the Invention

[0007] According to the above embodiment, it is possible to provide a semiconductor device that suppresses the concentration of current at the lower part of the active cell region.

Brief Description of the Drawings

[0008]

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Modes for Carrying Out the Invention

[0009] For the sake of clarity of description, the following descriptions and drawings are appropriately omitted and simplified as needed. In each drawing, the same reference numerals are assigned to the same elements, and redundant descriptions are omitted as necessary.

[0010] Consideration Leading to Embodiments First, the IGBT 10 according to the comparative example will be described. Referring to FIG. 1, the outline of the IGBT 10 according to the comparative example will be described. The IGBT 10 includes an active cell region 41. A trench 43 is formed in the active cell region 41. The electrode embedded in the trench 43 formed in the active cell region 41 is connected to the gate. The active cell region 41 is basically configured in the same manner as an IE-type trench gate IGBT according to the prior art. However, tungsten is implanted in the contact implantation region 44, which is different in that it has a shrink structure.

[0011] FIG. 2 is a schematic cross-sectional view of the active cell region of the IGBT 10. The IGBT 10 includes an n-type semiconductor substrate 11. The semiconductor substrate 11 has a main surface 11a and a main surface 11b. The main surface 11b is the surface opposite to the main surface 11a. The semiconductor substrate 11 contains, for example, silicon as a material.

[0012] Here, for the sake of convenience of description, an XYZ orthogonal coordinate system is introduced. The direction orthogonal to the main surfaces 11a and 11b is defined as the Z-axis direction, and the direction from the main surface 11b toward the main surface is defined as the +Z-axis direction. Two orthogonal directions in the plane parallel to the main surfaces 11a and 11b are defined as the X-axis direction and the Y-axis direction. The +Z-axis direction is also referred to as upward, and the -Z-axis direction is also referred to as downward. Note that the XYZ axis directions, as well as upward and downward, are for convenience of explaining the IGBT 10 and do not indicate the directions when using the IGBT 10.

[0013] The semiconductor substrate 11 includes an n-type semiconductor region 21. A p-type well region 12 is formed around the active cell region. Also, an emitter electrode 13 is formed on the main surface 11a side of the semiconductor substrate 11, and a collector electrode 14 is formed on the main surface 11b side.

[0014] Two trenches are formed in the semiconductor region on the main surface 11a side of the semiconductor substrate 11. A trench gate electrode 16a is embedded in one of the trenches via a gate insulating film 15a. A trench gate electrode 16b is embedded in the other trench via a gate insulating film 15b. When the gate insulating films 15a and 15b are not distinguished from each other, they may simply be referred to as the gate insulating film 15. When the trench gate electrodes 16a and 16b are not distinguished from each other, they may simply be referred to as the trench gate electrode 16. The gate insulating film 15a insulates the trench gate electrode 16a from the channel region (also referred to as the first channel region) formed by the trench gate electrode 16a. Similarly, the gate insulating film 15b insulates the trench gate electrode 16b from the channel region (also referred to as the second channel region) formed by the trench gate electrode 16b.

[0015] A p-type semiconductor region 17 is formed between the trench gate electrode 16a and the trench gate electrode 16b, and n-type source regions 18a and 18b are formed on its surface. Lg represents the channel length of the channel formed by the trench gate electrodes 16a and 16b. The source region 18a is in contact with the gate insulating film 15a, and the source region 18b is in contact with the gate insulating film 15b. When the source regions 18a and 18b are not distinguished from each other, they may simply be referred to as the source region 18. The source region 18a injects carriers (e.g., electrons) into the first channel region. The source region 18b injects carriers into the second channel region.

[0016] An oxide film 19 is formed on the surface of the semiconductor substrate 11, and an opening is provided in the oxide film 19. The source regions 18a and 18b are electrically connected to the emitter electrode 13 through the opening of the oxide film 19.

[0017] FIG. 3 is a schematic top view of the cell region of the IGBT 10. For clarity, some illustrations of the oxide film 19 and the emitter electrode 13 are omitted.

[0018] The trench gate electrodes 16a and 16b extend in the Y direction. The regions where the source region 18 is formed and the regions where the source region 18 is not formed are alternately provided in the Y direction.

[0019] Wg represents the channel width of the channel formed by the trench gate electrode 16. The channel width represents the length of the channel region in the Y direction. The position range in the Y direction (also referred to as the first position range) of the channel region (the first channel region) formed by the trench gate electrode 16a and the position range in the Y direction (also referred to as the second position range) of the channel region (the second channel region) formed by the second trench gate electrode 16b overlap each other.

[0020] In the IGBT 10, since the above-described first position range and second position range overlap each other, there is a problem that current tends to concentrate and heat is easily generated at the lower part of the active cell region.

[0021] Embodiment 1 In the IGBT 100 according to Embodiment 1, the above-described first position range and second position range are different from each other. Thereby, it is possible to prevent current from concentrating at the lower part of the active cell region.

[0022] FIG. 4 shows a schematic top view of an IGBT 100a which is a first specific example of the IGBT 100. The position ranges of the source region 18a and the source region 18b in the Y direction are configured not to overlap each other. Therefore, the above-described first position range and the second position range do not overlap each other. In the IGBT 100a, since the first position range and the second position range do not overlap, the effect of suppressing current concentration is particularly large. Note that since the length of the source region 18a and the length of the source region 18b in the Y direction per unit area (the area surrounded by the dotted line) have not been changed from the IGBT 10, a sufficient current output can be obtained.

[0023] FIG. 5 is a schematic top view of an IGBT 100b which is a second specific example of the IGBT 100. Comparing FIG. 4 and FIG. 5, an n-type semiconductor region 18c is added. Since the pattern including the source region 18a, the source region 18b, and the semiconductor region 18c is not relatively fine, there is an advantage that the lithography difficulty is low. Note that since the semiconductor region 18c does not contact the gate insulating film 15, a channel region is not formed around the semiconductor region 18c. Since the first position range and the second position range do not overlap each other, the IGBT 100b can achieve the same effect as the IGBT 100a.

[0024] FIG. 6 is a schematic top view of an IGBT 100c which is a third specific example of the IGBT 100. The source regions 18a and 18b are provided along a straight line extending obliquely in the X direction. Since the above-described first position range and the second position range do not overlap each other, the IGBT 100c can achieve the same effect as the IGBT 100a. Also, there is an advantage that the pattern including the source regions 18a and 18b is not relatively fine.

[0025] FIG. 7 is a schematic top view of an IGBT 100d which is a fourth specific example of the IGBT 100. The source region 18 is formed in a trapezoidal shape, and the shorter base of the trapezoid (also referred to as the upper base) is in contact with the gate insulating film 15. The source regions 18a and 18b are arranged offset from each other in the Y direction, and exhibit the same effect as the IGBT100a. Also, there is an advantage that the pattern including the source regions 18a and 18b is not relatively fine.

[0026] FIG. 8 is a schematic top view of an IGBT 100e which is a fifth specific example of the IGBT 100. The source region 18 is formed in a trapezoidal shape, and the longer base of the trapezoid (also referred to as the lower base) is in contact with the gate insulating film 15. The source regions 18a and 18b are arranged offset from each other in the Y direction, and exhibit the same effect as the IGBT 100a. Also, in the IGBT 100e, there is an advantage that it is less likely to cause a parasitic bipolar action leading to thermal breakdown.

[0027] FIG. 9 is a diagram for explaining the equivalent circuit diagram of the IGBT 100. The IGBT 100 includes bipolar transistors Tr1 and Tr2 connected in series with each other. The base of the transistor Tr1 is connected to a p+-type semiconductor region 20 (contact) via a base resistance rb. A p+-type semiconductor region 22 (contact) is formed below the n-type semiconductor region 21. The base of the bipolar transistor Tr2 is connected to the p+-type semiconductor region 20 via a capacitor C.

[0028] The voltage drop between the emitter and the base of the bipolar transistor Tr1 is calculated as the product of the hole current Ib flowing through the resistor rb and the value of the resistor rb. When the voltage drop between the emitter and the base is large, the parasitic bipolar transistor Tr1 is turned on, resulting in a large current that cannot be controlled by the gate voltage, and the IGBT 100 is thermally destroyed. In the IGBT 100e, since the area where the source region 18 and the emitter electrode 13 (contact) are in contact is narrow, the hole current easily flows accordingly, the resistance rb becomes low, and the bipolar transistor Tr1 is less likely to turn on, so the possibility of thermal breakdown can be reduced.

[0029] Referring to FIG. 10, the IGBT 100f, which is the sixth specific example of the IGBT 100, will be described. The lower diagram in FIG. 10 shows a schematic top view of the IGBT 10 according to the comparative example, the middle diagram shows a schematic top view of the IGBT 100f, and the upper diagram shows a schematic top view of the IGBT 100a described above.

[0030] Referring to the middle diagram, in the IGBT 100f, the source region 18a and the source region 18b are arranged so as to be shifted from each other in the Y direction. Therefore, the above-described first position range and the second position range are different from each other. In the IGBT 100f, unlike the IGBT 100a, although the first position range and the second position range partially overlap, it has a certain effect in preventing current concentration. However, the effect exhibited by the IGBT 100f is smaller than the effect exhibited by the IGBT 100a.

[0031] FIG. 11 is a schematic top view of the IGBT 100g, which is the seventh example of the IGBT 100. The IGBT 100g includes the source region 18b and does not include the source region 18a. The length of the source region 18b in the Y direction in the IGBT 100g is twice the length of the source region 18b in the Y direction in the IGBT 10.

[0032] FIG. 12 shows, in a heat map format, the results of the thermal analysis of the IGBT 10 according to the comparative example and the results of the thermal analysis of the IGBT 100g. The left figure shows the results of the thermal analysis of the IGBT 10, and the right figure shows the results of the thermal analysis of the IGBT 100g. "1" represents the location where the electron current converges in the IGBT 10, and "2" represents the location with the highest temperature.

[0033] FIG. 13 shows the monitoring results of the time course of the Joule heat at "1" and "2". The upper figure shows the monitoring results of "1", and the lower figure shows the monitoring results of "2". The curve 91 included in the upper figure and the curve 92 included in the lower figure represent the monitoring results of the IGBT 10. The curve 93 included in the upper figure and the curve 94 included in the lower figure represent the monitoring results of the IGBT 100g. For both "1" and "2", the Joule heat generated in the IGBT 100g is reduced by approximately 30% from the Joule heat generated in the IGBT 10. Therefore, the IGBT 100g can reduce the generation of Joule heat. Similarly, it is considered that the IGBTs 100a to 100f can also reduce the generation of Joule heat.

[0034] The IGBT 100 according to Embodiment 1 can prevent the current from concentrating at the lower part of the active cell region and suppress the generation of Joule heat.

[0035] As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof.

[0036] For example, in the IGBT according to the above embodiment, a configuration in which the conductivity type (p-type or n-type) of the semiconductor substrate, semiconductor layer, diffusion layer (diffusion region), etc. is reversed may be used. Therefore, when one of the n-type and p-type conductivity types is defined as the first conductivity type and the other is defined as the second conductivity type, the first conductivity type can be p-type and the second conductivity type can be n-type, or conversely, the first conductivity type can be n-type and the second conductivity type can be p-type.

[0037] In the above embodiment, the case where the semiconductor device is an IGBT has been described as an example, but the present invention is not limited thereto. The above embodiment can also be applied to semiconductor devices other than IGBTs, such as power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors).

Explanation of Reference Numerals

[0038] 10, 100, 100a, 100b, 100c, 100d, 100e, 100f, 100g IGBT 11 Semiconductor substrate 11a, 11b Main surfaces 12 Well region 13 Emitter electrode 14 Collector electrode 15, 15a, 15b Gate insulating film 16, 16a, 16b Trench gate electrode 17, 18c, 20, 21, 22 Semiconductor regions 18, 18a, 18b Source regions 19 Oxide film Tr1, Tr2 Bipolar transistors rb Resistance C Capacitor 91, 92, 93, 94 Curves

Claims

1. a first trench gate electrode extending in a first width direction; a second trench gate electrode facing the first trench gate electrode; comprising a first position range in the first width direction of a first channel region formed by the first trench gate electrode and a second position range in the first width direction of a second channel region formed by the second trench gate electrode are different from each other a semiconductor device.

2. the first position range and the second position range do not overlap each other the semiconductor device according to Claim 1.

3. a first gate insulating film insulating the first trench gate electrode from the first channel region; a second gate insulating film insulating the second trench gate electrode from the second channel region; a first source region injecting carriers into the first channel region; a second source region injecting carriers into the second channel region; comprising the first source region and the second source region are provided along a straight line extending obliquely along a second width direction orthogonal to the first width direction the semiconductor device according to Claim 2.

4. a first gate insulating film insulating the first trench gate electrode from the first channel region; a second gate insulating film insulating the second trench gate electrode from the second channel region; a first source region injecting carriers into the first channel region; a second source region injecting carriers into the second channel region; comprising the first source region and the second source region are formed in a trapezoidal shape in a top view, and a shorter bottom side of the trapezoid contacts the first gate insulating film or the second gate insulating film the semiconductor device according to Claim 2.

5. a first gate insulating film insulating the first trench gate electrode from the first channel region; a second gate insulating film insulating the second trench gate electrode from the second channel region; a first source region injecting carriers into the first channel region; a second source region injecting carriers into the second channel region; comprising the first source region and the second source region are formed in a trapezoidal shape in a top view, and a longer bottom side of the trapezoid contacts the first gate insulating film or the second gate insulating film the semiconductor device according to Claim 2.

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