Amplifier and motor device

Abstract

To provide an amplifier capable of increasing response speed.SOLUTION: An amplifier (A1) includes: a first switched-capacitor amplifier (1A) and a second switched-capacitor amplifier (1B) to which input ends (INP, INN) are commonly connected; a controller (2) configured to execute a first control state in which the first switched-capacitor amplifier is in a reference acquisition phase and the second switched-capacitor amplifier is in a signal propagation phase, and a second control state in which the first switched-capacitor amplifier is in the signal propagation phase and the second switched-capacitor is in the reference acquisition phase; and a selector (3) configured to select and output an output in the signal propagation phase from the output of the first switched-capacitor amplifier and the output of the second switched-capacitor amplifier.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to an amplifier and a motor device.

Background Art

[0002] Conventionally, a switched capacitor amplifier circuit is known as a form of amplifier (see, for example, Patent Document 1).

[0003] The switched capacitor amplifier circuit disclosed in Patent Document 1 alternately switches between a first operation of receiving an input voltage from a signal source and holding a charge corresponding to the input voltage, and a second operation of outputting an output voltage obtained by amplifying the input voltage.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] [Summary] Since the switched capacitor amplifier circuit disclosed in Patent Document 1 has a configuration in which the first operation and the second operation are alternately switched, there is a problem that the response speed depends on the switching period.

[0006] In order to increase the response speed of the switched capacitor amplifier circuit disclosed in Patent Document 1, it is necessary to shorten the switching period.

[0007] However, since the minimum value to which the switching period can be shortened is determined by the response speed of the operational amplifier itself, which is a component of the switched capacitor amplifier circuit disclosed in Patent Document 1, there is a limit to shortening the switching period.

[0008] The amplifier according to the present disclosure includes a first switched-capacitor amplifier and a second switched-capacitor amplifier whose input terminals are commonly connected, a first control state in which the first switched-capacitor amplifier is in a reference acquisition phase and the second switched-capacitor amplifier is in a signal propagation phase, and a second control state in which the first switched-capacitor amplifier is in the signal propagation phase and the second switched-capacitor amplifier is in the reference acquisition phase, a controller configured to execute the above, and a selector configured to select and output the output of the first switched-capacitor amplifier and the output of the second switched-capacitor amplifier that is in the signal propagation phase among the outputs.

[0009] The motor device according to the present disclosure includes a motor, a motor driver configured to drive the motor, a shunt resistor configured to detect a current flowing through the motor, and the above amplifier configured to amplify a potential difference across both ends of the shunt resistor.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

[0011] [Detailed Description] <Schematic Configuration of the Amplifier According to the Embodiment> FIG. 1 is a block diagram showing the configuration of an amplifier A1 (hereinafter abbreviated as "amplifier A1") according to an embodiment. The amplifier A1 includes a positive input terminal INP, a negative input terminal INN, a first switched capacitor amplifier 1A, a second switched capacitor amplifier 1B, a controller 2, a selector 3, an output amplifier 4, and an output terminal OUT.

[0012] The positive input end of the first switched capacitor amplifier 1A and the negative input end of the second switched capacitor amplifier 1A are commonly connected and connected to the positive input terminal INP. The positive input terminal INP is a terminal configured to receive a positive input voltage Vinp.

[0013] The negative input end of the first switched capacitor amplifier 1A and the negative input end of the second switched capacitor amplifier 1A are commonly connected and connected to the negative input terminal INN. The negative input terminal INN is a terminal configured to receive a negative input voltage Vinn.

[0014] In the present embodiment, the first switched capacitor amplifier 1A and the second switched capacitor amplifier 1B have the same configuration. In the following description, when it is not necessary to distinguish between the first switched capacitor amplifier 1A and the second switched capacitor amplifier 1B, they may be collectively referred to as the switched capacitor amplifier 1. Note that, unlike the present embodiment, the first switched capacitor amplifier 1A and the second switched capacitor amplifier 1B may have different configurations from each other.

[0015] The controller 2 controls the first switch capacitor amplifier 1A and the second switch capacitor amplifier 1B. More specifically, the controller 2 controls the switches in the first switch capacitor amplifier 1A and the switches in the second switch capacitor amplifier 1B. The controller 2 further controls the selector 3. The controller 2 can be composed of a combination circuit of a delay circuit and logic, but a DSP (digital signal processor), a microcontroller, an FPGA (field-programmable gate array), etc. may also be used. The details of the control content of the controller 2 will be described later.

[0016] The selector 3 selects either the output of the first switch capacitor amplifier 1A or the output of the second switch capacitor amplifier 1B and outputs it to the output amplifier 4. The details of the selection content of the selector 3 will be described later.

[0017] The output amplifier 4 amplifies the signal output from the selector 3 (the output of the first switch capacitor amplifier 1A or the output of the second switch capacitor amplifier 1B) and supplies it to the output terminal OUT. If a desired gain can be obtained by the switch capacitor amplifier 1, the amplifier 1A may be configured without the output amplifier 4.

[0018] <Reference acquisition phase and signal propagation phase of the switch capacitor amplifier> The switch capacitor amplifier 1 becomes either a reference acquisition phase or a signal propagation phase under the control of the controller 2.

[0019] Figure 2 is a diagram showing the switch capacitor amplifier 1 during the reference acquisition phase. The switch capacitor amplifier 1 includes resistors R1 and R2, Zener diodes D1 and D2, switches SW1a, SW2b, SW3a, SW4a, SW5b, and SW6b, capacitors C0p, C0n, C1p, and C1n, and a fully differential amplifier FDA1.

[0020] The first terminal of resistor R1 is connected to the positive input terminal INP. The first terminal of resistor R2 is connected to the negative input terminal INN. The second terminal of resistor R1 is connected to the cathode of Zener diode D1, the anode of Zener diode D2, the first terminal of switch SW1a, and the first terminal of capacitor C0p. The second terminal of resistor R2 is connected to the anode of Zener diode D1, the cathode of Zener diode D2, and the first terminal of switch SW2b. The second terminals of switch SW1a and switch SW2b are connected to the first terminal of capacitor C0n.

[0021] The second terminal of capacitor C0p is connected to the positive input terminal of fully differential amplifier FDA1, the first terminal of switch SW3a, and the first terminal of capacitor C1p. The second terminal of capacitor C1p is connected to the first terminal of switch SW5b. The second terminals of switch SW3a and switch SW5b are connected to the positive output terminal of fully differential amplifier FDA1.

[0022] The second terminal of capacitor C0n is connected to the negative input terminal of fully differential amplifier FDA1, the first terminal of switch SW4a, and the first terminal of capacitor C1n. The second terminal of capacitor C1n is connected to the first terminal of switch SW6b. The second terminals of switch SW4a and switch SW6b are connected to the negative output terminal of fully differential amplifier FDA1.

[0023] In the switched capacitor amplifier 1 during the reference acquisition phase, as shown in Figure 2, switches SW1a, SW3a, and SW4a are in the on state (conducting state), and switches SW2b, SW5b, and SW6b are in the off state (blocking state).

[0024] In the switched capacitor amplifier 1 during the reference acquisition phase, with the positive input voltage Vinp applied to both the first terminal of capacitor C0p and the first terminal of capacitor C0n, the fully differential amplifier FDA1 enters the buffer state, so capacitors C0p and C0n hold zero voltage (the voltage corresponding to when the differential voltage between the positive input voltage Vinp and the negative input voltage Vinn becomes 0 [V]).

[0025] Figure 3 is a diagram showing the switch capacitor amplifier 1 during the signal propagation phase.

[0026] In the switch capacitor amplifier 1 during the signal propagation phase, as shown in FIG. 3, the switches SW1a, SW3a, and SW4a are in the off state (open state), and the switches SW2b, SW5b, and SW6b are in the on state (conducting state).

[0027] In the switch capacitor amplifier 1 during the signal propagation phase, the fully differential amplifier FDA1 is released from the buffer state, and the voltage applied to the capacitor C0n becomes the negative input voltage Vinn. Therefore, the fully differential amplifier FDA1 outputs a voltage VOUT proportional to the differential voltage between the positive input voltage Vinp and the negative input voltage Vinn.

[0028] <Control content of the controller and selection content of the selector> Figure 4 is a timing chart showing the state of the amplifier A1. In FIG. 4, 1st SCA indicates that the selector 3 selects the output of the first switch capacitor amplifier 1A. 2nd SCA in FIG. 4 indicates that the selector 3 selects the output of the second switch capacitor amplifier 1B. 1st CNT in FIG. 4 indicates that the controller 2 is executing the first control state. 2nd CNT in FIG. 4 indicates that the controller 2 is executing the second control state. 3rd CNT in FIG. 4 indicates that the controller 2 is executing the third control state.

[0029] The controller 2 executes a first control state in which the first switch capacitor amplifier 1A is in the reference acquisition phase and the second switch capacitor amplifier 1B is in the signal propagation phase, and a second control state in which the first switch capacitor amplifier 1A is in the signal propagation phase and the second switch capacitor amplifier 1B is in the reference acquisition phase.

[0030] The controller 2 makes the period of each reference acquisition phase shorter than the period of each signal propagation phase. Then, the controller 2 further executes a third control state in which both the first switch capacitor amplifier 1A and the second switch capacitor amplifier 1B are in the signal propagation phase. From another perspective, the controller 2 controls the switch capacitor amplifier 1 so that the period during which the first switch capacitor amplifier 1A is in the reference acquisition phase and the period during which the second switch capacitor amplifier is in the reference acquisition phase are separated. In other words, the controller 2 controls the switch capacitor amplifier 1 so that the period during which the first switch capacitor amplifier 1A is in the reference acquisition phase and the period during which the second switch capacitor amplifier is in the reference acquisition phase do not overlap.

[0031] The controller 2 alternately executes the first control state and the second control state. As a result, it is always possible to ensure the switch capacitor amplifier 1 during the signal propagation phase, so the response speed can be increased.

[0032] The controller 2 executes a third control state between the first control state and the second control state. As a result, even when one of the control of the first switch capacitor amplifier 1A by the controller 2 and the control of the second switch capacitor amplifier 1B by the controller 2 is delayed due to the influence of the control signal transmission path length or the like, it is always possible to ensure the switch capacitor amplifier 1 during the signal propagation phase, so the response speed can be increased more reliably.

[0033] The controller 2 controls the switch capacitor amplifier 1 and the selector 3 so that the period from the start of the third control state to the selection switching timing of the selector 3 is longer than the period from the selection switching timing of the selector 3 to the end of the third control state. As a result, after the selection switching timing, the selector 3 will transition from the reference acquisition phase to the signal propagation phase and select the switch capacitor amplifier 1 that is stable in the signal propagation phase. Thereby, it is possible to suppress the output of the amplifier A1 from becoming unstable immediately after the selection switching timing.

[0034] The controller 2 controls the switch capacitor amplifier 1 and the selector 3 such that the third control state ends immediately after the selection switching timing of the selector 3. That is, the controller 2 controls the switch capacitor amplifier 1 and the selector 3 while avoiding the coincidence of the selection switching timing of the selector 3 and the end timing of the third control state, and making the selection switching timing of the selector 3 approach the end timing of the third control state. Thereby, it is possible to further suppress the output of the amplifier A1 from becoming unstable immediately after the selection switching timing.

[0035] The selector 3 selects and outputs the output of the first switch capacitor amplifier 1A and the output of the second switch capacitor amplifier 1B that is in the signal propagation phase. Thereby, the output of the amplifier A1 becomes a real-time output with respect to the input of the amplifier A1.

[0036] FIG. 5 and FIG. 6 are diagrams showing waveforms in the embodiment. The waveform W1 is the waveform of the input of the amplifier A1 (the differential voltage Vinp - Vinn between the positive input voltage Vinp and the negative input voltage Vinn). The waveform W2 is the waveform of the output of the first switch capacitor amplifier 1A. The waveform W3 is the waveform of the output of the second switch capacitor amplifier 1B. The waveform W4 is the waveform of the output of the selector 3. Note that in FIGS. 5 and 6, the waveforms in the case where the gain of the switch capacitor amplifier 1 is 1 are illustrated, but the gain of the switch capacitor amplifier 1 is not limited to 1.

[0037] It can be seen from the waveform W4 that the output of the amplifier A1 is a real-time output with respect to the input of the amplifier A1 as described above.

[0038] Figs. 7 and 8 are diagrams showing waveforms in the comparative example. In the comparative example, only one switch capacitor amplifier 1 is provided, and the output of the switch capacitor amplifier 1 is sample-held by a sample and hold circuit. Waveform W1 is the waveform of the input of the amplifier according to the comparative example (the differential voltage Vinp - Vinn between the positive input voltage Vinp and the negative input voltage Vinn). Waveform W2 is the waveform of the output of the switch capacitor amplifier. Waveform W5 is the waveform of the output of the sample and hold circuit.

[0039] From waveform W5, it can be seen that in the amplifier according to the comparative example, the response speed cannot be increased.

[0040] <Application Example> Amplifier A1 is used, for example, as a current detection amplifier. Figs. 9 and 10 are diagrams showing application examples as a current detection amplifier.

[0041] In the application example shown in Fig. 9, the power supply voltage V+ is applied to the first end of the shunt resistor SR1, the first end of the load circuit LD1 is connected to the second end of the shunt resistor SR1, and the second end of the load circuit LD1 is connected to the ground potential. The potential difference across both ends of the shunt resistor SR1 serves as the input to the amplifier A1.

[0042] In the application example shown in Fig. 10, the power supply voltage V+ is applied to the first end of the load circuit LD1, the first end of the shunt resistor SR1 is connected to the second end of the load circuit LD1, and the second end of the shunt resistor SR1 is connected to the ground potential. The potential difference across both ends of the shunt resistor SR1 serves as the input to the amplifier A1.

[0043] Amplifier A1 may be incorporated into a motor device. Fig. 11 is a diagram showing a configuration example of a motor device.

[0044] The motor device 10 shown in Fig. 11 includes a motor 11, a motor driver 12 configured to drive the motor 11, a shunt resistor SR1, and an amplifier A1 that amplifies the potential difference across both ends of the shunt resistor SR1.

[0045] The motor driver 12 includes an inverter and an inverter control circuit that controls the inverter. The amplifier A1 detects the current drawn by the inverter from the motor 11 based on the potential difference across one shunt resistor SR1. The inverter control circuit controls the inverter using the detection result of the amplifier A1.

[0046] <Others> The above embodiments should be considered illustrative in all respects and not restrictive. The technical scope of the present disclosure is indicated not by the description of the above embodiments but by the claims, and it should be understood that all modifications belonging to the meaning and scope equivalent to the claims are included.

[0047] For example, in the above-described embodiment, the amplifier A1 includes two switch capacitor amplifiers 1, but the amplifier A1 may include three or more switch capacitor amplifiers 1. For example, when the amplifier A1 includes three or more switch capacitor amplifiers 1, the controller 2 may switch the phases of the three switch capacitor amplifiers 1 (first to third switch capacitor amplifiers) as shown in FIG. 12, for example.

[0048] <Supplementary Note> A supplementary note is provided for the present disclosure in which specific configuration examples were shown in the above embodiments.

[0049] The amplifier (A1) of the present disclosure includes a first switched-capacitor amplifier (1A) and a second switched-capacitor amplifier (1B) whose input terminals (INP, INN) are commonly connected, a first control state in which the first switched-capacitor amplifier is in a reference acquisition phase and the second switched-capacitor amplifier is in a signal propagation phase, and a second control state in which the first switched-capacitor amplifier is in the signal propagation phase and the second switched-capacitor amplifier is in the reference acquisition phase. A controller (2) configured to execute, and a selector (3) configured to select and output the output of the first switched-capacitor amplifier and the output of the second switched-capacitor amplifier that is in the signal propagation phase among the outputs of the first switched-capacitor amplifier and the second switched-capacitor amplifier. It is a configuration (first configuration).

[0050] According to the amplifier of the first configuration, it is possible to always ensure a switched-capacitor amplifier during the signal propagation phase, so the response speed can be increased.

[0051] In the amplifier of the first configuration, the controller may be configured to control the selector (second configuration).

[0052] In the amplifier of the first configuration, the period of each reference acquisition phase may be shorter than the period of each signal propagation phase (third configuration).

[0053] In the amplifier of the third configuration, the controller may be configured to execute a third control state in which both the first switched-capacitor amplifier and the second switched-capacitor amplifier are in the signal propagation phase (fourth configuration).

[0054] In the amplifier of the fourth configuration, the period from the start of the third control state to the selection switching timing of the selector may be longer than the period from the selection switching timing of the selector to the end of the third control state (fifth configuration).

[0055] In the amplifier of the fifth configuration described above, the third control state may end immediately after the selection switching timing of the selector (sixth configuration).

[0056] In the amplifier of any one of the third to sixth configurations described above, the period in which the first switch capacitor amplifier is in the reference acquisition phase and the period in which the second switch capacitor amplifier is in the reference acquisition phase may be separated from each other (seventh configuration).

[0057] The motor device (10) of the present disclosure includes a motor (11), a motor driver (12) configured to drive the motor, a shunt resistor (SR1), and an amplifier (A1) of any one of the first to seventh configurations described above configured to amplify the potential difference across both ends of the shunt resistor (eighth configuration).

Description of Reference Numerals

[0058] 1 Switch capacitor amplifier 1A First switch capacitor amplifier 1B Second switch capacitor amplifier 2 Controller 3 Selector 4 Output amplifier 10 Motor device 11 Motor 12 Motor driver A1 Amplifier according to the embodiment FDA1 Fully differential amplifier C0n, C0p, C1n, C1p Capacitors D1, D2 Zener diodes R1, R2 Resistors SR1 Shunt resistor SW1a, SW2b, SW3a, SW4a, SW5b, SW6b Switches INP Positive input terminal INN Negative input terminal OUT Output terminal W1~W5 Waveforms

Claims

1. A first switch capacitor amplifier and a second switch capacitor amplifier whose input terminals are commonly connected, a controller configured to execute a first control state in which the first switch capacitor amplifier is in a reference acquisition phase and the second switch capacitor amplifier is in a signal propagation phase, and a second control state in which the first switch capacitor amplifier is in the signal propagation phase and the second switch capacitor amplifier is in the reference acquisition phase; a selector configured to select and output the output of the first switch capacitor amplifier and the output of the second switch capacitor amplifier that is in the signal propagation phase among the outputs of the first switch capacitor amplifier and the second switch capacitor amplifier; An amplifier comprising.

2. The amplifier according to claim 1, wherein the controller is configured to control the selector.

3. The amplifier according to claim 1, wherein the period of each of the reference acquisition phases is shorter than the period of each of the signal propagation phases.

4. The amplifier according to claim 3, wherein the controller is configured to execute a third control state in which both the first switch capacitor amplifier and the second switch capacitor amplifier are in the signal propagation phase.

5. The amplifier according to claim 4, wherein the period from the start of the third control state to the selection switching timing of the selector is longer than the period from the selection switching timing of the selector to the end of the third control state.

6. The amplifier according to claim 5, wherein the third control state ends immediately after the selection switching timing of the selector.

7. The amplifier according to claim 3, wherein the period during which the first switch capacitor amplifier is in the reference acquisition phase and the period during which the second switch capacitor amplifier is in the reference acquisition phase are separated from each other.

8. A motor, a motor driver configured to drive the motor, a shunt resistor, an amplifier according to any one of claims 1 to 7 configured to amplify the potential difference across both ends of the shunt resistor; A motor device comprising.

Images