Amplifier circuit

Abstract

To provide an amplifier circuit capable of suppressing degradation of characteristics.SOLUTION: An amplifier circuit 100 comprises: a first splitter 14 which splits an input signal Si into a first signal S1 and a second signal S2; a control amplifier 10 which amplifies the first signal S1 and outputs the amplified signal as a third signal S3; a second splitter 16 which splits the second signal S2 into a fourth signal S4 and a fifth signal S5, which have different phases at the center frequency of the operating bandwidth; a first auxiliary amplifier 12a which amplifies the fourth signal S4 and outputs the amplified signal as a sixth signal S6; a second auxiliary amplifier 12b which amplifies the fifth signal S5 and outputs the amplified signal as a seventh signal S7; and a lumped-constant branch-line coupler 18 which synthesizes the third signal S3, the sixth signal S6, and the seventh signal S7 and outputs the synthesized signal as an output signal So. The power amplitude of the third signal S3 is smaller than the power amplitude of the output signal So, and the power amplitude of the sixth signal S6 is greater than that of the seventh signal S7.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an amplifier circuit.

Background Art

[0002] An LMBA (Load Modulated Balanced Amplifier) includes a control amplifier that amplifies one of the input signals that are distributed, and a balance amplifier that amplifies the other of the input signals that are distributed. It is known to use a 3dB branch line coupler for a synthesizer that synthesizes the output signal of the control amplifier and the output signal of the balance amplifier (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In an LMBA, from the viewpoint of the characteristics of the coupler, a 1 / 4 wavelength line is used as the 3dB branch line coupler. When a distributed constant type branch line coupler is used, the amplifier circuit becomes large. When a lumped constant type branch line coupler is used as the 3dB branch line coupler, the loss increases and the characteristics deteriorate.

[0005] The present disclosure has been made in view of the above problems, and an object thereof is to suppress deterioration of characteristics.

Means for Solving the Problems

[0006] One embodiment of the present disclosure includes a first distributor that distributes an input signal into a first signal and a second signal, a control amplifier that amplifies the first signal and outputs the amplified signal as a third signal, a second distributor that distributes the second signal into a fourth signal and a fifth signal having different phases at the center frequency of the operating band, a first auxiliary amplifier that amplifies the fourth signal and outputs the amplified signal as a sixth signal, a second auxiliary amplifier that amplifies the fifth signal and outputs the amplified signal as a seventh signal, a first node into which the sixth signal is input, a second node into which the seventh signal is input, a third node into which the third signal is input, and a fourth node that outputs an output signal. The sixth signal, the seventh signal, and the third signal are combined, and the combined signal is output as the output signal. The amplitude of the power of the signal at the center frequency input to the first node and distributed to the third node is smaller than the amplitude of the power of the signal distributed to the fourth node. The circuit further includes a lumped-constant branch-line coupler. The amplitude of the power of the sixth signal is greater than the amplitude of the power of the seventh signal.

Advantages of the Invention

[0007] According to the present disclosure, deterioration of characteristics can be suppressed.

Brief Description of the Drawings

[0008]

Figure 1

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Figure 14

Mode for Carrying Out the Invention

[0009] [Description of Embodiments of the Present Disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure includes a first distributor that distributes an input signal into a first signal and a second signal, a control amplifier that amplifies the first signal and outputs the amplified signal as a third signal, a second distributor that distributes the second signal into a fourth signal and a fifth signal having different phases at the center frequency of the operating band, a first auxiliary amplifier that amplifies the fourth signal and outputs the amplified signal as a sixth signal, a second auxiliary amplifier that amplifies the fifth signal and outputs the amplified signal as a seventh signal, a first node into which the sixth signal is input, a second node into which the seventh signal is input, a third node into which the third signal is input, and a fourth node that outputs an output signal. The sixth signal, the seventh signal, and the third signal are combined and the combined signal is output as the output signal. The amplitude of the power of the signal at the center frequency input to the first node and distributed to the third node is smaller than the amplitude of the power of the signal distributed to the fourth node. The circuit further includes a lumped - type branch - line coupler, and an amplifier circuit in which the amplitude of the power of the sixth signal is larger than the amplitude of the power of the seventh signal. Thereby, deterioration of characteristics can be suppressed. (2) In the above (1), the lumped - type branch - line coupler includes a first inductor having a first end connected to the first node and a second end connected to the second node, a second inductor having a first end connected to the first node and a second end connected to the third node, a third inductor having a first end connected to the third node and a second end connected to the fourth node, and a fourth inductor having a first end connected to the second node and a second end connected to the fourth node. When the center frequency is fo, the reference impedance is Zo, the first inductance of the first inductor and the third inductor is L1, and the second inductance of the second inductor and the fourth inductor is L2, L1 < Zo / 2πfo and L2 > L1 / √2 may be satisfied. Thereby, the losses of the first to fourth inductors can be suppressed. (3) In the above (2), the lumped-constant branch-line coupler includes a first capacitor shunt-connected to the first node, a second capacitor shunt-connected to the second node, a third capacitor shunt-connected to the third node, and a fourth capacitor shunt-connected to the fourth node. When the capacitances of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor are C, it may be C > 1 / (πfo×Zo). Thereby, it can function as a branch-line coupler. (4) In the above (1), the lumped-constant branch-line coupler includes a first inductor shunt-connected to a first intermediate node located on a first path connecting the first node and the second node, a second inductor shunt-connected to a second intermediate node located on a second path connecting the first node and the third node, a third inductor shunt-connected to a third intermediate node located on a third path connecting the third node and the fourth node, and a fourth inductor shunt-connected to a fourth intermediate node located on a fourth path connecting the second node and the fourth node. When the center frequency is fo, the reference impedance is Zo, the first inductance of the first inductor and the third inductor is L1, and the second inductance of the second inductor and the fourth inductor is L2, it may be L1 < Zo / 2πfo and L2 > L1 / √2. Thereby, the losses of the first to fourth inductors can be suppressed. (5) In the above (4), the lumped constant type branch line coupler includes a pair of first capacitors connected in series in the first path with the first intermediate node therebetween, a pair of second capacitors connected in series in the second path with the second intermediate node therebetween, a pair of third capacitors connected in series in the third path with the third intermediate node therebetween, and a pair of fourth capacitors connected in series in the fourth path with the fourth intermediate node therebetween. When the capacitance of each of the pair of first capacitors and the pair of third capacitors is C1, and the capacitance of each of the pair of second capacitors and the pair of fourth capacitors is C2, it may be that C1 > 1 / (2πfo×Zo) and C2 < √2 / (2πfo×Zo). Thereby, it can function as a branch line coupler. (6) In any one of the above (2) to (5), the reference impedance may be the characteristic impedance of a transmission line provided between the fourth node and the output terminal from which the output signal is output. Thereby, the reference impedance can be set. (7) In any one of the above (1) to (6), the difference between the first ratio of the amplitude of the power of the sixth signal to the amplitude of the power of the seventh signal and the second ratio of the amplitude of the power of the signal distributed to the fourth node to the amplitude of the power of the signal distributed to the third node of the signal having the center frequency input to the first node may be 1 dB or less. Thereby, the variation in impedance at the third node can be reduced. (8) In the above (7), the second ratio may be 2 dB or more. Thereby, the branch line coupler can be made smaller. (9) In any one of the above (1) to (8), the saturation power of the first auxiliary amplifier may be greater than the saturation power of the second auxiliary amplifier. Thereby, the first ratio can be made greater than 1. (10) In the above (9), the ratio of the saturation power of the first auxiliary amplifier to the saturation power of the second auxiliary amplifier may be 2 dB or more. Thereby, the first ratio can be made greater than 1. (11) In any of (1) to (8) above, the physical size of the first auxiliary amplifier may be larger than the physical size of the second auxiliary amplifier. Thereby, the first ratio can be made larger than 1. (12) In any of (1) to (11) above, the amplitude of the power of the fourth signal may be larger than the amplitude of the power of the fifth signal. Thereby, the first ratio can be made larger than 1. (13) In (12) above, the ratio of the amplitude of the power of the fourth signal to the amplitude of the power of the fifth signal may be 2 dB or more. Thereby, the first ratio can be made larger than 1. [Details of Embodiments of the Present Disclosure] A specific example of the amplifier circuit according to the embodiment of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, and is shown by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0010] [Example 1] FIG. 1 is a circuit diagram of the amplifier circuit according to Example 1. As shown in FIG. 1, in the amplifier circuit 100 of Example 1, a control amplifier 10 and a balance amplifier 11 are connected in parallel between an input terminal Tin and an output terminal Tout. A high-frequency signal is input as an input signal Si to the input terminal Tin. When the amplifier circuit 100 is used for a base station of mobile communication, the frequency of the high-frequency signal is, for example, 0.5 GHz or more and 10 GHz or less. A distributor 14 (first distributor) distributes the input signal Si input to the input terminal Tin into a signal S1 (first signal) and a signal S2 (second signal).

[0011] The signal S1 passes through the matching network 20 and is input to the control amplifier 10. The matching network 20 matches the impedance seen from the matching network 20 to the distributor 14 and the impedance seen from the control amplifier 10 to the matching network 20. A bias circuit 26 for supplying the input bias voltage VG1 to the control amplifier 10 is connected to the node in the line between the distributor 14 and the control amplifier 10. The bias circuit 26 supplies the input bias voltage VG1 to the control amplifier 10 and suppresses the leakage of the signal S1 to the power supply that supplies the input bias voltage VG1.

[0012] The control amplifier 10 amplifies the signal S1 and outputs the amplified signal as the signal S3 (third signal). The signal S3 amplified by the control amplifier 10 passes through the matching network 24 and is input to the terminal T23 of the synthesizer 18. The matching network 24 matches the impedance seen from the control amplifier 10 to the matching network 24 and the impedance seen from the synthesizer 18 to the matching network 24. A bias circuit 27 for supplying the output bias voltage VD to the control amplifier 10 is connected to the node in the line between the control amplifier 10 and the synthesizer 18. The bias circuit 27 supplies the output bias voltage VD to the control amplifier 10 and suppresses the leakage of the signal S3 to the power supply that supplies the output bias voltage VD.

[0013] The signal S2 distributed by the distributor 14 is input to the balanced amplifier 11. The balanced amplifier 11 includes a distributor 16, auxiliary amplifiers 12a and 12b, and a synthesizer 18. The distributor 16 (second distributor) distributes the signal S2 input to the terminal T11 into the signal S4 (fourth signal) and the signal S5 (fifth signal), and outputs them from the terminals T13 and T14, respectively. The phase of the signal S5 is delayed by, for example, about 90° from the phase of the signal S4. The amplitudes of the signals S5 and S4 are, for example, substantially the same. The 90° does not have to be exactly 90°, and may be, for example, greater than 85° and less than 95°, or greater than or equal to 88° and less than or equal to 92°. The same applies to the synthesizer 18.

[0014] As the distributor 16, a distributed constant type branch line coupler using a distributed constant line, a lumped constant type branch line coupler using an inductor and a capacitor, a distributor using a Wilkinson type distributor and a λ / 4 transmission line, a distributed coupling type coupler in which two transmission lines are electromagnetically coupled, or a tightly wound coil coupler in which two inductors are electromagnetically coupled may be used.

[0015] The signal S4 passes through the matching circuit 22a and is input to the auxiliary amplifier 12a. The matching circuit 22a matches the impedance seen from the matching circuit 22a to the distributor 16 and the impedance seen from the matching circuit 22a to the auxiliary amplifier 12a. A bias circuit 28a that supplies the input bias voltage VG2a to the auxiliary amplifier 12a is connected to a node in the line between the distributor 16 and the auxiliary amplifier 12a. The bias circuit 28a supplies the input bias voltage VG2a to the auxiliary amplifier 12a and suppresses the signal S4 from leaking to the power supply that supplies the input bias voltage VG2a. The auxiliary amplifier 12a (first auxiliary amplifier) amplifies the signal S4 and outputs the amplified signal as a signal S6 (sixth signal). The signal S6 amplified by the auxiliary amplifier 12a is input to the terminal T21 of the synthesizer 18.

[0016] The signal S5 passes through the matching circuit 22b and is input to the auxiliary amplifier 12b. The matching circuit 22b matches the impedance seen from the matching circuit 22b to the distributor 16 and the impedance seen from the matching circuit 22b to the auxiliary amplifier 12b. A bias circuit 28b that supplies the input bias voltage VG2b to the auxiliary amplifier 12b is connected to a node in the line between the distributor 16 and the auxiliary amplifier 12b. The bias circuit 28b supplies the input bias voltage VG2b to the auxiliary amplifier 12b and suppresses the signal S5 from leaking to the power supply that supplies the input bias voltage VG2b. The auxiliary amplifier 12b (second auxiliary amplifier) amplifies the signal S5 and outputs the amplified signal as a signal S7 (seventh signal). The signal S7 amplified by the auxiliary amplifier 12b is input to the terminal T22 of the synthesizer 18.

[0017] An impedance matching circuit for impedance matching may be connected between the auxiliary amplifiers 12a and 12b and the synthesizer 18. In the first embodiment, the signal of the control amplifier 10 adjusts the loads of the auxiliary amplifiers 12a and 12b. Therefore, an impedance matching circuit may not be provided between the auxiliary amplifiers 12a and 12b and the synthesizer 18. A harmonic processing circuit that reflects harmonic signals in the signals S6 and S7 may be connected between the auxiliary amplifiers 12a and 12b and the synthesizer 18. The harmonic signals are, for example, second harmonics or third harmonics when the operating frequency of the amplifier circuit is used as the fundamental wave. A bias circuit that supplies an output bias voltage to the auxiliary amplifiers 12a and 12b may be provided between the auxiliary amplifiers 12a and 12b and the synthesizer 18. In the first embodiment, the output bias voltages of the auxiliary amplifiers 12a and 12b are supplied from the bias circuit 27 through the synthesizer 18 to the auxiliary amplifiers 12a and 12b.

[0018] The synthesizer 18 is a lumped constant type branch line coupler. The terminals T21 to T24 are the terminals of the branch line coupler. The terminals T21 and T24 are located diagonally, and the terminals T22 and T23 are located diagonally. The signal S6 is input to the terminal T21. The signal S7 is input to the terminal T22. The signal S3 is input to the terminal T23. The output signal So is output from the terminal T24. The synthesizer 18 synthesizes the signals S3, S6, and S7 and outputs the synthesized signal as the output signal So.

[0019] The control amplifier 10, auxiliary amplifiers 12a and 12b are transistors such as FETs (Field Effect Transistors), for example. The source is grounded, a high-frequency signal is input to the gate, and a high-frequency signal is output from the drain. The FET is, for example, a GaN HEMT (Gallium Nitride High Electron Mobility Transistor) or an LDMOS (Laterally Diffused Metal Oxide Semiconductor). The control amplifier 10, auxiliary amplifiers 12a and 12b may each be provided with a multi-stage FET. When the control amplifier 10, auxiliary amplifiers 12a and 12b are FETs, the input bias voltages VG1, VG2a and VG2b are gate bias voltages, and the output bias voltage VD is a drain bias voltage.

[0020] Figure 2 is a circuit diagram showing Example 1 of the synthesizer in Embodiment 1. As shown in Figure 2, the synthesizer 18 is a lumped constant type branch line coupler. Nodes N1 (first node), N2 (second node), N3 (third node) and N4 (fourth node) are electrically connected to terminals T21, T22, T23 and T24, respectively. The first end of the inductor L11 (first inductor) is electrically connected to node N1, and the second end is electrically connected to node N2. The first end of the inductor L12 (second inductor) is electrically connected to node N1, and the second end is electrically connected to node N3. The first end of the inductor L13 (third inductor) is electrically connected to node N3, and the second end is electrically connected to node N4. The first end of the inductor L14 (fourth inductor) is electrically connected to node N2, and the second end is electrically connected to node N4. Capacitors C11 (first capacitor), C12 (second capacitor), C13 (third capacitor) and C14 (fourth capacitor) are shunt-connected to nodes N1, N2, N3 and N4, respectively. From capacitors C11 to C14, a plurality of capacitors may be shunt-connected to each other.

[0021] FIG. 3 is a circuit diagram showing Example 2 of the synthesizer in Embodiment 1. As shown in FIG. 3, in synthesizer 18, a pair of capacitors C21 (first capacitor) are connected in series to a path P1 (first path) connecting nodes N1 and N2. An inductor L21 (first inductor) is shunt-connected to a node NM1 (first intermediate node) between the capacitors C21 in path P1. A pair of capacitors C22 (second capacitor) are connected in series to a path P2 (second path) connecting nodes N1 and N3. An inductor L22 (second inductor) is shunt-connected to a node NM2 (second intermediate node) between the capacitors C22 in path P2. A pair of capacitors C23 (third capacitor) are connected in series to a path P3 (third path) connecting nodes N3 and N4. An inductor L23 (third inductor) is shunt-connected to a node NM3 (third intermediate node) between the capacitors C23 in path P3. A pair of capacitors C24 (fourth capacitor) are connected in series to a path P4 (fourth path) connecting nodes N2 and N4. An inductor L24 (fourth inductor) is shunt-connected to a node NM4 (fourth intermediate node) between the capacitors C24 in path P4.

[0022] Matching circuits 20, 22a, 22b, and 24 are passive circuits including inductors and capacitors, and are, for example, inductors connected in series, π-type circuits of CLC configuration, T-type circuits of LCL configuration, L-type circuits of LC configuration, or circuits combining these circuits.

[0023] Control amplifier 10 corresponds to the main amplifier of the Doherty amplifier circuit, and auxiliary amplifiers 12a and 12b correspond to the peak amplifiers of the Doherty amplifier circuit. Control amplifier 10 operates in class AB or class B, and auxiliary amplifiers 12a and 12b operate in class C. When the input power of input signal Si is small, control amplifier 10 mainly amplifies input signal Si. When the input power increases, in addition to control amplifier 10, auxiliary amplifiers 12a and 12b amplify the peak of input signal Si. Thereby, control amplifier 10 and auxiliary amplifiers 12a and 12b amplify input signal Si.

[0024] [Comparative Example 1] As Comparative Example 1, the Doherty amplifier circuit will be described. FIG. 4 is a circuit diagram of the amplifier circuit according to Comparative Example 1. As shown in FIG. 4, in the amplifier circuit 110 of Comparative Example 1, a main amplifier 10a and a peak amplifier 12 are provided in parallel between an input terminal Tin and an output terminal Tout. A distributor 14 distributes an input signal Si into signals S1 and S2. The main amplifier 10a amplifies the signal S1 that has passed through the matching circuit 20, and outputs the amplified signal as a signal S3 to a synthesizer 18a via a matching circuit 24. The peak amplifier 12 amplifies the signal S2 that has passed through the matching circuit 22, and outputs the amplified signal as a signal S9 to the synthesizer 18a via a matching circuit 24a.

[0025] The synthesizer 18a includes λ / 4 transmission lines TL51 and TL52 as impedance converters. The impedance seen from the matching circuit 24 to the synthesizer 18a and the load impedance of the peak amplifier 12 are modulated using the λ / 4 transmission lines TL51 and TL52.

[0026] In Comparative Example 1, when the frequency changes, since the electrical length of the λ / 4 transmission line deviates from λ / 4, it is difficult to widen the operating bandwidth. In one example, the specific bandwidth of the synthesizer using the λ / 4 transmission lines TL51 and TL52 is about 8%. In the LMBA as in Example 1, since a branch-line coupler is used to modulate the load impedance of the auxiliary amplifiers 12a and 12b, it becomes possible to widen the operating bandwidth. The specific bandwidth of the branch-line coupler is up to 120% at maximum in, for example, a commercially available hybrid coupler. Thus, in the LMBA, the synthesizer 18 can be widened in bandwidth.

[0027] [Comparative Example 2] As Comparative Example 2, an LMBA in which the synthesis ratio of the synthesizer 18 is 1:1 will be described. FIGS. 5 and 6 are circuit diagrams showing a part of the amplifier circuit 112 in Comparative Example 2. In FIGS. 5 and 6, the circuits after a control amplifier 10 and a balance amplifier 11 are illustrated. In Comparative Example 2, in FIG. 6, the power synthesis ratio at which the synthesizer 18 synthesizes the signals S6 and S7 is 1:1.

[0028] Using FIG. 5, when the power of the input signal Si is small and the auxiliary amplifiers 12a and 12b are not operating, the signal S3 input from terminal T23 to the synthesizer 18 is split into signals S3a and S3b at terminals T21 and T22. The ratio of the power amplitudes of signals S3a and S3b is 1:1. The phase of signal S3b at terminal T22 lags behind the phase of signal S3a at terminal T21 by 90°. Signals S3a and S3b are reflected at terminals T21 and T22 respectively. The reflected signals S3a and S3b are combined at terminal T24. The phase of the signal S3a reflected at terminal T21 lags behind the phase of the signal S3b reflected at terminal T22 by 90°. As a result, at terminal T24, the phases of signals S3a and S3b are aligned and signal S3 is combined. The combined signal S3 is output as the output signal So to the output terminal Tout.

[0029] At this time, the reflection coefficients (i.e., the absolute values of the impedances Z3a and Z3b) seen from the auxiliary amplifiers 12a and 12b to the synthesizer 18 are approximately 1. The impedances Z3a and Z3b that are the loads of the auxiliary amplifiers 12a and 12b are substantially high. On the other hand, the impedance Z1 seen from the matching circuit 24 to terminal T23 is the reference impedance (e.g., 50 Ω) which is the input impedance of terminal T23.

[0030] Next, using FIG. 6, when the power of the input signal Si is large and the auxiliary amplifiers 12a and 12b are operating, the phase of signal S7 lags behind the phase of signal S6 by 90°. The phase of signal S3b at terminal T22 lags behind the phase of signal S3a at terminal T21 by 90°. Thus, by appropriately adjusting the phase difference between signals S1 and S2, the phases of signal S6 and S3a at terminal T21 are optimized (e.g., the phases of signals S6 and S3a are aligned), and the phases of signal S7 and S3b at terminal T22 are optimized (e.g., the phases of signals S7 and S3b are aligned). The signal S6 + S3a combined at terminal T21 and the signal S7 + S3b combined at terminal T22 are combined at terminal T24. The combined signal S3 + S6 + S7 is output as the output signal So to the output terminal Tout.

[0031] At this time, the signals incident on terminals T21 and T22 from auxiliary amplifiers 12a and 12b are substantially S6+S3a and S7+S3b respectively, and the signals reflected at terminals T21 and T22 are substantially S3a and S3b respectively. Therefore, the reflection coefficients seen from terminals T21 and T22 of auxiliary amplifiers 12a and 12b (i.e., the absolute values of impedances Z3a and Z3b) are less than 1, and become smaller as the power amplitudes of signals S6 and S7 are larger. The impedances Z3a and Z3b that are the loads of auxiliary amplifiers 12a and 12b become substantially lower as the power amplitudes of signals S6 and S7 are larger. Thus, synthesizer 18 modulates the impedances Z3a and Z3b that are the loads seen from auxiliary amplifiers 12a and 12b to synthesizer 18 depending on the amplitudes of signals S6 and S7. On the other hand, the impedance Z1 seen from terminal T23 of matching circuit 24 is a reference impedance (e.g., 50Ω) regardless of the magnitudes of the amplitudes of signals S6 and S7.

[0032] When the power of output signal So is the maximum value within the operating range of the amplifier circuit, the output power of output signal So is defined as saturation power Psat. At saturation power Psat, in Comparative Example 1, the output powers of main amplifier 10a and peak amplifier 12, and in Comparative Example 2, the output powers of control amplifier 10, auxiliary amplifiers 12a and 12b are saturated. Here, the output power being saturated includes a state that is 1 dB or less or 2 dB or less lower than the complete saturation state. When the power of output signal So is the minimum value within the operating range of the amplifier circuit, it is defined as back-off power Pbo. At back-off power Pbo, in Comparative Example 1, main amplifier 10a has started to saturate, and in Comparative Example 2, the output power of control amplifier 10 is saturated.

[0033] FIG. 7 shows an example of using a distributed-constant branch-line coupler as a synthesizer. As shown in FIG. 7, transmission lines TL21, TL22, TL23, and TL24 are respectively connected between node N1 and N2, between node N1 and N3, between node N3 and N4, and between node N2 and N4. Transmission lines TL21 to TL24 are λ / 4 transmission lines. The electrical length of the λ / 4 transmission line is, for example, approximately λ / 4. Here, λ is the wavelength of the center frequency fo of the operating band of the amplifier circuit 100. Between end T21 and node N1, between end T22 and node N2, between end T23 and node N3, and between end T24 and node N4 are connected by transmission lines. The signals S6 input to end T21, the signal S7 input to end T22, and the signal S3 input to end T23 are combined, and the combined signal is output from end T24 as output signal So.

[0034] The distributed-constant branch-line coupler increases in size because it uses λ / 4 lines. Therefore, as the synthesizer 18, a lumped-constant branch-line coupler as shown in FIGS. 2 and 3 is used. When the power combining ratio for the synthesizer 18 to combine signals S6 and S7 is 1:1, the inductances of inductors L11 to L14 increase. Inductors L11 to L14 with large inductances have large losses. For this reason, the characteristics of the LMBA deteriorate.

[0035] [Comparative Example 3] As Comparative Example 3, an LMBA in which the combining ratio of the synthesizer 18 is not 1:1 will be described. Instead of the combining ratio of the synthesizer 18, the distribution ratio of the power of the signal S6 input to end T21 being distributed to ends T24 and T23 is used as an index. Let the signal output to end T23 be signal S6a, and the signal output to end T24 be signal S6b. Let the amplitudes of the powers of signals S6, S6a, and S6b be A6, A6a, and A6b, respectively. The ratio of amplitude A6a to amplitude A6b is A6b:A6a, and in dB representation, it is A6a - A6b [dB]. Let the characteristic impedance of transmission line TL21 and transmission line TL23 in FIG. 7 be Zc1, and the characteristic impedance of transmission line TL22 and transmission line TL24 be Zc2.

[0036] Table 1 shows the characteristic impedances Zc1, Zc2, and √2×Zc2 / Zc1 for realizing the ratio A6a - A6b [dB]. [Table 1]

[0037] In Table 1, the reference impedance Zo is set to 50 Ω. The reference impedance Zo corresponds to the impedance seen from the outside of terminals T21, T22, T23, and T24, and in particular corresponds to the impedance seen from the outside of T24.

[0038] The method for determining the values of capacitors C11 to C14 and inductors L11 to L14 when using the lumped - constant branch - line coupler of Fig. 2 instead of the distributed - constant branch - line coupler of Fig. 7 will be described. Let the capacitances of capacitors C11 to C14 be C1, the inductances of inductors L11 and L13 be L1 (the first inductance), and the inductances of inductors L12 and L14 be L2 (the second inductance). Let the center frequency of the operating band be fo. At this time, the capacitance C1, and the inductances L1 and L2 are determined by the following equations. C1 = 1 / (2πfo×Zc1)+1 / (2πfo×Zc2) (Equation 1) L1 = Zc1 / (2πfo) (Equation 2) L2 = Zc2 / (2πfo) (Equation 3)

[0039] When using the lumped-element branch-line coupler of Fig. 3 instead of the distributed-constant branch-line coupler of Fig. 7, the method for determining the values of capacitors C21 to C24 and inductors L21 to L24 will be described. Let the capacitance of capacitors C21 and C23 be C1 (the first capacitance), the capacitance of capacitors C22 and C24 be C2 (the second capacitance), the inductance of inductors L11 and L13 be L1 (the first inductance), and the inductance of inductors L12 and L14 be L2 (the second inductance). Let the center frequency of the operating band be fo. At this time, the capacitance C1, inductances L1 and L2 are determined by the following equations. C1 = 1 / (2πfo×Zc1) (Equation 4) C2 = 1 / (2πfo×Zc2) (Equation 5) L1 = Zc1 / (2πfo) (Equation 6) L2 = Zc2 / (2πfo) (Equation 7)

[0040] As shown in Table 1, when the amplitudes A6a and A6b are equal, that is, when signal S6 is equally divided into S6a and S6b, the characteristic impedance Zc1 is 50Ω, the reference impedance Zo, and the characteristic impedance Zc2 is 35.35Ω, which is Zo / √2.

[0041] When making A6a - A6b smaller than when A6a - A6b = 0dB, the characteristic impedance Zc1 is made smaller than the reference impedance Zo, and the characteristic impedance Zc2 is made larger than Zc1 / √2. In this case, both the characteristic impedances Zc1 and Zc2 become smaller than Zc1 and Zc2 when A6a - A6b = 0dB, respectively. Therefore, the inductances L1 and L2 are made smaller, and the losses in inductors L11 to L14 and L21 to L24 can be suppressed.

[0042] When making A6a - A6b larger than when A6a - A6b = 0 dB, the characteristic impedance Zc1 is made larger than the reference impedance Zo, and the characteristic impedance Zc2 is made smaller than Zc1 / √2. In this case, both the characteristic impedances Zc1 and Zc2 become larger than Zc1 and Zc2 when A6a - A6b = 0 dB, respectively. Thus, the inductances L1 and L2 increase, and the losses in inductors L11 to L14 and L21 to L24 increase.

[0043] From the viewpoint of improving the high - frequency characteristics of the synthesizer 18, the characteristic impedance Zc1 is made smaller than the reference impedance Zo, and the characteristic impedance Zc2 is made smaller than Zc1 / √2. The characteristic impedance Zc1 can be set to 0.99 times or less, 0.90 times or less, 0.8 times or less, or 0.7 times or less of the reference impedance Zo. The characteristic impedance Zc2 can be set to 1.01 times or more, 1.1 times or more, 1.15 times or more, or 1.2 times or more of Zc1 / √2. From the viewpoint of not making A6a - A6b too small, the characteristic impedance Zc1 can be set to 0.1 times or more of the reference impedance Zo, and the characteristic impedance Zc2 can be set to 10 times or less of Zc1 / √2o.

[0044] As described above, the inductances L1 and L2 become smaller than the inductances when A6a - A6b = 0 dB, and the capacitance C1 becomes larger than the capacitance when A6a - A6b = 0 dB.

[0045] FIG. 8 is a schematic diagram for explaining the operation of the synthesizer in Comparative Example 3 and Example 1. The impedance seen from the outside of terminal T24 is the reference impedance Zo (for example, 50 Ω), which corresponds to the characteristic impedance of the transmission line connecting between node N4 and terminal T24. The inductance L1 of inductors L11 and L13, the inductance L2 of inductors L12 and L14, and the capacitance C1 of capacitors C11 to C14 are set to values calculated from the characteristic impedances Zc1 and Zc2 in Table 1.

[0046] The amplitude of the signal S6 input to the terminal T21 is A6, and the phase is 0°. The amplitude of the signal S7 input to the terminal T22 is A7, and the phase is -90°. The signals S6 and S7 are represented as (A6, 0°) and (A7, -90°), respectively. The signals output from the signal S6 distributed to the terminals T23 and T24 are the signals S6a and S6b, respectively. Let the ratio A6b:A6a of the amplitudes of the signals S6b and S6a in the W display be N:1 (N>1). At this time, the signals S6a and S6b are ((1 / (1 + N))×A6, -90°) and ((N / (1 + N))×A6, -180°), respectively. The signals S7a and S7b are ((N / (1 + N))×A7, -270°) and ((1 / (1 + N))×A7, -180°), respectively.

[0047] At the terminal T24, the signals S6b and S7b are in the same phase, and the signal S6b with an amplitude of (N / (1 + N))×A6 and the signal S7b with an amplitude of (1 / (1 + N))×A7 are combined.

[0048] At the terminal T23, the signals S6a and S7a are in opposite phases. When N = 1, the amplitudes of the signals S6a and S7a are (1 / 2)×A6 and (1 / 2)×A7, respectively. Since the amplitudes A6 and A7 are almost the same, the signals S6a and S7a are compensated. As a result, no signal is output from the terminal T23. Thereby, the impedance Z1 seen from the terminal T23 of the matching circuit 24 is constant regardless of the amplitudes of the signals S6 and S7, and is the reference impedance Zo.

[0049] When N > 1, Comparative Example 3 will be described. FIG. 9 is a circuit diagram showing the balance amplifier in Comparative Example 3. As shown in FIG. 9, in Comparative Example 3, as described in FIG. 6, in the synthesizer 18, the amplitude ratio A6b:A6a of the signals S6b and S6a is N:1 (N > 1). The distributor 16 is a branch line coupler. The signal S2 is input to the terminal T11, and the signals S4 and S5 are output from the terminals T13 and T14. The terminal T12 is grounded via a reference resistor R1 (for example, 50 Ω). The amplitude ratio of the signal S5 and the signal S4 in the distributor 16 is 1:1. Therefore, the signal S4 output to the terminal T13 is (A4, 0°). The signal S5 output from the terminal T14 is (A4, -90°). The amplitudes of the signals S4 and S5 are substantially the same and are A4. The physical sizes of the auxiliary amplifiers 12a and 12b are the same as each other, and the saturation powers are also the same as each other. The input bias voltages supplied to the auxiliary amplifiers 12a and 12b are the same as each other, and the output bias voltages are also the same as each other. As a result, the amplitudes of the signals S6 and S7 are substantially the same and become A6. Therefore, the signal S6 input to the terminal T21 is (A6, 0°), and the signal S7 input to the terminal T22 is (A6, -90°).

[0050] The signal S6a output from the terminal T23 is ((1 / (1 + N))×A6, -90°), and the signal S7a is ((N / (1 + N))×A6, -270°). Since the signals S6a and S7a are in opposite phases, the signal S6a + S7a becomes ((1 - N) / (1 + N)×A6, -90°). When N > 1, the signals S6a and S7a are not compensated. Therefore, when the magnitudes of the signals S6 and S7 change, the impedance Z1 that becomes the load of the control amplifier 10 changes. For example, when the output power Pout is the back-off power Pbo, the impedance Z1 is the reference impedance Zo. When the output power Pout is the saturation power Psat, due to the influence of the signal S6a + S7a output from the terminal T23 of the synthesizer 18, the impedance Z1 changes from the reference impedance Zo.

[0051] [Example 1 of Example 1] FIG. 10 is a circuit diagram showing a balance amplifier in Example 1 of Example 1. As shown in FIG. 10, the signal distribution ratio of the distributor 16 is 1:1. The physical size of the auxiliary amplifier 12a is about N times the physical size of the auxiliary amplifier 12b. For example, when the auxiliary amplifiers 12a and 12b are FETs, the gate width of the auxiliary amplifier 12a is about N times the gate width of the auxiliary amplifier 12b. The saturation power of the auxiliary amplifier 12a is about N times the saturation power of the auxiliary amplifier 12b.

[0052] The amplitudes of the signals S4 and S5 distributed by the distributor 16 are substantially the same and are A4. When both the auxiliary amplifiers 12a and 12b are used at saturation power, the amplitude A6 of the signal S6 is N times the amplitude A7 of the signal S7. Therefore, the signal S6 input to the terminal T21 is (N×A6, 0°), and the signal S7 input to the terminal T22 is (A6, -90°).

[0053] The signal S6a output from the terminal T23 is ((1 / (1+N))×N×A6, -90°), and the signal S7a is ((N / (1+N))×A6, -270°). The amplitudes of the signals S6a and S7a are both (N / (1+N)×A6), and since the signals S6a and S7a are in opposite phases, the amplitude of the signal S6a+S7a is almost 0. Thus, when the output power Pout is at the back-off power Pbo and at the saturation power Psat, the impedance Z1 is the reference impedance Zo.

[0054] [Example 2 of Example 1] FIG. 11 is a circuit diagram showing a balance amplifier in Example 2 of Example 1. As shown in FIG. 11, the signal distribution ratio of the distributor 16 is 1:N. The physical sizes of the auxiliary amplifiers 12a and 12b are substantially the same as each other. The saturation powers of the auxiliary amplifiers 12a and 12b are substantially the same as each other. The method of setting the distribution ratio of the distributor 16 to 1:N is, when the distributor 16 is a branch line coupler, as shown in Table 1, by setting the characteristic impedances Zc1 and Zc2. When other couplers are used for the distributor 16, the distribution ratio can be changed using known methods.

[0055] The amplitude of the signal S4 distributed by the distributor 16 is approximately N times the amplitude of the signal S5. Therefore, the signal S4 is (N×A4, 0°), and the signal S5 is (A4, -90°). If the auxiliary amplifiers 12a and 12b do not reach the saturation power and have approximately the same power gain, the amplitude A7 of the signal S7 is N times the amplitude of the signal S6. Therefore, the signal S6 is (N×A6, 0°), and the signal S7 is (A6, -90°).

[0056] Therefore, similar to Example 1, the signal S6a output from the terminal T23 is ((1 / (1 + N))×N×A6, -90°), and the signal S7a is ((N / (1 + N))×A6, -270°). The amplitude of the signal S6a + S7a becomes almost 0. For this reason, even if the magnitudes of the signals S6 and S7 change, the change in the impedance Z1 is suppressed.

[0057] [Implementation Example 1 of Synthesizer and Amplifier] FIG. 12 is a plan view showing Implementation Example 1 of the synthesizer and amplifier in Example 1. As shown in FIG. 12, semiconductor chips 31a, 31b and a passive element chip 40 are mounted on a substrate 30. The upper surface of the substrate 30 is, for example, a conductor layer to which a reference potential such as a ground potential is supplied. The semiconductor chips 31a and 31b each include a transistor 37 corresponding to the auxiliary amplifiers 12a and 12b, a substrate 32, and pads 33 and 34 provided on the substrate 32. The pad 33 is an input pad to which a high-frequency signal is input and is, for example, a gate pad. The pad 34 is an output pad from which a high-frequency signal is output and is, for example, a drain pad. When the transistor 37 is a GaN HEMT, the substrate 32 is, for example, a silicon carbide substrate, a sapphire substrate, or a gallium nitride substrate. The pads 33 and 34 are, for example, a gold layer, a copper layer, or an aluminum layer.

[0058] The passive element chip 40 is an IPD (Integrated Passive Device) formed using, for example, MMIC (Monolithic Microwave Integrated Circuit) technology. On the substrate 41 of the passive element chip 40, lines 42a to 42d, spiral inductors 43a to 43d, and MIM (Metal Insulator Metal) capacitors 44a to 44d are provided. The lines 42a to 42d are formed by a metal layer provided on the passive element chip 40. The MIM capacitors 44a to 44d are formed by a stack of a metal layer, a dielectric layer, and a metal layer provided on the passive element chip 40. The substrate 41 is, for example, a silicon substrate or a gallium arsenide substrate. The metal layer on the substrate 41 is, for example, a gold layer, a copper layer, or an aluminum layer. The dielectric layer of the MIM capacitors 44a to 44d is, for example, a silicon nitride layer or a silicon oxide layer.

[0059] The lines 42a to 42d form microstrip lines with the substrate 30. The microstrip lines formed by the lines 42a to 42d respectively correspond to the transmission lines between the ends T21 to T24 and the nodes N1 to N4 in FIG. 2. The characteristic impedance of the transmission lines formed by the lines 42a to 42d is the reference impedance. In particular, the line 42d is connected to the load via the output terminal Tout, and the characteristic impedance of the transmission line formed by the line 42d becomes the reference impedance. The spiral inductors 43a to 43d respectively correspond to the inductors L11 to L14 in FIG. 2. The MIM capacitors 44a to 44d respectively correspond to the capacitors C11 to C14 in FIG. 2. The pads 34 of the semiconductor chips 31a and 31b and the lines 42a and 42b are electrically connected by bonding wires 45.

[0060] As in Example 1 of Example 1 in FIG. 10, the size of the transistors (e.g., the gate width of the FET) of the semiconductor chip 31a is larger than that of the semiconductor chip 31b. The inductances of the spiral inductors 43a to 43d and the capacitances of the MIM capacitors 44a to 44d are values calculated from the characteristic impedances Zc1 and Zc2 in Table 1.

[0061] [Example 2 of Synthesizer and Amplifier Implementation] FIG. 13 is a plan view showing Example 2 of the synthesizer and amplifier implementation in Example 1. Referring to FIG. 13, a conductor layer to which a reference potential such as a ground potential is supplied is provided on the lower surface of the substrate 35. The substrate 35 is a dielectric substrate. On the substrate 35, a ground pattern 36, lines 42a to 42d, and patterns 46a to 46d are provided using a metal layer. The semiconductor chips 31a and 31b are mounted on the ground pattern 36. Chip capacitors 48a to 48d are respectively provided between the lines 42a to 42d and the patterns 46a to 46d. The pads 34 of the semiconductor chips 31a and 31b and the lines 42a and 42b are electrically connected by bonding wires 45. Between the lines 42a and 42b, between the lines 42a and 42c, between the lines 42c and 42d, and between the lines 42b and 42d, they are electrically connected by bonding wires 49a to 49d respectively. The patterns 46a to 46d are electrically connected to the conductor layer to which the reference potential of the lower surface of the substrate 35 is supplied via vias 47. The substrate 35 is, for example, a glass epoxy substrate or a ceramic substrate. The metal layer on the substrate 35 is, for example, a gold layer, a copper layer, or an aluminum layer. Other configurations are the same as those of Example 1 of the synthesizer and amplifier implementation in FIG. 12.

[0062] Lines 42a to 42d form microstrip lines. The microstrip lines formed by lines 42a to 42d respectively correspond to the transmission lines between terminals T21 to T24 and nodes N1 to N4 in FIG. 2. The characteristic impedance of the transmission lines formed by lines 42a to 42d is the reference impedance. Bonding wires 49a to 49d respectively correspond to inductors L11 to L14 in FIG. 2.

[0063] Chip capacitors 48a to 48d respectively correspond to capacitors C11 to C14 in FIG. 2. The inductance of bonding wires 49a to 49d and the capacitance of chip capacitors 48a to 48d are values calculated from characteristic impedances Zc1 and Zc2 in Table 1.

[0064] [Example of implementation of synthesizer and amplifier 3] FIG. 14 is a plan view showing Example of implementation of synthesizer and amplifier 3 in Example 1. As shown in FIG. 14, chip inductors 47a to 47d are respectively provided instead of bonding wires 49a to 49d. Other configurations are the same as those of the synthesizer and amplifier in Example 2 of FIG. 13, and the description thereof is omitted.

[0065] According to Example 1, when using the lumped - constant type branch - line coupler of FIG. 2 as the synthesizer 18, from Table 1 Zc1 < Zo (Equation 8) and Zc2 > Zc1 / √2 (Equation 9) Then, the inductance of inductors L11 to L14 can be reduced, and the loss of inductors L11 to L14 can be reduced. From Equations 2, 3, 8, and 9, L1 < Zo / 2πfo (Equation 10) And L2 > L1 / √2 (Equation 11) By setting it like this, Equations 8 and 9 can be satisfied.

[0066] As a result, the inductances of inductors L11 to L14 can be reduced. Therefore, the insertion loss of inductors L11 to L14 can be suppressed, and the degradation of characteristics can be suppressed.

[0067] From the perspective of reducing inductance L1, L1 < 0.9×Zo / 2πfo can be achieved, L1 < 0.8×Zo / 2πfo can be achieved, and L1 < 0.7×Zo / 2πfo can be achieved. From the perspective of functioning as a branch-line coupler, L2 > 1.1×L1 / √2 can be achieved, L2 > 1.15×L1 / √2 can be achieved, and L2 > 1.2×L1 / √2 can be achieved. From the perspective of reducing inductance L1, L2 < Zo / 2πfo.

[0068] As shown in Table 1, Zc2 < Zc1 (Equation 12). Therefore, from Equations 1, 8, and 12, C > 1 / (2πfo×Zo) + 1 / (2πfo×Zo) = 1 / (πfo×Zo) (Equation 13) is obtained. As a result, the synthesizer 18 can function as a branch-line coupler.

[0069] From the perspective of functioning as a branch-line coupler, C > 1.1 / (πfo×Zo) can be achieved, C > 1.2 / (πfo×Zo) can be achieved, and C > 1.3 / (πfo×Zo) can be achieved. Also, C < 5 / (πfo×Zo) can be achieved.

[0070] When using the lumped-constant type branch-line coupler of FIG. 3 as the synthesizer 18, the inductance values of inductors L21 to L24 that satisfy Equations 8 and 9 are the same as Equations 10 and 11 according to Equations 6 and 7. As a result, the insertion loss of inductors L21 to L24 can be suppressed, and the degradation of characteristics can be suppressed.

[0071] From the perspective of reducing the inductance L1, L1 < 0.9×Zo / 2πfo can be achieved, L1 < 0.8×Zo / 2πfo can be achieved, and L1 < 0.7×Zo / 2πfo can be achieved. From the perspective of functioning as a branch-line coupler, L2 > 1.1×L1 / √2 can be achieved, L2 > 1.15×L1 / √2 can be achieved, and L2 > 1.2×L1 / √2 can be achieved. From the perspective of reducing the inductance L1, L2 < Zo / 2πfo.

[0072] The capacitance values of capacitors C21 to C24 are from Equation 4 and Equation 8 C1 > 1 / (2πfo×Zo) (Equation 14) and from Equation 5, Equation 9, and Equation 12 C2 > 1 / (2πfo×Zo) (Equation 15) C2 < √2 / (2πfo×Zo) (Equation 16) Thus, the synthesizer 18 can function as a branch-line coupler.

[0073] From the perspective of functioning as a branch-line coupler, C1 > 1.1 / (2πfo×Zo) can be achieved, C1 > 1.2 / (2πfo×Zo) can be achieved, and C1 > 1.3 / (2πfo×Zo) can be achieved. Also, C1 < 5 / (2πfo×Zo) can be achieved. C2 > 1.05 / (2πfo×Zo) can be achieved, C2 > 1.1 / (2πfo×Zo) can be achieved. C2 < 0.9×√2 / (2πfo×Zo) can be achieved, C2 < 0.85×√2 / (2πfo×Zo) can be achieved, and C2 < 0.8×√2 / (2πfo×Zo) can be achieved.

[0074] Thus, when the synthesizer 18 is a lumped constant type branch line coupler, the amplitude of the power of the signal S6 input to the node N1 is smaller than the amplitude of the power of the signal distributed to the node N3. Thereby, the inductances of the inductors L11 to L14 and L21 to L24 can be reduced. Therefore, the insertion loss of the inductors L11 to L14 and L21 to L24 can be suppressed, and the deterioration of the characteristics can be suppressed. However, as in Comparative Example 3, the impedance Z1 seen from the control amplifier 10 to the synthesizer 18 changes due to the changes in the signals S6 and S7. Therefore, the amplitude of the power of the signal S6 is made larger than the amplitude of the power of the signal S7. Thereby, as in Example 1, Example 1 and Example 2, the signal S6a + S7a output from the terminal T23 can be reduced. Therefore, the variation of the impedance Z1 due to the changes in the signals S6 and S7 can be suppressed, and the deterioration of the characteristics can be suppressed.

[0075] The first ratio of the amplitude A6 of the power of the signal S6 to the amplitude A7 of the power of the signal S7 is A6 / A7. The second ratio of the amplitude A6b of the power of the signal S6b distributed to the terminal T24 to the amplitude A6a of the power of the signal S6a distributed to the terminal T23 when the signal S6 having the center frequency fo input to the terminal T21 is A6b / A6a. When the first ratio A6 / A7 and the second ratio A6b / A6a are expressed in dB, as in Example 1, Example 1 and Example 2, when both the first ratio and the second ratio are N, the difference between the first ratio A6 / A7 and the second ratio A6b / A6a is 0 dB. At this time, the signal S6a + S7a output from the terminal T23 becomes almost 0. From the viewpoint of suppressing the change in the impedance Z1 due to the magnitudes of the signals S6 and S7, the difference between the first ratio A6 / A7 and the second ratio A6b / A6a can be 1 dB or less, can be 0.5 dB or less, and can be 0.3 dB or less. Note that the difference between A6 / A7 and A6b / A6a corresponds to |A6 / A7 - A6b / A6a|.

[0076] From the perspective of miniaturizing the synthesizer 18, the second ratio A6b / A6a can be 2 dB or more, can be 3 dB or more, and can be 4 dB or more. If the second ratio A6b / A6a is too large, the signal output from the terminal T24 will deteriorate. From this perspective, the second ratio A6b / A6a can be 10 dB or less.

[0077] As in Example 1 of Example 1, from the perspective of increasing the first ratio A6 / A7, the saturation power of the auxiliary amplifier 12a is greater than the saturation power of the auxiliary amplifier 12b. The saturation power of the auxiliary amplifier 12a with respect to the saturation power of the auxiliary amplifier 12b can be 1 dB or more, can be 2 dB or more, and can be 3 dB or more. From the perspective of not increasing the first ratio A6 / A7 too much, the saturation power of the auxiliary amplifier 12a with respect to the saturation power of the auxiliary amplifier 12b can be 10 dB or less.

[0078] To make the saturation power of the auxiliary amplifier 12a greater than the saturation power of the auxiliary amplifier 12b, the physical size of the auxiliary amplifier 12a is larger than the physical size of the auxiliary amplifier 12b. For example, when the auxiliary amplifiers 12a and 12b are FETs, the gate width of the auxiliary amplifier 12a can be made larger than the gate width of the auxiliary amplifier 12b, and can be 1.3 times or more, 1.6 times or more, or 2 times or more the gate width of the auxiliary amplifier 12b. Also, the gate width of the auxiliary amplifier 12a can be 10 times or less the gate width of the auxiliary amplifier 12b.

[0079] As in Example 2 of Example 1, from the perspective of increasing the first ratio A6 / A7, the amplitude A4 of the power of the signal S4 is greater than the amplitude A5 of the power of the signal S5. The ratio of the amplitude A4 of the power of the signal S4 to the amplitude A5 of the power of the signal S5 can be 1 dB or more, can be 2 dB or more, and can be 3 dB or more. From the perspective of not increasing the first ratio A6 / A7 too much, the ratio of the amplitude A5 to the amplitude A4 can be 10 dB or less.

[0080] As a method of making the first ratio A6 / A7 greater than 1, in addition to Example 1 and Example 2 of Embodiment 1, for example, there is a method of combining Example 1 and Example 2. That is, the saturation power of the auxiliary amplifier 12a may be made greater than the saturation power of the auxiliary amplifier 12b, and the amplitude A4 of the power of the signal S4 may be made greater than the amplitude A5 of the power of the signal S5. Further, the first ratio A6 / A7 may be made greater than 1 by appropriately setting the bias voltages of the auxiliary amplifiers 12a and 12b.

[0081] The reference impedance is the characteristic impedance of the transmission line formed by the line 42d in FIGS. 12 to 14 (the transmission line provided between the node N4 and the output terminal Tout). This is because a load having the reference impedance is connected to the output terminal Tout.

[0082] It should be considered that all aspects of the embodiments disclosed this time are illustrative and not restrictive. The scope of the present disclosure is shown not by the above meaning but by the claims, and it is intended that all modifications within the meaning and scope equivalent to the claims are included.

Explanation of Reference Numerals

[0083] 10 Control Amplifier 10a Main Amplifier 11 Balance Amplifier 12 Peak Amplifier 12a (First Auxiliary Amplifier), 12b (Second Auxiliary Amplifier) Auxiliary Amplifier 14 (First Divider), 16 (Second Divider) Divider 18, 18a Combiner 20, 22, 22a, 22b, 24, 24a Matching Circuit 26, 27, 28a, 28b Bias Circuit 30, 32, 35, 41 Substrate 31a, 31b Semiconductor Chip 33, 34 Pad 36 Ground Pattern 37 Transistor 40 Passive Element Chip Lines 42a, 42b, 42c, 42d Spiral inductors 43a, 43b, 43c, 43d MIM capacitors 44a, 44b, 44c, 44d Bonding wires 45, 49a, 49b, 49c, 49d Patterns 46a, 46b, 46c, 46d Via 47 Chip inductors 47a, 47b, 47c, 47d Chip capacitors 48a, 48b, 48c, 48d Amplifier circuits 100, 110, 112 Capacitors C11 (first capacitor), C12 (second capacitor), C13 (third capacitor), C14 (fourth capacitor), C21 (first capacitor), C22 (second capacitor), C23 (third capacitor), C24 (fourth capacitor) Inductors L11 (first inductor), L12 (second inductor), L13 (third inductor), L14 (fourth inductor), L21 (first inductor), L22 (second inductor), L23 (third inductor), L24 (fourth inductor) Nodes N1 (first node), N2 (second node), N3 (third node), N4 (fourth node), NM1 (first intermediate node), NM2 (second intermediate node), NM3 (third intermediate node), NM4 (fourth intermediate node) Paths P1 (first path), P2 (second path), P3 (third path), P4 (fourth path) Signals S1 (first signal), S2 (second signal), S3 (third signal), S4 (fourth signal), S5 (fifth signal), S6 (sixth signal), S7 (seventh signal) Input signal Si Output signal So

Claims

1. A first distributor that distributes an input signal into a first signal and a second signal; A control amplifier that amplifies the first signal and outputs the amplified signal as a third signal; A second distributor that distributes the second signal into a fourth signal and a fifth signal having different phases at the center frequency of the operating band; A first auxiliary amplifier that amplifies the fourth signal and outputs the amplified signal as a sixth signal; A second auxiliary amplifier that amplifies the fifth signal and outputs the amplified signal as a seventh signal; A first node into which the sixth signal is input, a second node into which the seventh signal is input, a third node into which the third signal is input, and a fourth node that outputs an output signal, wherein the sixth signal, the seventh signal, and the third signal are combined, and the combined signal is output as the output signal, and the amplitude of the power of the signal at the center frequency input to the first node and distributed to the third node is smaller than the amplitude of the power of the signal distributed to the fourth node, a lumped - type branch - line coupler; Comprising; An amplifier circuit in which the amplitude of the power of the sixth signal is larger than the amplitude of the power of the seventh signal.

2. The lumped - type branch - line coupler is: A first inductor having a first end connected to the first node and a second end connected to the second node; A second inductor having a first end connected to the first node and a second end connected to the third node; A third inductor having a first end connected to the third node and a second end connected to the fourth node; A fourth inductor having a first end connected to the second node and a second end connected to the fourth node; Comprising; When the center frequency is \(f_0\), the reference impedance is \(Z_0\), the first inductance of the first inductor and the third inductor is \(L_1\), and the second inductance of the second inductor and the fourth inductor is \(L_2\), the amplifier circuit according to Claim 1, wherein \(L_1\lt Z_0 / 2\pi f_0\) and \(L_2\gt L_1 / \sqrt{2}\).

3. The lumped - type branch - line coupler is: A first capacitor shunt - connected to the first node; A second capacitor shunt - connected to the second node; A third capacitor shunt - connected to the third node; A fourth capacitor shunt - connected to the fourth node; Comprising; The amplifier circuit according to claim 2, wherein when the capacitances of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor are C, C > 1 / (πf₀×Z₀).

4. The lumped - constant branch - line coupler is a first inductor shunt - connected to a first intermediate node located on a first path connecting the first node and the second node; a second inductor shunt - connected to a second intermediate node located on a second path connecting the first node and the third node; a third inductor shunt - connected to a third intermediate node located on a third path connecting the third node and the fourth node; a fourth inductor shunt - connected to a fourth intermediate node located on a fourth path connecting the second node and the fourth node; and includes The amplifier circuit according to claim 1, wherein the center frequency is f₀, the reference impedance is Z₀, the first inductance of the first inductor and the third inductor is L1, and the second inductance of the second inductor and the fourth inductor is L2, and L1 < Z₀ / 2πf₀ and L2 > L1 / √2.

5. The lumped - constant branch - line coupler is a pair of first capacitors connected in series in the first path, with the first intermediate node therebetween; a pair of second capacitors connected in series in the second path, with the second intermediate node therebetween; a pair of third capacitors connected in series in the third path, with the third intermediate node therebetween; a pair of fourth capacitors connected in series in the fourth path, with the fourth intermediate node therebetween; and includes The amplifier circuit according to claim 4, wherein when the capacitance of each of the pair of first capacitors and the pair of third capacitors is C1, and the capacitance of each of the pair of second capacitors and the pair of fourth capacitors is C2, C1 > 1 / (2πf₀×Z₀) and C2 < √2 / (2πf₀×Z₀).

6. The amplifier circuit according to any one of claims 2 to 5, wherein the reference impedance is the characteristic impedance of a transmission line provided between the fourth node and an output terminal from which an output signal is output.

7. The difference between the first ratio of the amplitude of the power of the sixth signal to the amplitude of the power of the seventh signal and the second ratio of the amplitude of the power of the signal distributed to the fourth node to the amplitude of the power of the signal distributed to the third node of the signal of the center frequency input to the first node is 1 dB or less. The amplifier circuit according to any one of claims 1 to 5.

8. The amplifier circuit according to claim 7, wherein the second ratio is 2 dB or more.

9. The amplifier circuit according to any one of claims 1 to 5, wherein the saturation power of the first auxiliary amplifier is greater than the saturation power of the second auxiliary amplifier.

10. The amplifier circuit according to claim 9, wherein the ratio of the saturation power of the first auxiliary amplifier to the saturation power of the second auxiliary amplifier is 2 dB or more.

11. The amplifier circuit according to any one of claims 1 to 5, wherein the physical size of the first auxiliary amplifier is larger than the physical size of the second auxiliary amplifier.

12. The amplifier circuit according to any one of claims 1 to 5, wherein the amplitude of the power of the fourth signal is greater than the amplitude of the power of the fifth signal.

13. The amplifier circuit according to claim 12, wherein the ratio of the amplitude of the power of the fourth signal to the amplitude of the power of the fifth signal is 2 dB or more.

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