Amplifier circuit

Abstract

To provide an amplifier circuit capable of being miniaturized.SOLUTION: An amplifier circuit 100 comprises: a first splitter 14 which splits an input signal Si into a first signal S1 and a second signal S2; a control amplifier 10 which amplifies the first signal and outputs the amplified signal as a third signal S3; a second splitter 16 which splits the second signal into a fourth signal S4 and a fifth signal S5, which have different phases at the center frequency of the operating bandwidth; a first auxiliary amplifier 12a which amplifies the fourth signal and outputs the amplified signal as a sixth signal; a second auxiliary amplifier 12b which amplifies the fifth signal and outputs the amplified signal as a seventh signal; and a synthesizer 18, which is a branch-line coupler.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an amplifier circuit.

Background Art

[0002] An LMBA (Load Modulated Balanced Amplifier) includes a control amplifier that amplifies one of the input signals that are distributed, and a balance amplifier that amplifies the other of the input signals that are distributed. It is known to use a 3dB branch line coupler as a synthesizer for synthesizing the output signal of the control amplifier and the output signal of the balance amplifier (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In an LMBA, from the viewpoint of the characteristics of the coupler, a distributed constant type branch line coupler using a 1 / 4 wavelength line is used as the 3dB branch line coupler. However, because a 1 / 4 wavelength line is used, the distributed constant type branch line coupler is large, and the amplifier circuit becomes large-sized.

[0005] The present disclosure has been made in view of the above problems, and an object thereof is to provide an amplifier circuit that can be miniaturized.

Means for Solving the Problems

[0006] One embodiment of the present disclosure includes a first distributor that distributes an input signal into a first signal and a second signal, a control amplifier that amplifies the first signal and outputs the amplified signal as a third signal, a second distributor that distributes the second signal into a fourth signal and a fifth signal having different phases at the center frequency of the operating band, a first auxiliary amplifier that amplifies the fourth signal and outputs the amplified signal as a sixth signal, a second auxiliary amplifier that amplifies the fifth signal and outputs the amplified signal as a seventh signal, a first terminal into which the sixth signal is input, a second terminal into which the seventh signal is input, a third terminal into which the third signal is input, a fourth terminal that outputs an output signal, a first transmission line connecting the first terminal and the second terminal, a second transmission line connecting the first terminal and the third terminal, a third transmission line connecting the third terminal and the fourth terminal, and a fourth transmission line connecting the second terminal and the fourth terminal, and a branch-line coupler in which a first characteristic impedance at the center frequency of the first transmission line and the third transmission line at the center frequency of the operating band is higher than a reference impedance, and a second characteristic impedance at the center frequency of the second transmission line and the fourth transmission line is lower than the first characteristic impedance / √2, and the amplitude of the power of the seventh signal is larger than the amplitude of the power of the sixth signal.

Advantages of the Invention

[0007] According to the present disclosure, an amplifying circuit capable of miniaturization can be provided.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

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Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Embodiments for Carrying Out the Invention

[0009] [Description of Embodiments of the Present Disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure includes a first distributor that distributes an input signal into a first signal and a second signal, a control amplifier that amplifies the first signal and outputs the amplified signal as a third signal, a second distributor that distributes the second signal into a fourth signal and a fifth signal having different phases at the center frequency of the operating band, a first auxiliary amplifier that amplifies the fourth signal and outputs the amplified signal as a sixth signal, a second auxiliary amplifier that amplifies the fifth signal and outputs the amplified signal as a seventh signal, a first terminal into which the sixth signal is input, a second terminal into which the seventh signal is input, a third terminal into which the third signal is input, a fourth terminal that outputs an output signal, a first transmission line connecting the first terminal and the second terminal, a second transmission line connecting the first terminal and the third terminal, a third transmission line connecting the third terminal and the fourth terminal, and a fourth transmission line connecting the second terminal and the fourth terminal, and a branch line coupler in which a first characteristic impedance at the center frequency of the first transmission line and the third transmission line in the operating band is higher than a reference impedance, and a second characteristic impedance at the center frequency of the second transmission line and the fourth transmission line is lower than the first characteristic impedance / √2, and the amplitude of the power of the seventh signal is larger than the amplitude of the power of the sixth signal. Thereby, the branch line coupler can be miniaturized, and fluctuations in the load impedance of the control amplifier can be suppressed. (2) In the above (1), the difference between a first ratio of the amplitude of the power of the seventh signal to the amplitude of the power of the sixth signal and a second ratio of the amplitude of the power of the signal distributed to the third terminal to the amplitude of the power of the signal distributed to the fourth terminal of the signal of the center frequency input to the first terminal may be 1 dB or less. Thereby, fluctuations in the load impedance of the control amplifier can be suppressed. (3) In the above (2), the second ratio may be 2 dB or more. Thereby, the branch line coupler can be miniaturized. (4) In any one of (1) to (3) above, the first characteristic impedance may be 1.2 times or more the reference impedance, and the second characteristic impedance may be 0.9 / √2 times or less the first characteristic impedance. Thereby, the branch line coupler can be miniaturized. (5) In any one of (1) to (4) above, the first width of the first transmission line and the third transmission line may be smaller than the second width of a fifth transmission line connected to the first end, the second end, the third end, and the fourth end, and the third width of the second transmission line and the fourth transmission line may be larger than the first width. Thereby, the branch line coupler can be miniaturized. (6) In any one of (1) to (5) above, the saturation power of the second auxiliary amplifier may be larger than the saturation power of the first auxiliary amplifier. Thereby, fluctuations in the load impedance of the control amplifier can be suppressed. (7) In any one of (1) to (5) above, the ratio of the saturation power of the second auxiliary amplifier to the saturation power of the first auxiliary amplifier may be 2 dB or more. Thereby, fluctuations in the load impedance of the control amplifier can be suppressed. (8) In any one of (1) to (5) above, the physical size of the second auxiliary amplifier may be larger than the physical size of the first auxiliary amplifier. Thereby, fluctuations in the load impedance of the control amplifier can be suppressed. (9) In any one of (1) to (8) above, the amplitude of the power of the fifth signal may be larger than the amplitude of the power of the fourth signal. Thereby, fluctuations in the load impedance of the control amplifier can be suppressed. (10) In (9) above, the ratio of the amplitude of the power of the fifth signal to the amplitude of the power of the fourth signal may be 2 dB or more. Thereby, fluctuations in the load impedance of the control amplifier can be suppressed. [Details of Embodiments of the Present Disclosure] A specific example of an amplifier circuit according to an embodiment of the present disclosure will be described below with reference to the drawings. It should be noted that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0010] [Example 1] FIG. 1 is a circuit diagram of an amplifier circuit according to Example 1. As shown in FIG. 1, in the amplifier circuit 100 of Example 1, a control amplifier 10 and a balance amplifier 11 are connected in parallel between an input terminal Tin and an output terminal Tout. A high-frequency signal is input as an input signal Si to the input terminal Tin. When the amplifier circuit 100 is used in a base station of mobile communication, the frequency of the high-frequency signal is, for example, 0.5 GHz or more and 10 GHz or less. A distributor 14 (first distributor) distributes the input signal Si input to the input terminal Tin into a signal S1 (first signal) and a signal S2 (second signal).

[0011] The signal S1 passes through a matching circuit (MN: Matching Network) 20 and is input to the control amplifier 10. The matching circuit 20 matches the impedance seen from the distributor 14 to the matching circuit 20 and the impedance seen from the matching circuit 20 to the control amplifier 10. A bias circuit (BC: Bias Circuit) 26 that supplies an input bias voltage VG1 to the control amplifier 10 is connected to a node in the line between the distributor 14 and the control amplifier 10. The bias circuit 26 supplies the input bias voltage VG1 to the control amplifier 10 and suppresses the signal S1 from leaking to the power supply that supplies the input bias voltage VG1.

[0012] The control amplifier 10 amplifies the signal S1 and outputs the amplified signal as a signal S3 (third signal). The signal S3 amplified by the control amplifier 10 passes through the matching circuit 24 and is input to the terminal T23 of the synthesizer 18. The matching circuit 24 matches the impedance seen from the control amplifier 10 to the matching circuit 24 and the impedance seen from the matching circuit 24 to the synthesizer 18. A bias circuit 27 that supplies the output bias voltage VD to the control amplifier 10 is connected to a node in the line between the control amplifier 10 and the synthesizer 18. The bias circuit 27 supplies the output bias voltage VD to the control amplifier 10 and suppresses the leakage of the signal S3 to the power supply that supplies the output bias voltage VD.

[0013] The signal S2 distributed by the distributor 14 is input to the balun 11. The balun 11 includes a distributor 16, auxiliary amplifiers 12a and 12b, and a synthesizer 18. The distributor 16 (second distributor) distributes the signal S2 input to the terminal T11 into a signal S4 (fourth signal) and a signal S5 (fifth signal), and outputs them from the terminals T13 and T14, respectively. The phase of the signal S5 lags behind the phase of the signal S4 by, for example, about 90°. The amplitudes of the signals S5 and S4 are, for example, substantially the same. The 90° does not have to be exactly 90°, and may be, for example, greater than 85° and less than 95°, or greater than or equal to 88° and less than or equal to 92°. The same applies to the synthesizer 18.

[0014] The signal S4 passes through the matching circuit 22a and is input to the auxiliary amplifier 12a. The matching circuit 22a matches the impedance seen from the distributor 16 to the matching circuit 22a and the impedance seen from the matching circuit 22a to the auxiliary amplifier 12a. A bias circuit 28a that supplies the input bias voltage VG2a to the auxiliary amplifier 12a is connected to a node in the line between the distributor 16 and the auxiliary amplifier 12a. The bias circuit 28a supplies the input bias voltage VG2a to the auxiliary amplifier 12a and suppresses the leakage of the signal S4 to the power supply that supplies the input bias voltage VG2a. The auxiliary amplifier 12a (first auxiliary amplifier) amplifies the signal S4 and outputs the amplified signal as a signal S6 (sixth signal). The signal S6 amplified by the auxiliary amplifier 12a is input to the terminal T21 of the synthesizer 18.

[0015] The signal S5 passes through the matching circuit 22b and is input to the auxiliary amplifier 12b. The matching circuit 22b matches the impedance seen from the distributor 16 to the matching circuit 22b and the impedance seen from the matching circuit 22b to the auxiliary amplifier 12b. A bias circuit 28b that supplies the input bias voltage VG2b to the auxiliary amplifier 12b is connected to a node in the line between the distributor 16 and the auxiliary amplifier 12b. The bias circuit 28b supplies the input bias voltage VG2b to the auxiliary amplifier 12b and suppresses the leakage of the signal S5 to the power supply that supplies the input bias voltage VG2b. The auxiliary amplifier 12b (second auxiliary amplifier) amplifies the signal S5 and outputs the amplified signal as a signal S7 (seventh signal). The signal S7 amplified by the auxiliary amplifier 12b is input to the terminal T22 of the synthesizer 18.

[0016] An impedance matching circuit for impedance matching may be connected between the auxiliary amplifiers 12a and 12b and the synthesizer 18. In the first embodiment, the signal of the control amplifier 10 adjusts the loads of the auxiliary amplifiers 12a and 12b. Therefore, an impedance matching circuit may not be provided between the auxiliary amplifiers 12a and 12b and the synthesizer 18. A harmonic processing circuit that reflects the harmonic signals in the signals S6 and S7 may be connected between the auxiliary amplifiers 12a and 12b and the synthesizer 18. The harmonic signals are, for example, second harmonics or third harmonics when the operating frequency of the amplifier circuit is taken as the fundamental wave. A bias circuit that supplies an output bias voltage to the auxiliary amplifiers 12a and 12b may be provided between the auxiliary amplifiers 12a and 12b and the synthesizer 18. In the first embodiment, the output bias voltages of the auxiliary amplifiers 12a and 12b are supplied from the bias circuit 27 through the synthesizer 18 to the auxiliary amplifiers 12a and 12b.

[0017] The synthesizer 18 is a distributed constant type branch line coupler. The terminals T21 to T24 are the terminals of the branch line coupler. The terminals T21 and T24 are located diagonally, and the terminals T22 and T23 are located diagonally. The signal S6 is input to the terminal T21 (the first terminal). The signal S7 is input to the terminal T22 (the second terminal). The signal S3 is input to the terminal T23 (the third terminal). The output signal So is output from the terminal T24 (the fourth terminal). The synthesizer 18 synthesizes the signals S3, S6, and S7 and outputs the synthesized signal as the output signal So.

[0018] The control amplifier 10, auxiliary amplifiers 12a and 12b are transistors such as FETs (Field Effect Transistors), for example. The source is grounded, a high-frequency signal is input to the gate, and a high-frequency signal is output from the drain. The FETs are, for example, GaN HEMTs (Gallium Nitride High Electron Mobility Transistors) or LDMOSs (Laterally Diffused Metal Oxide Semiconductors). The control amplifier 10, auxiliary amplifiers 12a and 12b may each be provided with multiple stages of FETs. When the control amplifier 10, auxiliary amplifiers 12a and 12b are FETs, the input bias voltages VG1, VG2a and VG2b are gate bias voltages, and the output bias voltage VD is a drain bias voltage.

[0019] [Divider 16] FIG. 2 is a circuit diagram showing the distributor 16 in Example 1. As shown in FIG. 2, the distributor 16 uses a distributed constant type branch line coupler. Transmission lines TL11, TL12, TL13, and TL14 are respectively connected between node N11 and N12, between node N11 and N13, between node N13 and N14, and between node N12 and N14. Transmission lines TL11 to TL14 are λ / 4 transmission lines. The electrical length of the λ / 4 transmission line is approximately λ / 4, for example. Here, λ is the wavelength of the center frequency fo of the operating band of the amplifier circuit 100. The electrical length of the λ / 4 transmission line does not have to be exactly λ / 4, and may be, for example, 3λ / 16 or more and 5λ / 16 or less, or 7λ / 32 or more and 9λ / 32 or less. The same applies to other λ / 4 transmission lines. Between end T11 and node N11, between end T12 and node N12, between end T13 and node N13, and between end T14 and node N14 are connected by transmission line 32. The signal S2 input to end T11 is distributed to signals S4 and S5 and output from ends T13 and T14, respectively. The phase of the signal S5 at the center frequency fo is approximately 90° later than the phase of the signal S4 at the center frequency fo. End T12 is connected to the reference potential via resistor R1. The resistance value of resistor R1 is, for example, the reference impedance (for example, 50Ω).

[0020] As the distributor 16, a Wilkinson type distributor, a distributor using a λ / 4 transmission line, a lumped multiplier type branch line coupler using an inductor and a capacitor, a distributed coupling type coupler in which two transmission lines are electromagnetically coupled, or a closely wound coil coupler in which two inductors are electromagnetically coupled may be used.

[0021] [Synthesizer 18] FIG. 3 is a circuit diagram showing an example of the synthesizer 18 in the first embodiment. As shown in FIG. 3, the synthesizer 18 is a distributed constant type branch line coupler. Transmission lines TL21 (first transmission line), TL22 (second transmission line), TL23 (third transmission line), and TL24 (fourth transmission line) are connected between node N21 and N22, between node N21 and N23, between node N23 and N24, and between node N22 and N24, respectively. The transmission lines TL21 to TL24 are λ / 4 transmission lines. Between end T21 and node N21, between end T22 and node N22, between end T23 and node N23, and between end T24 and node N24 are connected by transmission line 32. The signals S6 input to end T21, the signal S7 input to end T22, and the signal S3 input to end T23 are synthesized, and the synthesized signal is output from end T24 as output signal So.

[0022] FIG. 4 is a plan view of the branch line coupler in the first embodiment. As shown in FIG. 4, the transmission lines TL21 to TL24 and the transmission line 32 are formed by a conductor pattern 31 provided on the dielectric substrate 30. A metal layer to which a reference potential is supplied is provided on the lower surface of the dielectric substrate 30. The transmission lines TL21 to TL24 and the transmission line 32 are microstrip lines. The characteristic impedance of the transmission line 32 is the reference impedance Zo, for example, 50 Ω. The widths of the transmission lines TL21 and TL23 are width W1, the widths of the transmission lines TL22 and TL24 are width W2, and the width of the transmission line 32 is width W3.

[0023] When the dielectric substrate 30 is a mounting substrate, the dielectric substrate 30 is, for example, a glass epoxy resin substrate or a ceramics substrate. When the distributor 16 and the synthesizer 18 are monolithically integrated with the control amplifier 10, the auxiliary amplifiers 12a and 12b, the dielectric substrate 30 is, for example, a silicon carbide substrate, a gallium nitride substrate, a gallium arsenide substrate, or a silicon substrate. The conductor pattern 31 is a metal layer such as a gold layer, a copper layer, or an aluminum layer.

[0024] Integrated circuits 20, 22a, 22b, and 24 are passive circuits including inductors and capacitors, and are, for example, inductors connected in series, a π-type circuit of a CLC configuration, a T-type circuit of an LCL configuration, an L-type circuit of an LC configuration, or a circuit combining these circuits.

[0025] Control amplifier 10 corresponds to the main amplifier of the Doherty amplifier circuit, and auxiliary amplifiers 12a and 12b correspond to the peak amplifiers of the Doherty amplifier circuit. Control amplifier 10 operates in class AB or class B, and auxiliary amplifiers 12a and 12b operate in class C. When the input power of input signal Si is small, control amplifier 10 mainly amplifies input signal Si. When the input power increases, in addition to control amplifier 10, auxiliary amplifiers 12a and 12b amplify the peak of input signal Si. Thereby, control amplifier 10 and auxiliary amplifiers 12a and 12b amplify input signal Si.

[0026] [Comparative Example 1] As Comparative Example 1, a Doherty amplifier circuit will be described. FIG. 5 is a circuit diagram of the amplifier circuit according to Comparative Example 1. As shown in FIG. 5, in the amplifier circuit 110 of Comparative Example 1, a main amplifier 10a and a peak amplifier 12 are provided in parallel between an input terminal Tin and an output terminal Tout. Divider 14 distributes input signal Si into signals S1 and S2. Main amplifier 10a amplifies signal S1 that has passed through matching circuit 20, and outputs the amplified signal as signal S3 to combiner 18a via matching circuit 24. Peak amplifier 12 amplifies signal S2 that has passed through matching circuit 22, and outputs the amplified signal as signal S9 to combiner 18a via matching circuit 24a.

[0027] Combiner 18a includes λ / 4 transmission lines TL51 and TL52 as impedance converters. The impedance seen from matching circuit 24 to combiner 18a and the load impedance of peak amplifier 12 are modulated using λ / 4 transmission lines TL51 and TL52.

[0028] In Comparative Example 1, when the frequency changes, the electrical length of the λ / 4 transmission line deviates from λ / 4, making it difficult to broaden the operating band. In one example, the specific band of the synthesizer using the λ / 4 transmission lines TL51 and TL52 is about 8%. In the LMBA as in Example 1, by using a branch-line coupler and modulating the load impedances of the auxiliary amplifiers 12a and 12b, it becomes possible to broaden the operating band. The specific band of the branch-line coupler is up to 120% at maximum in, for example, a commercially available hybrid coupler. Thus, in the LMBA, the synthesizer 18 can be broadened in bandwidth.

[0029] [Comparative Example 2] As Comparative Example 2, an LMBA in which the synthesis ratio of the synthesizer 18 is 1:1 will be described. FIGS. 6 and 7 are circuit diagrams showing a part of the amplifier circuit 112 in Comparative Example 2. In FIGS. 6 and 7, the circuits after the control amplifier 10 and the balance amplifier 11 are illustrated. In Comparative Example 2, in FIG. 7, the power synthesis ratio at which the synthesizer 18 synthesizes the signals S6 and S7 is 1:1.

[0030] Using FIG. 6, when the power of the input signal Si is small and the auxiliary amplifiers 12a and 12b are not operating, the signal S3 input to the synthesizer 18 from the terminal T23 is divided into two signals S3a and S3b at the terminals T21 and T22. The ratio of the power amplitudes of the signals S3a and S3b is 1:1. The phase of the signal S3b at the terminal T22 lags 90° behind the phase of the signal S3a at the terminal T21. The signals S3a and S3b are reflected at the terminals T21 and T22 respectively. The reflected signals S3a and S3b are synthesized at the terminal T24. The phase of the signal S3a reflected at the terminal T21 is 90° later than the phase of the signal S3b reflected at the terminal T22. As a result, at the terminal T24, the phases of the signals S3a and S3b are aligned and the signal S3 is synthesized. The synthesized signal S3 is output as the output signal So to the output terminal Tout.

[0031] At this time, the reflection coefficients seen from the synthesizer 18 from the auxiliary amplifiers 12a and 12b (i.e., the absolute values of the impedances Z3a and Z3b) are greater than 1, and the impedances Z3a and Z3b that are the loads of the auxiliary amplifiers 12a and 12b are substantially high. On the other hand, the impedance Z1 seen from the terminal T23 from the matching circuit 24 is a reference impedance (e.g., 50 Ω) that is the input impedance of the terminal T23.

[0032] Next, using FIG. 7, when the power of the input signal Si is large and the auxiliary amplifiers 12a and 12b are operating, the signal S7 lags behind the signal S6 in phase by 90°. The signal S3b at the terminal T22 lags behind the signal S3a at the terminal T21 in phase by 90°. Thereby, by appropriately adjusting the phase difference between the signals S1 and S2, the phases of the signals S6 and S3a at the terminal T21 are optimized (e.g., the phases of the signals S6 and S3a are aligned), and the phases of the signals S7 and S3b at the terminal T22 are optimized (e.g., the phases of the signals S7 and S3b are aligned). The signal S6 + S3a synthesized at the terminal T21 and the signal S7 + S3b synthesized at the terminal T22 are synthesized at the terminal T24. The synthesized signal S3 + S6 + S7 is output as the output signal So to the output terminal Tout.

[0033] At this time, the signals incident on terminals T21 and T22 from auxiliary amplifiers 12a and 12b are substantially S6+S3a and S7+S3b respectively, and the signals reflected at terminals T21 and T22 are substantially S3a and S3b respectively. Therefore, the reflection coefficients (i.e., the absolute values of impedances Z3a and Z3b) seen from terminals T21 and T22 of auxiliary amplifiers 12a and 12b are less than 1, and become smaller as the power amplitudes of signals S6 and S7 are larger. The impedances Z3a and Z3b that are the loads of auxiliary amplifiers 12a and 12b become substantially lower as the power amplitudes of signals S6 and S7 are larger. In this way, synthesizer 18 modulates the impedances Z3a and Z3b that are the loads seen from synthesizer 18 from auxiliary amplifiers 12a and 12b depending on the amplitudes of signals S6 and S7. On the other hand, the impedance Z1 seen from terminal T23 from matching circuit 24 is a reference impedance (e.g., 50 Ω) regardless of the magnitudes of the amplitudes of signals S6 and S7.

[0034] When the power of output signal So is at the maximum value in the operating range of the amplifier circuit, the output power of output signal So is defined as saturation power Psat. At saturation power Psat, in Comparative Example 1, the output powers of main amplifier 10a and peak amplifier 12, and in Comparative Example 2, the output powers of control amplifier 10, auxiliary amplifiers 12a and 12b are saturated. Here, the output power being saturated includes a state that is 1 dB or less or 2 dB or less lower than the complete saturation state. When the power of output signal So is at the minimum value in the operating range of the amplifier circuit, it is defined as back-off power Pbo. At back-off power Pbo, in Comparative Example 1, main amplifier 10a has started to saturate, and in Comparative Example 2, the output power of control amplifier 10 is saturated.

[0035] Since no high-power signal is applied to the distributor 16, it is possible to use a distributor that can be miniaturized even with low high-frequency characteristics. However, a high power is applied to the synthesizer 18. Therefore, a coupler with high high-frequency characteristics is required for the synthesizer 18. As a coupler with high high-frequency characteristics, a distributed constant type branch line coupler as shown in FIGS. 3 and 4 is used. However, since the distributed constant type branch line coupler uses four λ / 4 transmission lines, it becomes large-sized. Referring to FIG. 4, when the width W2 is large as in the transmission lines TL22 and TL24, the area occupied by the transmission lines TL22 and TL24 becomes large. When the power combining ratio for the synthesizer 18 to combine the signals S6 and S7 is 1:1, the characteristic impedance Zc1 at the center frequency fo of the transmission lines TL21 and TL23 is the reference impedance Zo. The characteristic impedance Zc2 at the center frequency fo of the transmission lines TL22 and TL24 is Zc1 / √2. Therefore, when the dielectric constant and thickness of the dielectric substrate 30 in FIG. 4 are determined, the widths W1 and W2 of the transmission lines TL21 to TL24 are determined. Thus, in Comparative Examples 1 and 2, the synthesizer 18 becomes large-sized, and it is difficult to miniaturize the amplifier circuit 112.

[0036] [Comparative Example 3] As Comparative Example 3, an LMBA in which the combining ratio of the synthesizer 18 is not 1:1 will be described. Instead of the combining ratio of the synthesizer 18, the distribution ratio in which the power of the signal S6 input to the terminal T21 is distributed to the terminals T24 and T23 is used as an index. The signal output to the terminal T23 is defined as the signal S6a, and the signal output to the terminal T24 is defined as the signal S6b. Let the amplitudes of the powers of the signals S6, S6a, and S6b be A6, A6a, and A6b, respectively. The ratio of the amplitude A6a to the amplitude A6b is A6b:A6a, and in dB representation, it is A6a - A6b [dB]. Let the characteristic impedances of the transmission lines TL21 and TL23 in FIGS. 3 and 4 be Zc1, and the characteristic impedances of the transmission lines TL22 and TL24 be Zc2.

[0037] Table 1 is a diagram showing the characteristic impedances Zc1 and Zc2 for realizing the ratio A6a - A6b [dB].

Table 1

[0038] In Table 1, the reference impedance Zo is set to 50 Ω. The reference impedance Zo corresponds to the impedance seen from the outside of terminals T21, T22, T23, and T24. As shown in Table 1, when the amplitudes A6a and A6b are equal, that is, when the signal S6 is equally divided into S6a and S6b, the characteristic impedance Zc1 is 50 Ω of the reference impedance Zo, and the characteristic impedance Zc2 is 35.35 Ω which is Zo / √2.

[0039] When making A6a - A6b smaller than when A6a - A6b = 0 dB, the characteristic impedance Zc1 is made lower than the reference impedance Zo, and the characteristic impedance Zc2 is made higher than Zc1 / √2. In this case, both the characteristic impedances Zc1 and Zc2 become lower than Zc1 and Zc2 when A6a - A6b = 0 dB, respectively. Therefore, the widths W1 and W2 in FIG. 4 are made larger than the widths W1 and W2 when A6a - A6b = 0 dB, respectively. Thus, the synthesizer 18 becomes larger.

[0040] When making A6a - A6b larger than when A6a - A6b = 0 dB, the characteristic impedance Zc1 is made higher than the reference impedance Zo, and the characteristic impedance Zc2 is made lower than Zc1 / √2. In this case, both the characteristic impedances Zc1 and Zc2 become higher than Zc1 and Zc2 when A6a - A6b = 0 dB, respectively. Therefore, the widths W1 and W2 in FIG. 4 are made thinner than the widths W1 and W2 when A6a - A6b = 0 dB, respectively. Thus, the synthesizer 18 can be miniaturized.

[0041] From the perspective of miniaturizing the synthesizer 18, the characteristic impedance Zc1 is made higher than the reference impedance Zo, and the characteristic impedance Zc2 is made lower than Zc1 / √2. The characteristic impedance Zc1 can be set to 1.01 times or more, 1.2 times or more, 1.4 times or more, or 1.7 times or more of the reference impedance Zo. The characteristic impedance Zc2 can be set to 0.99 times or less, 0.85 times or less, 0.7 times or less, or 0.6 times or less of Zc1 / √2. From the perspective of not making A6a - A6b too large, the characteristic impedance Zc1 can be set to 3 times or less of the reference impedance Zo, and the characteristic impedance Zc2 can be set to 0.5 times or more of Zc1 / √2o.

[0042] The width W1 can be set to 0.99 times or less, 0.7 times or less, or 0.5 times or less of the width W3. The width W1 can be set to 0.2 times or more of the width W3. The width W2 can be set to 1.01 times or more or 1.2 times or more of the width W1, and can be set to 1.5 times or less.

[0043] Figure 8 is a schematic diagram for explaining the operation of the synthesizer in Comparative Example 3 and Example 1. The characteristic impedance of the transmission line 32 is the reference impedance Zo, for example, 50Ω. The width W3 of the transmission line 32 is determined such that the characteristic impedance of the transmission line 32 becomes the reference impedance Zo. As shown in Table 1, the characteristic impedances Zc1 of the transmission lines TL21 and TL23 are larger than the reference impedance Zo. Therefore, the widths W1 of the transmission lines TL21 and TL23 are smaller than the width W3 of the transmission line 32. The characteristic impedances Zc2 of the transmission lines TL22 and TL24 are smaller than the reference impedance Zo. Therefore, the widths W2 of the transmission lines TL22 and TL24 are larger than the width W3 of the transmission line 32.

[0044] The amplitude of the signal S6 input to the terminal T21 is A6, and the phase is 0°. The amplitude of the signal S7 input to the terminal T22 is A7, and the phase is -90°. The signals S6 and S7 are represented as (A6, 0°) and (A7, -90°), respectively. The signals output to the terminals T23 and T24 when the signal S6 is distributed are the signals S6a and S6b, respectively. Let the ratio A6b:A6a of the amplitudes of the signals S6b and S6a in the W display be 1:N (N>1). At this time, the signals S6a and S6b are ((N / (1 + N))×A6, -90°) and ((1 / (1 + N))×A6, -180°), respectively. The signals S7a and S7b are ((1 / (1 + N))×A7, -270°) and ((N / (1 + N))×A7, -180°), respectively.

[0045] At the terminal T24, the signals S6b and S7b are in the same phase, and the signal S6a with an amplitude of (1 / (1 + N))×A6 and the signal S7b with an amplitude of (N / (1 + N))×A7 are combined.

[0046] At the terminal T23, the signals S6a and S7a are in opposite phases. When N = 1, the amplitudes of the signals S6a and S7a are (1 / 2)×A6 and (1 / 2)×A7, respectively. Since the amplitudes A6 and A7 are almost the same, the signals S6a and S7a are compensated. As a result, no signal is output from the terminal T23. Thereby, the impedance Z1 seen from the terminal T23 of the matching circuit 24 is constant regardless of the amplitudes of the signals S6 and S7 and is the reference impedance Zo.

[0047] When N > 1, Comparative Example 3 will be described. FIG. 9 is a circuit diagram showing a balance amplifier in Comparative Example 3. As shown in FIG. 9, in Comparative Example 3, as described in FIG. 6, in the synthesizer 18, the amplitude ratio A6b:A6a of the signals S6b and S6a is 1:N (N > 1). The amplitude ratio of the signal S5 and the signal S4 in the distributor 16 is 1:1. Therefore, the signal S4 output to the terminal T13 is (A4, 0°). The signal S5 output from the terminal T14 is (A4, -90°). The amplitudes of the signals S4 and S5 are substantially the same and are A4. The physical sizes of the auxiliary amplifiers 12a and 12b are the same as each other, and the saturation powers are also the same as each other. The input bias voltages supplied to the auxiliary amplifiers 12a and 12b are the same as each other, and the output bias voltages are also the same as each other. As a result, the amplitudes of the signals S6 and S7 are substantially the same and become A6. Therefore, the signal S6 input to the terminal T21 is (A6, 0°), and the signal S7 input to the terminal T22 is (A6, -90°).

[0048] The signal S6a output from the terminal T23 is ((N / (1 + N))×A6, -90°), and the signal S7a is ((1 / (1 + N))×A6, -270°). Since the signals S6a and S7a are out of phase, the signal S6a + S7a becomes ((N - 1) / (1 + N)×A6, -90°), and when N > 1, the signals S6a and S7a are not compensated. For this reason, the impedance Z1 that becomes the load of the control amplifier 10 changes. For example, when the output power Pout is the back-off power Pbo, the impedance Z1 is the reference impedance Zo. When the output power Pout is the saturation power Psat, due to the influence of the signal S6a + S7a output from the terminal T23 of the synthesizer 18, the impedance Z1 changes from the reference impedance Zo.

[0049] [Example 1 of Example 1] FIG. 10 is a circuit diagram showing a balance amplifier in Example 1 of Example 1. As shown in FIG. 10, the signal distribution ratio of the distributor 16 is 1:1. The physical size of the auxiliary amplifier 12b is about N times the physical size of the auxiliary amplifier 12a. For example, when the auxiliary amplifiers 12a and 12b are FETs, the gate width of the auxiliary amplifier 12b is about N times the gate width of the auxiliary amplifier 12a. The saturation power of the auxiliary amplifier 12b is about N times the saturation power of the auxiliary amplifier 12a.

[0050] The amplitudes of the signals S4 and S5 distributed by the distributor 16 are substantially the same and are A4. When both the auxiliary amplifiers 12a and 12b are used at saturation power, the amplitude A7 of the signal S7 is N times the amplitude A6 of the signal S6. Therefore, the signal S6 input to the terminal T21 is (A6, 0°), and the signal S7 input to the terminal T22 is (N×A6, -90°).

[0051] The signal S6a output from the terminal T23 is ((N / (1 + N))×A6, -90°), and the signal S7a is ((1 / (1 + N))×N×A6, -270°). The amplitudes of the signals S6a and S7a are both (N / (1 + N)×A6), and since the signals S6a and S7a are in opposite phases, the amplitude of S6a + S7a is almost 0. Thus, when the output power Pout is at the back-off power Pbo and at the saturation power Psat, the impedance Z1 is the reference impedance Zo.

[0052] [Example 2 of Example 1] FIG. 11 is a circuit diagram showing a balance amplifier in Example 2 of Example 1. As shown in FIG. 11, the signal distribution ratio of the distributor 16 is N:1. The physical sizes of the auxiliary amplifiers 12a and 12b are substantially the same as each other. The saturation powers of the auxiliary amplifiers 12a and 12b are substantially the same as each other. The method of setting the distribution ratio of the distributor 16 to N:1 is to set the characteristic impedances of the transmission lines TL11 to TL14 as shown in Table 1 when the distributor 16 is a branch-line coupler. When other couplers are used for the distributor 16, the distribution ratio can also be changed using known methods.

[0053] The amplitude of the signal S5 distributed by the distributor 16 is approximately N times the amplitude of the signal S4. Therefore, the signal S4 is (A4, 0°), and the signal S5 is (N×A4, -90°). If the auxiliary amplifiers 12a and 12b do not reach the saturation power and have approximately the same power gain, the amplitude A7 of the signal S7 is N times the amplitude of the signal S6. Therefore, the signal S6 is (A6, 0°), and the signal S7 is (N×A6, -90°).

[0054] Therefore, similar to Example 1, the signal S6a output from the terminal T23 is ((N / (1 + N))×A6, -90°), and the signal S7a is ((1 / (1 + N))×N×A6, -270°). The amplitude of S6a + S7a becomes almost 0. For this reason, even if the magnitudes of the signals S6 and S7 change, the change in the impedance Z1 is suppressed.

[0055] According to Example 1, in the branch-line coupler, the characteristic impedance Zc1 (first characteristic impedance) of the transmission lines TL21 and TL23 at the center frequency fo is higher than the reference impedance Zo. The characteristic impedance Zc2 (second characteristic impedance) of the transmission lines TL22 and TL24 at the center frequency fo is lower than Zc1 / √2. Thereby, as shown in Table 1, the synthesizer 18 can be miniaturized. However, as in Comparative Example 3, the impedance Z1 seen from the control amplifier 10 to the synthesizer 18 changes due to the changes in the signals S6 and S7. Therefore, the power amplitude of the signal S7 is made larger than the power amplitude of the signal S6. Thereby, as in Example 1 and Example 2 of Example 1, the signal S6a + S7a output from the terminal T23 can be made small. Therefore, the variation of the impedance Z1 due to the changes in the signals S6 and S7 can be suppressed.

[0056] The first ratio of the amplitude A7 of the power of signal S7 to the amplitude A6 of the power of signal S6 is A7 / A6. The second ratio of the amplitude A6a of the power of signal S6a distributed to terminal T23 to the amplitude A6b of the power of signal S6b distributed to terminal T24 for the signal S6 with the center frequency fo input to terminal T21 is A6a / A6b. When the first ratio A7 / A6 and the second ratio A6a / A6b are expressed in dB, as in Example 1 and Example 2 of Embodiment 1, when both the first ratio and the second ratio are N, the difference between the first ratio A7 / A6 and the second ratio A6a / A6b is 0 dB. At this time, the signal S6a + S7a output from terminal T23 becomes almost 0. From the viewpoint of suppressing the change in the impedance Z1 due to the magnitudes of signals S6 and S7, the difference between the first ratio A7 / A6 and the second ratio A6a / A6b can be 1 dB or less, can be 0.5 dB or less, and can be 0.3 dB or less. Note that the difference between A7 / A6 and A6a / A6b corresponds to |A7 / A6 - A6a / A6b|.

[0057] From the viewpoint of miniaturizing the synthesizer 18, the second ratio A6a / A6b can be 2 dB or more, can be 3 dB or more, and can be 4 dB or more. Also, the characteristic impedance Zc1 can be 1.2 times or more the reference impedance Zo, can be 1.4 times or more, and can be 1.6 times or more. The characteristic impedance Zc2 can be 0.9×Zc1 / √2 times or less, can be 0.8×Zc1 / √2 times or less, and can be 0.7×Zc1 / √2 times or less.

[0058] If the second ratio A6a / A6b is too large, the signal output from terminal T24 deteriorates. From this viewpoint, the second ratio A6a / A6b can be 10 dB or less. The characteristic impedance Zc1 can be 3 times or less the reference impedance Zo. The characteristic impedance Zc2 can be 0.3×Zx1 / √2 or more.

[0059] When the characteristic impedances Zc1 and Zc2 are set as described above, the widths W1 (first width) of the transmission lines TL21 and TL23 are smaller than the width W3 (second width) of the transmission line 32 (fifth transmission line) connected to the ends T21, T22, T23, and T24. Also, the widths W2 (third width) of the transmission lines TL22 and TL24 are larger than the width W1.

[0060] From the viewpoint of increasing the second ratio A6a / A6b, the width W1 can be 0.7 times or less, and can be 0.5 times or less, of the width W3. The width W2 can be 2.1 times or more, and can be 2.5 times or more, of the width W1. From the viewpoint of not increasing the second ratio A6a / A6b too much, the width W1 can be 10 times or less of the width W3, and the width W2 can be 10 times or less of the width W1.

[0061] As in Example 1 of Example 1, from the viewpoint of increasing the first ratio A7 / A6, the saturation power of the auxiliary amplifier 12b is larger than the saturation power of the auxiliary amplifier 12a. The saturation power of the auxiliary amplifier 12b with respect to the saturation power of the auxiliary amplifier 12a can be 1 dB or more, can be 2 dB or more, and can be 3 dB or more. From the viewpoint of not increasing the first ratio A7 / A6 too much, the saturation power of the auxiliary amplifier 12b with respect to the saturation power of the auxiliary amplifier 12a can be 10 dB or less.

[0062] To make the saturation power of the auxiliary amplifier 12b larger than the saturation power of the auxiliary amplifier 12a, the physical size of the auxiliary amplifier 12b is larger than the physical size of the auxiliary amplifier 12a. For example, when the auxiliary amplifiers 12a and 12b are FETs, the gate width of the auxiliary amplifier 12b can be made larger than the gate width of the auxiliary amplifier 12a, and can be 1.3 times or more, 1.6 times or more, or 2 times or more of the gate width of the auxiliary amplifier 12a. Also, the gate width of the auxiliary amplifier 12b can be 10 times or less of the gate width of the auxiliary amplifier 12a.

[0063] As in Example 2 of Example 1, from the viewpoint of making the first ratio A7 / A6 larger, the amplitude A5 of the power of signal S5 is larger than the amplitude A4 of the power of signal S4. The ratio of the amplitude A5 of the power of signal S5 to the amplitude A4 of the power of signal S4 can be 1 dB or more, can be 2 dB or more, and can be 3 dB or more. From the viewpoint of not making the first ratio A7 / A6 too large, the ratio of amplitude A4 to amplitude A5 can be 10 dB or less.

[0064] As a method of making the first ratio A7 / A6 larger than 1, in addition to Example 1 and Example 2 of Example 1, for example, there is a method of combining Example 1 and Example 2. That is, the saturation power of the auxiliary amplifier 12b may be made larger than the saturation power of the auxiliary amplifier 12a, and the amplitude A5 of the power of signal S5 may be made larger than the amplitude A4 of the power of signal S4. Also, the first ratio A7 / A6 may be made larger than 1 by appropriately setting the bias voltages of the auxiliary amplifiers 12a and 12b.

[0065] It should be considered that all aspects of the embodiments disclosed this time are illustrative and not restrictive. The scope of the present disclosure is not the above meaning, but is indicated by the claims, and all modifications within the meaning and scope equivalent to the claims are intended to be included.

Explanation of Reference Numerals

[0066] 10 Control Amplifier 10a Main Amplifier 11 Balanced Amplifier 12 Peak Amplifier 12a (First Auxiliary Amplifier), 12b (Second Auxiliary Amplifier) Auxiliary Amplifier 14 (First Divider), 16 (Second Divider) Divider 18, 18a Combiner 20, 22, 22a, 22b, 24, 24a Matching Circuit 26, 27, 28a, 28b Bias Circuit 30 Dielectric Substrate 31 Conductor Pattern 32 Transmission Line 100, 110, 112 Amplification circuits S1 (First signal), S2 (Second signal), S3 (Third signal), S4 (Fourth signal), S5 (Fifth signal), S6 (Sixth signal), S7 (Seventh signal) Signals Si Input signal So Output signal TL21 (First transmission line), TL22 (Second transmission line), TL23 (Third transmission line), TL24 (Fourth transmission line) Transmission lines

Claims

1. A first distributor that distributes an input signal into a first signal and a second signal; A control amplifier that amplifies the first signal and outputs the amplified signal as a third signal; A second distributor that distributes the second signal into a fourth signal and a fifth signal having different phases at the center frequency of the operating band; A first auxiliary amplifier that amplifies the fourth signal and outputs the amplified signal as a sixth signal; A second auxiliary amplifier that amplifies the fifth signal and outputs the amplified signal as a seventh signal; A first branch line coupler including a first terminal into which the sixth signal is input, a second terminal into which the seventh signal is input, a third terminal into which the third signal is input, a fourth terminal that outputs an output signal, a first transmission line connecting the first terminal and the second terminal, a second transmission line connecting the first terminal and the third terminal, a third transmission line connecting the third terminal and the fourth terminal, and a fourth transmission line connecting the second terminal and the fourth terminal, wherein a first characteristic impedance at the center frequency of the first transmission line and the third transmission line in the operating band is higher than a reference impedance, and a second characteristic impedance at the center frequency of the second transmission line and the fourth transmission line is lower than the first characteristic impedance / √2; Comprising; An amplifier circuit in which the amplitude of the power of the seventh signal is larger than the amplitude of the power of the sixth signal.

2. The amplifier circuit according to claim 1, wherein a difference between a first ratio of the amplitude of the power of the seventh signal to the amplitude of the power of the sixth signal and a second ratio of the amplitude of the power of the signal distributed to the third terminal to the amplitude of the power of the signal distributed to the fourth terminal of the signal of the center frequency input to the first terminal is 1 dB or less.

3. The amplifier circuit according to claim 2, wherein the second ratio is 2 dB or more.

4. The amplifier circuit according to any one of claims 1 to 3, wherein the first characteristic impedance is 1.2 times or more of the reference impedance, and the second characteristic impedance is 0.9 / √2 times or less of the first characteristic impedance.

5. The amplifier circuit according to any one of claims 1 to 3, wherein a first width of the first transmission line and the third transmission line is smaller than a second width of a fifth transmission line connected to the first terminal, the second terminal, the third terminal, and the fourth terminal, and a third width of the second transmission line and the fourth transmission line is larger than the first width.

6. The saturation power of the second auxiliary amplifier is greater than the saturation power of the first auxiliary amplifier. The amplifier circuit according to any one of claims 1 to 3. **Claim 7** The ratio of the saturation power of the second auxiliary amplifier to the saturation power of the first auxiliary amplifier is 2 dB or more. The amplifier circuit according to any one of claims 1 to 3. **Claim 8** The physical size of the second auxiliary amplifier is larger than the physical size of the first auxiliary amplifier. The amplifier circuit according to any one of claims 1 to 3. **Claim 9** The amplitude of the power of the fifth signal is greater than the amplitude of the power of the fourth signal. The amplifier circuit according to any one of claims 1 to 3. **Claim 10** The ratio of the amplitude of the power of the fifth signal to the amplitude of the power of the fourth signal is 2 dB or more. The amplifier circuit according to claim 9.

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