Semiconductor device

Abstract

To provide a semiconductor device capable of improving resistance to malfunction and destruction caused by noise and the like.SOLUTION: A semiconductor device includes a first conductive type substrate 1, a second conductive type first well region 2 that is provided on the substrate 1 and in which a high-side circuit 102 is formed, a first conductive type second well region 7 provided on an upper part of the first well region 2, a second conductive type first withstand voltage region 8 provided around the first well region 2, a second conductive type contact region 2a provided on an upper part of the first well region 2 or the first withstand voltage region 8, a first conductive type slit region 6 that is provided between the second well region 7 and the contact region 2a on the upper part of the first well region 2 and connected to the second well region 7 via a resistor R11, a first conductive type second withstand voltage region 3 provided on the outer periphery side of the first withstand voltage region 8, and level shifters 10a, 10b for transmitting signals between the low-side circuit 101 and the high-side circuit 102.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a configuration in which, in a high-voltage integrated circuit (HVIC), a p-type region of a reference potential (VS potential) of a high-side circuit is formed separately from an n-type region of a power supply potential (VB potential) of the high-side circuit, thereby not forming a parasitic pnp bipolar transistor.

[0003] Patent Document 2 discloses a configuration in which, in an HVIC, in order to enhance the resistance to noise in which the VB potential < the ground potential (GND potential), a side where a p-type slit is formed and a side where a p-type slit is not formed are provided, and a hole current is absorbed by the side where the p-type slit is not formed, thereby making it difficult for a current to flow into the high-side circuit. - type slit forming side and p - type slit not forming side are provided, and p - type slit not forming side absorbs hole current, thereby making it difficult for a current to flow into the high-side circuit.

[0004] Patent Document 3 discloses a configuration in which, in an HVIC, not only an n-type region but also a p-type region are formed in a contact region of the VB potential, and a hole current is absorbed by the n-type region and the p-type region, thereby making it difficult for a current to flow into the high-side circuit. + type region but also p + type region are formed, and n + type region and p + type region absorb hole current, thereby making it difficult for a current to flow into the high-side circuit.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0006] When operating the HVIC, it is used while maintaining the potential relationship of VB potential > VS potential ≥ GND potential. However, if this potential relationship is disrupted due to noise or the like, parasitic operation is induced, leading to malfunction or destruction. The techniques described in Patent Documents 1 to 3 may not be applicable depending on the target chip size and design concept, and in some cases, the noise tolerance may be insufficient when used alone. Therefore, noise countermeasures using different methods are always required.

[0007] In view of the above problems, an object of the present invention is to provide a semiconductor device capable of improving resistance to malfunction and destruction due to noise or the like.

Means for Solving the Problems

[0008] One aspect of the present invention includes a substrate of a first conductivity type, a first well region of a second conductivity type provided in the substrate and in which a high-side circuit is formed, a second well region of the first conductivity type provided above the first well region, a first breakdown voltage region of the second conductivity type provided around the first well region and having a lower impurity concentration than the first well region, a contact region of the second conductivity type provided above the first well region or the first breakdown voltage region and having a higher impurity concentration than the first well region, a slit region of the first conductivity type provided between the second well region above the first well region and the contact region and connected to the second well region via a resistor, a second breakdown voltage region of the first conductivity type provided in contact with the first breakdown voltage region on the outer peripheral side of the first breakdown voltage region, and a level shifter that performs signal transmission between a low-side circuit and a high-side circuit formed on the outer peripheral side of the second breakdown voltage region. The gist is that it is a semiconductor device comprising these components.

Effects of the Invention

[0009] According to the present invention, it is possible to provide a semiconductor device capable of improving resistance to malfunction and destruction due to noise or the like.

Brief Description of the Drawings

[0010]

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Embodiments for Carrying Out the Invention

[0011] Hereinafter, the first to fifth embodiments of the present invention will be described with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and redundant descriptions are omitted. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. may be different from the actual ones. Also, there may be portions where the dimensional relationships and ratios are different between the drawings. Further, the first to fifth embodiments shown below are examples of devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention does not specify the material, shape, structure, arrangement, etc. of the components as follows.

[0012] In this specification, the "carrier supply region" means a semiconductor region that supplies a large number of carriers constituting the main current, such as the source region of a field effect transistor (FET) or a static induction transistor (SIT), or the emitter region of an insulated gate bipolar transistor (IGBT). Also, in a diode, a static induction (SI) thyristor, or a gate turn-off (GTO) thyristor, the anode region serves as the carrier supply region. Further, the "carrier receiving region" means a semiconductor region that receives a large number of carriers constituting the main current, such as the drain region of an FET or an SIT, or the collector region of an IGBT. In a diode, an SI thyristor, or a GTO thyristor, the cathode region functions as the carrier receiving region.

[0013] In addition, in this specification, the definitions of directions such as up and down are merely for convenience of explanation and do not limit the technical idea of the present invention. For example, if the object is rotated by 90° and observed, up and down are read as left and right, and if it is rotated by 180° and observed, up and down are read in reverse, which goes without saying.

[0014] In addition, in this specification, the case where the first conductivity type is p-type and the second conductivity type is n-type will be exemplarily described. However, the conductivity types may be selected in the reverse relationship, with the first conductivity type being n-type and the second conductivity type being p-type. Also, the “+” and “-” attached to “n” and “p” mean semiconductor regions with relatively higher or lower impurity concentrations, respectively, compared to the semiconductor regions without the attached “+” and “-”. However, even for semiconductor regions with the same “n” attached, it does not mean that the impurity concentrations of the respective semiconductor regions are exactly the same. Furthermore, in the following description, members and regions with the limitation of “the first conductivity type” and “the second conductivity type” mean members and regions made of semiconductor materials even without specific explicit limitation.

[0015] (First Embodiment) <Circuit of Semiconductor Device> As a semiconductor device according to the first embodiment, as shown in FIG. 1, a high-voltage integrated circuit (HVIC) 100 is exemplified. The HVIC 100 drives, as a driving target, for example, a power conversion unit 200 which is one phase of a power conversion bridge circuit. The power conversion unit 200 constitutes a half-bridge circuit by connecting a high-potential side switching element T3 and a low-potential side switching element T4 in series. In FIG. 1, IGBTs are exemplified as the high-potential side switching element T3 and the low-potential side switching element T4, but other power switching elements such as metal-oxide-semiconductor field-effect transistors (MOSFETs) may be used.

[0016] The collector of the high-potential side switching element T3 is connected to the high-potential side HV potential. The emitter of the low-potential side switching element T4 is connected to the low-potential side ground potential (GND potential). The connection point (midpoint of the half-bridge circuit) 105 between the emitter of the high-potential side switching element T3 and the collector of the low-potential side switching element T4 is connected to the VS potential on the negative electrode side of the high-potential side power supply (high-potential side power supply) 104. Further, a load such as a motor (not shown) is connected to the connection point 105.

[0017] The HVIC100 applies a drive signal that turns on and off the gate of the high-potential side switching element T3 to the gate of the high-potential side switching element T3 in response to an input signal IN from an external microcomputer or the like. The HVIC100 includes a low-potential side circuit (low side circuit) 101 and a high-potential side circuit (high side circuit) 102. The low side circuit 101 is connected to the VCC potential on the positive electrode side of the low-potential side power supply (low-potential side power supply) 103 and the GND potential on the negative electrode side of the low-potential side power supply 103. Further, the gates of level shift elements (level shifters) T1, T2 are connected to the low side circuit 101.

[0018] The low side circuit 101 operates with the GND potential as the reference potential and the VCC potential higher than the GND potential as the power supply potential. The low side circuit 101 generates an on / off signal based on the GND potential in response to an input signal IN from an external microcomputer or the like and outputs it to the gates of the level shifters T1, T2.

[0019] The level shifters T1, T2 perform signal transmission between the low side circuit 101 and the high side circuit 102. The level shifters T1, T2 convert an on / off signal based on the GND potential from the low side circuit 101 into an on / off signal based on the VS potential and output the converted on / off signal to the high side circuit 102. The level shifters T1, T2 are composed of, for example, high breakdown voltage n-channel MOSFETs.

[0020] The source of level shifter T1 is connected to the GND potential. One end of the high-side circuit 102 and the level shift resistor R1 is connected to the drain of level shifter T1. The VB potential on the positive electrode side of the high potential side power supply 104 is connected to the other end of the level shift resistor R1. The cathode of diode D1 is connected to the drain of level shifter T1 and one end of the level shift resistor R1. The VS potential on the negative electrode side of the high-side circuit 102 and the high potential side power supply 104 is connected to the anode of diode D1. Diode D1 has a function of preventing an excessive drop in the drain potential of level shifter T1.

[0021] The source of level shifter T2 is connected to the GND potential. One end of the high-side circuit 102 and the level shift resistor R2 is connected to the drain of level shifter T2. The VB potential on the positive electrode side of the high potential side power supply 104 is connected to the other end of the level shift resistor R2. The cathode of diode D2 is connected to the drain of level shifter T2 and one end of the level shift resistor R2. The VS potential on the negative electrode side of the high-side circuit 102 and the high potential side power supply 104 is connected to the anode of diode D2. Diode D2 has a function of preventing an excessive drop in the drain potential of level shifter T2.

[0022] The cathode of a high-voltage diode D0 called a breakdown junction terminal (HVJT) is connected to the other ends of the level shift resistors R1 and R2 and the VB potential on the positive electrode side of the high potential side power supply 104. The GND potential is connected to the anode of diode D0.

[0023] The high-side circuit 102 operates with the VS potential as the reference potential and the VB potential higher than the VS potential as the power supply potential. The high-side circuit 102 outputs a drive signal based on the VS potential to the gate of the high potential side switching element T3 in response to the on / off signals from the level shifters T1 and T2, and drives the gate of the high potential side switching element T3. The high-side circuit 102 includes, for example, a CMOS circuit of an n-channel MOSFET and a p-channel MOSFET in the output stage.

[0024] The VB potential is the highest potential applied to the HVIC100 and is maintained about 15V higher than the VS potential in the normal state without being affected by noise. The VS potential repeatedly rises and falls between the HV potential (e.g., about 400V to 600V) on the high potential side and the GND potential on the low potential side as the high potential side switching element T3 and the low potential side switching element T4 are complementarily turned on and off, and varies between 0V and several hundred volts. Note that the VS potential may be a negative potential.

[0025] <Structure of semiconductor device> FIG. 2 shows a planar layout of a semiconductor device according to a first embodiment corresponding to the HVIC100 shown in FIG. 1. The HVIC100 includes a substrate (semiconductor chip) 1 of a first conductivity type (p - -type). The substrate 1 is composed of, for example, a silicon (Si) substrate. Note that the substrate 1 may be composed of a semiconductor substrate such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), gallium arsenide (GaAs), diamond (C), etc. The substrate 1 may be composed of a semiconductor substrate of the p - -type or the like and a p - -type epitaxial layer provided on the semiconductor substrate. The lower surface of the substrate 1 may be fixed at the GND potential.

[0026] On the upper part of the substrate 1, a well region (first well region) 2 of a second conductivity type (n-type) is provided. The well region 2 has a substantially rectangular planar pattern. A high side circuit (high side circuit region) 102 is formed in the well region 2. In FIG. 2, illustration of various elements included in the high side circuit 102 is omitted.

[0027] On the upper part of the well region 2, a second conductivity type (n +A pickup area (contact area) 2a of type ) is provided. In FIG. 2, the case where the contact area 2a is provided annularly along the outer periphery of the well area 2 is illustrated. The contact area 2a does not necessarily have to be annular. For example, one or a plurality of contact areas may be provided partially. Instead of providing the contact area 2a at the upper part of the well area 2, it may be provided at the upper part of the portion of the pressure-resistant area (first pressure-resistant area) 8 of type n - - in contact with the well area 2. The VB potential, which is the power supply potential of the high-side circuit 102, is applied to the well area 2 via the contact area 2a.

[0028] A p-type well area (second well area) 7 is provided at the upper part of the well area 2. The well area 7 has a substantially rectangular planar pattern. In the plan view of FIG. 2, the case where it is provided at the lower left side of the well area 2 is illustrated, but the arrangement position of the well area 7 is not particularly limited as long as it is inside the well area 2. The size of the well area 7 is not particularly limited. A plurality of well areas 7 may be provided at the upper part of the well area 2. The VS potential, which is the reference potential of the high-side circuit 102, is applied to the well area 7.

[0029] A p-type slit area 6 is provided between the contact area 2a at the upper part of the well area 2 and the well area 7. In the plan view of FIG. 2, the slit area 6 has a substantially L-shaped planar pattern. The slit area 6 is provided partially between the two sides closer to the contact area 2a of the well area 7 and the contact area 2a. By providing the slit area 6 partially, the area required to provide the slit area 6 can be reduced as compared with the case where the slit area 6 is provided annularly. The distance between the slit area 6 and the well area 7, the distance between the slit area 6 and the contact area 2a, and the width of the slit area 6 can be adjusted as appropriate.

[0030] Note that the slit region 6 may be provided with a planar pattern that is substantially linear (strip-shaped) partially between one side closest to the contact region 2a of the well region 7 and the contact region 2a. The slit region 6 may be provided in an annular shape so as to surround the well region 7 and the high-side circuit 102. When there are a plurality of well regions 7, one or a plurality of p-type slit regions 6 may be provided between the plurality of well regions 7 and the contact region 2a.

[0031] The slit region 6 is connected to the well region 7 via the resistor R11. The VS potential, which is the reference potential of the high-side circuit 102, is applied to the slit region 6 via the resistor R11. The resistance value of the resistor R11 is, for example, about 10 Ω or more and 1 kΩ or less, but is not limited thereto. The resistor R11 is, for example, composed of a polysilicon resistor. The resistor R11 may be a diffusion resistor.

[0032] An n-type breakdown voltage region 8 having a lower impurity concentration than the well region 2 is provided in contact with the well region 2 so as to surround the periphery of the well region 2. - The breakdown voltage region 8 is annular and has a planar pattern with a substantially rectangular outer shape. A p-type breakdown voltage region (second breakdown voltage region) 3 is provided at a predetermined distance from the well region 2. The breakdown voltage region 3 is annular and has a planar pattern with a substantially rectangular outer shape. The GND potential is applied to the breakdown voltage region 3. The outer periphery of the breakdown voltage region 3 is surrounded by the substrate 1.

[0033] A high-voltage junction termination (HVJT) (3, 8) is formed by the pn junction of the breakdown voltage region 8 and the breakdown voltage region 3. The HVJT (3, 8) corresponds to the high-voltage diode D0 shown in FIG. 1. The HVJT (3, 8) is substantially annular and has a planar pattern with a substantially rectangular outer shape. The HVJT (3, 8) electrically separates the well region 2 on the inner peripheral side of the breakdown voltage region 8 from the low-side circuit (low-side circuit region) 101 formed in the substrate 1 on the outer peripheral side of the breakdown voltage region 8. Even when the potential of the high-side circuit 102 becomes several hundreds of volts higher than the potential of the low-side circuit 101 due to the HVJT (3, 8), it is designed to operate normally.

[0034] n - In a part of the HVJT(3,8) composed of an n-type high-voltage region 8 and a p-type high-voltage region 3, level shifters 10a and 10b are integrally formed. The level shifters 10a and 10b are composed of high-voltage n-channel MOSFETs. The level shifters 10a and 10b correspond to the level shifters T1 and T2 shown in FIG. 1.

[0035] Here, the formation methods of the MOSFETs constituting the level shifters T1 and T2 shown in FIG. 1 are roughly classified into two types. One is called the wire bonding method (WB method), and the other is called the self-sealing method (SS method). The WB method forms a MOSFET separately from the HVJT(3,8) and connects the drain potential (Dr potential) of the MOSFET to the high-side circuit 102 with a bonding wire. The SS method is a method of integrally forming a MOSFET in the HVJT(3,8). In the semiconductor device according to the first embodiment, the case where the level shifters 10a and 10b are formed by the SS method is exemplified.

[0036] The level shifters 10a and 10b are respectively provided on opposite sides of the rectangle formed by the planar pattern of the HVJT(3,8). The planar patterns of the well region 2 and the contact region 2a have recesses that are recessed inward so as to surround a part of the level shifters 10a and 10b. Note that the positions of the level shifters 10a and 10b are not particularly limited. For example, both of the level shifters 10a and 10b may be provided on one side of the rectangle formed by the planar pattern of the HVJT(3,8). The level shifters 10a and 10b are electrically separated from the well region 2 by p - type isolation regions 5a and 5b. The isolation regions 5a and 5b have a U-shaped planar pattern so as to surround the periphery of the level shifters 10a and 10b.

[0037] The level shifter 10a faces the well region 7 with the isolation region 5a, the contact region 2a, and the slit region 6 in between. The level shifter 10a has an n + type carrier supply region (source region) 11a, a gate electrode 12a, and an n +It includes a carrier receiving region (drain region) 13a of the p-type. The source region 11a, the gate electrode 12a, and the drain region 13a have linear planar patterns extending parallel to each other. A part of the breakdown voltage region 8 sandwiched between the source region 11a and the drain region 13a constitutes the drift region 14a of the level shifter 10a. A GND potential is applied to the source region 11a as the source potential (So potential). A drain potential (Dr potential) is applied to the drain region 13a.

[0038] The level shifter 10b has the same configuration as the level shifter 10a. That is, the level shifter 10b includes an n + -type source region 11b, a gate electrode 12b, and an n + -type drain region 13b. The source region 11b, the gate electrode 12b, and the drain region 13b have linear planar patterns extending parallel to each other. A part of the breakdown voltage region 8 sandwiched between the source region 11b and the drain region 13b constitutes the drift region 14b of the level shifter 10b. A GND potential is applied to the source region 11b as the source potential (So potential). A drain potential (Dr potential) is applied to the drain region 13b.

[0039] Fig. 3 shows a cross-section taken along the line A-A' passing through the level shifter 10a, the separation region 5a, the slit region 6, and the well region 7 in Fig. 2. As shown from the center to the right side of Fig. 3, on the upper part of the p - -type substrate 1, an n-type well region 2 is provided. On the upper part of the well region 2, an n + -type pickup region (contact region) 2a with a higher impurity concentration than the well region 2 is provided. A VB potential is applied to the contact region 2a.

[0040] On the upper part of the well region 2, a p-type well region 7 is provided at a distance from the contact region 2a. On the upper part of the well region 7, a p +A pick-up region (contact region) 7a of a certain type is provided. A VS potential is applied to the contact region 7a. In FIG. 2, the illustration of the contact region 7a shown in FIG. 3 is omitted. The planar pattern shape of the contact region 7a is not particularly limited.

[0041] A p-type slit region 6 is provided between the contact region 2a above the well region 2 and the well region 7. The slit region 6 can be formed, for example, in the same process as the well region 7. By forming the slit region 6 in the same process as the well region 7, an increase in the man-hour for forming the slit region 6 can be suppressed. The depth of the slit region 6 is substantially the same as the depth of the well region 7. The impurity concentration of the slit region 6 is substantially the same as the impurity concentration of the well region 7 and is higher than the impurity concentration of the substrate 1.

[0042] The slit region 6 may be formed in a process different from that of the well region 7. When the slit region 6 is formed in a process different from that of the well region 7, the depth of the slit region 6 may be substantially the same as the depth of the well region 7, may be deeper than the depth of the well region 7, or may be shallower than the depth of the well region 7. When the slit region 6 is formed in a process different from that of the well region 7, the impurity concentration of the slit region 6 may be substantially the same as the impurity concentration of the well region 7, may be higher than the impurity concentration of the well region 7, or may be lower than the impurity concentration of the well region 7.

[0043] By increasing the depth of the slit region 6, the well region 2, which is the main noise current path, can be narrowed, so that the noise resistance can be improved. When there is no buried layer 13 below the slit region 6, the breakdown voltage decreases when the depletion layer extending from the interface between the n-type well region 7 and the p - type substrate 1 reaches the bottom surface of the slit region 6. Therefore, the depth of the slit region 6 is adjusted so that the depletion layer does not reach the bottom surface of the slit region 6. On the other hand, when there is a buried layer 13 below the slit region 6, since the depletion layer hardly extends toward the buried layer 13 side, the deeper the depth of the slit region 6, the more preferable.

[0044] As described below, the slit region 6 may function as a noise current source (see FIGS. 8 and 10) or as a noise current absorption destination (see FIG. 12). When the slit region 6 functions as a noise current source, the noise tolerance can be improved by reducing the impurity concentration of the slit region 6. On the other hand, when the slit region 6 functions as a noise current absorption destination, the noise tolerance can be improved by increasing the impurity concentration of the slit region 6.

[0045] Above the slit region 6, a p-type pickup region (contact region) 6a with an impurity concentration higher than that of the slit region 6 is provided. The contact region 7a is connected to the contact region 6a via a resistor R11. The contact region 6a may be connected to the VS potential via the resistor R11 without passing through the contact region 7a. In FIG. 2, the illustration of the contact region 6a shown in FIG. 3 is omitted. The planar pattern shape of the contact region 6a is not particularly limited. The resistor R11 is formed of, for example, a polysilicon resistor. The resistor R11 may be formed of a diffusion resistor. + Above the slit region 6, a p-type pickup region (contact region) 6a with an impurity concentration higher than that of the slit region 6 is provided. The contact region 7a is connected to the contact region 6a via a resistor R11. The contact region 6a may be connected to the VS potential via the resistor R11 without passing through the contact region 7a. In FIG. 2, the illustration of the contact region 6a shown in FIG. 3 is omitted. The planar pattern shape of the contact region 6a is not particularly limited. The resistor R11 is formed of, for example, a polysilicon resistor. The resistor R11 may be formed of a diffusion resistor.

[0046] FIG. 4 shows a cross section of a region including the polysilicon resistor 35 when the resistor R11 shown in FIG. 3 is the polysilicon resistor 35. An insulating film 31 is provided on the upper surfaces of the well region 2, the slit region 6, and the well region 7. A polysilicon resistor 35 is provided on the upper surface of the insulating film 31. The polysilicon resistor 35 is composed of polysilicon doped with a high concentration of p-type or n-type impurities. An insulating film 32 is provided so as to cover the upper surface of the insulating film 31, the upper surface, and the side surfaces of the polysilicon resistor 35. Metal wiring layers 33 and 34 are provided on the upper surface of the insulating film 32. The metal wiring layer 33 connects the contact region 7a and one end of the polysilicon resistor 35 through openings (contact holes) provided in the insulating films 31 and 32. The metal wiring layer 34 connects the contact region 6a and the other end of the polysilicon resistor 35 through openings (contact holes) provided in the insulating films 31 and 32.

[0047] As shown in FIG. 3, below the well region 2, in contact with the lower surface of the well region 2, an n-implanted layer 13 with a higher impurity concentration than that of the well region 2 is provided. + The implanted layer 13 is uniformly provided in the horizontal direction along between the substrate 1 and the well region 2. The implanted layer 13 has a function of reducing the amplification factor of a pnp bipolar transistor formed by the p-type well region 7, the n-type well region 2, and the p-type substrate 1, and reducing the generated current amount. In FIG. 3, a case where the slit region 6 is provided at a position overlapping with the end of the implanted layer 13 in the depth direction and above the implanted layer 13 is illustrated. The slit region 6 may be provided at a position inside (on the well region 7 side) of the end of the implanted layer 13 and above the implanted layer 13, or may be provided at a position outside (on the contact region 2a side) of the end of the implanted layer 13 and at a position where there is no implanted layer 13 below. - By providing the slit region 6 at a position overlapping with the end of the implanted layer 13 or at a position inside the end of the implanted layer 13, since the slit region 6 is located above the implanted layer 13, compared with the case where there is no implanted layer 13 below the slit region 6, the well region 2 that becomes the main noise current path can be further narrowed by the slit region 6 and the implanted layer 13, and the noise resistance can be further improved.

[0048]

[0049] On the outer peripheral side of the well region 2 at the upper part of the substrate 1, an n-type breakdown voltage region 8 is selectively provided in contact with the well region 2. The depth of the breakdown voltage region 8 is shallower than the depth of the well region 2. On the upper part of the substrate 1, a p-type isolation region 5a is provided so as to penetrate the breakdown voltage region 8 in the depth direction. The depth of the isolation region 5a is deeper than the depth of the breakdown voltage region 8. The impurity concentration of the isolation region 5a is lower than the impurity concentration of the substrate 1. - -

[0050] The level shifter 10a is electrically separated from the well region 2 by the isolation region 5a. A part of the breakdown voltage region 8 surrounded by the isolation region 5a is the n- of the level shifter 10a. - ​​​functions as a drift region 14a of the type. On the upper part of the drift region 14a, n + type drain region 13a is provided. The breakdown voltage region 3 in contact with the drift region 14a functions as the p-type base region of the level shifter 10a. On the upper part of the breakdown voltage region 3, n + type source region 11a and p + type contact region 4 are provided. Above the breakdown voltage region 3 sandwiched between the source region 11a and the drift region 14a, a gate electrode 12a is provided via a gate insulating film (not shown). The cross-sectional structure of the level shifter 10b shown in FIG. 2 is the same as the cross-sectional structure of the level shifter 10a shown in FIG. 3.

[0051] FIG. 5 shows a cross-section cut along the B-B' line orthogonal to the A-A' line in FIG. 2. On the upper part of the p - type substrate 1, an n-type well region 2 is provided. On the upper part of the well region 2, an n-type contact region 2a with a higher impurity concentration than the well region 2 is provided. A VB potential is applied to the contact region 2a. + type contact region 2a is provided. A VB potential is applied to the contact region 2a.

[0052] On the upper part of the well region 2, a p-type well region 7 is provided at a distance from the contact region 2a. On the upper part of the well region 7, a p + type contact region 7a with a higher impurity concentration than the well region 7 is provided. A VS potential is applied to the contact region 7a.

[0053] Between the contact region 2a on the upper part of the well region 2 and the well region 7, a p-type slit region 6 is provided. On the upper part of the slit region 6, a p + type contact region 6a with a higher impurity concentration than the slit region 6 is provided. The contact region 7a is connected to the contact region 6a via a resistor R11.

[0054] On the upper part of the substrate 1, in contact with the well region 2, n -A pressure-resistant region 8 of a certain type is selectively provided. On the upper part of the substrate 1, on the opposite side of the well region 2 and in contact with the pressure-resistant region 8, a p-type pressure-resistant region 3 is provided. On the upper part of the pressure-resistant region 3, a p + -type contact region 4 is provided. A GND potential is applied to the contact region 4. The breakdown voltage is maintained by mainly expanding the depletion layer spreading from the pn junction between the pressure-resistant region 8 and the pressure-resistant region 3 to the pressure-resistant region 8 side.

[0055] Next, the operation and effects of the semiconductor device according to the first embodiment will be described in comparison with the semiconductor device according to the comparative example. FIG. 6 shows a plan layout of the semiconductor device according to the comparative example. As shown in FIG. 6, the semiconductor device according to the comparative example is different from the semiconductor device according to the first embodiment shown in FIG. 2 in that it does not have a p-type slit region 6 between the n + -type contact region 2a and the p-type well region 7, and a resistor R11 connecting the slit region 6 and the well region 7.

[0056] When operating the HVIC, it is used while maintaining the potential relationship that the VB potential is greater than the VS potential and the VS potential is equal to or greater than the GND potential (VB potential > VS potential ≥ GND potential). However, if this potential relationship is disrupted due to noise or the like, parasitic operation is induced, which may cause malfunction or destruction. Hereinafter, three patterns will be described when the potential relationships are such that the VS potential is greater than the VB potential, the VB potential is much greater than the GND potential (VS potential > VB potential ≫ GND potential), the VB potential is less than the VS potential (VB potential < VS potential), and the VB potential is less than the GND potential (VB potential < GND potential).

[0057] <Regarding VS potential > VB potential ≫ GND potential> FIG. 7 is a cross-sectional view of the semiconductor device according to the comparative example cut along the line A-A' in FIG. 6, and schematically shows with arrows the parasitic current I11 generated when the potential relationship is VS potential > VB potential ≫ GND potential. As shown in FIG. 7, in the semiconductor device according to the comparative example, when the potential relationship becomes VS potential > VB potential ≫ GND potential, for example, due to the VS potential rising steeply due to noise or the like, p -A parasitic pnp bipolar transistor T11 formed by a substrate 1 of a certain type, an n-type well region 2, and a p-type well region 7 operates under a high voltage applied, and a large parasitic current I11 may flow from the well region 7 toward the contact region 4 and the source region 11a, inducing destruction due to heat generation.

[0058] In contrast, FIG. 8 is a cross-sectional view of a semiconductor device according to the first embodiment cut along the line A-A' of FIG. 2, and schematically shows parasitic currents I12 and I13 generated when the potential relationship is VS potential > VB potential ≫ GND potential with arrows. As shown in FIG. 8, in the semiconductor device according to the first embodiment, when the potential relationship is VS potential > VB potential ≫ GND potential, parasitic currents I12 and I13 flow from the slit region 6 and the well region 7 connected to the VS potential toward the contact region 4 and the source region 11a. At this time, the parasitic current I12 from the slit region 6 has its current limited by the connected resistor R11, and the parasitic current I13 from the well region 7 has its current limited by the diffusion resistor R12 with increased resistance due to the slit region 6, so destruction can be suppressed.

[0059] <Regarding VB potential < VS potential> FIG. 9 is a cross-sectional view of a semiconductor device according to a comparative example cut along the line A-A' of FIG. 6, and schematically shows a parasitic current I14 generated when the potential relationship is VB potential < VS potential with an arrow. As shown in FIG. 9, in the semiconductor device according to the comparative example, for example, when the VS potential rises steeply due to noise or the like, when the potential relationship is VB potential < VS potential, a parasitic current I14, which is a forward current, flows through the parasitic diode D11 formed by the p-type well region 7 and the n-type well region 2 and flows toward the contact region 2a. Therefore, carriers accumulate near the p - type isolation region 5a where electrical isolation is performed, resulting in a decrease in the isolation function and possibly inducing malfunction.

[0060] In contrast, FIG. 10 is a cross-sectional view of the semiconductor device according to the first embodiment cut along line A-A' of FIG. 2, and schematically shows the parasitic currents I15 and I16 generated when the VB potential < the VS potential in an arrow manner. As shown in FIG. 10, in the semiconductor device according to the first embodiment, when the potential relationship of VB potential < VS potential is established, a parasitic current I15, which is a forward current, flows through the parasitic diode D12 formed by the p-type slit region 6 and the n-type well region 2, and a parasitic current I16, which is a forward current, flows through the parasitic diode D13 formed by the p-type well region 7 and the n-type well region 2. The parasitic currents I15 and I16 flow from the slit region 6 and the well region 7 connected to the VS potential toward the contact region 2a of the outermost VB potential. At this time, the parasitic current I15 from the slit region 6 has its current limited by the connected resistor R11, and the parasitic current I16 from the well region 7 has its current limited by the diffusion resistor R13 with increased resistance due to the slit region 6. Therefore, the carriers accumulating around the contact region 2a of the outermost VB potential are reduced, and malfunction can be suppressed.

[0061] <Regarding the VB potential < GND potential> FIG. 11 is a cross-sectional view of the semiconductor device according to the comparative example cut along line B-B' of FIG. 6, and schematically shows the parasitic currents I17 and I18 generated when the VB potential < the GND potential in an arrow manner. As shown in FIG. 11, in the semiconductor device according to the comparative example, for example, when the VB potential becomes lower than that during normal operation due to noise or the like, when the potential relationship of VB potential < GND potential is established, a parasitic current I17 and I18, which are forward currents, flow through the parasitic diode D14 formed by the p-type breakdown voltage region 3 and the - n-type breakdown voltage region 8. A part of the parasitic currents I17 and I18, that is, the parasitic current I17, flows toward the contact region 2a, but when a part of the parasitic currents I17 and I18, that is, the parasitic current I18, reaches the high-side circuit 102, the logic circuit may malfunction.

[0062] In contrast, FIG. 12 is a cross-sectional view of a semiconductor device according to the first embodiment taken along line B-B' of FIG. 2, and schematically shows parasitic currents I19, I20, and I21 generated when the VB potential < the GND potential with arrowheads. As shown in FIG. 12, in the semiconductor device according to the first embodiment, when the potential relationship is VB potential < GND potential, a part of the parasitic currents I19, I20, and I21 flowing in from the contact region 4 of the GND potential, the parasitic current I19, flows toward the contact region 2a, and a part of the parasitic currents I19, I20, and I21, the parasitic current I20, flows toward the slit region 6. A part of the parasitic currents I19, I20, and I21, the parasitic current I21, also tries to flow into the high-side circuit 102, but since most of the carriers are absorbed in the slit region 6 and the inflow into the high-side circuit 102 is suppressed, malfunction can be suppressed.

[0063] As described above, according to the semiconductor device according to the first embodiment, by providing a p-type slit region 6 connected to the VS potential via a resistor R11 between the well region 7 connected to the VS potential and the contact region 2a of the VB potential, it is possible to improve the resistance to malfunction and destruction when falling into a potential relationship different from the normal operation such as VS potential > VB potential >> GND potential, VB potential < VS potential, VB potential < GND potential, etc. due to noise or the like.

[0064] (Second Embodiment) FIG. 13 is a cross-sectional view of a semiconductor device according to the second embodiment, corresponding to the position of the cross-sectional view of the semiconductor device according to the first embodiment shown in FIG. 3. FIG. 14 is a cross-sectional view of a semiconductor device according to the second embodiment, corresponding to the position of the cross-sectional view of the semiconductor device according to the first embodiment shown in FIG. 5.

[0065] As shown in FIGS. 13 and 14, the semiconductor device according to the second embodiment is different from the semiconductor device according to the first embodiment shown in FIGS. 3 and 5 in that an n + type buried layer 13 is not provided below the n-type well region 2. The lower surface of the well region 2 is p -It is in contact with the substrate 1 of the type. Since other configurations of the semiconductor device according to the second embodiment are the same as those of the semiconductor device according to the first embodiment, duplicate explanations are omitted.

[0066] According to the semiconductor device according to the second embodiment, similar to the semiconductor device according to the first embodiment, between the well region 7 connected to the VS potential and the contact region 2a of the VB potential, a p-type slit region 6 connected to the VS potential via a resistor R11 is provided. By doing so, it is possible to improve the resistance to malfunction and destruction when falling into a potential relationship different from the normal operation such as VS potential > VB potential >> GND potential, VB potential < VS potential, VB potential < GND potential, etc. due to noise or the like.

[0067] (Third Embodiment) FIG. 15 is a plan view of a semiconductor device according to the third embodiment. As shown in FIG. 15, the semiconductor device according to the third embodiment is different from the semiconductor device according to the first embodiment shown in FIG. 2 in that a p-type slit region 6 between the n-type contact region 2a and the p-type well region 7 is provided in an annular shape. The slit region 6 is provided so as to surround the well region 7 and the high-side circuit 102. Since other configurations of the semiconductor device according to the third embodiment are the same as those of the semiconductor device according to the first embodiment, duplicate explanations are omitted. + According to the semiconductor device according to the third embodiment, similar to the semiconductor device according to the first embodiment, between the well region 7 connected to the VS potential and the contact region 2a of the VB potential, a p-type slit region 6 connected to the VS potential via a resistor R11 is provided. By doing so, it is possible to improve the resistance to malfunction and destruction when falling into a potential relationship different from the normal operation such as VS potential > VB potential >> GND potential, VB potential < VS potential, VB potential < GND potential, etc. due to noise or the like. Furthermore, according to the semiconductor device according to the third embodiment, by providing the slit region 6 in an annular shape, it is possible to more reliably suppress malfunctions and destruction when falling into a potential relationship different from the normal operation as compared with the case where the slit region 6 is provided partially.

[0068]

[0069] ​(Fourth Embodiment) FIG. 16 is a cross-sectional view of a semiconductor device according to the fourth embodiment, corresponding to the position of the cross-sectional view of the semiconductor device according to the first embodiment shown in FIG. 3. FIG. 17 is a cross-sectional view of a semiconductor device according to the second embodiment, corresponding to the position of the cross-sectional view of the semiconductor device according to the first embodiment shown in FIG. 5.

[0070] As shown in FIGS. 16 and 17, in the semiconductor device according to the fourth embodiment, the substrate 1 is different from the semiconductor device according to the first embodiment shown in FIGS. 3 and 5 in that the substrate 1 is composed of a p - -type semiconductor substrate 1a and a p - -type epitaxial layer 1b provided on the semiconductor substrate 1a. Other configurations of the semiconductor device according to the fourth embodiment are the same as those of the semiconductor device according to the first embodiment, so redundant descriptions are omitted.

[0071] According to the semiconductor device according to the fourth embodiment, similar to the semiconductor device according to the first embodiment, a p-type slit region 6 connected to the VS potential via a resistor R11 is provided between the well region 7 connected to the VS potential and the contact region 2a of the VB potential, so that when the potential relationship is different from the normal operation such as VS potential > VB potential ≫ GND potential, VB potential < VS potential, VB potential < GND potential, etc. due to noise or the like, the tolerance to malfunction and breakdown can be improved.

[0072] (Fifth Embodiment) FIG. 18 is a plan view of a semiconductor device according to the fifth embodiment. As shown in FIG. 18, the semiconductor device according to the fifth embodiment is different from the semiconductor device according to the first embodiment shown in FIG. 2 in that level shifters 20a and 20b are formed by the WB method. The level shifters 20a and 20b are provided outside the p-type breakdown voltage region 3. The level shifters 20a and 20b have a substantially circular planar pattern. The level shifters 20a and 20b are composed of high-voltage n-channel MOSFETs.

[0073] The level shifter 20a includes an n + -type carrier supply region (source region) 22a, a gate electrode 23a, an n -The drift region 24a of the type and n + type carrier receiving region (drain region) 25a. The source region 22a has an annular planar pattern. The drift region 24a is provided on the inner peripheral side of the source region 22a and has an annular planar pattern. The gate electrode 23a is provided via a gate insulating film (not shown) above an annular p-type base region (not shown) sandwiched between the source region 22a and the drift region 24a. The drain region 25a is provided above the drift region 24a and has a circular planar pattern.

[0074] Above the drain region 25a, a drain electrode 26a is provided. To the drain electrode 26a, a pad 18a is connected via a bonding wire 17a. On the outer peripheral side of the source region 22a, p + type base region 21a is provided. The base region 21a has an annular planar pattern.

[0075] The level shifter 20b has the same configuration as the level shifter 20a. The level shifter 20b has an n + type source region 22b, gate electrode 23b, n - type drift region 24b and n + type drain region 25b. The source region 22b has an annular planar pattern. The drift region 24b is provided on the inner peripheral side of the source region 22b and has an annular planar pattern. The gate electrode 23b is provided via a gate insulating film (not shown) above an annular p-type base region (not shown) sandwiched between the source region 22b and the drift region 24b. The drain region 25b is provided above the drift region 24b and has a circular planar pattern.

[0076] Above the drain region 25b, a drain electrode 26b is provided. To the drain electrode 26b, a pad 18b is connected via a bonding wire 17b. On the outer peripheral side of the source region 22b, p +A base region 21b of a type is provided. The base region 21b has an annular planar pattern. Since other configurations of the semiconductor device according to the fifth embodiment are the same as those of the semiconductor device according to the first embodiment, duplicate descriptions are omitted.

[0077] According to the semiconductor device according to the fifth embodiment, similar to the semiconductor device according to the first embodiment, by providing a p-type slit region 6 connected to the VS potential via a resistor R11 between the well region 7 connected to the VS potential and the contact region 2a of the VB potential, when falling into a potential relationship different from the normal operation such as VS potential > VB potential >> GND potential, VB potential < GND potential, etc. due to noise or the like, the resistance to malfunction and destruction can be improved. In the semiconductor device according to the fifth embodiment, since the level shifters 20a and 20b are formed by the WB method, the malfunction in the case of the potential relationship of VB potential < VS potential in the SS method does not become a problem.

[0078] (Other Embodiments) As described above, although the present invention has been described by the first to fifth embodiments, it should not be understood that the discussions and drawings forming a part of this disclosure limit the present invention. Various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art from this disclosure.

[0079] For example, although a configuration having a one-phase high-side circuit 102 is exemplified as the semiconductor device according to the first to fifth embodiments, it is not limited thereto, and for example, a configuration having a three-phase high-side circuit may be used. In the case of a configuration having a three-phase high-side circuit, in each of the three-phase high-side circuits, a p-type slit region connected to the VS potential via a resistor may be provided between the p-type well region connected to the VS potential and the p + type contact region of the VB potential.

[0080] Moreover, the configurations disclosed in the first to fifth embodiments can be appropriately combined within a range where no contradiction occurs. Thus, the present invention naturally includes various embodiments and the like not described herein. Therefore, the technical scope of the present invention is defined only by the invention-specific matters according to the legitimate claims from the above description.

Explanation of Reference Numerals

[0081] 1…Substrate (semiconductor chip) 1a…Semiconductor substrate 1b…Epitaxial layer 2…Well region 2a…Contact region 3…Breakdown voltage region 5a…Isolation region 6…Slit region 6a…Contact region 7…Well region 7a…Contact region 8…Breakdown voltage region 10a,10b…Level shifter 11a,11b…Source region 12a,12b…Gate electrode 13…Embedded layer 13a,13b…Drain region 14a,14b…Drift region 17a,17b…Bonding wire 18a,18b…Pad 20a,20b…Level shifter 21a,21b…Base region 22a,22b…Source region 23a,23b…Gate electrode 24a,24b…Drift region 25a,25b…Drain region 26a,26b…Drain electrode 31,32…Insulating film 33,34…Metal wiring layer 35…Polysilicon resistor 101…Low-side circuit 102…High-side circuit 103…Low-potential side power supply 104…High-potential side power supply 105…Connection point 100…High-voltage integrated circuit (HVIC) 200…Power conversion unit D0, D1, D2…Diodes D11~D14…Parasitic diodes I11~I21…Parasitic currents R1, R2…Level-shifting resistors R11…Resistor R12, R13…Diffusion resistors T1, T2…Level shifters T11…Parasitic pnp bipolar transistor T3…High-potential side switching element T4…Low-potential side switching element

Claims

1. A substrate of a first conductivity type, a first well region of a second conductivity type provided on the substrate and in which a high-side circuit is formed, a second well region of the first conductivity type provided above the first well region, a first breakdown voltage region of the second conductivity type provided around the first well region and having a lower impurity concentration than the first well region, a contact region of the second conductivity type provided above the first well region or the first breakdown voltage region and having a higher impurity concentration than the first well region, a slit region of the first conductivity type provided between the second well region above the first well region and the contact region and connected to the second well region via a resistor, a second breakdown voltage region of the first conductivity type provided in contact with the first breakdown voltage region on the outer peripheral side of the first breakdown voltage region, a level shifter that performs signal transmission between a low-side circuit formed on the outer peripheral side of the second breakdown voltage region and the high-side circuit, A semiconductor device comprising the above.

2. The semiconductor device according to claim 1, wherein the level shifter is provided in part of the first breakdown voltage region and the second breakdown voltage region. The semiconductor device according to claim 1.

3. The semiconductor device according to claim 2, further comprising a separation region of the first conductivity type that separates the level shifter and the first well region. The semiconductor device according to claim 2.

4. The semiconductor device according to claim 2 or 3, wherein the slit region is provided between the level shifter and the second well region. The semiconductor device according to claim 2 or 3.

5. A carrier receiving region of the level shifter is provided above the first breakdown voltage region, A carrier supply region of the level shifter is provided above the second breakdown voltage region. The semiconductor device according to claim 2 or 3.

6. The semiconductor device according to claim 1, wherein the level shifter is provided on the outer peripheral side of the second breakdown voltage region. The semiconductor device according to claim 1.

7. The semiconductor device according to claim 1 or 2, further comprising an embedded layer of the second conductivity type provided below the first well region and having a higher impurity concentration than the first well region. The semiconductor device according to claim 1 or 2.

8. The semiconductor device according to claim 7, wherein the slit region is provided at a position overlapping with an end portion of the embedded layer. The semiconductor device according to claim 7.

9. The semiconductor device according to claim 1 or 2, wherein the slit region is selectively provided between the second well region and the contact region. The semiconductor device according to claim 1 or 2.

10. The semiconductor device according to claim 1 or 2, wherein the slit region is provided in an annular shape so as to surround the second well region and the high-side circuit. The semiconductor device according to claim 1 or 2.

11. The depth of the slit region is the same as the depth of the second well region The semiconductor device according to claim 1 or 2

12. The impurity concentration of the slit region is the same as the impurity concentration of the second well region The semiconductor device according to claim 1 or 2

13. The resistor is a polysilicon resistor The semiconductor device according to claim 1 or 2

14. A first potential is applied to the contact region, A second potential lower than the first potential is applied to the second well region, The second potential is applied to the slit region via the resistor The semiconductor device according to claim 1 or 2

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