Semiconductor device

Abstract

To increase the time that can be allocated to a main process.SOLUTION: An interrupt reception unit 111 receives an interrupt request. In response to a received interrupt request, an interrupt processing unit 114 performs an interrupt process of a first priority or an interrupt process of a second priority having a lower priority than the first priority. An interrupt suppression control unit 112 controls the number of interrupt processes of the second priority processed by the interrupt processing unit in a cycle time according to a suppression condition. The suppression condition is set on the basis of a cycle in which the interrupt process of the second priority occurs and the total number of the interrupt processes of the second priority occurring within a period corresponding to the cycle.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, for example, a semiconductor device having a processor that performs interrupt processing.

Background Art

[0002] As related art, Patent Document 1 discloses a data processing system excellent in the immediacy of interrupt processing. The data processing system described in Patent Document 1 includes a plurality of central processing units, a plurality of interrupt controllers separately assigned to the central processing units, and a circuit module that can be commonly used by the plurality of central processing units. Separate interrupt request signals are supplied from the circuit module to the plurality of interrupt controllers. The plurality of interrupt controllers notify the corresponding central processing units of an interrupt in response to the input interrupt request signals.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In recent years, in-vehicle MCUs (Micro Controller Units) or SoCs (System on a Chips) have seen an increase in the number of asynchronous communications in order to exchange information with a large number of ECUs (Electronic Control Units). In in-vehicle MCUs, as the number of asynchronous communications increases, the number of interrupt processes in the asynchronous communication system also increases. Processors such as CPUs (Central Processing Units) mounted on in-vehicle MCUs perform application processing and the processing of information in asynchronous communications. In the CPU, the more the number of asynchronous interrupt processes increases, the shorter the time allocated for application processing becomes. In response to such problems, a mechanism that can ensure the time allocated for application processing is desired even when the number of asynchronous communications increases.

[0005] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] According to one embodiment, a semiconductor device is provided. In the semiconductor device, an interrupt processing unit performs interrupt processing with a first priority or interrupt processing with a second priority lower than the first priority in response to an interrupt request. An interrupt suppression control unit controls the number of interrupt processes with the second priority processed by the interrupt processing unit in a cycle time according to a suppression condition. The suppression condition is set based on the cycle in which the interrupt process with the second priority occurs and the total number of interrupt processes with the second priority occurring within the period corresponding to the cycle.

Effects of the Invention

[0007] According to the above embodiment, the time that can be allocated to main processing can be increased.

Brief Description of the Drawings

[0008]

Figure 1

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DETAILED DESCRIPTION OF THE INVENTION

[0009] Prior to the description of the embodiments, the background leading to the following embodiments will be described. In an MCU such as an in-vehicle MCU, while the CPU is executing a predetermined application process (hereinafter also referred to as a main process), it performs interrupt processing caused by a plurality of asynchronous communications. The main process includes, for example, a high-priority main process and a main process other than high-priority. Examples of the high-priority main process include chassis processes for controlling turning and stopping of the vehicle. Also, examples of the main process other than high-priority include power train processes and body processes. The main process is started at the start of a predetermined cycle time.

[0010] The main process is designed to be completed within a determined time. For example, the high-priority main process is designed to be completed within a time range of 1 ms to 2 ms. The main processes other than the high-priority ones are designed to be completed within a time range of, for example, 3 ms to 10 ms. At this time, the CPU needs to perform interrupt processing due to asynchronous communication in addition to the main process. The cycle time, which is also the startup interval time of the main process, and the processing time of the main process need to satisfy the following relational expression. Cycle time > Main process time + Total interrupt processing time

[0011] In the above formula, the total interrupt processing time is the total time of the processing times of all possible interrupts that can occur within the cycle time. For example, if there is a possibility that 6 interrupts of asynchronous communication occur during the cycle time, the total interrupt processing time is the sum of the processing times of the 6 interrupts. In this case, the MCU is designed such that the main process and the 6 interrupt processes are completed within the cycle time. This means that the time that can be allocated to the main process during the cycle time is the time obtained by subtracting the total time of the processing times of all possible interrupts from the cycle time.

[0012] In the above design, the CPU can process all interrupts within one cycle time. However, if no interrupt occurs during a certain cycle time, no interrupt processing is performed during that cycle time, so idle time is created in the CPU. Also, when not all interrupts occur within one cycle time and the interrupts occur dispersed over multiple cycle times, idle time occurs in the CPU in each cycle time.

[0013] In recent years, in MCUs or SoCs, the number of asynchronous communication channels has increased in order to handle a large amount of information. The more the number of asynchronous communication channels increases, the more prominent the above-mentioned problem becomes. The inventor has discovered that when determining the main process time based on the total interrupt processing time in the worst-case scenario where an interrupt occurs, the functions realized by the main process are limited, and has come up with the following embodiments.

[0014] Hereinafter, embodiments in which means for solving the above problems are applied will be described in detail with reference to the drawings. For the sake of clarity of explanation, the following description and drawings have been appropriately omitted and simplified. In each drawing, the same reference numerals are assigned to the same elements, and redundant descriptions are omitted as necessary.

[0015] In the following embodiments, for convenience, when necessary, they are divided into a plurality of sections or embodiments for explanation. However, unless otherwise specified, they are not independent of each other, and one is related to a partial or complete modification example, application example, detailed explanation, supplementary explanation, etc. of the other. Also, in the following embodiments, when referring to the number of elements, etc. (including the number, numerical value, quantity, and range, etc.), unless otherwise specified or clearly limited to a specific number in principle, it is not limited to that specific number, and it may be more than or less than the specific number.

[0016] Furthermore, in the following embodiments, the components (including operation steps, etc.) are not necessarily essential unless otherwise specified or clearly considered essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the components, etc., unless otherwise specified or clearly considered otherwise in principle, those substantially approximating or similar to the shape, etc. are included. This also applies to the above numbers, etc. (including the number, numerical value, quantity, and range).

[0017] [Embodiment 1] FIG. 1 shows a configuration example of a semiconductor device according to Embodiment 1 of the present disclosure. In the present embodiment, the semiconductor device is configured as an MCU or an SoC. The MCU 100 shown in FIG. 1 includes a plurality of CPU cores 101, an interrupt controller 102, a plurality of communication interfaces 103-0 to 103-15, a timer unit 104, a plurality of interrupt suppression tables 105, and a memory 106. The MCU 100 is used, for example, as an in-vehicle MCU that realizes functions such as an advanced driver-assistance system (ADAS) and autonomous driving. The MCU 100 may be used, for example, as a domain controller or a zone controller in an E / E (Electrical / Electronic) architecture.

[0018] The CPU core 101 executes various processes such as main processing and interrupt processing in the MCU 100. The CPU core 101 is, for example, a CPU core included in a multi-core CPU. The timer unit 104 includes a timer that measures a predetermined cycle time. In the timer unit 104, the timer generates a timeout every time the predetermined cycle time elapses. When the timer times out, the timer unit 104 notifies the interrupt controller 102 of an interrupt request IRQ_OSTM.

[0019] The memory 106 stores a program. The program includes a group of instructions or software code for causing the CPU core 101 to execute various processes when executed by the CPU core 101. In the present embodiment, the processes performed by the CPU core 101 include main processing and interrupt processing. The CPU core 101 starts main processing every time the start of a predetermined cycle time arrives. Also, every time an interrupt occurs, the CPU core 101 executes interrupt processing corresponding to the occurred interrupt.

[0020] The above program may be stored in a non-transitory computer-readable medium or a tangible storage medium. By way of example and not limitation, the computer-readable medium or tangible storage medium includes RAM (Random Access Memory), ROM (Read Only Memory), flash memory, SSD (solid-state drive) or other memory technologies, CD (Compact Disc)-ROM, DVD (digital versatile disc), Blu-ray (registered trademark) disc or other optical disc storage, magnetic cassette, magnetic tape, magnetic disc storage or other magnetic storage devices. The program may be transmitted on a transitory computer-readable medium or a communication medium. By way of example and not limitation, the transitory computer-readable medium or communication medium includes electrical, optical, acoustic, or other forms of propagated signals.

[0021] Communication interfaces 103-0 (CAN00) to 103-15 (CAN15) are communication interfaces that communicate with external devices connected to the MCU100 via a communication bus, respectively. When the conditions for generating an interrupt are satisfied for communication interfaces 103-0 to 103-15, they notify the interrupt controller 102 of interrupt requests IRQ_CAN00 to IRQ_CAN15, respectively. Communication interfaces 103-0 to 103-15 perform asynchronous communication with external devices, and the timing at which communication interfaces 103-0 to 103-15 notify interrupt requests may vary for each communication interface.

[0022] In this embodiment, communication interfaces 103-0 to 103-15 are grouped into two groups according to the priority of interrupt processing. In the example of FIG. 1, communication interfaces 103-0 to 103-05 are communication interfaces corresponding to high-priority (first priority) interrupt processing, that is, interrupt processing with high priority. On the other hand, communication interfaces 103-6 to 103-15 are communication interfaces corresponding to interrupt processing with a priority other than high priority (second priority). High-priority interrupt processing is, for example, interrupt processing in which the data processed by the interrupt is used in the above high-priority main processing. Interrupt processing other than high priority is, for example, interrupt processing in which the data processed by the interrupt is used in main processing other than the above high priority. For the sake of convenience, interrupt processing with a priority other than high priority is also called low-priority interrupt processing or interrupt processing with low priority.

[0023] Note that communication interfaces 103-0 to 103-15 are also called communication interface 103 when there is no need to particularly distinguish them. In this embodiment, it is assumed that communication interface 103 is a CAN interface that communicates with devices connected to a Controller Area Network (CAN). Communication interface 103 may include interfaces of other communication standards such as Ethernet (registered trademark). The numbers of communication interfaces 103 correspond to channel numbers. In MCU 100, the number of channels, that is, the number of communication interfaces 103, is arbitrary and is not particularly limited to 16.

[0024] The interrupt controller 102 controls which of the interrupt requests notified from the plurality of communication interfaces 103 are to be notified to the CPU core 101. For example, when the communication interface 103-0 notifies the interrupt request IRQ-CAN00 to the interrupt controller 102, the interrupt controller 102 transmits an interrupt signal INT indicating that an interrupt has occurred at channel 00 to one of the plurality of CPU cores 101. Assume that it is defined in advance which CPU core among the plurality of CPU cores 101 performs the interrupt processing for which channel. When an interrupt request is notified from a certain communication interface 103, the interrupt controller 102 outputs an interrupt signal to the CPU core 101 that performs the interrupt processing for that communication interface. When an interrupt request is notified from the timer unit 104, the interrupt controller 102 notifies each of the plurality of CPU cores 101 that a timer interrupt has occurred.

[0025] In this embodiment, the interrupt processing performed by the CPU core 101 includes one or more high-priority interrupt processes and one or more low-priority interrupt processes. When an interrupt is notified from the communication interfaces 103-0 to 103-05, the CPU core 101 performs a high-priority interrupt process. The high-priority interrupt process includes, for example, a process of generating data used in a high-priority main process. In this embodiment, assume that the data generated in the interrupt process is used in the high-priority main process in the next cycle time. Therefore, it is required that the high-priority interrupt process finish the process within the cycle time when the interrupt occurs. When an interrupt is notified from the communication interfaces 103-6 to 103-15, the CPU core 101 performs a low-priority interrupt process. In this embodiment, each of the one or more low-priority interrupt processes occurs once every N cycle times, where N is a natural number, for example, an integer of 2 or more. In this embodiment, it is required that the low-priority interrupt process finish the process before the next low-priority interrupt occurs. In other words, it is required that the low-priority interrupt process finish the process within N cycle times from the start of the cycle time when the interrupt occurs.

[0026] In this embodiment, the CPU core 101 suppresses interrupt processing with a priority other than high priority under a predetermined condition within one cycle time. Each of the plurality of interrupt suppression tables 105 is a table in which parameters related to interrupt suppression are registered. The interrupt suppression table 105 is generated corresponding to each CPU core 101, for example, for each CPU core 101. The interrupt suppression table 105 includes information defining a communication interface to be the interrupt suppression target. The communication interface to be the interrupt suppression target is synonymous with the communication interface corresponding to interrupt processing with a priority other than high priority. Further, the interrupt suppression table 105 includes a suppression condition. In this embodiment, the suppression condition (first suppression condition) indicates the upper limit of the number of interrupt processes of the interrupt suppression target in the cycle time. The suppression condition is set based on the cycle in which low-priority interrupt processing occurs and the total number of low-priority interrupt processes occurring within the period corresponding to that cycle. Here, the total number of low-priority interrupt processes occurring within the period corresponding to the cycle in which low-priority interrupt processing occurs means not only the actual total number of interrupt processes occurring in that period, but also the total number of interrupt processes that may occur in that period in terms of design or operation. Furthermore, the interrupt suppression table 105 includes a suppression state indicating whether the interrupt of the communication interface to be the interrupt suppression target is in a suppressed state or an unsuppressed state. Note that the data of the interrupt suppression table 105 may be stored in the memory 106 or a storage area (not shown) in the MCU 100.

[0027] Figure 2 shows an example of an interrupt suppression table 105 corresponding to a certain CPU core 101. In this example, the interrupt suppression table includes an interrupt suppression target, the total number of interrupts to be suppressed, a request period, and a suppression state. The interrupt suppression target defines which communication interface or channel's interrupt is to be the suppression target. For example, when ch06 and ch13 - ch15 are registered as the interrupt suppression target, among the communication interfaces 103 - 0 to 103 - 15 of the MCU100, communication interfaces 103 - 6 and 103 - 13 to 103 - 15 are defined as the communication interfaces to be suppressed. The total number of interrupts to be suppressed indicates the total number of low - priority interrupts that occur within a period corresponding to the period in which low - priority interrupts for which the corresponding CPU core 101 is responsible for interrupt processing occur.

[0028] The request period is information indicating within how many cycle times the low - priority interrupt processing, that is, the interrupt processing to be suppressed, is required to finish processing. For example, when low - priority interrupts occur at a rate of once every four cycle times, the low - priority interrupt processing is required to finish processing within four cycle times including the cycle time when the interrupt occurred. In that case, "4" is registered in the request period of the interrupt suppression table. The request period is related to the occurrence frequency of the low - priority interrupt processing, that is, how often it occurs in one cycle. In this embodiment, it is assumed that all the interrupt processing to be suppressed occurs at the same cycle, and the request periods of the interrupt processing to be suppressed are the same. In other words, in this embodiment, it is assumed that all interrupt processing other than high - priority interrupts is required to finish within the period of the same request cycle. When all the interrupts to be suppressed occur at the same cycle, the total number of interrupts to be suppressed is equal to the number of communication interfaces 103 of the interrupt suppression target. The suppression condition indicates the condition under which the low - priority interrupt processing is suppressed. In this embodiment, the suppression condition indicates the upper limit of the number of low - priority interrupt processing operations that can be performed within one cycle time. In other words, the suppression condition defines when the low - priority interrupt processing is suppressed when the low - priority interrupt processing occurs a certain number of times. The suppression condition is given, for example, as m / N (ceiling), where m is a natural number representing the total number of interrupts to be suppressed and N is a natural number representing the request period.

[0029] The inhibition state indicates whether the low-priority interrupt processing is inhibited or not. The inhibition state is initialized to "release" at the start of each cycle time. When the number of low-priority interrupt processes equals the number indicated by the inhibition condition, the inhibition state is changed to "inhibit". When the inhibition state is "release", an interrupt request notified from the communication interface to be interrupted is input to the CPU core 101, and in the CPU core 101, low-priority interrupt processing is performed. When the inhibition state is changed to "inhibit", the output of the interrupt request is inhibited in the communication interface to be interrupted, and in the CPU core 101, low-priority interrupt processing is not performed.

[0030] Figure 3 shows an example of the logical configuration of the CPU core 101. The CPU core 101 includes an interrupt reception unit 111, an interrupt inhibition control unit 112, a main processing unit 113, and an interrupt processing unit 114. The interrupt inhibition control unit 112 includes an initialization unit 121, an inhibition target determination unit 122, a counter 123, and an inhibition determination unit 124.

[0031] The interrupt reception unit 111 receives an interrupt input from the interrupt controller 102. When the interrupt received by the interrupt reception unit 111 is an interrupt request output from the timer unit 104, that is, a timer interrupt, the interrupt reception unit 111 instructs the main processing unit 113 to start the main processing. Also, the interrupt reception unit 111 notifies the interrupt inhibition control unit 112 that a timer interrupt has occurred. The main processing unit 113 starts the main processing when there is a timer interrupt. When the interrupt received by the interrupt reception unit 111 is an interrupt request output from any of the communication interfaces 103, the interrupt reception unit 111 instructs the interrupt processing unit 114 to start the interrupt processing. The interrupt processing unit 114 performs interrupt processing in response to the received interrupt.

[0032] The interrupt suppression control unit 112 controls the suppression of low-priority interrupt processing, and controls the number of low-priority interrupt processes processed by the interrupt processing unit 114 within one cycle time to be less than the total number of low-priority interrupt processes. The initialization unit 121 of the interrupt suppression control unit 112 initializes the suppression state of the interrupt suppression table 105 to "released" when a timer interrupt is notified. Also, the count value of the counter 123 is reset to 0. The suppression target determination unit 122 determines whether the interrupt received by the interrupt reception unit 111 is subject to interrupt suppression control. The suppression target determination unit 122 compares the communication interface of the source of the received interrupt with the communication interface registered as the interrupt suppression target in the interrupt suppression table 105, and determines whether the received interrupt is an interrupt output from the communication interface registered as the interrupt suppression target.

[0033] For example, assume that the interrupt reception unit 111 receives an interrupt corresponding to an interrupt request output from the communication interface 103-0 (ch0). In that case, since "ch0" does not exist in the interrupt suppression target of the interrupt suppression table 105 shown in FIG. 2, the suppression target determination unit 122 determines that the ch0 interrupt is not subject to interrupt suppression control. Next, assume that the interrupt reception unit 111 receives an interrupt corresponding to an interrupt request output from the communication interface 103-6 (ch6). In that case, since "ch6" is included in the interrupt suppression target of the interrupt suppression table 105 shown in FIG. 2, the suppression target determination unit 122 determines that the ch6 interrupt is subject to interrupt suppression control.

[0034] When the interrupt reception determination unit 122 determines that the received interrupt is a target for interrupt suppression control, the counter 123 increments its count value by one. In other words, the counter 123 counts the number of times it is determined that the received interrupt is an interrupt output from the communication interface 103 registered as an interrupt suppression target. The suppression determination unit 124 determines whether to suppress the low-priority interrupt process based on the count value of the counter 123 and the suppression condition in the interrupt suppression table 105. For example, when the count value reaches the number of times of the suppression condition, that is, when the count value matches the number of times of the suppression condition, the suppression determination unit 124 determines to suppress the low-priority interrupt process.

[0035] When it is determined to suppress the low-priority interrupt process, the suppression determination unit 124 outputs a suppression signal to the communication interface registered as the interrupt suppression target in the interrupt suppression table 105. When the communication interface 103 receives the suppression signal, it suppresses the output of the interrupt request. When the suppression state of the counter 123 and the interrupt suppression table is initialized, the suppression determination unit 124 stops outputting the suppression signal. When the output of the suppression signal is stopped, the communication interface 103 releases the suppression of the output of the interrupt request.

[0036] FIG. 4 shows a configuration example of the communication interface 103. The communication interface 103 includes a buffer 131, a buffer control unit 132, and an interrupt control unit 133. The buffer 131 stores messages transmitted from an external device connected via a communication bus such as a CAN bus. For example, a FIFO (First-In First-Out) buffer is used for the buffer 131. The number of stages of the FIFO buffer is set based on, for example, one cycle time, / message length, and message interval. When a predetermined number of messages are stored in the buffer 131, for example, when the FIFO buffer becomes full, the buffer control unit 132 notifies the interrupt control unit 133 that a predetermined number of messages are stored in the buffer 131.

[0037] When a predetermined number of messages are stored in buffer 131, interrupt control unit 133 sends an interrupt request to CPU core 101 via interrupt controller 102. At this time, if a suppression signal is output from suppression determination unit 124 of CPU core 101, interrupt control unit 133 suppresses the transmission of the interrupt request. Interrupt control unit 133 suppresses the transmission of the interrupt request until the output of the suppression signal stops, and when the output of the suppression signal stops, it sends the interrupt request to CPU core 101. When the interrupt request is received by CPU core 101, interrupt processing unit 114 of CPU core 101 performs interrupt processing. In the interrupt processing, interrupt processing unit 114 acquires the message stored in buffer 131 and performs interrupt processing using the acquired message.

[0038] Subsequently, the operation procedure will be described. FIG. 5 shows the operation procedure of MCU 100 when a timer interrupt occurs. Timer unit 104 measures a predetermined time using a timer and outputs a timer interrupt request to CPU core 101 via interrupt controller 102 at a predetermined cycle time, for example, every 1 ms. Interrupt reception unit 111 of CPU core 101 receives a timer interrupt request from timer unit 104 via interrupt controller 102 (step A1).

[0039] When a timer interrupt request is received, initialization unit 121 initializes the count value of counter 123 to 0 and initializes the suppression state of the interrupt suppression table to "released" (step A2). Suppression determination unit 124 determines that low-priority interrupt processing is not suppressed because counter 123 is initialized. If suppression determination unit 124 output a suppression signal to communication interface 103 in the previous cycle time, it stops the output of the suppression signal (step A3). Interrupt reception unit 111 instructs main processing unit 113 to start main processing. When receiving the start instruction, main processing unit 113 starts main processing (step A4).

[0040] Figure 6 shows the operation procedure of the MCU 100 when an interrupt request is transmitted from the communication interface 103. In the communication interface 103, for example, when the number of messages stored in the buffer 131 reaches a predetermined number, the interrupt control unit 133 transmits an interrupt request to the CPU core 101 via the interrupt controller 102 (step B1). Note that the transmission of this interrupt request is asynchronous with the cycle time. In the MCU 100, multiple interrupt requests can be transmitted from multiple communication interfaces 103 within one cycle time.

[0041] In the CPU core 101, the interrupt reception unit 111 receives the interrupt request transmitted from the communication interface 103. The suppression target determination unit 122 determines whether the communication interface 103 that output the interrupt request is a target of interrupt suppression control (step B2). In step B2, the suppression target determination unit 122 checks whether the communication interface 103 that output the interrupt request is registered as an interrupt suppression target in the interrupt suppression table 105. If the communication interface 103 that output the interrupt request is registered as an interrupt suppression target, the suppression target determination unit 122 determines that the received interrupt is a target of interrupt suppression control.

[0042] If it is determined that the received interrupt is a target of interrupt suppression control, the counter 123 increments the count value by one (step B3). The suppression determination unit 124 determines whether the suppression condition in the interrupt suppression table 105 is satisfied based on the count value of the counter 123 (step B4). In step B4, the suppression determination unit 124 compares the count value with the upper limit of the number of times indicated by the suppression condition, and determines that the suppression condition is satisfied when the count value reaches the upper limit of the number of times indicated by the suppression condition.

[0043] When it is determined that the inhibition condition is satisfied, the inhibition determination unit 124 outputs an inhibition signal to the communication interface 103 that is the target of the interrupt inhibition control (step B5). In step B5, the inhibition determination unit 124 refers to, for example, the interrupt inhibition table 105 shown in FIG. 2, and identifies the communication interfaces of cch06 and ch13 - ch15 as the communication interfaces to be inhibited from interrupts. In that case, the inhibition determination unit 124 outputs the inhibition signal to each of the low - priority communication interfaces 103 - 6 and 103 - 13 to 103 - 15. The communication interfaces 103 - 6 and 103 - 13 to 103 - 15 inhibit the transmission of interrupt requests while the inhibition signal is being output. At this time, the inhibition determination unit 124 does not output the inhibition signal to the high - priority communication interfaces 103 - 0 to 103 - 05. Therefore, the communication interfaces 103 - 0 to 103 - 05 can transmit interrupt requests to the CPU core 101.

[0044] The interrupt processing unit 114 performs interrupt processing corresponding to the interrupt received in step B1 (step B6). If it is determined in step B2 that the communication interface 103 that output the interrupt request is not the target of the interrupt inhibition control, steps B3 to B5 are skipped, and interrupt processing is performed in step B6. If it is determined in step B4 that the inhibition condition is not satisfied, step B5 is skipped, and interrupt processing is performed in step B6.

[0045] For example, assume that at a certain cycle time, all m interrupt processes other than the high - priority interrupts, that is, the low - priority interrupt processes, occur. In this case, at each cycle time, ⌈m / N⌉ low - priority interrupts are received by the CPU core 101, and low - priority interrupt processing is performed. Therefore, the CPU core 101 can complete all m low - priority interrupt processes from a certain cycle time to the N - th cycle time. Thus, in this embodiment, the CPU core 101 can disperse and perform m interrupt processes other than the high - priority interrupts within N cycle times. The time during which the CPU core 101 can perform the main process at each cycle time can be expressed by the following relational expression. Main processing time < Cycle time - (Processing time of all high-priority interrupts + Processing time of all non-high-priority interrupts / N)

[0046] Subsequently, a specific operation example will be described. FIG. 7 schematically shows the execution of the processing performed by the CPU core 101. Here, one cycle time is set to 1 ms, and the request period of the interrupt processing with a priority other than high priority is N = 2. Also, assume that a certain CPU core included in the CPU core 101 performs interrupt processing from ch0, ch5, ch6, and ch13 to ch15, that is, from the communication interfaces 103-0, 103-5, 103-6, and 103-13 to 103-15. Assume that ch6 and ch13 to ch15 among the communication interfaces 103 are registered as the interrupt suppression targets in the interrupt suppression table 105. Among the interrupt processes, the number of non-high-priority interrupt processes is m = 4.

[0047] At time t0, the timer unit 104 generates a timer interrupt. When the timer unit 104 generates a timer interrupt, the main processing unit 113 of the CPU core 101 starts main processing. Also, the initialization unit 121 initializes the count value of the counter 123 to 0 and initializes the suppression state of the interrupt suppression table 105 to "released".

[0048] At time t1, when the number of messages stored in the buffer 131 reaches a predetermined number in the communication interface 103-6, that is, the communication interface of ch6, the interrupt control unit 133 outputs an interrupt request to the interrupt controller 102. The interrupt reception unit 111 of the CPU core 101 receives the interrupt request output from ch6. In the CPU core, the main processing unit 113 interrupts the main processing, and the interrupt processing unit 114 performs the interrupt processing of ch6.

[0049] The interrupt suppression target determination unit 122 refers to the interrupt suppression target in the interrupt suppression table 105 and determines whether ch6 where the interrupt has occurred is a suppression target. Since ch6 is registered as an interrupt suppression target, the interrupt suppression target determination unit 122 determines that ch6 is a suppression target. In that case, the count value of the counter 123 is incremented by 1 and becomes "1". The suppression determination unit 124 compares the count value "1" with the suppression condition m / N = 2. Since the count value has not reached the suppression condition m / N = 2, the suppression determination unit 124 determines not to suppress the low-priority interrupt processing.

[0050] At time t2, the interrupt reception unit 111 receives an interrupt request output from ch0. The interrupt processing unit 114 performs the interrupt processing of ch0. The interrupt suppression target determination unit 122 refers to the interrupt suppression target in the interrupt suppression table 105 and determines that ch0 where the interrupt has occurred is not a suppression target. In that case, the counter 123 does not change the count value.

[0051] At time t3, the interrupt reception unit 111 receives an interrupt request output from ch15. The interrupt processing unit 114 performs the interrupt processing of ch15. The interrupt suppression target determination unit 122 refers to the interrupt suppression target in the interrupt suppression table 105 and determines that ch15 where the interrupt has occurred is a suppression target. In that case, the counter 123 increments the count value by 1 and updates the count value to "2". Since the suppression determination unit 124 determines that the count value has reached the suppression condition m / N = 2, it determines to suppress the low-priority interrupt processing. The suppression determination unit 124 outputs suppression signals from the communication interfaces 103-6 of ch6 to ch15, and 103-13 to 103-15 to suppress the occurrence of future low-priority interrupts.

[0052] At time t4, the interrupt reception unit 111 receives an interrupt request output from ch5. Since the communication interface 103-5 of ch5 has high priority, no suppression signal is output to ch5, and the interrupt control unit 133 of the communication interface 103-5 can output the interrupt request to the CPU core 101. The interrupt processing unit 114 performs the interrupt processing of ch5. The suppression target determination unit 122 refers to the interrupt suppression target in the interrupt suppression table 105 and determines that ch5 where the interrupt has occurred is not a suppression target. In that case, the counter 123 does not change the count value.

[0053] At time t5, in the communication interface 103-14, that is, the communication interface of ch14, the number of messages stored in the buffer 131 reaches a predetermined number. However, since a suppression signal is output from the suppression determination unit 124 of the CPU core 101, the interrupt control unit 133 of the communication interface 103-14 does not output an interrupt request at this timing. In the CPU core 101, after the main processing unit 113 finishes the interrupt processing of ch5, the main processing resumes.

[0054] At time t6, in the communication interface 103-13, that is, the communication interface of ch13, the number of messages stored in the buffer 131 reaches a predetermined number. However, since a suppression signal is output from the suppression determination unit 124 of the CPU core 101, the interrupt control unit 133 of the communication interface 103-13 does not output an interrupt request at this timing.

[0055] At time t7, the timer unit 104 generates a timer interrupt, and the next cycle time starts. When the timer unit 104 generates a timer interrupt, the main processing unit 113 activates the main processing. Also, the initialization unit 121 initializes the count value of the counter 123 to 0 and initializes the suppression state of the interrupt suppression table 105 to "released". The suppression determination unit 124 stops the output of the suppression signal. Since the suppression signal output from the suppression determination unit 124 has stopped, the interrupt control units 133 of the communication interfaces 103-13 and 103-14 can output an interrupt request to the interrupt controller 102.

[0056] At time t8, the interrupt reception unit 111 of the CPU core 101 receives an interrupt request output from the communication interface of ch14. The interrupt processing unit 114 performs the interrupt processing of ch14. The suppression target determination unit 122 determines that the communication interface of ch14 is a suppression target. The counter 123 updates the count value to "1". Since the suppression condition is m / N = 2, the suppression determination unit 124 determines not to suppress the interrupt processing of low priority.

[0057] At time t9, the interrupt reception unit 111 of the CPU core 101 receives an interrupt request output from the communication interface of ch13. The interrupt processing unit 114 performs the interrupt processing of ch13. The suppression target determination unit 122 determines that the communication interface of ch13 is a suppression target. The counter 123 updates the count value to "2". Since the count value has reached the suppression condition, the suppression determination unit 124 determines to suppress the interrupt processing of low priority. The suppression determination unit 124 outputs a suppression signal to the communication interfaces of ch6 and ch13-ch15 to suppress the occurrence of future interrupts of low priority.

[0058] Note that in the case where the low-priority interrupt process is delayed by the suppression signal for the longest time, it is delayed by N cycle times. In this case, the buffer 131 of the communication interface 103 requires an additional N cycle times until the delayed interrupt process is processed. Therefore, in order to be able to store new messages generated within that time, the size of the buffer 131 may be extended to a size capable of storing messages for a time twice that of N cycle times. In this way, by doubling the size of the buffer 131 to twice the N cycle times, it is possible to avoid the messages transmitted from the external device overflowing from the buffer 131 while the interrupt process is delayed. Further, the buffer control unit 132 may output an interrupt request to the interrupt control unit 133 when messages are stored up to half of the capacity of the buffer 131. Thereby, the influence due to the delay of the interrupt process can be suppressed.

[0059] In this embodiment, by dividing the total number of interrupts other than the high priority by the period N of the interrupts other than the high priority, the upper limit of the number of interrupt processes other than the high priority to be processed in one cycle time is set. Thereby, the CPU core 101 can process the interrupts other than the high priority generated in the time of the period N in a distributed manner. By doing so, in each cycle time, the main processing time can be determined based on the distributed interrupt processing time. For this reason, the main processing time can be ensured as compared with the case where the control of interrupt suppression is not performed. That is, the CPU core 101 can execute the main process for a longer time as compared with the case where the control of interrupt suppression is not performed.

[0060] [Embodiment 2] FIG. 8 shows a configuration example of a semiconductor device according to Embodiment 2 of the present disclosure. In this embodiment, in addition to the configuration of the MCU 100 shown in FIG. 1, the MCU 100a has a suppression condition setting unit 107. The suppression condition setting unit 107 generates a suppression condition that is a condition for suppressing the low-priority interrupt process and registers it in the interrupt suppression table 105.

[0061] For example, the user stores the value of a natural number m, which indicates the number of interrupts other than high priority, i.e., the number of interrupts to be suppressed, in a register (not shown) of the MCU 100. Also, the user stores the value of a natural number N, which indicates the value representing the occurrence period of interrupt processing other than high priority, in the register. In other words, the user stores the value N, which indicates within how many cycle times the interrupt processing other than high priority is required to finish processing, in the register. The suppression condition setting unit 107 reads the value of m and the value of N from the register. The suppression condition setting unit 107 calculates m / N, and registers, as a suppression condition, the value obtained by rounding up the fraction of the calculated value in the interrupt suppression table 105.

[0062] In this embodiment, the suppression condition setting unit 107 registers the value of the suppression condition in the interrupt suppression table 105 according to the value given by the user. By using the suppression condition setting unit 107, the user can easily register the value of the suppression condition in the interrupt suppression table. Other effects are the same as those in the first embodiment.

[0063] [Embodiment 3] Embodiment 3 will be described. In the above-described first and second embodiments, an example in which all interrupt processing other than high priority is required to finish within the same N cycle times has been described. However, the periods required for interrupt processing other than high priority are not necessarily single. For some interrupt processing, it may be required to finish processing within 2 cycles, while for other interrupt processing, it may be sufficient to finish processing within 4 cycles. In this embodiment, the interrupt suppression control unit 112 controls the suppression of interrupt processing other than high priority for interrupt processing of a plurality of priorities having a plurality of different required periods.

[0064] In this embodiment, the interrupt processing other than the high priority includes two interrupt processes with different priorities. The interrupt processing other than the high priority includes an interrupt process with a medium priority and an interrupt process with a low priority. The interrupt process with a medium priority (the second priority) is also called an interrupt process with a medium priority. The interrupt process with a low priority (the third priority) is also called an interrupt process with a low priority. In this embodiment, the interrupt suppression table 105 stores, for each of the interrupt processes with a medium priority and a low priority, the communication interface to be interrupted, the number of interrupts to be suppressed, the request period, the suppression condition, and the suppression state.

[0065] FIG. 9 shows an example of the interrupt suppression table 105 used in Embodiment 3. In this example, the interrupt suppression table 105 stores information that the communication interfaces to be interrupted for the interrupt process with a medium priority are from ch06 to ch09. In this case, the number m1 of interrupts to be suppressed is m1 = 4. Also, the interrupt suppression table 105 stores the request period N1 = 2 for the interrupt process with a medium priority. In this case, the suppression condition (the first suppression condition) for the interrupt process with a medium priority is m1 / N1 = 2.

[0066] Further, the interrupt suppression table 105 stores information that the communication interfaces to be interrupted for the interrupt process with a low priority are from ch010 to ch15. In this case, the number m2 of interrupts to be suppressed is m2 = 6. The interrupt suppression table 105 stores the request period N2 = 3 for the interrupt process with a low priority. In this case, the suppression condition (the second suppression condition) for the interrupt process with a low priority is m2 / N2 = 2.

[0067] In this embodiment, the suppression target determination unit 122 of the interrupt suppression control unit 112 determines whether the interrupt received by the interrupt reception unit 111 is a target of medium-priority interrupt suppression control and whether the interrupt received by the interrupt reception unit 111 is a target of low-priority interrupt suppression control. When the communication interface of the source of the received interrupt is registered as a medium-priority interrupt suppression target, the suppression target determination unit 122 determines that the received interrupt is a target of medium-priority interrupt suppression control. When the communication interface of the source of the received interrupt is registered as a low-priority interrupt suppression target, the suppression target determination unit 122 determines that the received interrupt is a target of low-priority interrupt suppression control.

[0068] In this embodiment, the counter 123 counts the number of occurrences of interrupt processing for each of low priority and medium priority. When it is determined in the suppression target determination unit 122 that it is a target of medium-priority interrupt suppression control, the counter 123 increments the medium-priority counter value by one. When it is determined in the suppression target determination unit 122 that it is a target of low-priority interrupt suppression control, the counter 123 increments the low-priority counter value by one.

[0069] The suppression determination unit 124 determines whether to suppress the medium-priority interrupt processing based on the medium-priority count value of the counter 123 and the medium-priority suppression condition of the interrupt suppression table 105 for the medium-priority interrupt processing. The suppression determination unit 124 determines whether to suppress the low-priority interrupt processing based on the low-priority count value of the counter 123 and the low-priority suppression condition of the interrupt suppression table 105 for the low-priority interrupt processing.

[0070] When it is determined to suppress the interrupt process with medium priority, the suppression determination unit 124 outputs a suppression signal to the communication interface registered as the interrupt suppression target with medium priority in the interrupt suppression table 105. When it is determined to suppress the interrupt process with low priority, the suppression determination unit 124 outputs a suppression signal to the communication interface registered as the interrupt suppression target with low priority in the interrupt suppression table 105. When the communication interface 103 receives the suppression signal, it suppresses the output of the interrupt request.

[0071] In the example of FIG. 9, for medium priority, the CPU core 101 performs m1 / N1 = 2 interrupt processes at each cycle time. For low priority, the CPU core 101 performs m2 / N2 = 2 interrupt processes at each cycle time. In this case, for medium priority, the CPU core 101 can disperse and perform m1 medium-priority interrupt processes during N1 cycle times. Also, for low priority, the CPU core 101 can disperse and perform m2 medium-high-priority interrupt processes during N2 cycle times. In this case, at each cycle time, the time that the CPU core 101 can use for the main process is Main process time < Cycle time - {Processing time of all high-priority interrupts + (Processing time of all medium-priority interrupts / N1) + (Processing time of all medium-priority interrupts / N2)} becomes.

[0072] In this embodiment, interrupt suppression control is performed for interrupt processes with priorities other than the two priorities with different request periods, excluding high priority. If interrupt suppression control is performed without distinguishing between low priority and medium priority, then for the interrupt suppression condition, the request period of the medium-priority interrupt process, which has a strict request, is used to determine the suppression condition. In that case, the time that the CPU core 101 can use for the main process is Main process time < Cycle time - {Processing time of all high-priority interrupts + (Processing time of all medium-priority interrupts + Processing time of all medium-priority interrupts) / N1)} This becomes the case. In the present embodiment, by performing control of interrupt suppression for each of low priority and medium priority, it is possible to extend the time available for main processing in each cycle time as compared with the case where low priority and medium priority are not distinguished.

[0073] As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible without departing from the gist thereof.

Explanation of Reference Numerals

[0074] 100: MCU 101: CPU core 102: Interrupt controller 103: Communication interface 104: Timer section 105: Interrupt suppression table 106: Memory 107: Suppression condition setting section 111: Interrupt reception section 112: Interrupt suppression control section 113: Main processing section 114: Interrupt processing section 121: Initialization section 122: Suppression target determination section 123: Counter 124: Suppression determination section 131: Buffer 132: Buffer control section 133: Interrupt control section

Claims

1. A main processing unit that starts main processing at the start of a cycle time, A plurality of communication interfaces connected to a communication bus and outputting interrupt requests, An interrupt reception unit that receives the interrupt requests, An interrupt processing unit that performs interrupt processing including interrupt processing of a first priority and interrupt processing of a second priority lower than the first priority, and performs the interrupt processing of the first priority or the interrupt processing of the second priority in response to an interrupt request received by the interrupt reception unit, A semiconductor device comprising: an interrupt suppression control unit that controls the number of interrupt processes of the second priority processed by the interrupt processing unit in the cycle time according to a first suppression condition set based on a cycle in which the interrupt process of the second priority occurs and the total number of interrupt processes of the second priority occurring within a period corresponding to the cycle.

2. The first suppression condition defines an upper limit on the number of times of interrupt processing of the second priority performed by the interrupt processing unit in the cycle time, The semiconductor device according to claim 1, wherein the interrupt control unit performs control of the interrupt suppression using an interrupt suppression table including the suppression condition.

3. The interrupt suppression table includes an interrupt suppression target that defines a communication interface corresponding to the interrupt processing of the second priority among the plurality of communication interfaces, The interrupt control unit, A suppression target determination unit that determines whether or not an interrupt request received by the interrupt reception unit is an interrupt request output from a communication interface registered in the interrupt suppression target, A counter that counts the number of times it is determined that the received interrupt request is an interrupt request output from a communication interface registered in the interrupt suppression target, The semiconductor device according to claim 2, further comprising: a suppression determination unit that determines whether or not to suppress the interrupt request output from a communication interface registered in the interrupt suppression target based on a count value of the counter and the upper limit of the number of times defined by the first suppression condition.

4. The semiconductor device according to claim 3, wherein the suppression determination unit determines to suppress the interrupt request output from a communication interface registered in the interrupt suppression target when the count value of the counter reaches the upper limit of the number of times defined by the first suppression condition.

5. The semiconductor device according to claim 3, wherein the inhibition determination unit outputs an inhibition signal for inhibiting the output of the interrupt request to the communication interface registered as the interrupt inhibition target, thereby inhibiting the interrupt request output from the communication interface registered as the interrupt inhibition target.

6. The semiconductor device according to claim 5, wherein the inhibition determination unit releases the output of the inhibition signal each time the start of the cycle time occurs.

7. The semiconductor device according to claim 3, wherein the interrupt inhibition control unit further includes an initialization unit that initializes the counter each time the start of the cycle time occurs.

8. The semiconductor device according to claim 1, wherein the period in which the interrupt process of the second priority occurs is represented by N times the cycle time, where N is a natural number.

9. The semiconductor device according to claim 8, wherein the interrupt inhibition control unit controls the number of interrupt processes of the second priority processed by the interrupt processing unit within one cycle time to be less than or equal to the integer obtained by rounding up the decimal part of the value of m / N, where m is a natural number indicating the total number of interrupt processes of the second priority occurring within the period corresponding to the cycle.

10. The semiconductor device according to claim 1, further comprising an inhibition condition setting unit that calculates an integer obtained by rounding up the decimal part of the value of m / N by using, as inputs, the value of the natural number N indicating the period in which the interrupt process of the second priority occurs and the value of the natural number m indicating the total number of interrupt processes of the second priority occurring within the period corresponding to the cycle, and sets the calculated integer as the first inhibition condition.

11. The interrupt process includes an interrupt process of a third priority that is lower in priority than the second priority. The interrupt processing unit performs the interrupt process of the first priority, the interrupt process of the second priority, or the interrupt process of the third priority in response to an interrupt request received by the interrupt reception unit. The semiconductor device according to claim 1, wherein the interrupt inhibition control unit further controls the number of interrupt processes of the third priority processed by the interrupt processing unit in the cycle time according to a second inhibition condition set based on the period in which the interrupt process of the third priority occurs and the total number of interrupt processes of the third priority occurring within the period corresponding to the cycle.

12. The period in which the interrupt process of the second priority occurs is represented by N1 times the period time, where N1 is a natural number, and the period in which the interrupt process of the third priority occurs is represented by N2 times the period time, where N2 is a natural number. The interrupt suppression control unit controls the number of interrupt processes of the second priority processed by the interrupt processing unit within one period time to be equal to or less than the integer obtained by rounding up the fraction of the value of m1 / N1, where m1 is a natural number indicating the total number of interrupt processes of the second priority occurring during the period of N1 times the period time, and controls the number of interrupt processes of the third priority processed by the interrupt processing unit within one period time to be equal to or less than the integer obtained by rounding up the fraction of the value of m2 / N2, where m2 is a natural number indicating the total number of interrupt processes of the second priority occurring during the period of N2 times the period time. The semiconductor device according to claim 11.

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