Solar cell and manufacturing method thereof

Abstract

To provide a solar cell and a method for manufacturing the solar cell which have the advantages of high efficiency and low cost.SOLUTION: The present application provides a solar cell and a method for manufacturing the solar cell, the solar cell includes a silicon substrate, a tunneling layer and a polysilicon layer sequentially formed on a rear surface of the silicon substrate, a dielectric layer formed on a rear surface of the polysilicon layer, a first electrode and a second electrode penetrating the dielectric layer and contacting the polysilicon layer, a first doping region extending from the first electrode to the inside of the silicon substrate, a second doping region extending from the second electrode to the inside of the silicon substrate, and a separation trench located between the first doping region and the second doping region and extending at least to a preset depth of the polysilicon layer. The solar cell and the method for manufacturing the solar cell according to the present application are advantageous in that they are highly efficient and low cost.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] 〔Technical Field〕 This application mainly relates to the field of solar energy technology, and particularly relates to solar cells and methods for manufacturing solar cells.

Background Art

[0002] 〔Background Art〕 A solar cell can convert light energy into electrical energy. The principle of a solar cell is the photovoltaic effect. Specifically, when sunlight irradiates the solar cell, electron-hole pairs are generated in the N-region and P-region inside the solar cell. Then, the electrons are pushed into the N-region by the electric field, and the holes are pushed into the P-region by the electric field respectively. Improving the efficiency of a solar cell can enhance the ability of the solar cell to generate electrical energy. Therefore, improving the efficiency of a solar cell is one of the important research directions.

Summary of the Invention

Problems to be Solved by the Invention

[0003] 〔Content of the Invention〕 The technical problem to be solved by this application is to provide a solar cell and a method for manufacturing a solar cell that have the advantages of high efficiency and low cost.

Means for Solving the Problems

[0004] To solve the above technical problems, the present application provides a solar cell comprising a silicon substrate, a tunneling layer and a polysilicon layer sequentially formed on the back surface of the silicon substrate, a dielectric layer formed on the back surface of the polysilicon layer, a first electrode and a second electrode penetrating the dielectric layer and contacting the polysilicon layer, a first doping region starting from the first electrode and extending into the silicon substrate, a second doping region starting from the second electrode and extending into the silicon substrate, and a separation groove located between the first doping region and the second doping region and penetrating at least to a preset depth of the polysilicon layer.

[0005] In one embodiment of the present application, the tunneling layer contains one or more of silicon dioxide, silicon nitride, silicon oxynitride, and aluminum oxide, and the polysilicon layer contains intrinsic polysilicon.

[0006] In one embodiment of the present application, the minimum distance between the first doping region and the second doping region is 30 μm or more.

[0007] In one embodiment of the present application, the polysilicon layer contains one or more of oxygen element, carbon element, and nitrogen element.

[0008] In one embodiment of the present application, the width of the first doping region located in the silicon substrate is not less than the width of the first doping region located in the polysilicon layer, and the width of the first doping region located in the polysilicon layer is not less than the width of the contact portion between the first electrode and the polysilicon layer.

[0009] In one embodiment of the present application, the width of the second doping region located in the silicon substrate is not less than the width of the second doping region located in the polysilicon layer, and the width of the second doping region located in the polysilicon layer is not less than the width of the contact portion between the second electrode and the polysilicon layer.

[0010] In one embodiment of the present application, the dielectric layer covers the bottom surface and side walls of the isolation groove.

[0011] In one embodiment of the present application, the dielectric layer contains one or more of silicon dioxide, silicon nitride, silicon oxynitride, and aluminum oxide.

[0012] In one embodiment of the present application, the preset depth is at least half of the thickness of the polysilicon layer, or the isolation groove penetrates the polysilicon layer, or the isolation groove penetrates the polysilicon layer and the tunneling layer.

[0013] In one embodiment of the present application, the first electrode contains the same doping element as the doping element in the first doping region, and the second electrode contains the same doping element as the doping element in the second doping region.

[0014] In one embodiment of the present application, the bottom surface of the isolation groove has a pyramid pile morphology.

[0015] In one embodiment of the present application, a passivation antireflection layer formed on the front surface of the silicon substrate is further provided.

[0016] In another form of the present application, a method for manufacturing a solar cell is further provided, which includes the steps of providing a silicon substrate, sequentially forming a tunneling layer and a polysilicon layer on the back surface of the silicon substrate, forming a dielectric layer on the back surface of the polysilicon layer, forming a first electrode and a second electrode that penetrate the dielectric layer and contact the polysilicon layer, where the first electrode has a first type of doping element and the second electrode has a second type of doping element, and forming a first doping region and a second doping region, and the method for forming the first doping region and the second doping region includes the step of heat-treating the first electrode and the second electrode.

[0017] In one embodiment of the present application, the dielectric layer contains a hydrogen element.

[0018] In one embodiment of the present application, the method further includes annealing the dielectric layer so that the hydrogen element in the dielectric layer diffuses into the polysilicon layer, the tunneling layer, and the silicon substrate.

[0019] In one embodiment of the present application, the first doping region starts from the first electrode and extends into the silicon substrate, and the second doping region starts from the second electrode and extends into the silicon substrate.

[0020] In one embodiment of the present application, the width of the first doping region located in the silicon substrate is equal to or greater than the width of the first doping region located in the polysilicon layer, and the width of the first doping region located in the polysilicon layer is equal to or greater than the width of the contact portion between the first electrode and the polysilicon layer.

[0021] In one embodiment of the present application, the width of the second doping region located in the silicon substrate is equal to or greater than the width of the second doping region located in the polysilicon layer, and the width of the second doping region located in the polysilicon layer is equal to or greater than the width of the contact portion between the second electrode and the polysilicon layer.

[0022] In one embodiment of the present application, the tunneling layer contains one or more of silicon dioxide, silicon nitride, silicon oxynitride, and aluminum oxide, and the polysilicon layer contains intrinsic polysilicon.

[0023] In one embodiment of the present application, the minimum distance between the first doping region and the second doping region is 30 μm or more.

[0024] In one embodiment of the present application, the polysilicon layer contains one or more of an oxygen element, a carbon element, and a nitrogen element.

[0025] In one embodiment of the present application, before forming the dielectric layer, a separation groove is formed between the first doping region and the second doping region, and the separation groove penetrates at least to a preset depth within the polysilicon layer.

[0026] In one embodiment of the present application, in the method of forming the separation groove, an initial separation groove that penetrates the corrosion-resistant layer is formed. The initial separation groove exposes the polysilicon layer. The corrosion-resistant layer includes one or more of a silicon oxide layer, a silicon nitride layer, and an aluminum oxide layer. Texturing is performed on the front surface of the silicon substrate. In the texturing process, the separation groove is obtained by etching the polysilicon layer exposed from the initial separation groove.

[0027] In one embodiment of the present application, the bottom surface of the separation groove has a pyramid pile morphology.

[0028] In one embodiment of the present application, before performing texturing on the front surface of the silicon substrate, the dielectric layer is formed on the back surface of the corrosion-resistant layer.

[0029] In one embodiment of the present application, the dielectric layer covers the bottom surface and the side walls of the separation groove.

[0030] In one embodiment of the present application, the method of forming the polysilicon layer includes a step of forming an amorphous silicon layer on the back surface of the tunneling layer, and a step of converting the amorphous silicon layer into the polysilicon layer by performing a crystallization process on the amorphous silicon layer.

[0031] In one embodiment of the present application, after performing the crystallization process on the amorphous silicon layer and before performing texturing on the front surface of the silicon substrate, the dielectric layer is formed on the side of the polysilicon layer away from the silicon substrate.

[0032] This application can improve the efficiency of a solar cell by avoiding the generation of a short - circuit current between a first doping region and a second doping region through a polysilicon layer located between the first doping region and the second doping region. Further, in order to ensure that there is no short - circuit current between the first doping region and the second doping region, a separation groove is provided between the first doping region and the second doping region in this application. Also, this application can save the cost of adding a hydrogen source by hydrogenating the solar cell using hydrogen elements in the dielectric layer. Moreover, this application forms the first doping region and the second doping region by heat - treating the first electrode and the second electrode, and has developed a completely new doping method.

Brief Description of the Drawings

[0033] 〔Description of the Drawings〕 Including the accompanying drawings is for providing a further understanding of this application. These drawings are incorporated and constitute a part of this application. The accompanying drawings show embodiments of this application and serve to explain the principles of this application together with this specification.

[0034] In the drawings,

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Mode for Carrying Out the Invention

[0035] 〔Specific Embodiment〕 To more clearly explain the technical idea of the embodiment of the present application, the drawings necessary for the description of the embodiment will be briefly described below. Obviously, the drawings related to the following description are only several examples or embodiments of the present application, and for those skilled in the art, the present application can also be applied to other similar scenarios based on these drawings without paying inventive labor. Unless otherwise clarified from the language environment or otherwise explained, the same reference numerals in the drawings represent the same configuration or operation.

[0036] As shown in the present application and the claims, unless otherwise explicitly suggested in the context, terms such as "a", "one", "a kind", and / or "the" do not particularly refer to the singular, but may also include the plural. Generally, the terms "comprising" and "including" only indicate that they include the clearly identified steps and elements, and these steps and elements do not constitute an exclusive list, and the method or device may include other steps or elements.

[0037] Unless otherwise specified, the relative arrangements, mathematical formulas, and numerical values of the components and steps described in these embodiments do not limit the scope of this application. On the other hand, it should be understood that the dimensions of each part shown in the drawings are not drawn in actual proportional relationships for the sake of facilitating the description. Regarding the technologies, methods, and devices known to those skilled in the relevant art, no detailed discussion will be carried out, but where appropriate, such technologies, methods, and devices should be regarded as part of the patented specification. In all the examples shown and discussed here, any specific value should be construed as illustrative rather than limiting. Therefore, other examples of the exemplary embodiments may have different values. It should be noted that in the following drawings, similar reference numerals and letters indicate similar items. Therefore, if an item is defined in one drawing, there is no need to discuss it further in subsequent drawings.

[0038] In the specification of this application, it should be understood that the orientation or positional relationship indicated by orientation terms such as "front, rear, top, bottom, left, right", "lateral direction, longitudinal direction, vertical, horizontal", and "top, bottom" is usually based on the orientation or positional relationship shown in the drawings, and is only for the purpose of facilitating and simplifying the description of this application. Unless otherwise explained, these orientation terms do not indicate or imply that the specified device or element must have a specific orientation, be configured, or operate in a specific orientation, so it cannot be understood that they limit the protection scope of this application. The orientation terms "inside, outside" mean inside and outside the contour of each component itself.

[0039] For ease of explanation, here, the spatial positional relationship between one component or feature shown in the drawings and another component or feature can be described using spatial relational terms such as "above...", "over...", "upper surface of...", "at the upper surface". It should be understood that the spatial relational terms are intended to include directions of the components during use or operation other than the directions shown in the drawings. For example, if a component in the drawings is inverted, a component described as "above another component or structure" or "on another component or structure" will be positioned as "below another component or structure" or "under another component or structure". Therefore, the exemplary term "above..." can include two orientations, "above..." and "below...". The component may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used here may be appropriately explained.

[0040] Also, the use of terms such as "first", "second", etc. to limit components is merely to facilitate the distinction of the corresponding components. Without a separate statement, these terms have no special meaning, and it is necessary to explain that they cannot be understood as a limitation on the protection scope of this application. Furthermore, the terms used in this application are selected from well-known terms, but among the terms described in the specification of this application, there are also those selected by the applicant at his own discretion, and their detailed meanings will be explained in the relevant parts of the description of this specification. Also, it is required to understand this application not only in terms of the actual terms used but also in terms of the meanings included in each individual term.

[0041] In this application, a flowchart is used to explain the operations performed by the system according to the embodiments of this application. It should be understood that the above or following operations are not necessarily executed exactly in order. On the contrary, various steps can be processed in reverse order or simultaneously. Also, other operations can be added to these procedures, or one or more operations of these procedures can be removed.

[0042] Next, examples will be used to describe the solar cell and the method for manufacturing the solar cell of the present application.

[0043] Referring to the schematic cross-sectional view of the solar cell of an embodiment shown in FIG. 1, the solar cell of this embodiment includes a silicon substrate 110, a tunneling layer 120, a polysilicon layer 130, a first electrode 150, a second electrode 160, a first doping region 170, and a second doping region 180.

[0044] Specifically, the silicon substrate 110 may be single-crystalline silicon or polycrystalline silicon, and the doping type of the silicon substrate 110 may be P-type or N-type. When the doping type of the silicon substrate 110 is P-type, the doping element may be one or more of boron element (B), aluminum element (Al), and gallium element (Ga). When the doping type of the silicon substrate 110 is N-type, the doping element may be one or more of phosphorus element (P), nitrogen element (N), and arsenic element (As).

[0045] On the back surface 111 of the silicon substrate 110, a tunneling layer 120 and a polysilicon layer 130 are sequentially formed. The tunneling layer 120 can contain one or more of silicon dioxide (SiO2), silicon nitride (SiN x )、 silicon oxynitride (SiO x N y ) and aluminum oxide (Al2O3). The tunneling layer 120 has a tunneling effect. The thickness of the tunneling layer 120 is 3.5 nm or less, for example, 1 nm, 1.5 nm, 2 nm, 2.5 nm, or 3 nm. When the thickness of the tunneling layer 120 exceeds 3.5 nm, the tunneling effect decreases.

[0046] The polysilicon layer 130 may be intrinsic polysilicon, or when it is doped polycrystalline silicon, the doping element in the polysilicon layer 130 may be the same as or different from the doping element in the silicon substrate 110. In one embodiment, the polysilicon layer 130 can contain one or more of oxygen element (O), carbon element (C), and nitrogen element (N). For example, when the polysilicon layer 130 is doped polycrystalline silicon, the doping element in the polysilicon layer 130 can simultaneously contain the same doping element as the doping element in the silicon substrate 110 and one or more of oxygen element, carbon element, and nitrogen element. Also, for example, when the polysilicon layer 130 is doped polycrystalline silicon, the doping element in the polysilicon layer 130 is one or more of oxygen element, carbon element, and nitrogen element, and does not contain the same doping element as the doping element in the silicon substrate 110. In the present application, doping one or more of oxygen element, carbon element, and nitrogen element into the polysilicon layer 130 has the advantages of improving the passivation effect of the polysilicon layer 130 on the solar cell and the selectivity for carriers, increasing the open-circuit voltage and fill factor (FF), and optically reducing the parasitic absorption loss of the polysilicon layer 130, thereby improving the short-circuit current density of the solar cell.

[0047] In one embodiment, the thickness of the polysilicon layer 130 is 10 nm to 600 nm, for example, 100 nm, 200 nm, 300 nm, 400 nm, or 500 nm.

[0048] The silicon substrate 110 further has a front surface 112 facing the back surface 111. During the operation of the solar cell, the front surface 112 faces the sun and receives sunlight. The front surface 112 may have a pyramid pile morphology such that sunlight is incident on the silicon substrate 110 from the front surface 112 side during the operation of the solar cell. Since this pyramid pile morphology has the effect of trapping light and reducing reflection, it improves the utilization rate of sunlight by the solar cell.

[0049] In one embodiment, the solar cell further includes a passivation antireflection layer 190 on the front surface 112. The passivation antireflection layer 190 is SiN x , SiO x N y , SiO2, Al2O3, or any combination thereof. The thickness of the passivation antireflection layer 190 is 150 nm or less, for example, 40 nm, 80 nm, or 120 nm. The passivation antireflection layer 190 has a passivation effect and an antireflection effect.

[0050] A dielectric layer 140 is formed on the back surface 131 of the polysilicon layer 130. The dielectric layer 140 may contain one or more of SiN x , SiO x N y , SiO2, Al2O3, for example, it may be composed of a stacked SiN x thin film and an Al2O3 thin film. The thickness of the dielectric layer 140 is 200 nm or less, for example, 50 nm, 100 nm, or 150 nm. The dielectric layer 140 has a passivation effect.

[0051] The first electrode 150 and the second electrode 160 are disposed adjacent to the back surface of the dielectric layer 140 (i.e., the surface of the dielectric layer 140 away from the substrate). The first electrode 150 penetrates the dielectric layer 140, and the end close to the silicon substrate 110 is in contact with the polysilicon layer 130. Here, the end of the first electrode 150 close to the silicon substrate 110 may be in contact with the back surface 131 of the polysilicon layer 130 (i.e., the surface of the polysilicon layer 130 away from the substrate), or may penetrate into the interior of the polysilicon layer 130. Similarly, the second electrode 160 penetrates the dielectric layer 140, and the end close to the silicon substrate 110 is in contact with the polysilicon layer 130. Here, the end of the second electrode 160 close to the silicon substrate 110 may be in contact with the back surface 131 of the polysilicon layer 130, or may penetrate into the interior of the polysilicon layer 130.

[0052] The first doping region 170 starts from the first electrode 150 and extends into the silicon substrate 110. Alternatively, the end of the first doping region 170 away from the silicon substrate 110 contacts the first electrode 150, and the end of the first doping region 170 close to the silicon substrate 110 extends into the silicon substrate 110. The doping type of the first doping region 170 may be either P-type or N-type.

[0053] Similarly, the second doping region 180 starts from the second electrode 160 and extends into the silicon substrate 110. Alternatively, the end of the second doping region 180 away from the silicon substrate 110 contacts the second electrode 160, and the end of the second doping region 180 close to the silicon substrate 110 extends into the silicon substrate 110. The doping type of the second doping region 180 may be either P-type or N-type, and the doping type of the second doping region 180 is opposite to the doping type of the first doping region 170. For example, when the doping type of the first doping region 170 is P-type, the doping type of the second doping region 180 is N-type. The doping element for forming P-type doping may be one or more of boron element, aluminum element, and gallium element, and the doping element for forming N-type doping may be one or more of phosphorus element, nitrogen element, and arsenic element.

[0054] In one embodiment, the first electrode 150 contains the same doping element as the doping element in the first doping region 170, and the second electrode 160 contains the same doping element as the doping element in the second doping region 180. Specifically, if the first doping region 170 is P-type doping and the doping element for forming P-type doping is boron element, and the second doping region 180 is N-type doping and the doping element for forming N-type doping is phosphorus element, then the first electrode 150 contains boron element and the second electrode 160 contains phosphorus element.

[0055] Also, the doping element in the first doping region 170 is the doping element from the first electrode 150, and the doping element in the second doping region 180 is the doping element from the second electrode 160. This is because the first doping region 170 is formed by the thermal diffusion of the doping element in the first electrode 150, and the second doping region 180 is formed by the thermal diffusion of the doping element in the second electrode 160. This will be described later.

[0056] As shown in FIG. 1, the first doping region 170 can be divided into a lower first doping region 171 and an upper first doping region 172 according to the position. Here, the lower first doping region 171 is located in the polysilicon layer 130, starts from the first electrode 150, and extends to the interface between the tunneling layer 120 and the polysilicon layer 130. The upper first doping region 172 is located in the silicon substrate 110, starts from the interface between the tunneling layer 120 and the silicon substrate 110, and extends into the interior of the silicon substrate 110. The tunneling layer 120 located between the lower first doping region 171 and the upper first doping region 172 contains the same doping element as the doping element in the first doping region 170.

[0057] Similarly, the second doping region 180 can be divided into a lower second doping region 181 and an upper second doping region 182 depending on the position. Here, the lower second doping region 181 is located within the polysilicon layer 130, starts from the second electrode 160, and extends to the interface between the tunneling layer 120 and the polysilicon layer 130. The upper second doping region 182 is located within the silicon substrate 110, starts from the interface between the tunneling layer 120 and the silicon substrate 110, and extends into the interior of the silicon substrate 110. The tunneling layer 120 located between the lower second doping region 181 and the upper second doping region 182 contains the same doping element as the doping element in the second doping region 180.

[0058] In one embodiment, the width of the upper first doping region 172 is greater than or equal to the width of the lower first doping region 171, and the width of the lower first doping region 171 is greater than or equal to the width of the contact portion between the first electrode 150 and the polysilicon layer 130. Similarly, the width of the upper second doping region 182 is greater than or equal to the width of the lower second doping region 181, and the width of the lower second doping region 181 is greater than or equal to the width of the contact portion between the second electrode 160 and the polysilicon layer 130. The above widths mean the maximum widths. For example, the "width of the upper first doping region 172" means the "maximum width of the upper first doping region 172".

[0059] As shown in FIG. 1, the minimum distance L1 in the first direction D1 between the first doping region 170 and the second doping region 180 is 30 μm or more, for example, 35 μm, 40 μm, 45 μm, or 50 μm. The polysilicon layer 130 located between the first doping region 170 and the second doping region 180 in the first direction D1 can separate the first doping region 170 and the second doping region 180. Therefore, the current transmission between the first doping region 170 and the second doping region 180 through the polysilicon layer 130 can be blocked, and thus the generation of the short-circuit current between the first doping region 170 and the second doping region 180 can be prevented, and the efficiency of the solar cell can be improved. In order to obtain the above technical effect, the polysilicon layer 130 must be electrically non-conductive or have a very small resistance. For example, the polysilicon layer 130 is intrinsic polysilicon. Note that due to the constraints of the process steps themselves, etc., the doping element may diffuse into the intrinsic polysilicon. For example, when the doping element in the silicon substrate 110 diffuses into the intrinsic polysilicon, the polysilicon layer 130 is doped polysilicon and not intrinsic polysilicon. However, since the concentration of the doping element in the polysilicon layer 130 is negligibly low, the polysilicon layer 130 located between the first doping region 170 and the second doping region 180 can block (or reduce) the current transmission between the first doping region 170 and the second doping region 180. Further, in order to ensure that there is no current transmission between the first doping region 170 and the second doping region 180, the above embodiment sets the minimum distance L1 between the first doping region 170 and the second doping region 180 to 30 μm or more.

[0060] FIG. 2 is a schematic cross-sectional view of a solar cell in another embodiment. The main difference between FIG. 2 and FIG. 1 is that the solar cell in FIG. 2 has a separation groove 210. Specifically, the separation groove 210 is located between the first doping region 170 and the second doping region 180 in the first direction, and the separation groove 210 extends into the polysilicon layer 130 to a preset depth H1 at least. The preset depth H1 is the distance between the bottom surface 211 and the back surface 131 of the polysilicon layer 130. The dielectric layer 140 in FIG. 2 covers the bottom surface 211 and the side walls of the separation groove 210.

[0061] In FIG. 2, the bottom surface 211 of the separation groove 210 is a plane, and in other embodiments, the bottom surface 211 may have a pyramid pile morphology.

[0062] Next, the depth of the separation groove 210 will be described. In FIG. 2, the separation groove 210 extends into the polysilicon layer 130. That is, the bottom surface 211 is located within the polysilicon layer 130. As described above, the polysilicon layer 130 located between the first doping region 170 and the second doping region 180 has the role of blocking current transmission between the first doping region 170 and the second doping region 180. However, the doping element may diffuse into the polysilicon layer 130. In order to ensure that there is no current transmission between the first doping region 170 and the second doping region 180, in the present application, a separation groove 210 is provided between the first doping region 170 and the second doping region 180. By extending into the polysilicon layer 130, this separation groove 210 blocks the current from being transmitted between the first doping region 170 and the second doping region 180 through the polysilicon layer 130.

[0063] In addition, in FIG. 2, the isolation groove 210 does not penetrate the polysilicon layer 130, and there is a polysilicon layer 130 with a certain thickness between the bottom surface 211 and the tunneling layer 120. Since the polysilicon layer 130 between the bottom surface 211 and the tunneling layer 120 is thin, it is difficult for current to flow. In some embodiments, the preset depth H1 is more than half of the thickness of the polysilicon layer 130, whereby the thickness of the polysilicon layer 130 between the bottom surface 211 and the tunneling layer 120 is reduced, and it is ensured that there is no current transmission or almost no current flows between the first doping region 170 and the second doping region 180.

[0064] As shown in FIG. 3, the isolation groove 210 may penetrate the polysilicon layer 130 and the tunneling layer 120, and the bottom surface 211 may penetrate into the silicon substrate 110. Since the isolation groove 210 penetrates the polysilicon layer 130, the first doping region 170 and the second doping region 180 cannot transmit current through the polysilicon layer therebetween. Even if the doping concentration in the polysilicon layer 130 is high, since the isolation groove 210 completely blocks the polysilicon layer 130 between the first doping region 170 and the second doping region 180, current cannot be transmitted between the first doping region 170 and the second doping region 180 through the polysilicon layer therebetween. In some other embodiments, the isolation groove 210 may penetrate the polysilicon layer 130 instead of the tunneling layer 120.

[0065] In addition, the present application also proposes a method for manufacturing a solar cell. Referring to the flowchart of the method for manufacturing a solar cell in an embodiment shown in FIG. 4, the manufacturing method in this embodiment includes the following steps.

[0066] Step S110: Provide a silicon substrate.

[0067] Step S120: Sequentially form a tunneling layer and a polysilicon layer on the back surface of the silicon substrate.

[0068] Step S130: A dielectric layer is formed on the back surface of the polysilicon layer.

[0069] Step S140: A first electrode and a second electrode are formed to penetrate the dielectric layer and contact the polysilicon layer. The first electrode has a first type of doping element, and the second electrode has a second type of doping element.

[0070] Step S150: A first doping region and a second doping region are formed. Here, the method of forming the first doping region and the second doping region includes heat-treating the first electrode and the second electrode.

[0071] FIGS. 5 to 12 are schematic cross-sectional views of intermediate products in the manufacturing process of a solar cell according to a method for manufacturing a solar cell in an embodiment. Next, steps S110 to S150 will be described with reference to FIGS. 5 to 12.

[0072] As shown in FIG. 5, in step S110, a silicon substrate 110 having opposing back surface 111 and front surface 112 is provided.

[0073] As shown in FIGS. 5 to 7, in step S120, a tunneling layer 120 and a polysilicon layer 130 are sequentially formed on the back surface 111 of the silicon substrate 110. The tunneling layer 120 contains one or more of SiN x , SiO x N y , SiO2, and Al2O3. The method of forming the tunneling layer 120 includes plasma enhanced chemical vapor deposition (PECVD) and atomic layer deposition (ALD).

[0074] In one embodiment, the method of forming the polysilicon layer 130 includes the following steps. First, an amorphous silicon layer 130-1 is formed on the back surface of the tunneling layer 120. Next, the amorphous silicon layer 130-1 is crystallized to convert the amorphous silicon layer 130-1 into a polysilicon layer 130. The crystallization method includes thermal oxidation. In the thermal oxidation process, a first corrosion-resistant layer 221 is formed on the front surface 112 of the silicon substrate 110, and a second corrosion-resistant layer 222 is formed on the back surface 131 of the polysilicon layer 130. Among them, the first corrosion-resistant layer 221 is a silicon oxide (SiO x ) layer formed by oxidizing a silicon substrate with a certain thickness on the front surface 112, and the second corrosion-resistant layer 222 is a silicon oxide (SiO x ) layer formed by oxidizing a polysilicon layer with a certain thickness on the back surface 131. In some other embodiments, the first corrosion-resistant layer 221 can further include one or more of a silicon oxide layer, a silicon nitride layer, and an aluminum oxide layer. For example, the first corrosion-resistant layer 221 is a composite layer composed of a silicon nitride layer and an aluminum oxide layer. Similarly, the second corrosion-resistant layer 222 can also include one or more of a silicon oxide layer, a silicon nitride layer, and an aluminum oxide layer. For example, the second corrosion-resistant layer 222 is a composite layer composed of a silicon nitride layer and an aluminum oxide layer.

[0075] The polysilicon layer 130 includes intrinsic polysilicon or doped polysilicon. When the polysilicon layer 130 is doped polysilicon, the reason for forming the doped polysilicon is that during the process of crystallizing the amorphous silicon layer 130-1, the doping element in the silicon substrate 110 diffuses into the amorphous silicon layer 130-1, and after the crystallization process, the amorphous silicon containing the doping element is converted into doped polysilicon. Note that during the crystallization process, the doping element in the silicon substrate 110 does not necessarily diffuse into the amorphous silicon layer 130-1. In some embodiments, the polysilicon layer 130 can include one or more of oxygen element, carbon element, and nitrogen element.

[0076] As shown in FIGS. 7 to 9, in step S130, a dielectric layer 140 is formed on the back surface 131 of the polysilicon layer 130. The dielectric layer 140 is SiN x , SiO x N y , SiO2, Al2O3, or any combination thereof. The dielectric layer 140 may contain a hydrogen element (H), and the hydrogen element may be from the raw materials used to form the dielectric layer 140.

[0077] In one embodiment, before performing step S130, texturing is performed on the front surface 112 so that the front surface 112 has a pyramid pile morphology. The second corrosion-resistant layer 222 in FIG. 7 may be used to protect the polysilicon layer 130 from etching during the texturing process. Specifically, the chemical solution (e.g., an alkaline chemical solution) used in the texturing process step has an etching effect on polysilicon and no or a weak etching effect on the second corrosion-resistant layer 222. Therefore, the second corrosion-resistant layer 222 can protect the polysilicon layer 130 from etching. Note that in FIG. 7, since it is a cross-sectional view of a partial structure, no corrosion-resistant layer is formed on the side surfaces of the silicon substrate 110 and the polysilicon layer 130.

[0078] In one embodiment, after performing a crystallization process step on the amorphous silicon layer 130-1 and before performing the texturing process step, a dielectric layer 140 is formed on the side of the polysilicon layer 130 away from the silicon substrate 110, i.e., the back surface of the second corrosion-resistant layer 222. In this way, during the texturing process, both the dielectric layer 140 and the second corrosion-resistant layer 222 protect the polysilicon layer 130 from etching by the chemical solution.

[0079] As shown in FIGS. 8 and 9, in one embodiment, a passivation antireflection layer 190 may also be formed on the front surface 112 of the silicon substrate 110.

[0080] As shown in FIGS. 10 to 12, in step S140, a first electrode 150 and a second electrode 160 that penetrate the dielectric layer 140 and contact the polysilicon layer 130 are formed. The first electrode 150 has a first type of doping element, and the second electrode 160 has a second type of doping element.

[0081] Specifically, as shown in FIGS. 9 and 10, the dielectric layer 140 is subjected to an opening process to form a first opening 230 and a second opening 240. The first opening 230 and the second opening 240 expose the polysilicon layer 130. In FIG. 10, the first opening 230 extends into the interface between the polysilicon layer 130 and the dielectric layer 140, and the second opening 240 also extends into the interface between the polysilicon layer 130 and the dielectric layer 140. In other words, the first opening 230 and the second opening 240 expose the back surface 131 of the polysilicon layer 130. In some other embodiments, the first opening 230 may also extend into the polysilicon layer 130, and the first opening 230 may also extend into the polysilicon layer 130. The first opening 230 may be a dot-shaped opening or a line-shaped opening. The second opening 240 may be a dot-shaped opening or a line-shaped opening. The "dot-shaped opening" means that when looking at the opening from the bottom to the top in FIG. 10, the opening is dot-shaped. For example, the dot shape may be circular or rectangular. The "line-shaped opening" means that when looking at the opening from the bottom to the top in FIG. 10, the opening is elongated.

[0082] Next, as shown in FIGS. 10 and 11, a first electrode 150 is formed in the first opening 230, and a second electrode 160 is formed in the second opening 240. In one embodiment, the first electrode 150 includes an upper first electrode 151 and a lower first electrode 152. The upper first electrode 151 is located within the first opening 230 and is in contact with the polysilicon layer 130. The lower first electrode 152 is in contact with the upper first electrode 151 and is located on the back surface 141 of the dielectric layer 140. The second electrode 160 includes an upper second electrode 161 and a lower second electrode 162. The upper second electrode 161 is located within the second opening 240 and is in contact with the polysilicon layer 130. The lower second electrode 162 is in contact with the upper second electrode 161 and is located on the back surface 141 of the dielectric layer 140.

[0083] As shown in FIGS. 11 and 12, in step S150, a first doping region 170 and a second doping region 180 are formed. Specifically, as described above, the first electrode 150 includes a first type of doping element, and the first type of doping element may be a P-type doping element or an N-type doping element. The second electrode 160 includes a second type of doping element, and the second type of doping element may be a P-type doping element or an N-type doping element. The doping type of the first type of doping element is opposite to the doping type of the second type of doping element. In other words, when the first type of doping element is a P-type doping element, the second type of doping element is an N-type doping element, and when the first type of doping element is an N-type doping element, the second type of doping element is a P-type doping element.

[0084] The first electrode 150 is heat-treated to diffuse the first type of doping element in the first electrode 150 into the polysilicon layer 130 and the silicon substrate 110, thereby forming a first doping region 170. Similarly, the second electrode 160 is heat-treated to diffuse the second type of doping element in the second electrode 160 into the polysilicon layer 130 and the silicon substrate 110, thereby forming a second doping region 180. The above heat treatment method includes heat treatment using a laser beam.

[0085] As shown in FIG. 12, the first doping region 170 starts from the first electrode 150 and extends into the silicon substrate 110, and the second doping region 180 starts from the second electrode 160 and extends into the silicon substrate 110. In one embodiment, the width of the first doping region located in the silicon substrate 110 is equal to or greater than the width of the first doping region located in the polysilicon layer 130, and the width of the first doping region located in the polysilicon layer 130 is equal to or greater than the width of the contact portion between the first electrode 150 and the polysilicon layer 130. Similarly, the width of the second doping region located in the silicon substrate 110 is equal to or greater than the width of the second doping region located in the polysilicon layer 130, and the width of the second doping region located in the polysilicon layer 130 is equal to or greater than the width of the contact portion between the second electrode 160 and the polysilicon layer 130. In an embodiment, the minimum distance between the first doping region 170 and the second doping region 180 is 30 μm or more. For details of this part, reference can be made to the related part described above, so it will not be mentioned here.

[0086] As shown in FIG. 12, in one embodiment, the manufacturing method of the present application further includes a hydrogenation treatment of the solar cell. Specifically, the dielectric layer 140 is annealed so that the hydrogen element in the dielectric layer 140 diffuses into the silicon substrate 110. During the annealing process, the hydrogen element in the dielectric layer 140 diffuses into the polysilicon layer 130 and the tunneling layer 120, and further diffuses into the silicon substrate 110. The hydrogen element can neutralize the defects in the polysilicon layer 130 and the silicon substrate 110, and can reduce the carrier recombination. As described above, since the dielectric layer 140 of the present application contains a hydrogen element, when the dielectric layer 140 is hydrogenated, it is not necessary to provide an additional hydrogen source (for example, a gas containing a hydrogen element), and the cost due to the additional hydrogen source can be saved.

[0087] FIGS. 13 to 17 are schematic cross-sectional views of intermediate products in the manufacturing process of a solar cell by a manufacturing method of a solar cell in other embodiments. Here, the processing procedures up to FIG. 13 are similar to FIGS. 5 to 7, and related contents can be referred to FIGS. 5 to 7. As shown in FIGS. 13 to 17, before forming the dielectric layer 140, a separation groove 210 is formed between the first doping region 170 and the second doping region 180, and this separation groove 210 penetrates at least to a preset depth within the polysilicon layer 130.

[0088] Specifically, as shown in FIG. 13, a separation groove 210 penetrating the polysilicon layer 130 and the tunneling layer 120 is formed, and the bottom surface 211 of the separation groove 210 is located within the silicon substrate 110. In some other embodiments, the separation groove 210 may not penetrate the tunneling layer 120 and may only penetrate the polysilicon layer 130. The separation groove 210 may not penetrate the polysilicon layer 130 and may also penetrate to a preset depth within the polysilicon layer 130. For the details of this part, the foregoing description can be referred to, and thus will not be elaborated here.

[0089] As shown in FIGS. 13 and 14, a dielectric layer 140 is formed. The dielectric layer 140 covers the back surface 131 of the polysilicon layer 130, the bottom surface and the side surfaces of the isolation groove 210. A passivation antireflection layer 190 can also be formed on the front surface 112 of the silicon substrate 110.

[0090] As shown in FIG. 15, a first opening 230 and a second opening 240 that penetrate the dielectric layer 140 are formed. Both the first opening 230 and the second opening 240 expose the polysilicon layer 130. As shown in FIGS. 15 and 17, a first electrode 150 is formed in the first opening 230, and a second electrode 160 is formed in the second opening 240. As shown in FIGS. 16 and 17, the first electrode 150 is heat-treated to form a first doping region 170. The second electrode 160 is heat-treated to form a second doping region 180. For the details of FIGS. 15 to 17, reference can be made to the foregoing description of FIGS. 10 to 12, so they will not be elaborated here.

[0091] The method for forming the isolation groove is not limited to the above embodiments. Here, a method for forming the isolation groove in another embodiment is provided.

[0092] First, as shown in FIG. 18, an initial isolation groove 210-1 is formed. The initial isolation groove 210-1 penetrates the second corrosion-resistant layer 222 and exposes the polysilicon layer 130. The initial isolation groove 210-1 can be formed using a laser beam. It should be understood that the initial isolation groove 210-1 is located between the first doping region and the second doping region formed in subsequent process steps.

[0093] Next, as shown in FIG. 19, the front surface 112 of the silicon substrate 110 is subjected to a texturing process. During this texturing process, the polysilicon layer 130 exposed from the initial isolation groove 210-1 is etched by, for example, a chemical solution used in the texturing process, thereby increasing the depth of the initial isolation groove 210-1, and finally the isolation groove 210 is obtained.

[0094] In the process of forming the initial isolation groove 210-1 using laser light, the laser light damages the polysilicon layer 130 exposed from the initial isolation groove 210-1. Similarly, when directly forming the isolation groove 210 using laser light, the laser light damages the polysilicon layer 130 exposed by the isolation groove 210. When the solar cell operates, the damage caused by the laser becomes a carrier recombination center, reducing the efficiency of the solar cell. In order to remove the damage to the polysilicon layer 130 caused by the laser, in the present application, first the initial isolation groove 210-1 is formed, and then the initial isolation groove 210-1 is etched with a chemical solution used in the texturing process step, thereby increasing the depth of the initial isolation groove 210-1. At the same time, the chemical solution removes the damage to the polysilicon layer 130 caused by the laser, removes the damage to the polysilicon layer 130 caused by the laser, and can improve the efficiency of the solar cell. In addition, forming the isolation groove 210 by etching the initial isolation groove 210-1 with a chemical solution used in the texturing process step has another advantage. That is, compared with the case of directly forming the isolation groove 210 using a laser, the method of forming the isolation groove 210 in the present application has a smaller depth of the initial isolation groove 210-1 than the depth of the isolation groove 210, so the laser usage time can be shortened. Thus, the method of forming the isolation groove 210 as described above in the present application can reduce the laser cost and shorten the formation time of the isolation groove 210.

[0095] As shown in connection with FIGS. 9, 18, and 19, in some embodiments, the dielectric layer 140 may be formed on the back surface of the second corrosion-resistant layer 222 before performing texturing on the front surface 112. Specifically, the dielectric layer 140 can be formed before forming the initial isolation groove 210-1. In this case, the initial isolation groove 210-1 penetrates through the dielectric layer 140 and the second corrosion-resistant layer 222. The dielectric layer 140 can also be formed on the back surface of the second corrosion-resistant layer 222 after forming the initial isolation groove 210-1 and before performing texturing on the front surface 112.

[0096] As shown in FIG. 19, the bottom surface 211 of the separation groove 210 has a pyramid pile morphology. This is because a texturing process is performed on the surface 112, and at the same time, a texturing process is also performed on the silicon substrate 110 exposed from the bottom surface 211.

[0097] In the above, the basic concepts have been described. However, it is obvious to those skilled in the art that the above disclosure is only an example and does not limit the present application. Although not specified here, those skilled in the art may make various modifications, improvements, and corrections to the present application. Such modifications, improvements, and corrections are proposed in the present application and belong to the spirit and scope of the exemplary embodiments of the present application.

[0098] At the same time, the present application uses specific terms to describe the embodiments of the present application. For example, "one embodiment", "an embodiment", and / or "some embodiments" mean features, configurations, or characteristics related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that the "one embodiment" or "one embodiment" or "one alternative embodiment" mentioned more than twice in different places in this specification does not necessarily mean the same embodiment. Furthermore, some features, configurations, or characteristics in one or more embodiments of the present application can be appropriately combined.

[0099] Similarly, in order to facilitate the understanding of one or more embodiments of the invention, note that in the foregoing description of the embodiments of the present application, for the purpose of simplifying the expressions disclosed in this specification, multiple features may be integrated into one embodiment, drawing, or their descriptions. However, this disclosure method does not mean that there are more features required for the subject matter of the present application than those described in the claims. In fact, the features of the embodiments are fewer than all the features of the single embodiment disclosed above.

[0100] In some embodiments, numbers are used to describe the number of components and attributes. However, it should be understood that the numbers used to describe such embodiments may, in some instances, be modified using modifiers such as "about", "substantially", or "approximately". Unless otherwise specified, "about", "substantially", or "approximately" means that the numerical value allows for a variation of ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, and these approximate values may be changed according to the characteristics required by individual embodiments. In some embodiments, numerical parameters should consider a predetermined number of significant digits and adopt a general method for maintaining the number of digits. In some embodiments of the present application, the numerical fields and parameters used to confirm the scope are approximate values. However, in a specific embodiment, the setting of such numerical values is as accurate as possible within the possible range.

[0101] The present application is described with reference to current specific embodiments. However, the above embodiments are for explaining the present application, and various equivalent changes or substitutions can be made without departing from the spirit of the present application. Therefore, as long as it is within the substantial spirit scope of the present application, the changes and modifications of the above embodiments are included within the scope of the claims of the present application.

Description of Reference Numerals

[0102] 110 Silicon substrate 120 Tunneling layer 130 Polysilicon layer 140 Dielectric layer 150 First electrode 160 Second electrode 170 First doping region 180 Second doping region 210 Isolation groove

Claims

1. A silicon substrate; a tunneling layer and a polysilicon layer sequentially formed on a rear surface of the silicon substrate; a dielectric layer formed on a back surface of the polysilicon layer; a first electrode and a second electrode extending through the dielectric layer and contacting the polysilicon layer; a first doped region originating from the first electrode and extending into the silicon substrate, and a second doped region originating from the second electrode and extending into the silicon substrate; an isolation trench located between the first doped region and the second doped region and extending at least to a predetermined depth into the polysilicon layer; Equipped with a width of a first doping region located on the silicon substrate is equal to or greater than a width of a first doping region located on the polysilicon layer, the width of the first doping region located on the polysilicon layer is equal to or greater than a width of a contact portion between the first electrode and the polysilicon layer, a width of a second doping region located on the silicon substrate is equal to or greater than a width of a second doping region located on the polysilicon layer, and a width of the second doping region located on the polysilicon layer is equal to or greater than a width of a contact portion between the second electrode and the polysilicon layer, the polysilicon layer is formed on a back surface of the tunneling layer, and the first electrode and the second electrode are heat-treated to form the first doping region and the second doping region in the same polysilicon layer, and the polysilicon separated between the first doping region and the second doping region is intrinsic polysilicon.

2. 2. The solar cell of claim 1, wherein the tunneling layer comprises one or more of silicon dioxide, silicon nitride, silicon oxynitride, and aluminum oxide, and the polysilicon layer comprises intrinsic polysilicon.

3. 3. The solar cell according to claim 2, wherein the minimum distance between the first doped region and the second doped region is 30 [mu]m or more.

4. 2. The solar cell according to claim 1, wherein the polysilicon layer contains at least one of an oxygen element, a carbon element, and a nitrogen element.

5. The solar cell according to claim 1 , wherein the dielectric layer covers a bottom surface and a side wall of the isolation groove.

6. 2. The solar cell of claim 1, wherein the dielectric layer comprises one or more of silicon dioxide, silicon nitride, silicon oxynitride, and aluminum oxide.

7. 2. The solar cell of claim 1, wherein the predetermined depth is equal to or greater than half the thickness of the polysilicon layer, or the isolation trench penetrates the polysilicon layer, or the isolation trench penetrates the polysilicon layer and the tunneling layer.

8. 2. The solar cell of claim 1 , wherein the first electrode comprises the same doping element as the first doping region, and the second electrode comprises the same doping element as the second doping region.

9. 2. The solar cell according to claim 1, wherein the bottom surface of the separation groove has a pyramidal pile shape.

10. 10. The solar cell of claim 1, further comprising a passivation layer formed on a front surface of the silicon substrate.

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