Bonded memory device and fabrication method thereof

Abstract

To disclose embodiments of a three dimensional (3D) memory device formed by a bonded semi-conductor device and a method for forming the three dimensional (3D) memory device.SOLUTION: In one example, a method for forming a bonded semi-conductor device includes the following operations. First, a first wafer and a second wafer are formed. The first wafer may comprise a functional layer over a substrate. Single crystal silicon may not be essential to the substrate, and the substrate may not include single crystal silicon. The first wafer may be inverted to bond to the second wafer to form a bonded semiconductor device, such that the substrate is above the functional layer. At least a portion of the substrate may be removed to form a top surface of the bonded semiconductor device. Further, bond pads may be formed over the top surface.SELECTED DRAWING: Figure 2D

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a bonded three-dimensional (3D) memory device and a method of fabricating the same.

Background Art

[0002] Planar memory cells are scaled down to a smaller size by improving process technology, circuit design, program algorithms, and fabrication processes. However, as the shape dimensions of the memory cells approach the lower limit, planar processes and fabrication techniques become difficult and costly. As a result, the storage density for planar memory cells approaches the upper limit.

[0003] A 3D memory structure can address the density limitations in planar memory cells. A 3D memory structure includes a memory array and a peripheral device for controlling signals traveling between the memory arrays.

Summary of the Invention

Means for Solving the Problems

[0004] Embodiments of a method and structure for forming a wafer, and a method and structure for forming a bonded semiconductor structure with the wafer are disclosed herein.

[0005] In one example, a method for forming a bonded semiconductor device is disclosed. The method includes the following operations. First, a first wafer and a second wafer are formed. The first wafer may include a functional layer over a substrate. In one example, single crystal silicon is not essential for the substrate. The first wafer may be inverted to bond to the second wafer to form a bonded semiconductor device such that the substrate is on top of the functional layer. At least a portion of the substrate may be removed to form an upper surface of the bonded semiconductor device. Further, bonding pads may be formed over the upper surface.

[0006] In another example, a method for forming a semiconductor device is disclosed. The method includes the following operations. First, an insulating material layer can be formed across a substrate. In one example, single-crystalline silicon is not essential for the substrate. The insulating material layer can be patterned to form a isolation structure and a plurality of trenches in the isolation structure. A semiconductor material can be deposited to fill the plurality of trenches and form a plurality of array base regions in the isolation structure, and the isolation structure insulates the plurality of array base regions from each other. Further, a plurality of memory arrays can be formed across the plurality of array base regions, and an insulating structure can be formed to cover the plurality of memory arrays and the plurality of array base regions.

[0007] In yet another example, a method for forming a semiconductor device is disclosed. The method includes the following operations. First, an insulating material layer can be formed across a substrate. In one example, single-crystalline silicon is not essential for the substrate. A semiconductor material layer can be formed across the insulating material layer. The semiconductor material layer can be patterned to remove a portion of the semiconductor material layer, expose another insulating material layer, and form a plurality of array base regions. The same material as the insulating material layer can be deposited to fill the space formed by the removed portion of the semiconductor material layer, connect with the insulating material layer, and form a isolation structure. A plurality of memory arrays can be formed across the plurality of array base regions, and an insulating structure can be formed to cover the plurality of memory arrays and the plurality of array base regions.

[0008] In a further example, a bonded semiconductor device is disclosed. The bonded semiconductor device includes a functional layer across a wafer. The functional layer can include a plurality of array base regions in an insulating structure that are connected to a plurality of memory arrays across the plurality of memory arrays. The dimension of the upper surface of each of the plurality of array base regions can be different from the dimension of the lower surface. The functional layer can also include a isolation structure that covers the plurality of array base regions and insulates them from each other.

[0009] In different examples, wafers are disclosed. The wafer may comprise a functional layer across a substrate. The functional layer may comprise a separation structure across the substrate. The separation structure can surround a plurality of array base regions and insulate them from each other. The wafer may also comprise a plurality of memory arrays across the plurality of array base regions. The dimensions of the upper surface of each of the plurality of array base regions may be different from the dimensions of the lower surface. The wafer may further comprise an insulating structure covering the plurality of memory arrays and the plurality of array base regions, and a plurality of interconnect structures within the insulating structure across the plurality of memory arrays.

[0010] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure and to enable those skilled in the art to practice and use the present disclosure.

Brief Description of the Drawings

[0011]

Figure 1A

Figure 1B

Figure 1C

Figure 1D

Figure 2A

Figure 2B

Figure 2C

Figure 2D

Figure 3A

Figure 3B

DETAILED DESCRIPTION OF THE INVENTION

[0012] Embodiments of the present disclosure are described with reference to the accompanying drawings.

[0013] Specific configurations and arrangements are considered, but it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure can be adopted in various other applications.

[0014] In this specification, references to "an embodiment", "embodiments", "exemplary embodiments", "some embodiments", etc. mean that the disclosed embodiments may include specific features, structures, or characteristics, but not all embodiments necessarily include those specific features, structures, or characteristics. Further, such language does not necessarily refer to the same embodiment. Moreover, when specific features, structures, or characteristics are described in connection with an embodiment, whether explicitly described or not, it is within the knowledge of those skilled in the art to implement such features, structures, or characteristics in connection with other embodiments.

[0015] Generally, technical terms can be understood, at least in part, from their use in context. For example, as used herein, the term "one or more" can be used, at least in part, depending on the context, to describe any feature, structure, or property in the singular sense, or to describe a combination of features, structures, or properties in the plural sense. Similarly, terms such as "one" or "the" can be understood, at least in part, depending on the context, to convey either a singular or a plural use. Also, the term "based on" should not necessarily be understood to convey an exclusive set of factors, but rather, here too, at least in part, depending on the context, it can allow for the presence of additional factors that are not necessarily explicitly recited.

[0016] As used in this disclosure, the meanings of "on," "above," and "across" should be interpreted in a broad sense such that "on" means not only that something is "directly on top of" something else, but also that it is "on top of" something with intervening features or layers in between, and that "above" or "across" means not only that something is "above" or "across" something else, but also that it is "above" or "across" something directly (i.e., directly on top of something) without intervening features or layers in between.

[0017] Furthermore, spatially relative terms such as "under," "below," "beneath," "above," "over," etc. may be used herein for ease of explanation to describe the relationship of one element or feature to another element or feature, as shown in the figures. Spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatially relative descriptions used herein may be interpreted accordingly.

[0018] As used herein, the term "substrate" refers to a material onto which subsequent material layers are added. The substrate itself can be patterned. The material added on the substrate can be patterned or can remain unpatterned. Further, the substrate can include a wide variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as a glass, plastic, or sapphire wafer.

[0019] As used herein, the term "layer" refers to a portion of material that includes a region with thickness. A layer can extend across the entire underlying or overlying structure, or can have an extent less than the extent of the underlying or overlying structure. Further, a layer can be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer can be positioned between any pair of horizontal planes, between the top and bottom surfaces of a continuous structure, or on such top and bottom surfaces. A layer can extend laterally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers, and / or can have one or more layers on it, above it, and / or below it. A layer can include a plurality of layers. For example, an interconnect layer can include one or more conductors and layers of contacts (wherein interconnecting lines and / or via contacts are formed), and one or more dielectric layers.

[0020] As used herein, the term "nominal" refers to the desired value or target value of a characteristic or parameter for a component or process operation that is set together with a range of values above and / or below the desired value during aspects of the design of a product or during a process. The range of values may be due to some variation or tolerance in the manufacturing process. As used herein, the term "about" indicates a value of a given quantity that may vary based on the specific technology node associated with the subject semiconductor device. Based on the specific technology node, the term "about" may indicate a value of a given quantity that varies within, for example, 10 - 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0021] As used herein, the term "3D memory device" refers to a semiconductor device that includes vertically oriented strings of memory cell transistors (referred to herein as "memory strings" such as NAND memory strings) in a laterally oriented substrate such that the memory strings extend vertically with respect to the substrate. As used herein, the term "vertical" means nominally perpendicular to the side surface of the substrate. As used herein, the x-axis and y-axis (not shown) can each represent a horizontal direction and can be in a horizontal plane. The z-axis can represent the vertical direction and can be perpendicular to the horizontal plane. The y-axis is perpendicular to the x-z plane.

[0022] As used herein, the term "wafer" refers to a structure or device that can include any suitable components, such as one or more substrates and various functional components within or on the substrate (e.g., memory arrays, peripheral circuits, semiconductor devices, interconnects, insulating structures, bonding pads, and / or wiring). For example, an array-formed wafer refers to a structure that includes a substrate and a memory array formed across the substrate, a periphery-formed wafer refers to a structure that includes a substrate and a peripheral circuit formed across the substrate, and a bonding wafer refers to a structure / device formed by bonding two wafers (e.g., an array-formed wafer and a periphery-formed wafer) or any two suitable devices / structures. The term "wafer" does not indicate the form or function of the structure / device in the description.

[0023] In the fabrication of 3D memory devices, the memory array and the peripheral circuit can be formed on different wafers and can be bonded to form a bonding wafer. The memory array and the peripheral circuit can be formed simultaneously and then bonded to form a bonded memory device. This approach can have several advantages. First, it can be made such that the peripheral circuit is less affected by the manufacturing process of the memory array (e.g., chemical and thermal processes used in manufacturing). The fabrication of the peripheral circuit can achieve a higher yield, and the performance of the peripheral circuit can be improved. Also, the peripheral circuit and the memory array do not need to be formed on the same wafer, and thus, more space can be used to form each of the memory array and the peripheral circuit. Therefore, the storage density can be kept small enough to avoid the complexity caused by the large storage density in the bonded memory device. Further, the memory array and the peripheral circuit can be fabricated either at the same time or at different times, enhancing the flexibility of fabrication. For example, the memory array and the peripheral circuit can be fabricated simultaneously and then integrally bonded to form a bonded memory device, shortening the time for the overall manufacturing process.

[0024] However, the manufacturing process for forming a bonded memory device may require two or more wafers each including a single crystal substrate. The cost of the single crystal substrate may increase the manufacturing cost for forming the bonded memory device.

[0025] Various embodiments according to the present disclosure provide a structure of a wafer for forming a bonded memory device and a manufacturing method for forming the structure and the bonded memory device. The disclosed structure and method solve the above problems related to the increase in manufacturing cost. For example, by replacing the single crystal substrate of the wafer for forming a memory array with a suitable low-cost substrate (e.g., a lower-cost substrate), the cost of the manufacturing process for forming the bonded memory device can be reduced. On the other hand, the memory array can be formed across a polycrystalline silicon region on the low-cost substrate to ensure the desired functions of the memory array. The low-cost substrate can be completely removed or partially removed (e.g., thinned or planarized) after the wafer for forming the memory array and the wafer for forming the peripheral circuit are integrally bonded, with little or no impact on the bonded memory device. Other devices and / or structures may be formed across the bonded memory device after the complete removal / partial removal of the low-cost substrate. Therefore, the manufacturing cost for forming the bonded memory device can be reduced without impairing the functions of the bonded memory device.

[0026] Each of FIGS. 1A to 1D shows an exemplary array-forming wafer (e.g., a wafer for forming a memory array) at different stages of a manufacturing process according to an embodiment of the present disclosure. Each of FIGS. 2A to 2D shows the structure of a bonding wafer at different stages of a manufacturing process according to an embodiment of the present disclosure. The bonding wafers shown in FIGS. 2A to 2D can be formed with the array-forming wafers shown in FIGS. 1B and 1C. FIG. 3A shows an exemplary manufacturing process 300 for forming the array-forming wafer shown in FIGS. 1A to 1D. FIG. 3B shows an exemplary manufacturing process 310 for forming the bonding wafer shown in FIGS. 2A to 2D.

[0027] As shown in FIG. 3A, at the beginning of the manufacturing process, a base material layer can be formed across the substrate (operation 3001). FIG. 1A shows the corresponding structure 100.

[0028] As shown in FIG. 1A, the base material layer 103 can be formed across the substrate 101. The substrate 101 can comprise any suitable substrate having a top surface with sufficient rigidity, smoothness, and uniformity. The substrate 101 can include a material that is easy to remove (e.g., easy to peel, etch, and / or planarize). In some embodiments, the substrate 101 includes a material that is of lower cost, commonly used, and / or easier to fabricate. In some embodiments, the substrate 101 does not include single-crystalline silicon. For example, the substrate 101 can include polycrystalline silicon, amorphous silicon, a mixture of polycrystalline silicon and amorphous silicon, a compound substrate, a polymer substrate, glass, quartz, graphene, or a combination thereof. The base material layer 103 can include any suitable material that can provide electrical insulation between the functional components of the array-forming wafer 100. For example, the base material layer 103 can include silicon oxide (SiO), silicon nitride (SiN), and / or silicon oxynitride (SiON). In some embodiments, the base material layer 103 includes silicon oxide. The base material layer 103 can have a thickness d1 along a direction perpendicular to the top surface of the substrate 101 (e.g., the vertical direction or the z-axis). In some embodiments, to hold a sufficient portion of the base material layer 103 across the substrate 101 to provide insulation between different components, the thickness d1 is from about 1 μm to about 5 μm, such as between 1 μm and about 5 μm. In some embodiments, the thickness d1 is between about 1.5 μm and about 3 μm, such as between 1.5 μm and 3 μm (e.g., 1.5 μm, 1.8 μm, 2 μm, 2.5 μm, 3 μm, any range defined by a lower bound by any of these values, or any range defined by any two of these values).

[0029] In some embodiments, the array-forming wafer 100 includes a liner layer 102 positioned between the substrate 101 and the base material layer 103. The liner layer 102 may have a single-layer structure or a multi-layer structure. The liner layer 102 can provide a foundation for the formation of the base material layer 103. For example, the base material layer 103 and the substrate 101 may have different structures and / or different materials. To improve the adhesion between the base material layer 103 and the substrate 101, to improve the surface conditions of the substrate 101 for the deposition of the base material layer 103, and / or to reduce the stress in the base material layer 103, the liner layer 102 can be formed across the substrate 101 and the base material layer 103 can be formed across the liner layer 102. Thus, the base material layer 103 can be deposited across the substrate 101 in a state with improved uniformity and stability. The liner layer 102 can include any material that can improve the adhesion and growth conditions of the base material layer 103 across the substrate 101. For example, when the base material layer 103 includes silicon oxide, the liner layer 102 can include titanium nitride and / or titanium. The material composition of the liner layer 102 can depend on the selection of the materials of the substrate 101 and the base material layer 103. In some embodiments, the liner layer 102 has a multi-layer structure having one or more materials. In one example, the multi-layer structure can gradually change the surface structure on which the base material layer 103 is deposited, further improving the growth of the base material layer 103. The specific structure and properties of the liner layer 102 should be determined based on the materials of the substrate 101 and the base material layer 103 and should not be limited by the embodiments of the present disclosure.

[0030] The base material layer 103 and the liner layer 102 can be formed by any suitable deposition method such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and / or atomic layer deposition (ALD). In some embodiments, a substrate 101 is provided and a cleaning process is performed to remove radicals or contaminants on the upper surface of the substrate 101. Next, the liner layer 102 and the base material layer 103 can be continuously deposited over the upper surface of the substrate 101. In some embodiments, the liner layer 102 contains titanium oxide and is formed by ALD. In some embodiments, the base material layer 103 contains silicon oxide and is formed by CVD. Optionally, a surface planarization process is performed over the base material layer 103 to form other structures / devices (e.g., memory arrays) over the base material layer 103 later. The planarization process can include one or more of a recess etching process (dry / wet etching) and chemical mechanical polishing (CMP).

[0031] Referring to FIG. 3A, after the base material layer is formed over the substrate, a shallow trench isolation (STI) structure can be formed based on the base material layer, and an array base region can be formed in the STI structure. A memory array can be formed over the array base region. An insulating structure can be formed to cover the memory array and the array base region, and an interconnect structure can be formed in the insulating structure (operation 3002). Each of FIGS. 1B and 1C shows the corresponding structures 110 and 120.

[0032] As shown in FIG. 1B, one or more array base regions 111 can be formed in the STI structure 113 to provide a basis for the formation of the memory array 112. One or more memory arrays 112 can be formed across the array base region 111. In some embodiments, the thickness / depth d2 of the array base region 111 along the vertical direction (e.g., z-axis) is in the range of about 1 μm to about 3 μm, such as between 1 μm and 3 μm. In some embodiments, the thickness / depth d2 is between about 1.2 μm and about 2.5 μm, such as between 1.2 μm and 2.5 μm (e.g., 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.5 μm, any range defined by the lower bound by any of these values, or any range defined by any two of these values). In some embodiments, the distance d3 from the bottom of the array base region 111 to the liner layer 102 (or the substrate 101 if the liner layer 102 is not formed) is in the range of about 1 μm to about 2 μm, such as between 1 μm and 2 μm. In some embodiments, the distance d3 is between about 1.2 μm and about 1.8 μm, such as between 1.2 μm and 1.8 μm (e.g., 1.2 μm, 1.5 μm, 1.8 μm, any range defined by the lower bound by any of these values, or any range defined by any two of these values). An insulating structure 115 can be formed to cover the memory array 112 and the array base region 111, so that the memory arrays 112 are within the insulating structure 115 and can be electrically insulated from each other. One or more interconnect structures 114 can be formed in the insulating structure 115 to connect the desired devices / structures to each other or to connect the memory array 112 to other devices / structures.

[0033] Each array base region 111 can be surrounded and an STI structure 113 can be formed by a portion of the base material layer 103 that insulates the array base region 111 from each other and from the substrate 101, for example. The array base region 111 can include a suitable material or a suitable structure that provides a foundation for the deposition and fabrication of the memory array 112. The array base region 111 can have sufficient rigidity, surface uniformity, and / or doping concentration for the proper operation of the memory array 112. For example, the array base region 111 can include a doped semiconductor material and can function as a well region. In some embodiments, the array base region 111 includes doped polycrystalline silicon (e.g., P-type or N-type), and the formation of the dopant polarity is determined, for example, by the formation of the polarity of the source electrode of the memory array 112. In some embodiments, the array base region 111 includes P-type polycrystalline silicon.

[0034] The STI structure 113 can be formed by a removed portion of the base material layer 103. The location of the removed portion of the base material layer 103 can correspond to the location of the array base region 111. Any suitable patterning / etching process can be implemented to form the STI structure 113. For example, a photoresist layer to be patterned can be formed over the base material layer 103. The patterned photoresist layer can include an opening that exposes the portion of the base material layer 103 to be removed. A suitable etching process (e.g., wet / dry etching) can be implemented to remove the exposed portion of the base material layer 103 and to form one or more trenches in the base material layer 103. The location of the trenches corresponds to the location of the memory array 112. In some embodiments, the etching time of the etching process is controlled such that a sufficient portion of the base material layer 103 can be retained between the bottom of the trenches and the upper surface of the substrate 101 / liner layer 102. The remaining portion of the base material layer 103 can form the STI structure 113.

[0035] The doped semiconductor material can be formed in the trench to form the array base region 111. In one example, polycrystalline silicon can be deposited to fill the trench. The polycrystalline silicon can be doped with a suitable dopant, for example, by an ion implantation process or an in-situ doping process. In some embodiments, P-type dopants such as boron, aluminum, indium, and / or gallium are doped into the polycrystalline silicon material to form the array base region 111. In some embodiments, the width Wt1 of the upper surface of the array base region 111 can be larger than the width Wb1 of the lower surface of the array base region 111 along the x-axis (or horizontal plane). Optionally, a surface planarization process is performed over the STI structure 113 and the array base region 111 to remove excess material from the formation of the array base region 111 and the STI structure 113. The upper surface of the planarized array base region 111 can have sufficient uniformity and / or smoothness to facilitate the subsequent formation of the memory array 112. The planarization process can include one or more of a recess etching process (dry / wet etching) and CMP. The slurry used for CMP can be determined based on, for example, the material composition and / or surface area / ratio of the array base region 111 and / or the STI structure 113. For example, the slurry can include a chemical mainly used to planarize the material of the STI structure 113 when the surface area of the array base region 111 is sufficiently small compared to the surface area of the STI structure 113 (e.g., less than a predetermined ratio), and vice versa.

[0036] The memory array 112 can be formed across the array base region 111. For illustrative purposes, one memory array 112 is shown as an example across the array base region 111 as shown in FIG. 1B. In various embodiments, the number of memory arrays formed across the array base region 111 is determined by the actual design / fabrication requirements. The memory array 112 can include any suitable device / structure in which memory cells are formed. For example, the memory array 112 can have one or more blocks extending along a direction parallel to the upper surface of the substrate (e.g., along a horizontal plane or an x-y plane), and each memory block can have a plurality of memory cells. The specific structure of the memory array 112 can be determined by different design / fabrication requirements.

[0037] The memory array 112 can be formed by any suitable process. In one example, a plurality of sacrificial material layers and a plurality of insulating material layers can be alternately deposited along the vertical direction over the STI structure 113 and the array base region 111 to form a stack structure. The sacrificial material layer and the insulating material layer have different material compositions and can have the same thickness or different thicknesses. A patterned photoresist layer can be formed over the stack structure to expose the portion of the stack structure to be removed. An appropriate etching process (dry / wet etching) can be performed to remove the exposed portion of the stack structure to expose the STI structure 113 and form an array stack in the array base region 111. Each array block can be subjected to repeated etching along the vertical direction (e.g., the z-axis) to form a staircase structure. The staircase structure can be formed, for example, by repeatedly forming an etching mask (e.g., a patterned photoresist layer) over each stack structure to expose the portions of the sacrificial material layer and the insulating material layer to be removed and removing the exposed portions. The etching mask can be repeatedly trimmed / etched to expose the portion of the stack structure to be removed. The sacrificial layer and the base material layer can be repeatedly formed by etching the sacrificial material layer and the insulating material layer. Next, a staircase structure can be formed. The semiconductor channels can be formed in the staircase structure so as to extend from the upper surface of the staircase structure to the array base region 111. For example, source electrodes can be formed in the staircase structure to divide the staircase structure into different memory blocks. Drain electrodes can be formed over the staircase structure. The gate electrode (e.g., functioning as a word line) can be formed by replacing the sacrificial layer with a suitable conductor layer such as tungsten, aluminum, cobalt, copper, and / or polycrystalline silicon (or a conductor layer each surrounded by a high-k dielectric layer such as an aluminum oxide layer and / or a silicon oxynitride layer). The alternately arranged conductor layers and the base material layer can be stacked along the vertical direction over the array base region 111. The intersection of the gate electrode and the semiconductor channel can form a memory cell.

[0038] To form semiconductor vias in a stepped structure, a plurality of via holes can be formed in respective stepped structures. The plurality of via holes can be formed by forming a photoresist layer to be patterned across the stepped structure. The patterned photoresist layer can include a plurality of openings that expose a portion of the stepped structure. The location of the exposed portion of the stepped structure can correspond to the location of the semiconductor via. An etching process can be performed to remove the portion of the stepped structure exposed by an opening for exposing the substrate 101. Via holes can be formed. Optionally, a recess etching process is performed to remove the portion of the substrate 101 exposed at the bottom of each via hole. Optionally, an appropriate deposition process is performed to form a semiconductor portion at the bottom of the via hole as part of each semiconductor via. The semiconductor portion can subsequently contact the formed via formation structure. The semiconductor portion can include an appropriate semiconductor material such as polycrystalline silicon, and the deposition process can include CVD, PVD, selective deposition, and / or ALD. The thickness of the semiconductor portion along the vertical direction can be controlled to have a desired range. For example, the upper surface of the semiconductor portion can be positioned between at least two conductor layers along the vertical direction. Optionally, a cleaning / recess etching process is performed to remove excess material of the semiconductor portion on the sidewalls of the via holes before the via formation structure fills the via holes.

[0039] After the semiconductor portion is formed in the vias, a via formation structure is formed to fill each via. The via formation structure can include, for example, a blocking layer, a memory layer, a tunnel layer, a semiconductor layer, and a dielectric core that are continuously deposited from the sidewalls of each via toward the center of the via. Each of the blocking layer, the memory layer, the tunnel layer, and the semiconductor layer may include a single-layer structure or a multi-layer structure. For example, the blocking layer may include a double-layer structure. The first blocking layer may include a dielectric metal oxide having a sufficiently large dielectric constant (e.g., greater than 7.9). Examples of the first blocking layer include AlO, hafnium oxide (HfO2), lanthanum oxide (LaO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), their silicates, their nitrogen-doped compounds, and / or their alloys. The first blocking layer can be formed by an appropriate deposition method such as chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), and / or liquid mist chemical deposition. In some embodiments, the first blocking layer includes AlO. The second blocking layer can be formed over the first blocking layer and may include a dielectric material different from the first blocking layer. For example, the second blocking layer may include silicon oxide, silicon oxynitride, and / or silicon nitride. In some embodiments, the second blocking layer includes silicon oxide and can be formed by any suitable conformal deposition method such as low-pressure CVD (LPCVD) and / or ALD.

[0040] The memory layer can include a charge trapping material and can be formed across the blocking layer. The memory layer can include a conductive material and / or a semiconductor such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, their alloys, their nanoparticles, their silicides, and / or a polycrystalline or amorphous semiconductor material (e.g., polycrystalline silicon and amorphous silicon). The memory layer can also include one or more insulating materials such as SiN and / or SiON. In some embodiments, the memory layer includes a SiN layer sandwiched by SiON layers, and the SiON layers are further sandwiched by SiN layers. The memory layer can be formed by any suitable deposition method such as CVD, ALD, and physical vapor deposition (PVD). The tunnel layer can be formed across the memory layer, can include a single-layer structure or a multi-layer structure, and can include SiO, SiN, SiON, a dielectric metal oxide, a dielectric metal oxynitride, a dielectric metal silicate, and / or their alloys. The tunnel layer can be formed by a suitable deposition method such as CVD, ALD, and / or PVD. In some embodiments, the tunnel layer includes a plurality of SiON layers and SiO layers, and the plurality of SiON layers are positioned between the memory layer 222 and the SiO layer.

[0041] The semiconductor layer can facilitate the transport of charges and can be formed across the tunnel layer. The semiconductor layer can include one or more semiconductor materials, such as a single-element semiconductor material, a III-V group compound semiconductor material, a II-VI group compound semiconductor material, and / or an organic semiconductor material. The semiconductor layer can be formed by any suitable deposition method, such as LPCVD, ALD, and / or metal-organic chemical vapor deposition (MOCVD). In some embodiments, the semiconductor layer includes a polycrystalline silicon layer. The dielectric core can include a suitable dielectric material and can fill the space surrounded by the semiconductor layer. In some embodiments, the dielectric core includes SiO (e.g., SiO with a sufficiently high purity) and can be formed by any suitable deposition method, such as CVD, LPCVD, ALD, and / or PVD. Optionally, a surface planarization process is performed across the stepped structure to remove excess material from the formation of the semiconductor channel. The planarization process can include one or more of a recess etching process (dry / wet etching) and CMP. In various embodiments, the different portions of the memory array 112 and the specific order of forming the structure of each portion can be determined by the requirements of design / fabrication and should not be limited by the embodiments of the present disclosure.

[0042] Next, an insulating structure 115 can be formed to cover the memory array 112 and the array base region 111 and to insulate the memory array 112 and the array base region 111 from other structures / devices. The insulating structure 115 can include any suitable dielectric material, such as silicon oxide, and can be formed by a suitable deposition process, such as CVD, PVD, and / or ALD. Optionally, a surface planarization process is performed across the insulating structure 115 to planarize the upper surface of the insulating structure 115. The planarization process can include one or more of a recess etching process (dry / wet etching) and CMP.

[0043] Various interconnect structures 114 can be formed in the insulating structure 115. For illustrative purposes, the interconnect structure 114 is depicted as a block in FIG. 1B. The interconnect structure 114 can represent any structure / device (e.g., metal interconnects, contacts, and / or plugs) that conductively couples the array - forming wafer 110 to other wafers / devices. For example, the interconnect structure 114 can represent a metal interconnect extending from the top surface of the insulating structure 115 to the memory array 112 (e.g., the gate electrode of the memory array 112). The interconnect structure 114 can include a suitable conductive material such as tungsten, cobalt, aluminum, and / or copper. In some embodiments, the interconnect structure 114 can be formed by patterning / etching the insulating structure 115 to form an opening that couples the top surface of the insulating structure 115 to a desired portion of the memory array 112, and filling the opening with a desired conductive material. The patterning / etching of the opening can be performed by any suitable etching process (e.g., wet / dry etching), and the formation of the conductive material can include any suitable deposition process such as CVD, PVD, sputtering, and / or ALD.

[0044] Each of FIGS. 1C and 1D shows another exemplary array - forming wafer at different stages of other fabrication processes according to some embodiments. The STI structure and the array base region of the array - forming wafer 130 can be formed differently compared to the structures and processes associated with the array - forming wafer 110. In some embodiments, the structures and fabrication processes of the memory array 132, the insulating structure 135, and the interconnect structure 134 in FIG. 1D can be the same or similar to those of the memory array 112, the insulating structure 115, and the interconnect structure 114 in FIG. 1B. The same or similar substrate 101 and liner layer 102 can be used to form the array - forming wafer 110.

[0045] As shown in FIG. 1C, the base material layer can be formed across the substrate 101 (e.g., or across the liner layer 102). Different from the structure 100, the base material layer in FIG. 1C can include an insulating layer 123 across the substrate 100 and an array base layer 121 across the insulating layer 123. The material composition of the insulating layer 123 can be the same as or similar to that of the base material layer 103, and the material composition of the array base layer 121 can be the same as or similar to that of the array base region 111. In some embodiments, the array base layer 121 includes polycrystalline silicon or doped polycrystalline silicon, and the insulating layer 123 includes silicon oxide. The thickness d4 of the array base layer 121 can be the same as or similar to the thickness / depth d2 of the array base region 111, and the thickness d5 of the insulating layer 123 can be the same as or similar to the distance d3. In some embodiments, the thickness d4 and / or the distance d5 can be other desirable values / ranges.

[0046] A patterning / etching process can be performed to form the array base region 131 across the insulating layer 123. For example, a photoresist layer to be patterned can be formed across the array base layer 121. The patterned photoresist layer can include an opening that covers the portion of the array base layer 121 to be retained to form the array base region 131 and exposes the portion of the array base layer 121 to be removed. A suitable etching process (e.g., wet / dry etching) can be performed to remove the exposed portion of the array base layer 121 to expose the insulating layer 123. The remaining portion of the array base layer 121 can form the array base region 131. In some embodiments, the width Wt2 of the upper surface of the array base region 131 can be smaller than the width Wb2 of the lower surface of the array base region 131 along the x-axis (or horizontal plane).

[0047] Furthermore, the insulating material can be deposited to fill the space formed by the removal of a portion of the array base layer 121 (e.g., between the array base regions 131 and on the exposed portions of the insulating layer 123). In some embodiments, the insulating material is the same as or similar to the material of the insulating layer 123 and can be formed by any suitable deposition process such as CVD, PVD, ALD, and / or selective deposition. The insulating material can be deposited to fill the space formed by the removal of a portion of the array base layer 121 and to connect with the insulating layer 123. The structure formed by the insulating layer 123 adjacent to the insulating material can form the initial STI structure 133. Optionally, a surface planarization process is performed across the STI structure 133 and the array base region 131 to remove excess material from the formation of the STI structure 133. The planarization process can include one or more of a recess etching process (dry / wet etching) and chemical mechanical polishing (CMP). The slurry used for CMP can be determined based on, for example, the material composition and / or surface area / ratio of the array base region 131 and / or the STI structure 133. For example, if the surface area of the STI structure 133 is small enough compared to the surface area of the array base region 131, the slurry can include chemicals mainly used to planarize the material of the array base region 131, and vice versa. Furthermore, the memory array 132, the insulating structure 135, and the interconnect structure 134 can be formed. For the formation of these structures, reference can be made to the description of the memory array 112, the insulating structure 115, and the interconnect structure 114.

[0048] The array-forming wafers 110 / 120 can be joined to other structures / devices via the interconnect structure 114. In some embodiments, the array-forming wafers 110 / 120 and the peripheral-forming wafers (e.g., the wafers on which the peripheral circuits for the operation of the memory device are formed) can be integrally joined to form a joined wafer. Control signals / data can be applied to the peripheral circuits of the peripheral-forming wafer to control the operation (e.g., reading, writing, and / or holding) of the memory array. FIGS. 2A-2D show exemplary steps for forming a joined wafer with the array-forming wafers 110 / 120 and the peripheral-forming wafers. For ease of viewing, an array-forming wafer similar or identical to the array-forming wafer 110 is depicted in FIGS. 2A-2D for explaining the manufacturing process.

[0049] As shown in FIG. 3B, at the beginning of the manufacturing process, the array-forming wafer and the peripheral-forming wafer can be provided (operation 3101). FIG. 2A shows the corresponding structures 200 and 210.

[0050] As shown in FIG. 2A, the array-forming wafer 200 and the peripheral-forming wafer 210 can be provided. The array-forming wafer 200 can be the same or similar to the array-forming wafer 110 shown in FIG. 1B. Specifically, the manufacturing processes and structures of the substrate 101, the liner layer 102, the STI structure 113, the array base region 111, the memory array 112, the insulating structure 115, and the interconnect structure 114 can be the same or similar to the manufacturing processes and structures of the first substrate 201, the liner layer 202, the STI structure 203, the array base region 204, the memory array 205, the first insulating structure 206, and the first interconnect structure 207, respectively.

[0051] The peripheral-forming wafer 210 can include any device / structure for operating the memory array 205 by applying a bias to the memory array 205. The peripheral-forming wafer 210 can include a second substrate 211, a device layer 215 formed across the second substrate 211, a second insulating structure 216 across the device layer 215, and a plurality of second interconnect structures 217 in the second insulating structure 216.

[0052] The second substrate 211 may comprise any suitable material for providing a fabrication foundation for the formation of the peripheral circuits. The second substrate 211 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable material. In some embodiments, the second substrate 211 is a thin substrate (e.g., a semiconductor layer) that has been thinned from its normal thickness by grinding, wet / dry etching, and / or CMP. In some embodiments, the second substrate 211 includes single crystal silicon.

[0053] The device layer 215 may represent any functional device / structure that forms the peripheral circuits in the peripheral formation wafer 210. For example, the device layer 215 may comprise digital, analog, and / or mixed signal peripheral circuits that are used to facilitate the operation of the formed memory devices. The second insulating structure 216 may cover the device layer 215 to provide insulation between the devices / structures of the device layer 215 and between the device layer 215 and other components of the peripheral formation wafer 210. The second insulating structure 216 may include any suitable dielectric material such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0054] The second interconnect structure 217 can be formed in the second insulating structure 216 and can be exposed to connect with the first interconnect structure 207. The second interconnect structure 217 can represent any structure / device (e.g., metal interconnects, contacts, and / or plugs) that conductively connects the peripheral formation wafer 210 to other wafers / structures. For example, the second interconnect structure 217 can represent a metal interconnect that extends from the top surface of the second insulating structure 216 to the device layer 215. The second interconnect structure 217 can include a suitable conductive material such as tungsten, cobalt, aluminum, and / or copper. In some embodiments, the second interconnect structure 217 can be formed by patterning / etching the second insulating structure 216 to form an opening that connects the top surface of the second insulating structure 216 to a desired portion of the device layer 215, and filling the opening with a desired conductive material. The patterning / etching of the opening can be performed by any suitable etching process (e.g., wet / dry etching), and the formation of the conductive material can include any suitable deposition process such as CVD, PVD, sputtering, and / or ALD. In some embodiments, the arrangement of the second interconnect structures in the second interconnect structure 217 (e.g., the dimensions of the second interconnect structures and the separation distance between the second interconnect structures) can match the arrangement of the first interconnect structure 207 such that each first insulating structure 206 can be joined to the corresponding second interconnect structure 217. Optionally, a surface planarization process is performed over the second insulating structure 216 and the second interconnect structure 217 to planarize the top surfaces of the second insulating structure 216 and the second interconnect structure 217. The planarization process can include one or more of a recess etching process (dry / wet etching) and CMP.

[0055] The array-forming wafer 200 and the peripheral-forming wafer 210 can be formed by different manufacturing processes (e.g., separate manufacturing processes). In some embodiments, the array-forming wafer 200 and the peripheral-forming wafer 210 share the same manufacturing operations in some manufacturing steps, such as, for example, the formation of the first interconnect structure 207 and the second interconnect structure 217, and / or a planarization process. The specific processes for forming the array-forming wafer 200 and the peripheral-forming wafer 210 should follow different design / manufacturing requirements and should not be limited by the embodiments of the present disclosure.

[0056] Referring to FIG. 3B, after the array-forming wafer and the peripheral-forming wafer are provided, one of the wafers is inverted (operation 3102) to be joined to the other wafer such that the first interconnect structure and the second interconnect structure are joined to each other. FIG. 2B shows the corresponding joined wafer 220.

[0057] As shown in FIG. 2B, the array forming wafer 200 can be inverted to be joined to the peripheral forming wafer 210. A joined wafer or a joined semiconductor device can be formed. That is, the joined semiconductor device includes two wafers (for example, the array forming wafer 200 and the peripheral forming wafer 210) joined together. Each first interconnect structure 207 can be joined to a corresponding second interconnect structure 217. An appropriate joining process can be performed to form a join between the array forming wafer 200 and the peripheral forming wafer 210. In some embodiments, the array forming wafer 200 and the peripheral forming wafer 210 are joined by a hybrid bond. In some embodiments, the hybrid bond joins the first interconnect structure 207 to the second interconnect structure 217 and joins the first insulating structure 206 to the second insulating structure 216. In some embodiments, pressure is applied to form a bond between the first insulating structure 206 and the second insulating structure 216, and heat is applied to form a bond between the first interconnect structure 207 and the second interconnect structure 217. In some embodiments, the surfaces of the first insulating structure 206, the second insulating structure 216, the first interconnect structure 207, and the second interconnect structure 217 have sufficient uniformity such that little or no space is formed between the first insulating structure 206 and the second insulating structure 216 and between the first interconnect structure 207 and the second interconnect structure 217 after the joining.

[0058] Referring back to FIG. 3B, after the array forming wafer and the peripheral forming wafer are joined together, at least a portion of the first substrate is removed (operation 3103). FIG. 2C shows the corresponding joined wafer 230.

[0059] As shown in FIG. 2C, at least a portion of the first substrate 201 is removed. The remaining portion of the array formation wafer 200 is referred to as the array formation wafer 200-2 that is bonded to the peripheral formation wafer 210 to form the bonding wafer 230. For illustrative purposes, the first substrate 201 is shown as being completely removed in FIG. 2C. In some embodiments, the first substrate 201 and the liner layer 202 are removed to expose the STI structure 203. In some embodiments, the STI structure 203 is planarized or subjected to recess etching such that the thickness T1 of the STI structure 203 along the vertical direction (e.g., the z-axis) ranges from about 1 μm to about 5 μm, such as between 1 μm and 5 μm. In some embodiments, the thickness T1 is between about 1.5 μm and about 3 μm, such as between 1.5 μm and 3 μm (e.g., 1.5 μm, 1.8 μm, 2 μm, 2.5 μm, 3 μm, any range defined by any of these values with the lower boundary determined, or any range defined by any two of these values). The portion of the STI structure 203 between the exposed surface and the bottom of the array base region 204 is thick enough to insulate the device / structure (e.g., the device / structure formed across the exposed surface of the STI structure 203) from the memory array 205. In some embodiments, T2 ranges from about 1 μm to about 2 μm, such as between 1 μm and 2 μm. In some embodiments, T2 is between about 1.2 μm and about 1.8 μm, such as between 1.2 μm and 1.8 μm (e.g., 1.2 μm, 1.5 μm, 1.8 μm, any range defined by any of these values with the lower boundary determined, or any range defined by any two of these values). In some embodiments, a portion of the first substrate 201 is retained across the STI structure 203, for example, during the formation of other subsequent devices / structures. The first substrate 201 can be referred to as "thin". The amount of material removed from the first substrate 201 should be determined according to different design / fabrication requirements and should not be limited by the embodiments of the present disclosure.

[0060] The removal of the first substrate 201 may include an etching process (e.g., wet / dry etching) and / or a CMP process. The etching solution and / or slurry selected to remove the first substrate 201 should be determined based on the material forming the first substrate 201. In some embodiments, the etching solution selectively etches the first substrate 201 down to the STI structure 203.

[0061] Referring back to FIG. 3B, after the first substrate is removed or thinned, other structures or devices can be formed across the top surface of the bonded wafer (operation 3104). FIG. 2D shows the corresponding bonded wafer 240.

[0062] As shown in FIG. 2D, other structures / devices such as one or more bonding pads 241 can be formed across the top surface of the bonded wafer 240. The bonding pads 241 can be used, for example, for wire bonding pads, protrusion attachment locations, and / or electrical connection locations. The bonding pads 241 can include any suitable material for various uses. For example, if the bonding pad 241 is a wire bonding pad, the bonding pad 241 can include a metal material such as aluminum, copper, and / or gold. The bonding pads 241 can be formed by any suitable method, such as depositing a layer of the desired bonding material across the bonded wafer 240 (e.g., by CVD, sputtering, PVD, electron beam evaporation, and / or ALD) and patterning the deposited material layer to form the bonding pads 241 in the desired pattern (e.g., using a photolithography process and subsequent etching processes). In some embodiments, another liner layer (e.g., an adhesion layer or an adhesive layer) can be formed between the bonding pads 241 and the STI structure 203 to improve the adhesion between the bonding material and the STI structure 203. Other processes (e.g., more fabrication operations, wiring, and / or packaging) can be performed on the bonded wafer 240.

[0063] In the present disclosure, an array-forming wafer is used as an example for illustrating embodiments. It should be noted that the disclosed structures and methods can be used to form any suitable wafer on which the substrate is thinned or removed in subsequent manufacturing processes. The array-forming wafer can be an example of any suitable wafer with a functional layer over an alternative substrate, and the alternative substrate can comprise a structure / substrate having sufficient uniformity, rigidity, and / or smoothness for subsequent manufacturing processes. The alternative substrate can be easily removed (e.g., peeled, etched, and / or planarized) from the structure to which it is attached, can be of lower cost, and / or can be easily fabricated. The wafer can comprise a memory array, a circuit, a semiconductor device, and / or any other suitable structure / device. Thus, the overall manufacturing cost for forming the bonded wafer can be reduced.

[0064] In some embodiments, a method for forming a bonded semiconductor device includes the following operations. First, a first wafer and a second wafer are formed. The first wafer can comprise a functional layer over a substrate. Single-crystalline silicon may not be essential for the substrate, and the substrate may not include single-crystalline silicon. The first wafer can be inverted to be bonded to the second wafer to form a bonded semiconductor device such that the substrate is on top of the functional layer. At least a portion of the substrate can be removed to form the top surface of the bonded semiconductor device. Further, bonding pads can be formed over the top surface.

[0065] In some embodiments, forming the first wafer includes forming a separation structure over the substrate and forming a plurality of array base regions in the separation structure. The separation structure can insulate the plurality of array base regions from each other. Forming the first substrate includes forming a plurality of memory arrays over the plurality of array base regions, forming an insulating structure to cover the plurality of memory arrays and the plurality of array base regions, and forming a plurality of interconnect structures exposed at the top surface of the first wafer within the insulating structure.

[0066] In some embodiments, forming the isolation structure and forming the plurality of array base regions within the isolation structure includes forming an insulating material layer across the substrate, patterning the insulating material layer to form a plurality of trenches, and depositing a semiconductor material to fill the plurality of trenches to form the plurality of array base regions.

[0067] In some embodiments, forming the isolation structure and forming the plurality of array base regions within the isolation structure includes forming another insulating material layer across the substrate, forming a semiconductor material layer across the other insulating material layer, removing a portion of the semiconductor material layer to expose the other insulating material layer, and patterning the semiconductor material layer to form the plurality of array base regions. Forming the isolation structure and forming the plurality of array base regions within the isolation structure includes filling the space formed by the removed portion of the semiconductor material layer, connecting with the other insulating material layer, and depositing the same material as the other insulating material layer to form the isolation structure.

[0068] In one embodiment, the method further includes performing a planarization step to remove excess material on them after forming the plurality of array base regions and the isolation structure.

[0069] In some embodiments, forming the insulating material layer and the other insulating material layer includes depositing silicon oxide, and depositing the doped polycrystalline silicon includes depositing the semiconductor material and forming the semiconductor material layer.

[0070] In some embodiments, forming the plurality of memory arrays across the plurality of array base regions includes forming at least one memory array across each one of the plurality of array base regions.

[0071] In some embodiments, forming a plurality of memory arrays across a plurality of array base regions includes forming a staircase structure across each one of the plurality of array base regions, forming vias extending from the top surface of the staircase structure to the respective array base regions, and forming semiconductor portions at the bottoms of the vias. The semiconductor portions may be connected to the array base regions. Forming a plurality of memory arrays across a plurality of array base regions may also include forming a via-forming structure to fill the vias and form semiconductor vias.

[0072] In some embodiments, forming the semiconductor portions includes performing a deposition process to form a semiconductor material on the exposed portions of the respective array base regions at the bottoms of the vias.

[0073] In some embodiments, the deposition process for forming the semiconductor material includes depositing the same material as the material of the respective array base regions.

[0074] In some embodiments, the deposition process includes one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition, and selective deposition.

[0075] In some embodiments, the method further includes forming a plurality of gate electrodes in the staircase structure to be connected to a plurality of interconnect structures and to form a plurality of memory cells by intersection with the semiconductor vias.

[0076] In some embodiments, providing a second wafer includes providing a plurality of other interconnect structures on a substrate.

[0077] In some embodiments, inverting the first wafer to bond to the second wafer to form a bonded semiconductor device includes performing a hybrid bond to bond the first wafer to the second wafer such that the interconnect structure of the first wafer is bonded to the plurality of other interconnect structures of the second wafer.

[0078] In some embodiments, the method further includes forming a liner layer between the isolation structure and the substrate.

[0079] In some embodiments, removing at least a portion of the substrate includes one or more of an etching process, a peeling process, and a planarization process.

[0080] In some embodiments, a method for forming a semiconductor device includes the following operations. First, an insulating material layer can be formed over the substrate. Single-crystalline silicon is not necessarily essential for the substrate, and the substrate may not include single-crystalline silicon. The insulating material layer can be patterned to form an isolation structure and to form a plurality of trenches in the isolation structure. A semiconductor material can be deposited to fill the plurality of trenches and to form a plurality of array base regions in the isolation structure, and the isolation structure insulates the plurality of array base regions from each other. Further, a plurality of memory arrays can be formed over the plurality of array base regions, and an insulating structure can be formed to cover the plurality of memory arrays and the plurality of array base regions.

[0081] In some embodiments, the method further includes performing a planarization process to remove excess material over them after the formation of the plurality of array base regions and the isolation structure.

[0082] In some embodiments, forming the insulating material layer includes depositing silicon oxide, and depositing the semiconductor material includes depositing doped polycrystalline silicon.

[0083] In some embodiments, a method for forming a semiconductor device includes the following operations. First, an insulating material layer may be formed across a substrate. Single-crystalline silicon may not be essential for the substrate, and the substrate may not include single-crystalline silicon. A semiconductor material layer may be formed across the insulating material layer. The semiconductor material layer may be patterned to remove a portion of the semiconductor material layer, expose other insulating material layers, and form a plurality of array base regions. The same material as the insulating material layer may be deposited to fill the space formed by the removed portion of the semiconductor material layer, connect with the insulating material layer, and form a separation structure. A plurality of memory arrays may be formed across the plurality of array base regions, and an insulating structure may be formed to cover the plurality of memory arrays and the plurality of array base regions.

[0084] In some embodiments, the method further includes performing a planarization step to remove excess material on the plurality of array base regions and the separation structure after their formation.

[0085] In some embodiments, forming the insulating material layer includes depositing silicon oxide, and forming the semiconductor material layer includes depositing doped polycrystalline silicon.

[0086] In some embodiments, a bonded semiconductor device includes a functional layer across a wafer. The functional layer may include a plurality of array base regions within an insulating structure that are connected to the plurality of memory arrays across the plurality of memory arrays. The dimensions of the upper surface of each of the plurality of array base regions may be different from the dimensions of the lower surface. The functional layer may also include a separation structure that covers the plurality of array base regions and insulates them from each other.

[0087] In some embodiments, the separation structure includes silicon oxide, and the plurality of array base regions include doped polycrystalline silicon.

[0088] In some embodiments, the plurality of memory arrays include a staircase structure with semiconductor vias, and the semiconductor vias include a semiconductor portion connected to each array base region and a via formation structure across the semiconductor portion. The semiconductor portion may include polycrystalline silicon.

[0089] In some embodiments, the plurality of memory arrays further comprise a plurality of gate electrodes that intersect semiconductor vias to form a plurality of memory cells.

[0090] In some embodiments, the functional layer is bonded to the wafer by bonding to other isolation structures across the substrate, and the bonding includes a first bond between a plurality of interconnect structures in the isolation structure and a plurality of other interconnect structures in the other isolation structure, and a second bond between the isolation structure and the other isolation structure.

[0091] In some embodiments, the wafer further comprises a device layer within other isolation structures across the substrate, and the device layer is connected to a plurality of other interconnect structures. In some embodiments, the memory array is connected to a plurality of interconnect structures.

[0092] In some embodiments, the bonded semiconductor device further comprises bonding pads across the isolation structure.

[0093] In some embodiments, the wafer may comprise a functional layer across the substrate. The functional layer may comprise an isolation structure across the substrate. The isolation structure can surround a plurality of array base regions and be insulated from each other. The wafer may also comprise a plurality of memory arrays across the plurality of array base regions. The dimensions of the upper surface of each of the plurality of array base regions may be different from the dimensions of the lower surface. The wafer may further comprise an insulating structure covering the plurality of memory arrays and the plurality of array base regions, and a plurality of interconnect structures within the insulating structure across the plurality of memory arrays.

[0094] In some embodiments, the isolation structure comprises silicon oxide, and the plurality of array base regions comprise doped polycrystalline silicon.

[0095] In some embodiments, each of the plurality of memory arrays comprises a stepped structure with semiconductor vias, and the semiconductor vias comprise a semiconductor portion connected to a respective array base region and a via formation structure across the semiconductor portion. The semiconductor portion may comprise polycrystalline silicon.

[0096] In some embodiments, the plurality of memory arrays further comprise a plurality of gate electrodes that intersect semiconductor channels to form a plurality of memory cells.

[0097] In some embodiments, the thickness of the plurality of array base regions is in the range of about 1 μm to about 3 μm, and the distance from the lower surface of the plurality of array base regions to the substrate is in the range of about 1 μm to about 2 μm.

[0098] In some embodiments, the insulating structure includes silicon oxide and the plurality of interconnect structures include copper.

[0099] The foregoing description of specific embodiments is to disclose the general nature of the present disclosure so that others skilled in the art can, without departing from the broad concept of the present disclosure, apply the knowledge of those skilled in the art to easily modify and / or adapt such specific embodiments for various applications without undue experimentation. Therefore, such adaptations and modifications are intended to be within the equivalent meaning and scope of the disclosed embodiments based on the teachings and guidance presented herein. It is understood that the expressions or terms herein are for the purpose of description and not limitation, as they will be interpreted by those skilled in the art in view of the teachings and guidance.

[0100] Embodiments of the present disclosure have been described above using functional building blocks that show the implementation of the stated functions and their relationships. The boundaries of these functional building blocks are arbitrarily defined herein for the convenience of description. Alternative boundaries may be defined as long as the stated functions and their relationships are properly implemented.

[0101] The abstract and summary can describe one or more exemplary embodiments, but may not describe all exemplary embodiments contemplated by the inventors, and thus are not intended to limit the present disclosure and the appended claims in any way.

[0102] The scope and extent of the present disclosure should not be limited by any of the foregoing exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Explanation of Reference Numerals

[0103] 100, 110, 120, 130 Structure, Array-Forming Wafer 101 Substrate 102 Liner Layer 103 Base Material Layer 111 Array Base Region 112 Memory Array 113 STI Structure 114 Interconnection Structure 115 Insulation Structure 121 Array Base Layer 123 Insulation Layer 130 Array-Forming Wafer 131 Array Base Region 132 Memory Array 133 STI Structure 134 Interconnection Structure 135 Insulation Structure 200, 200-2 Structure, Array-Forming Wafer 201 First Substrate 202 Liner Layer 203 STI Structure 204 Array Base Region 205 Memory Array 206 First Insulation Structure 207 First Interconnection Structure 210 Structure, Peripheral-Forming Wafer 211 Second Substrate 215 Device Layer 216 Second Insulation Structure 217 Second Interconnection Structure 220, 230, 240 Bonding Wafer 241 Bonding Pad d1 Thickness d2 Thickness, Depth d3 Distance d4 Thickness d5 Thickness Widths Wb1, Wb2, Wt1, Wt2 Thickness T1

Claims

1. 1. A method for forming a junction semiconductor device, comprising: forming a first wafer and a second wafer, the first wafer having a functional layer across a substrate, the substrate not including single crystal silicon; inverting the first wafer for bonding to the second wafer so that the substrate is above the functional layer to form the bonded semiconductor device; removing at least a portion of the substrate to form a top surface of the junction semiconductor device; forming a bond pad over said top surface; The method includes:

2. The step of forming a first wafer includes: forming an isolation structure across the substrate; forming a plurality of array base regions in the isolation structure, the isolation structure insulating the plurality of array base regions from one another; forming a plurality of memory arrays across the plurality of array base regions; forming an insulating structure overlying the plurality of memory arrays and the plurality of array base regions; forming a plurality of interconnect structures in the insulating structure, the interconnect structures being exposed at a top surface of the first wafer; The method of claim 1 , comprising:

3. The steps of forming the isolation structure and forming the plurality of array group regions in the isolation structure include: forming a layer of insulating material over the substrate; patterning the insulating material layer to form a plurality of trenches in the insulating material layer; depositing a semiconductor material to fill the trenches and form the array base regions; The method of claim 2 , comprising:

4. The steps of forming the isolation structure and forming the plurality of array group regions in the isolation structure include: forming another layer of insulating material over the substrate; forming a layer of semiconductor material over said other layer of insulating material; patterning the layer of semiconductor material to remove portions of the layer of semiconductor material to expose the other layer of insulating material and form a plurality of array base regions; depositing a material the same as the other insulating material layer to fill spaces formed by the removed portions of the semiconductor material layer and to connect with the other insulating material layer to form the isolation structure; The method of claim 2 , comprising:

5. The method of claim 3 or 4, further comprising performing a planarization process to remove excess material thereon after formation of the plurality of alignment group regions and the isolation structures.

6. 6. The method of claim 5, wherein the steps of forming the layer of insulating material and the further layer of insulating material include depositing silicon oxide, and the steps of depositing semiconductor material and forming the layer of semiconductor material include depositing doped polycrystalline silicon.

7. 7. The method of claim 2, wherein forming the plurality of memory arrays across the plurality of array base areas comprises forming at least one memory array across each one of the plurality of array base areas.

8. forming the at least one memory array across each one of the plurality of array base regions, forming a staircase structure across each of the plurality of array base regions; forming a passage hole extending from an upper surface of the staircase structure to each of the array base regions; forming a semiconductor portion at a bottom of the via hole, the semiconductor portion being connected to the array base region; forming a via-forming structure to fill the via hole and form a semiconductor via; The method of claim 7, comprising:

9. 9. The method of claim 8, wherein forming the semiconductor portions comprises performing a deposition process to form a semiconductor material on the exposed portions of each of the array base regions at the bottoms of the via holes.

10. 10. The method of claim 9, wherein the depositing step for forming the semiconductor material comprises depositing a material that is the same as a material of each of the alignment group regions.

11. The method of claim 10 , wherein the depositing process comprises one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition, and selective evaporation.

12. 12. The method of claim 8, further comprising forming a plurality of gate electrodes on the staircase structure to be coupled with the plurality of interconnect structures and to form a plurality of memory cells by crossing with the semiconductor path.

13. 13. The method of claim 1, wherein the step of providing a second wafer comprises providing a substrate with a plurality of other interconnect structures.

14. 14. The method of claim 13, wherein flipping the first wafer to bond to the second wafer to form the bonded semiconductor device comprises performing hybrid bonding to bond the first wafer to the second wafer such that the interconnect structures of the first wafer are bonded to the plurality of other interconnect structures of the second wafer.

15. The method of claim 2 , further comprising forming a liner layer between the isolation structure and the substrate.

16. 16. The method of claim 1, wherein removing the at least a portion of the substrate comprises one or more of an etching process, a stripping process, and a planarizing process.

17. 1. A method for forming a semiconductor device, comprising: forming a layer of insulating material over a substrate, the substrate not comprising single crystal silicon; patterning the layer of insulating material to form an isolation structure and to form a plurality of trenches in the isolation structure; depositing a semiconductor material to fill the trenches and form a plurality of array base regions in the isolation structure, the isolation structure isolating the plurality of array base regions from one another; forming a plurality of memory arrays across the plurality of array base regions; forming an insulating structure overlying the plurality of memory arrays and the plurality of array base regions; The method includes:

18. 20. The method of claim 17, further comprising performing a planarization process to remove excess material thereon after formation of the plurality of alignment group regions and the isolation structures.

19. 20. The method of claim 17, wherein the forming a layer of insulating material comprises depositing silicon oxide and the depositing a semiconductor material comprises depositing doped polycrystalline silicon.

20. 1. A method for forming a semiconductor device, comprising: forming a layer of insulating material over a substrate, the substrate not comprising single crystal silicon; forming a layer of semiconductor material over the layer of insulating material; patterning the layer of semiconductor material to remove portions of the layer of semiconductor material to expose other layers of insulating material and form a plurality of array base regions; depositing a material that is the same as the insulating material layer to fill spaces formed by the removed portions of the semiconductor material layer and to connect with the insulating material layer to form isolation structures; forming a plurality of memory arrays across the plurality of array base regions; forming an insulating structure overlying the plurality of memory arrays and the plurality of array base regions; The method includes:

21. 21. The method of claim 20, further comprising performing a planarization process to remove excess material thereon after formation of the plurality of alignment group regions and the isolation structures.

22. 21. The method of claim 20, wherein the step of forming the layer of insulating material comprises depositing silicon oxide, and the step of forming the layer of semiconducting material comprises depositing doped polycrystalline silicon.

23. A bonded semiconductor device comprising a functional layer across a wafer, the functional layer comprising: a plurality of array base regions in the insulating structure, the array base regions being connected to the plurality of memory arrays across the plurality of memory arrays, each of the array base regions having a top surface dimension different from a bottom surface dimension; an isolation structure covering the plurality of array regions and insulating them from one another; A junction semiconductor device comprising:

24. 24. The junction semiconductor device of claim 23, wherein said isolation structure comprises silicon oxide and said plurality of array base regions comprise doped polycrystalline silicon.

25. the plurality of memory arrays comprising a staircase structure with a semiconductor passage; 25. The junction semiconductor device of claim 24, wherein the semiconductor via comprises a semiconductor portion coupled to a respective substrate region and a via-forming structure spanning the semiconductor portion, the semiconductor portion comprising polycrystalline silicon.

26. 26. The junction semiconductor device of claim 25, wherein said plurality of memory arrays further comprises a plurality of gate electrodes intersecting said semiconductor vias to form a plurality of memory cells.

27. the functional layer is bonded to the wafer by bonding to another isolation structure across the substrate; 27. The junction semiconductor device of claim 23, wherein the junctions include first junctions between a plurality of interconnect structures in the isolation structure and a plurality of other interconnect structures in the other isolation structure, and second junctions between the isolation structure and the other isolation structure.

28. the wafer further comprising a device layer over the substrate and within the other isolation structures, the device layer being coupled to the plurality of other interconnect structures; 30. The junction semiconductor device of claim 27, wherein the memory array is coupled to the plurality of interconnect structures.

29. 29. The junction semiconductor device of claim 23, further comprising a bond pad across the isolation structure.

30. A wafer comprising a functional layer over a substrate, the functional layer comprising: an isolation structure across the substrate that surrounds and insulates the plurality of array regions from one another; a plurality of memory arrays across the plurality of array base regions, each of the plurality of array base regions having a top surface dimension different from a bottom surface dimension; an insulating structure covering the plurality of memory arrays and the plurality of array base regions; a plurality of interconnect structures disposed within the isolation structure across the plurality of memory arrays; A wafer comprising:

31. 31. The wafer of claim 30, wherein the isolation structures comprise silicon oxide and the plurality of array base regions comprise doped polycrystalline silicon.

32. each of the plurality of memory arrays includes a staircase structure with a semiconductor passage; 32. The wafer of claim 31, wherein the semiconductor vias comprise semiconductor portions coupled with respective substrate regions and via-forming structures spanning the semiconductor portions, the semiconductor portions comprising polycrystalline silicon.

33. 33. The wafer of claim 32, wherein the plurality of memory arrays further comprise a plurality of gate electrodes intersecting the semiconductor vias to form a plurality of memory cells.

34. The thickness of the plurality of array base regions is in the range of about 1 μm to about 3 μm, and the distance from the lower surface of the plurality of array base regions to the substrate is in the range of about 1 μm to about 2 μm.

35. 35. The wafer of any one of claims 30 to 34, wherein the insulating structures comprise silicon oxide and the plurality of interconnect structures comprise copper.

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