Semiconductor device

Abstract

To provide a solid state image pickup element with a high potential keeping function, having a thin film transistor with stable electric characteristics.SOLUTION: By initializing a signal charge accumulation part of a solid state image pickup element to a cathode potential of a photoelectric conversion element, a reset transistor is omitted. By using a thin film transistor which uses an oxide semiconductor layer and an off-state current of which is 1×1 0-13 A or less, and under as a transfer transistor of the solid state image pickup element, potential of a signal charge storage part can be kept constant to improve a dynamic range. In addition, by using a silicon semiconductor that can manufacture a complementary metal oxide semiconductor element for a peripheral circuit, a semiconductor device of high speed and low consumption power can be manufactured.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device having a field effect transistor using an oxide semiconductor. Related.

[0002] In this specification, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices.

Background Art

Background Art

[0003] Techniques for constructing thin film transistors using semiconductor thin films formed on substrates having insulating surfaces have attracted attention. Thin film transistors are used in display devices such as liquid crystal televisions. Silicon-based semiconductor materials are known as semiconductor thin films applicable to thin film transistors, but oxide semiconductors are attracting attention as other materials. Techniques for constructing thin film transistors using semiconductor thin films formed on substrates having insulating surfaces have attracted attention. Thin film transistors are used in display devices such as liquid crystal televisions. Silicon-based semiconductor materials are known as semiconductor thin films applicable to thin film transistors, but oxide semiconductors are attracting attention as other materials. As a semiconductor thin film applicable to a thin film transistor, silicon-based semiconductor materials are known, but oxide semiconductors are attracting attention as other materials. As a semiconductor thin film applicable to a thin film transistor, silicon-based semiconductor materials are known, but oxide semiconductors are attracting attention as other materials.

[0004] As materials for oxide semiconductors, zinc oxide or materials containing zinc oxide are known. And thin film transistors formed of amorphous oxides (oxide semiconductors) having a carrier (electron) concentration of less than 10 / cm 18 / cm 3 are disclosed (Patent Documents 1 to 3). are disclosed (Patent Documents 1 to 3).

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0006] On the other hand, in a solid-state imaging device that has a configuration close to a display device and requires excellent electrical characteristics, field-effect transistors using an SOI substrate or a bulk single-crystalline silicon substrate are generally used.

[0007] However, even a field-effect transistor using single-crystalline silicon does not have ideal electrical characteristics. For example, the off-current (also called leakage current, etc.) is not substantially as small as zero. Also, silicon is a material with a relatively large change in temperature characteristics, and in particular, the off-current is likely to change. Therefore, when configuring a charge-holding type semiconductor device such as a solid-state imaging device, it is possible to ensure a sufficient potential holding period regardless of the surrounding environment, and the development of a device with a lower off-current

[0008] is desired. Therefore, one aspect of the present invention disclosed aims to provide a solid-state imaging device including a thin-film transistor having stable electrical characteristics (for example, an extremely reduced

Means for Solving the Problems

[0009] One aspect of the present invention relates to a solid-state imaging device having at least a photoelectric conversion element and an amplification transistor formed using a silicon semiconductor, and having a pixel in which a transfer transistor is formed of an oxide semiconductor.

[0010] Also, the oxide semiconductor in one aspect of the present invention is a pure or substantially pure semiconductor obtained by removing impurities that serve as electron donors (donors), and has an energy - The energy gap is large.

[0011] That is, one aspect of the present invention is to remove hydrogen or OH groups contained in the oxide semiconductor by which the concentration of hydrogen contained in the oxide semiconductor is at a minimum value in secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectroscopy) of 5 ×10 19 / cm 3 or less, preferably 5×10 18 / cm 3 or less, more preferably 5×1 0 17 / cm 3 or less, or 1×10 16 / cm 3 less than, and the carrier concentration is 1×10 1 4 / cm 3 less than, preferably 1×10 12 / cm 3 or less, and a solid-state imaging device having a thin-film transistor in which a channel region is formed is configured.

[0012] The energy gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more, to reduce impurities such as hydrogen that form donors as much as possible, and the carrier concentration is 1×10 14 / cm 3 or less, preferably 1×10 12 / cm 3 or less.

[0013] The oxide semiconductor purified in this way is used in the channel formation region of the thin-film transistor so that the electrical characteristics exhibit normally-off, and at a drain voltage of 1 V to 10 V, the off-current thereof is 1×10 -13 A or less, or 100 aA / μm (μm is the thin-film transistor Below the channel width of the transfer transistor), preferably 10 aA / μm or less, more preferably 1 aA / μ m or less can be made to act.

[0014] One aspect of the invention disclosed in this specification is a photoelectric conversion element portion embedded in a silicon semiconductor, a signal charge storage portion electrically connected to the photoelectric conversion element portion via a transfer transistor, and a signal charge storage portion and an amplification transistor whose gate electrode is electrically connected, and the transfer transistor The channel formation region of the transfer transistor is formed of an oxide semiconductor, and the channel of the amplification transistor A semiconductor device having a formation region formed of a silicon semiconductor is there.

[0015] Also, the amplification transistor may be formed of a thin film transistor using an oxide semiconductor . Further, a selection transistor may be provided in the pixel portion. Also, the peripheral circuit portion connected to the pixel portion is preferably configured as a complementary (CMOS) transistor using a bulk transistor made of a silicon semiconductor.

[0016] Another aspect of the invention disclosed in this specification is a photoelectric conversion element portion, an electrical connection between the photoelectric conversion element portion a transfer transistor, a signal charge storage connected to the transfer transistor portion, and an amplification transistor electrically connected to the signal charge storage portion, and the photoelectric conversion element The portion is forward-biased, the transfer transistor is turned on to initialize the signal charge storage portion to the cathode potential of the photoelectric conversion element portion, the photoelectric conversion element portion is reverse-biased, and the photoelectric conversion element portion is irradiated with light to change the potential of the signal charge storage portion, turn off the transfer transistor to hold the potential of the signal charge storage portion, and output a signal from the amplification transistor according to the potential of the signal charge storage portion and output a signal from the amplification transistor according to the potential of the signal charge storage portion. semiconductor device. It is a method of operating a conductor device.

[0017] Conventional CMOS (Complementary Metal Oxide Semico nductor) image sensors initialized the potential of the signal charge accumulation section by operating a reset transistor. However, in one aspect of the present invention, the signal charge accumulation section is reset by initializing it to the cathode potential of the photoelectric conversion element section (photodiode), and the reset transistor can be omitted.

[0018] In this specification and the like, terms such as "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring", and a " wiring" may be used as part of an "electrode". Furthermore, terms such as "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0019] Also, the substrate used for the "SOI substrate" is not limited to semiconductor substrates such as silicon wafers, but also includes non-semiconductor substrates such as glass substrates, quartz substrates, sapphire substrates, and metal substrates. That is, those having a layer made of a semiconductor material on an insulator substrate are also widely included in the "SOI substrate". Fur thermore, in this specification and the like, the "semiconductor substrate" does not refer only to a substrate made of only a semiconductor material, but refers to all substrates including semiconductor materials. That is, in this specification and the like, " SOI substrate" is also included in the "semiconductor substrate".

Advantages of the Invention

[0020] According to one embodiment of the present invention, the reset transistor is omitted, and the off-current is extremely small By using a thin-film transistor using an oxide semiconductor as a transfer transistor, the potential of the signal charge storage section can be kept constant, and the dynamic range can be improved. Also, by using a silicon semiconductor in which complementary transistors can be fabricated in the peripheral circuit , a semiconductor device with high-speed operation and low power consumption can be obtained.

Brief Description of the Drawings

[0021]

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Embodiments for Carrying Out the Invention

[0022] Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is described in the following It is not limited to this, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below. In the configuration of the present invention described below, the same reference numerals are commonly used for the same parts or parts having the same function in different drawings, and the repeated description thereof is omitted. In addition, in each drawing described in this specification, the sizes of the respective components and regions, the thickness of the layers, etc. may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. Note that the terms "first", "second", "third", etc. used in this specification are attached to avoid confusion of components and do not limit the order or the like. Therefore, for example, "the first" can be appropriately replaced with "the second" or "the third" and described. (Embodiment 1) One aspect of the present invention is a semiconductor device using a metal-insulator-semiconductor element, a so-called MIS (Metal Insulator Semiconductor) transistor. In this specification, an element using a thin-film semiconductor in the channel formation region is referred to as a thin-film transistor, and an element using a bulk semiconductor in the channel formation region is referred to as a bulk transistor. However, although it can be said that the semiconductor layer formed on the SOI (Silicon on Insulator) substrate is also a thin film, in this specification, the transistor formed of the semiconductor layer is regarded as a type of bulk transistor.

[0023] It is not limited thereto, and various changes can be made to its form and details without departing from the spirit and scope of the present invention. Therefore, those skilled in the art can easily understand this. Accordingly, the present invention is not to be construed as being limited to the description of the forms shown below. In the configuration of the present invention described below, the same reference numerals are commonly used for the same parts or parts having the same function in different drawings, and the repeated description thereof is omitted. In addition, in each figure described in this specification, the sizes of the respective components and regions, the thickness of the layers, etc. may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. That is, it is not limited thereto.

[0024] In addition, the terms "first", "second", "third", etc. used in this specification are used to avoid confusion of components and do not limit the order or the like. Therefore, for example, "the first" can be appropriately replaced with "the second" or "the third" and described. That is, for example, "the first" can be appropriately replaced with "the second" or "the third" and described. (Embodiment 1)

[0025] One aspect of the present invention is a semiconductor device using a metal-insulator-semiconductor element, a so-called MIS (Metal Insulator Semiconductor) transistor. In this specification, an element using a thin-film semiconductor in the channel formation region is referred to as a thin-film transistor, and an element using a bulk semiconductor in the channel formation region is referred to as a bulk transistor. However, although it can be said that the semiconductor layer formed on the SOI (Silicon on Insulator) substrate is also a thin film, in this specification, the transistor formed of the semiconductor layer is regarded as a type of bulk transistor. It is not limited to this, and various changes can be made to its form and details without departing from the spirit and scope of the present invention. Therefore, those skilled in the art can easily understand this. Accordingly, the present invention is not to be construed as being limited to the description of the forms shown below. In the configuration of the present invention described below, the same reference numerals are commonly used for the same parts or parts having the same function in different drawings, and the repeated description thereof is omitted. In addition, in each figure described in this specification, the sizes of the respective components and regions, the thickness of the layers, etc. may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. Note that the terms "first", "second", "third", etc. used in this specification are used to avoid confusion of components and do not limit the order or the like. Therefore, for example, "the first" can be appropriately replaced with "the second" or "the third" and described. That is, for example, "the first" can be appropriately replaced with "the second" or "the third" and described. (Embodiment 1) One aspect of the present invention is a semiconductor device using a metal-insulator-semiconductor element, a so-called MIS (Metal Insulator Semiconductor) transistor. In this specification, an element using a thin-film semiconductor in the channel formation region is referred to as a thin-film transistor, and an element using a bulk semiconductor in the channel formation region is referred to as a bulk transistor. However, although it can be said that the semiconductor layer formed on the SOI (Silicon on Insulator) substrate is also a thin film, in this specification, the transistor formed of the semiconductor layer is regarded as a type of bulk transistor. It is not limited thereto, and various changes can be made to its form and details without departing from the spirit and scope of the present invention. Therefore, those skilled in the art can easily understand this. Accordingly, the present invention is not to be construed as being limited to the description of the forms shown below. In the configuration of the present invention described below, the same reference numerals are commonly used for the same parts or parts having the same function in different drawings, and the repeated description thereof is omitted.

[0026] An example of a pixel constituting a solid-state imaging device including a thin-film transistor according to one aspect of the present invention is described below. This will be explained below. In this embodiment, as an example, a thin-film transistor included in a pixel of a solid-state imaging device, a photoelectric conversion element connected to the thin-film transistor, and a bulk transistor formed of a silicon semiconductor will be described. Note that a pixel is an element group including each element provided in a solid-state imaging device, for example, a photoelectric conversion element, a transistor, and wiring, and is an element group configured to output an image through electrical signal input / output.

[0027] Note that as shown in the cross-sectional view of FIG. 28(A), the pixel can be configured such that incident light passes through a lens 600, a color filter 602, and an interlayer insulating film 606 formed on the substrate surface side and is received by the photoelectric conversion element 608. However, as shown in the region surrounded by the dotted line frame, a part of the optical path indicated by the arrow may be blocked by a part of the wiring layer 604. As shown in FIG. 28(B), a lens 610 and a color filter 612 may be formed on the back surface side of the substrate so that incident light is efficiently received by the photoelectric conversion element 618. Also, when it is described that A and B are connected, it shall include the case where A and B are electrically connected and the case where A and B are directly connected. Here, A and B are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0028]

[0029] An example of a pixel portion of a solid-state imaging device according to one aspect of the present invention is shown in a cross-sectional view in FIG. 1. FIG. 1 is an example in which a thin-film transistor of an oxide semiconductor is used for the transfer transistor 101, and the amplification transistor 131 is an n-channel bulk transistor formed on a single-crystal silicon substrate 100 It is formed. The photoelectric conversion element 110 forms a photodiode including an n-type region 112 and a thin p-type region 114, and is connected to the source electrode 104 of the transfer transistor 101 Also, a signal charge accumulation portion 116 (also called a floating diffusion) is formed below the drain electrode of the transfer transistor 101 The transfer transistor 101 has a top gate structure in which an oxide semiconductor layer serves as a channel region. The amplification transistor 131 is an n-channel bulk transistor including n-type regions 132a and 132b and a gate electrode 138 The gate electrode 138 of the amplification transistor 131 is electrically connected to the signal charge accumulation portion 116 by a wiring 154 In the structure of FIG. 1, the gate insulating layer 136 of the bulk transistor also serves as the underlying insulating layer of the transfer transistor 101 which is a thin film transistor, and the signal charge accumulation portion 116 forms a capacitance using the gate insulating layer 136 as a dielectric In addition, the gate insulating layer 118 of the thin film transistor functions as a part of the interlayer insulating layer of the bulk transistor Although the thin film transistor using an oxide semiconductor for the channel formation region is shown by taking the top gate type as an example, a bottom gate type such as an inverted staggered structure may be used In addition, since it is necessary to irradiate the photoelectric conversion element 110 with light, an example is given in which a part of the source electrode of the transfer transistor 101 is connected to the light receiving portion of the photoelectric conversion element 110, but the source electrode may be formed of a translucent conductive material

[0030] and the connection state with the photoelectric conversion element 110 may be changed. For example, as shown in FIG. 2(A)

[0031] ​​​​​​​​If a transistor 201 having a source electrode 204 formed of a transparent conductive material is used as a transfer transistor, it can be connected to part or all of the light-receiving surface of the photoelectric conversion element 210. Also, as shown in Fig. 2(B), in order to secure an optical path to the photoelectric conversion element 310, a transistor 301 in which metal layers with low resistance are used as the source electrode 304 and the drain electrode 306, and transparent conductive material layers are laminated as buffer layers 305 and 307 may be used as the transfer transistor.

[0032] The photodiode formed as the photoelectric conversion element is formed by forming an n-type region in a p-type single-crystalline silicon substrate (in the case of SOI, it is a p-type single-crystalline silicon layer), and forming a thin p-type region on the top, i.e., forming an embedded-type photodiode. By forming a p-type region on the surface of the photodiode, noise due to dark current generated on the surface can be reduced.

[0033] Also, although an example using a single-crystalline semiconductor substrate was shown above, a substrate with an SOI structure may also be used. Also, the structure of the bulk transistor is not limited to this, and an LDD (Lightly Doped Drain) structure with sidewalls provided at the gate electrode end or a structure in which a low-resistance silicide or the like is formed in part of the source-drain region may also be used.

[0034] Also, a selection transistor electrically connected to the amplification transistor 131 may be provided in the pixel portion. Both the amplification transistor and the selection transistor can be formed using either a silicon semiconductor or an oxide semiconductor. However, the amplification transistor is preferably formed as a bulk transistor using a silicon semiconductor layer with a higher amplification factor.

[0035] In addition, an insulating layer is provided on the upper part of the bulk transistor, and a thin film transistor is provided on the insulating layer. For example, a transfer transistor formed of a thin film transistor can be replaced with a bulk transistor. If the amplifier transistor is placed on top of the amplifier, the surface area of ​​the transistor required for one pixel can be reduced. The product is about 1 / 2 to 2 / 3, which allows for improved integration and an increased light receiving area for the photodiode. This can reduce noise. Figure 3 shows an example of this. A conversion element 510 and an amplifying transistor 531 formed of a bulk transistor are formed, and an insulating A transfer transistor 501 formed of a thin film transistor is provided on the upper layer via an insulating film 541. This is an example in which the manufacturing processes for the photoelectric conversion element, bulk transistor, and thin film transistor are separated. However, the process for forming the signal charge storage portion 516 can be easily controlled. It is preferable to provide a capacitive electrode 540 .

[0036] Here, one embodiment of the present invention includes a thin film transistor including an oxide semiconductor layer. In addition, the solid-state imaging element CMOS (Complementary Metal Oxide A common component of Xide Semiconductor image sensors is the reset switch. The feature of this sensor is that it does not use a reset transistor. The potential of the signal charge storage section is initialized by operating the set transistor. However, in one aspect of the present invention, the signal charge storage unit is initialized to the cathode potential of the photodiode. First, the photodiode is forward biased and the transfer transistor is turned on. Then, the signal charge storage section has the same potential as the cathode of the photodiode. When the gate is reverse-biased and the photodiode is irradiated with light, the potential of the signal charge accumulation part discharges. Here, turn off the transfer transistor, and the signal can be output by the amplification transistor according to the held potential.

[0037] By combining the thin-film transistor and the bulk transistor with the above structure, the holding function of the potential of the signal charge accumulation part can be enhanced, and the pixel part of a solid-state imaging device with a wide dynamic range can be formed. However, in order to realize one aspect of the present invention, it is preferable to use a thin-film transistor with an extremely small off-current. Next, the manufacturing method will be described. One aspect of the present invention forms a pixel part of a solid-state imaging device by combining a bulk transistor using a single-crystalline silicon semiconductor and a thin-film transistor using an oxide semiconductor with extremely good electrical characteristics. Therefore, a detailed description will be given mainly on the manufacturing method of the thin-film transistor using the oxide semiconductor.

[0038] As an example, the manufacturing method of the structure shown in FIG. 1 will be described with reference to the cross-sectional views of FIGS. 4 and 5. First, form element formation regions separated by an insulating film 140 (also referred to as a field oxide film) on a P-type single-crystalline silicon substrate 100. The formation of the element isolation region can use methods such as the LOCOS method (Local Oxidation of Silicon) or the STI method (Shallow Trench Isolation). Here, the substrate is not limited to a single-crystalline silicon substrate, and an SOI (Silicon on Insulator) substrate or the like can also be used.

[0039] As an example, the manufacturing method of the structure shown in FIG. 1 will be described using the cross-sectional views of FIGS. 4 and 5. First, form element formation regions separated by an insulating film 140 (also called a field oxide film) on a P-type single-crystalline silicon substrate 100. For the formation of the element isolation region, methods such as the LOCOS method (Local Oxidation of Silicon) or the STI method (Shallow Trench Isolation) can be used. ation of Silicon) method) or the STI method (Shallow Trench Isolation) etc. can be used.

[0040] Here, the substrate is not limited to a single-crystalline silicon substrate, and an SOI (Silicon on Insul ator) substrate or the like can also be used.

[0041] ​​​​​​In this embodiment, a buried photodiode and an n-channel bulk transistor are Since this is a structure that uses a p-type single crystal silicon substrate, a p-well is formed. If this is done, an n-type single crystal silicon substrate can also be used.

[0042] Next, a gate insulating layer 136 is formed so as to cover the element forming region. For example, a heat treatment is performed. The surface of the element formation region provided on the single crystal silicon substrate 100 is oxidized. A silicon film can be formed. Also, after forming a silicon oxide film by thermal oxidation, In addition, the surface of the silicon oxide film is nitrided by a nitriding process, so that the silicon oxide film can be It may be formed of a laminated structure of a silicon film and a silicon oxynitride film.

[0043] As another method, for example, the surface of the element formation region provided on the single crystal silicon substrate 100 is The gate insulating layer 13 is then subjected to oxidation or nitridation by high density plasma treatment. The layer 6 can be made of a silicon oxide film or a silicon nitride film. After oxidizing the surface of the element formation area by Zuma treatment, high-density plasma treatment is performed again. In this case, the oxidized layer may be in contact with the surface of the element formation region. A silicon film is formed, a silicon oxynitride film is formed on the silicon oxide film, and a gate insulating film is formed on the silicon oxide film. The edge layer 136 is a film in which a silicon oxide film and a silicon oxynitride film are laminated.

[0044] Next, a conductive layer is formed to cover the gate insulating layer 136. Here, the conductive layer 138a and The conductive layer 138b is formed by stacking the conductive layers 138a and 138b in order. Of course, the conductive layer may be a single layer or a stack of two or more layers. It may be formed in a layer structure.

[0045] As the conductive layers 138a and 138b, tantalum (Ta), tungsten (W), titanium ( Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), ni obium (Nb), etc., or an alloy material or a compound material mainly composed of these elements can be used. Also, they can be formed of a metal nitride film obtained by nitriding these elements. In addition, they can also be formed of a semiconductor material typified by polycrystalline silicon doped with impurity elements such as phosphorus.

[0046] Here, tantalum nitride is used to form the conductive layer 138a, and tungsten is used to form a laminated structure on it as the conductive layer 138b. Also, in addition, as the conductive layer 138a, a single layer or a laminated film selected from tungsten nitride, molybdenum nitride, or titanium nitride is used, and as the conductive layer 138b, a single layer or a laminated film selected from tantalum, molybdenum, and titanium can be used.

[0047] Next, the laminated conductive layers 138a and 138b are selectively etched and removed, so that a part of the conductive layers 138a and 138b remains above the gate insulating layer 136 to form the gate electrode 138.

[0048] Next, a resist mask is selectively formed so as to cover the area other than the element formation region, and impurity elements are introduced using the resist mask and the gate electrode 138 as masks to form n-type regions 1 32a and 132b. Here, since an n-channel type bulk transistor is to be formed, as the impurity elements, phosphorus (P), arsenic (As), etc., which are impurity elements for imparting an n-type, can be used.

[0049] ​​​​ Next, a resist mask is selectively formed to fabricate a photodiode, which is a photoelectric conversion element. First, after introducing impurity elements such as phosphorus (P) and arsenic (As), which are n-type impurity elements, into a p-type single crystal silicon substrate to form a pn junction, boron (B), which is an impurity element for imparting p-type, is introduced into the surface layer of the n-type region to form an embedded-type photodiode. (B) can be formed.

[0050] At this stage, the structures of the bulk transistor shown on the right side of Fig. 4(A) and the photodiode shown on the left side are completed.

[0051] Next, a method for fabricating a thin film transistor having an oxide semiconductor layer as a channel region will be described.

[0052] In this embodiment, a thin film transistor is formed on the gate insulating layer 136 of the bulk transistor already provided on the single crystal silicon substrate 100. That is, the underlying film of the thin film transistor can also serve as the gate insulating layer of the bulk transistor. However, the following method can be used to form an insulating layer, and the underlying film may be a laminate.

[0053] The insulating layer in contact with the oxide semiconductor layer is preferably an oxide insulating layer such as a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or an aluminum oxynitride layer. As a method for forming the insulating layer, a plasma CVD method or a sputtering method can be used. However, in order to prevent a large amount of hydrogen from being contained in the insulating layer, it is preferable to form the insulating layer by the sputtering method.

[0054] An example of forming a silicon oxide layer by the sputtering method as the insulating layer will be described. Single crystal silicon The substrate 100 is transported into the processing chamber, and sputtering gas containing high-purity oxygen from which hydrogen and moisture have been removed is introduced. Using a silicon target, a silicon oxide layer is formed as an insulating layer on the single-crystal silicon substrate 100. The single-crystal silicon substrate 100 may be at room temperature or heated. For example, quartz (preferably synthetic quartz) is used as the target, the substrate temperature is 108 °C, the distance between the substrate and the target (T-S distance) is 60 mm, the pressure is 0.4 Pa, the high-frequency power supply is 1 .5 kW, and a silicon oxide layer is formed by RF sputtering in an atmosphere of oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1: 1). The film thickness is set to 100 nm. Note that silicon can be used instead of quartz as the target for forming the silicon oxide layer. In this case, oxygen or a mixed gas of oxygen and argon is used as the sputtering gas.

[0055] For example, quartz (preferably synthetic quartz) is used as the target, the substrate temperature is 108 °C, the distance between the substrate and the target (T-S distance) is 60 mm, the pressure is 0.4 Pa, the high-frequency power supply is 1 .5 kW, and a silicon oxide layer is formed by RF sputtering in an atmosphere of oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1: 1). The film thickness is 100 nm. Note that silicon can be used instead of quartz as the target for forming the silicon oxide layer. In this case, oxygen or a mixed gas of oxygen and argon is used as the sputtering gas. In this case, it is preferable to form the insulating layer while removing the residual moisture in the processing chamber. This is to prevent hydrogen, hydroxyl groups, or moisture from being included in the insulating layer. To remove the residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump.

[0056] For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, as the exhaust means, a turbo pump with a cold trap added may be used. The processing chamber evacuated using a cryopump exhausts, for example, hydrogen atoms and compounds containing hydrogen atoms such as water (H2 O), etc. Therefore, the concentration of impurities contained in the insulating layer formed in the processing chamber can be reduced.

[0057] For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, as the exhaust means, a turbo pump with a cold trap added may be used. The processing chamber evacuated using a cryopump exhausts, for example, hydrogen atoms and compounds containing hydrogen atoms such as water (H2 O), etc. Therefore, the concentration of impurities contained in the insulating layer formed in the processing chamber can be reduced. O), etc. Therefore, the concentration of impurities contained in the insulating layer formed in the processing chamber can be reduced. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, as the exhaust means, a turbo pump with a cold trap added may be used.

[0058] When forming the insulating layer, the sputtering gas used is preferably a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed to a concentration of about ppm or a concentration of about ppb.

[0059] The sputtering method includes the RF sputtering method using a high-frequency power supply for the sputtering power supply, the DC sputtering method using a DC power supply, and the pulsed DC sputtering method for applying a bias pulse. The RF sputtering method is mainly used when forming an insulating film, and the DC sputtering method is mainly used when forming a conductive film.

[0060] There is also a multi-source sputtering apparatus that can install a plurality of targets made of different materials. The multi-source sputtering apparatus can stack and deposit different material films in the same chamber, or can simultaneously discharge and deposit multiple types of materials in the same chamber.

[0061] There are also sputtering apparatuses that use the magnetron sputtering method equipped with a magnet mechanism inside the chamber, and ECR sputtering apparatuses that use plasma generated using microwaves without using glow discharge.

[0062] As a film-forming method using the sputtering method, there are a reactive sputtering method in which a chemical reaction is caused between the target substance and the sputtering gas component during film formation to form a compound thin film thereof, and a bias sputtering method in which a voltage is also applied to the substrate during film formation.

[0063] The insulating layer may have a laminated structure. For example, it may have a laminated structure of a nitride insulating layer such as a silicon nitride layer, a silicon oxynitride layer, an aluminum nitride layer, or an aluminum oxynitride layer from the substrate side and the above oxide insulating layer. ​

[0064] For example, a spatula containing high-purity nitrogen from which hydrogen and moisture have been removed is used between the silicon oxide layer and the substrate. A target gas is introduced and a silicon nitride layer is formed using a silicon target. In the same manner as for the silicon oxide layer, the silicon nitride layer is formed while removing the residual moisture in the processing chamber. It is preferable to coat the substrate with a film.

[0065] When forming a silicon nitride layer, the substrate may be heated during film formation.

[0066] When a silicon nitride layer and a silicon oxide layer are laminated as an insulating layer, the silicon nitride layer and the oxide layer Silicon layers can be deposited in the same process chamber using a common silicon target. First, nitrogen-containing sputtering gas is introduced to the silicon target mounted in the processing chamber. A silicon nitride layer is formed using a sputter gas containing oxygen. The silicon oxide layer is formed by replacing the silicon target with the silicon nitride layer. Since the silicon nitride layer and the silicon oxide layer can be formed successively without exposure to the atmosphere, It is possible to prevent impurities such as hydrogen and moisture from being adsorbed onto the surface.

[0067] Next, a thin film having a thickness of 2 nm or more and a thickness of 200 nm or more is deposited on the insulating layer (on the gate insulating layer 136 in this embodiment). An oxide semiconductor film having a thickness of 1 nm or less is formed.

[0068] In order to prevent hydrogen, hydroxyl groups, and moisture from being contained in the oxide semiconductor film as much as possible, As a pretreatment for film formation, the single crystal silicon substrate 100 is preheated in a preheating chamber of the sputtering device. It is preferable to desorb and exhaust impurities such as hydrogen and moisture adsorbed on the substrate. The exhaust means provided in the preheating chamber is preferably a cryopump. Note that this preheating process can also be omitted. Further, this preheating may be performed before forming the gate insulating layer 118 of the thin film transistor to be formed later, or before forming the conductive layer that will become the source electrode and drain electrode to be formed later.

[0069] Note that before forming the oxide semiconductor film by sputtering, it is preferable to introduce argon gas to perform reverse sputtering to generate plasma and remove the dust adhering to the surface of the insulating layer. Reverse sputtering is a method of applying a voltage using an RF power source to the substrate side in an argon atmosphere and colliding the ionized argon with the substrate to modify the surface. Note that nitrogen, helium, oxygen, etc. may be used instead of argon.

[0070] The oxide semiconductor film is formed by sputtering. As the oxide semiconductor film, a quaternary metal oxide In-Sn-Ga-Zn-O film, or a ternary metal oxide such as In-Ga-Zn- O film, In-Sn-Zn-O film, In-Al-Zn-O film, Sn-Ga-Zn-O film, A l-Ga-Zn-O film, Sn-Al-Zn-O film, or a binary metal oxide such as In-Zn -O film, Sn-Zn-O film, Al-Zn-O film, Zn-Mg-O film, Sn-Mg-O film, In-Mg-O film, In-O film, Sn-O film, Zn-O film, etc. can be used. Further, the above oxide semiconductor film may contain SiO2.

[0071] Also, as the oxide semiconductor film, a thin film represented by InMO3(ZnO) m (m>0) can be used. Here, M is one or more selected from Ga, Al, Mn, and Co. represents a metal element. For example, as M, there are Ga, Ga and Al, Ga and Mn, or Ga and Co, etc. InMO3(ZnO) m an oxide semiconductor film having a structure represented by (m>0) among them, an oxide semiconductor having a structure containing Ga as M is referred to as an In-Ga-Zn-O oxide semiconductor and its thin film is also referred to as an In-Ga-Zn-O film.

[0072] In this embodiment, the oxide semiconductor film is formed by sputtering using an In-Ga-Zn-O-based metal oxide target Further, the oxide semiconductor film can be formed by sputtering in an inert gas (typically argon ) atmosphere, an oxygen atmosphere, or a mixed atmosphere thereof .

[0073] The sputtering gas used when forming the oxide semiconductor film is a high-purity gas in which any impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed to a concentration of about ppm or a concentration of about ppb and it is preferably used.

[0074] As a target for producing the oxide semiconductor film by sputtering, a target of a metal oxide mainly composed of zinc oxide can be used For example, as a composition ratio, a metal oxide target of In2O3: Ga2O3:ZnO = 1:1:1 [mole ratio] can be used . Also, a metal oxide target of In2O3:Ga2O3:ZnO = 1:1:2 [mole ratio] can be used The filling rate of the metal oxide target is 90% or more and 100% or less, preferably 95% or more and 99.9%. By using a metal oxide target with a high filling rate , the formed oxide semiconductor film becomes a dense film.

[0075] An oxide semiconductor film is formed by holding a substrate in a processing chamber maintained under a reduced pressure, introducing a sputtering gas from which hydrogen and moisture have been removed while removing residual moisture in the processing chamber, and using a metal oxide as a target to form an oxide semiconductor film on an insulating layer. To remove the residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Further, as an exhaust means, a turbo pump with a cold trap added thereto may be used. The processing chamber evacuated using a cryopump can exhaust compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably, compounds containing carbon atoms as well), and thus the concentration of impurities contained in the oxide semiconductor film formed in the processing chamber can be reduced. Further, the substrate may be heated during the formation of the oxide semiconductor film. An example of the film formation conditions is as follows: substrate temperature is room temperature, the distance between the substrate and the target is 110 mm, the pressure is 0.4 Pa, the direct current (DC) power supply is 0.5 kW, and the conditions are applied in an atmosphere of oxygen and argon (oxygen flow rate: 15 sccm; argon flow rate: 30 sccm). When a pulsed DC power supply is used, it is preferable because the powdery substances (also referred to as particles and dust) generated during film formation are reduced and the film thickness distribution becomes uniform. The oxide semiconductor film is preferably 5 nm or more and 30 nm or less. Note that the appropriate thickness varies depending on the oxide semiconductor material to be applied, and the thickness may be appropriately selected according to the material. Next, the oxide semiconductor film is processed into island-shaped oxide semiconductor layers 102 by a first photolithography process and an etching process (see FIG. 4(B)). For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Further, as an exhaust means, a turbo pump with a cold trap added thereto may be used. The processing chamber evacuated using a cryopump can exhaust compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably, compounds containing carbon atoms as well), and thus the concentration of impurities contained in the oxide semiconductor film formed in the processing chamber can be reduced. Further, the substrate may be heated during the formation of the oxide semiconductor film. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Further, as an exhaust means, a turbo pump with a cold trap added thereto may be used. The processing chamber evacuated using a cryopump can exhaust compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably, compounds containing carbon atoms as well), and thus the concentration of impurities contained in the oxide semiconductor film formed in the processing chamber can be reduced.

[0076] An example of the film formation conditions is as follows: substrate temperature is room temperature, the distance between the substrate and the target is 110 mm, the pressure is 0.4 Pa, the direct current (DC) power supply is 0.5 kW, and the conditions are applied in an atmosphere of oxygen and argon (oxygen flow rate: 15 sccm; argon flow rate: 30 sccm). When a pulsed DC power supply is used, it is preferable because the powdery substances (also referred to as particles and dust) generated during film formation are reduced and the film thickness distribution becomes uniform. The oxide semiconductor film is preferably 5 nm or more and 30 nm or less. Note that the appropriate thickness varies depending on the oxide semiconductor material to be applied, and the thickness may be appropriately selected according to the material. When a pulsed DC power supply is used, it is preferable because the powdery substances (also referred to as particles and dust) generated during film formation are reduced and the film thickness distribution becomes uniform. The oxide semiconductor film is preferably 5 nm or more and 30 nm or less. Note that the appropriate thickness varies depending on the oxide semiconductor material to be applied, and the thickness may be appropriately selected according to the material.

[0077] Next, the oxide semiconductor film is processed into island-shaped oxide semiconductor layers 102 by a first photolithography process and an etching process (see FIG. 4(B)). Next, the oxide semiconductor film is processed into island-shaped oxide semiconductor layers 102 by a first photolithography process and an etching process (see FIG. 4(B)).

[0078] Note that the resist mask for forming the island-shaped oxide semiconductor layer may be formed by an inkjet method. When the resist mask is formed by the inkjet method, a photomask is not used, so the manufacturing cost can be reduced. Also, for the etching of the oxide semiconductor film here, either dry etching or wet etching may be used, or both may be used.

[0079] As the etching gas used for dry etching, a gas containing chlorine (chlorine-based gas, for example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride (CC l4), etc.) is preferable.

[0080] Also, a gas containing fluorine (fluorine-based gas, for example, carbon tetrafluoride (CF4), sulfur hexafluoride (S F6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (H Br), oxygen (O2), a gas obtained by adding a rare gas such as helium (He) or argon (Ar) to these gases, etc. can be used.

[0081] As the dry etching method, a parallel plate type RIE (Reactive Ion Etch ing) method or an ICP (Inductively Coupled Plasma: inductively coupled plasma) etching method can be used. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.) are appropriately adjusted so that etching can be performed into a desired processed shape.

[0082] As the etching solution used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid, ammonium persulfate (31 wt% hydrogen peroxide solution: 28 wt% ammonia water: water = 5:2:2), etc. can be used. Alternatively, ITO-07N (manufactured by Kanto Chemical Co., Inc.) may be used.

[0083] Further, the etching solution after wet etching is removed together with the etched material by washing. The waste liquid of the etching solution containing the removed material is purified, and the contained material may be reused. By recovering and reusing materials such as indium contained in the oxide semiconductor layer from the waste liquid after the etching, resources can be effectively utilized and costs can be reduced.

[0084] The etching conditions (etching solution, etching time, temperature, etc.) are appropriately adjusted according to the material so that etching can be performed into a desired shape.

[0085] In this embodiment, a wet etching method using a solution in which phosphoric acid, acetic acid, and nitric acid are mixed is used to process the oxide semiconductor film into island-shaped oxide semiconductor layers 102.

[0086] In this embodiment, a first heat treatment is performed on the oxide semiconductor layer 102 in an atmosphere of nitrogen or a noble gas such as helium, neon, or argon. The temperature of the first heat treatment is 400°C or higher and 750°C or lower, preferably 400°C or higher and less than the strain point of the substrate. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and a heat treatment is performed at 450°C for 1 hour in a nitrogen atmosphere with respect to the oxide semiconductor layer. The atmosphere may be switched to oxygen when the temperature is lowered from the heat treatment temperature. By this first heat treatment, dehydration or dehydrogenation of the oxide semiconductor layer 102 can be performed.

[0087] Note that the heat treatment apparatus is not limited to an electric furnace, and heat conduction or heat from a heating element such as a resistance heating element The apparatus may be equipped with a device for heating the object to be treated by radiation. For example, a GRTA (Gas Rapid Thermal Annealing) equipment, LRTA (Lamp Ra pid Thermal Annealing (RTA) equipment The LRTA device is a halogen laser annealing (HLTA) device. lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure nato The exposure to light (electromagnetic waves) emitted from lamps such as lithium lamps and high-pressure mercury lamps can cause The GRTA device is a device that uses high-temperature gas to heat materials. The gases include rare gases such as argon, or nitrogen, which can be treated by heat treatment. An inert gas that does not react with the material is used.

[0088] For example, the first heat treatment is performed by heating an inert gas to a high temperature of 650° C. or more and 700° C. or less. The substrate is then moved into the inert gas chamber and heated for a few minutes. GRTA can be used to heat the gas out. GRTA allows high-temperature heating in a short time. It becomes possible.

[0089] In the first heat treatment, the atmosphere is nitrogen, helium, neon, argon, or the like. It is preferable that the gas does not contain water, hydrogen, etc. Alternatively, the purity of the atmospheric gas is 6 N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e. impure The concentration of the substance is 1 ppm or less, preferably 0.1 ppm or less. Oxygen is used as the atmospheric gas. When used, it is preferable that it has a similar purity.

[0090] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, may crystallize and become a microcrystalline layer or a polycrystalline layer. For example, when the crystallization rate is 90% or more , or it may become an oxide semiconductor layer of microcrystals with a crystallization rate of 80% or more. Also, depending on the conditions of the first heat treatment , or the material of the oxide semiconductor layer, it may become an amorphous oxide semiconductor layer that does not contain a crystalline component . Also, there may be a case where the oxide semiconductor layer is a layer in which microcrystalline portions (particle size of 1 nm or more to 20 nm or less (typically 2 nm or more and 4 nm or less)) are mixed in the amorphous oxide semiconductor.

[0091] Also, the first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor film before it is processed into an island-shaped oxide semiconductor layer.

[0092] The heat treatment that has the effect of dehydration and dehydrogenation on the oxide semiconductor layer can be performed at any time after forming the oxide semiconductor layer, after laminating the source electrode and the drain electrode on the oxide semiconductor layer, and after forming the gate insulating layer on the source electrode and the drain electrode.

[0093] Next, an opening reaching the p-type region of the upper layer of the photodiode is formed in the insulating layer by the second photolithography process and the etching process, and a conductive layer is formed on the insulating layer and the oxide semiconductor layer 102. The conductive layer may be formed by a sputtering method or a vacuum evaporation method. As the material of the conductive layer are elements selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or alloys containing the above-mentioned elements as components, or alloy films combining the above-mentioned elements , etc. Also, a material selected from any one or more of manganese, magnesium, zirconium, beryllium, and yttrium may be used. Also, the metal conductive layer ​​​​​​​​It may be a single-layer structure or a laminated structure of two or more layers. For example, aluminum containing silicon A single-layer structure of a film, a two-layer structure in which a titanium film is laminated on an aluminum film, a titanium film, and a titanium A three-layer structure in which an aluminum film is laminated on the film and a titanium film is further formed thereon can be mentioned. In addition, a film, an alloy film, or a nitride film obtained by combining one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium with aluminum may be used.

[0094] Next, a resist mask is formed on the conductive layer in the third photolithography process, and selective etching is performed to form the source electrode 104 and the drain electrode 106 of the thin film transistor, and then the resist mask is removed (see FIG. 4(C)). Note that if the ends of the formed source electrode and drain electrode are tapered, the coverage of the gate insulating layer laminated thereon is improved, which is preferable. In this embodiment, a titanium film with a thickness of 150 nm is formed as the source electrode 104 and the drain electrode 106 by sputtering. Note that when etching the conductive layer, the oxide semiconductor layer 102 is not partially removed, and the insulating layer thereunder is not exposed. The respective materials and etching conditions

[0095] are appropriately adjusted. In this embodiment, a titanium film is used as the conductive layer, an In-Ga-Zn-O-based oxide semiconductor is used for the oxide semiconductor layer 102, and aqueous ammonia peroxide (a mixed solution of ammonia,

[0096] water, and hydrogen peroxide solution) is used as the etchant. When etching the conductive layer, the oxide semiconductor layer 102 is not partially removed, and the insulating layer thereunder is not exposed. The respective materials and etching conditions are appropriately adjusted.

[0097] In this embodiment, a titanium film is used as the conductive layer, an In-Ga-Zn-O-based oxide semiconductor is used for the oxide semiconductor layer 102, and aqueous ammonia peroxide (a mixed solution of ammonia, water, and hydrogen peroxide solution) is used as the etchant. water, and hydrogen peroxide solution) is used as the etchant.

[0098] In the third photolithography process and the etching process, only a part of the oxide semiconductor layer 102 may be etched to form an oxide semiconductor layer having a groove portion (recess). Also, a resist mask for forming the source electrode 104 and the drain electrode 106 may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced. For the exposure during the formation of the resist mask in the third photolithography process, ultraviolet light, KrF laser light, or ArF laser light is used. The channel length L of the thin film transistor formed later is determined by the distance between the lower end portions of the adjacent source electrodes and the lower end portions of the drain electrodes on the oxide semiconductor layer 102. When performing exposure with a channel length L < 25 nm, extreme ultraviolet light with a very short wavelength of several nm to several tens of nm is used for the exposure during the formation of the resist mask in the second photolithography process. Exposure with extreme ultraviolet light has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length L of the thin film transistor formed later to be 10 nm or more and 1000 nm or less, which can increase the operating speed of the circuit, and since the off-current value is extremely small, low power consumption can also be achieved. In the third photolithography process, ultraviolet light, KrF laser light, or ArF laser light is used for the exposure during the formation of the resist mask. The channel length L of the thin film transistor formed later is determined by the distance between the lower end portions of the adjacent source electrodes and the lower end portions of the drain electrodes on the oxide semiconductor layer 102. When performing exposure with a channel length L < 25 nm, extreme ultraviolet light with a very short wavelength of several nm to several tens of nm is used for the exposure during the formation of the resist mask in the second photolithography process. Extreme ultraviolet light exposure has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length L of the thin film transistor formed later to be 10 nm or more and 1000 nm or less, which can increase the operating speed of the circuit, and since the off-current value is extremely small, low power consumption can also be achieved. For the exposure during the formation of the resist mask in the third photolithography process, ultraviolet light, KrF laser light, or ArF laser light is used. The channel length L of the thin film transistor formed later is determined by the distance between the lower end portions of the adjacent source electrodes and the lower end portions of the drain electrodes on the oxide semiconductor layer 102. When performing exposure with a channel length L < 25 nm, extreme ultraviolet light with a very short wavelength of several nm to several tens of nm is used for the exposure during the formation of the resist mask in the second photolithography process. Extreme ultraviolet light exposure has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length L of the thin film transistor formed later to be 10 nm or more and 1000 nm or less, which can increase the operating speed of the circuit, and since the off-current value is extremely small, low power consumption can also be achieved.

[0099] For the exposure during the formation of the resist mask in the third photolithography process, ultraviolet light, KrF laser light, or ArF laser light is used. The channel length L of the thin film transistor formed later is determined by the distance between the lower end portions of the adjacent source electrodes and the lower end portions of the drain electrodes on the oxide semiconductor layer 102. When performing exposure with a channel length L < 25 nm, extreme ultraviolet light with a very short wavelength of several nm to several tens of nm is used for the exposure during the formation of the resist mask in the second photolithography process. Extreme ultraviolet light exposure has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length L of the thin film transistor formed later to be 10 nm or more and 1000 nm or less, which can increase the operating speed of the circuit, and since the off-current value is extremely small, low power consumption can also be achieved. For the exposure during the formation of the resist mask in the third photolithography process, ultraviolet light, KrF laser light, or ArF laser light is used. The channel length L of the thin film transistor formed later is determined by the distance between the lower end portions of the adjacent source electrodes and the lower end portions of the drain electrodes on the oxide semiconductor layer 102. When performing exposure with a channel length L < 25 nm, extreme ultraviolet light with a very short wavelength of several nm to several tens of nm is used for the exposure during the formation of the resist mask in the second photolithography process. Extreme ultraviolet light exposure has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length L of the thin film transistor formed later to be 10 nm or more and 1000 nm or less, which can increase the operating speed of the circuit, and since the off-current value is extremely small, low power consumption can also be achieved. For the exposure during the formation of the resist mask in the third photolithography process, ultraviolet light, KrF laser light, or ArF laser light is used. The channel length L of the thin film transistor formed later is determined by the distance between the lower end portions of the adjacent source electrodes and the lower end portions of the drain electrodes on the oxide semiconductor layer 102. When performing exposure with a channel length L < 25 nm, extreme ultraviolet light with a very short wavelength of several nm to several tens of nm is used for the exposure during the formation of the resist mask in the second photolithography process. Extreme ultraviolet light exposure has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length L of the thin film transistor formed later to be 10 nm or more and 1000 nm or less, which can increase the operating speed of the circuit, and since the off-current value is extremely small, low power consumption can also be achieved. For the exposure during the formation of the resist mask in the third photolithography process, ultraviolet light, KrF laser light, or ArF laser light is used. The channel length L of the thin film transistor formed later is determined by the distance between the lower end portions of the adjacent source electrodes and the lower end portions of the drain electrodes on the oxide semiconductor layer 102. When performing exposure with a channel length L < 25 nm, extreme ultraviolet light with a very short wavelength of several nm to several tens of nm is used for the exposure during the formation of the resist mask in the second photolithography process. Extreme ultraviolet light exposure has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length L of the thin film transistor formed later to be 10 nm or more and 1000 nm or less, which can increase the operating speed of the circuit, and since the off-current value is extremely small, low power consumption can also be achieved. For the exposure during the formation of the resist mask in the third photolithography process, ultraviolet light, KrF laser light, or ArF laser light is used. The channel length L of the thin film transistor formed later is determined by the distance between the lower end portions of the adjacent source electrodes and the lower end portions of the drain electrodes on the oxide semiconductor layer 102. When performing exposure with a channel length L < 25 nm, extreme ultraviolet light with a very short wavelength of several nm to several tens of nm is used for the exposure during the formation of the resist mask in the second photolithography process. Extreme ultraviolet light exposure has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length L of the thin film transistor formed later to be 10 nm or more and 1000 nm or less, which can increase the operating speed of the circuit, and since the off-current value is extremely small, low power consumption can also be achieved. For the exposure during the formation of the resist mask in the third photolithography process, ultraviolet light, KrF laser light, or ArF laser light is used. The channel length L of the thin film transistor formed later is determined by the distance between the lower end portions of the adjacent source electrodes and the lower end portions of the drain electrodes on the oxide semiconductor layer 102. When performing exposure with a channel length L < 25 nm, extreme ultraviolet light with a very short wavelength of several nm to several tens of nm is used for the exposure during the formation of the resist mask in the second photolithography process. Extreme ultraviolet light exposure has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length L of the thin film transistor formed later to be 10 nm or more and 1000 nm or less, which can increase the operating speed of the circuit, and since the off-current value is extremely small, low power consumption can also be achieved. For the exposure during the formation of the resist mask in the third photolithography process, ultraviolet light, KrF laser light, or ArF laser light is used. The channel length L of the thin film transistor formed later is determined by the distance between the lower end portions of the adjacent source electrodes and the lower end portions of the drain electrodes on the oxide semiconductor layer 102. When performing exposure with a channel length L < 25 nm, extreme ultraviolet light with a very short wavelength of several nm to several tens of nm is used for the exposure during the formation of the resist mask in the second photolithography process. Extreme ultraviolet light exposure has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length L of the thin film transistor formed later to be 10 nm or more and 1000 nm or less, which can increase the operating speed of the circuit, and since the off-current value is extremely small, low power consumption can also be achieved. For the exposure during the formation of the resist mask in the third photolithography process, ultraviolet light, KrF laser light, or ArF laser light is used. The channel length L of the thin film transistor formed later is determined by the distance between the lower end portions of the adjacent source electrodes and the lower end portions of the drain electrodes on the oxide semiconductor layer 102. When performing exposure with a channel length L < 25 nm, extreme ultraviolet light with a very short wavelength of several nm to several tens of nm is used for the exposure during the formation of the resist mask in the second photolithography process. Extreme ultraviolet light exposure has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length L of the thin film transistor formed later to be 10 nm or more and 1000 nm or less, which can increase the operating speed of the circuit, and since the off-current value is extremely small, low power consumption can also be achieved. For the exposure during the formation of the resist mask in the third photolithography process, ultraviolet light, KrF laser light, or ArF laser light is used. The channel length L of the thin film transistor formed later is determined by the distance between the lower end portions of the adjacent source electrodes and the lower end portions of the drain electrodes on the oxide semiconductor layer 102. When performing exposure with a channel length L < 25 nm, extreme ultraviolet light with a very short wavelength of several nm to several tens of nm is used for the exposure during the formation of the resist mask in the second photolithography process. Extreme ultraviolet light exposure has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length L of the thin film transistor formed later to be 10 nm or more and 1000 nm or less, which can increase the operating speed of the circuit, and since the off-current value is extremely small, low power consumption can also be achieved. For the exposure during the formation of the resist mask in the third photolithography process, ultraviolet light, KrF laser light, or ArF laser light is used. The channel length L of the thin film transistor formed later is determined by the distance between the lower end portions of the adjacent source electrodes and the lower end portions of the drain electrodes on the oxide semiconductor layer 102. When performing exposure with a channel length L < 25 nm, extreme ultraviolet light with a very short wavelength of several nm to several tens of nm is used for the exposure during the formation of the resist mask in the second photolithography process. Extreme ultraviolet light exposure has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length L of the thin film transistor formed later to be 10 nm or more and 1000 nm or less, which can increase the operating speed of the circuit, and since the off-current value is extremely small, low power consumption can also be achieved.

[0100] Next, a gate insulating layer 118 is formed on the insulating layer, the oxide semiconductor layer 102, the source electrode 104, and the drain electrode 106 (see Fig. 5(A)). At this time, the gate insulating layer 118 is also formed on the bulk transistor and becomes a part of the interlayer insulating film. Next, a gate insulating layer 118 is formed on the insulating layer, the oxide semiconductor layer 102, the source electrode 104, and the drain electrode 106 (see Fig. 5(A)). At this time, the gate insulating layer 118 is also formed on the bulk transistor and becomes a part of the interlayer insulating film. Next, a gate insulating layer 118 is formed on the insulating layer, the oxide semiconductor layer 102, the source electrode 104, and the drain electrode 106 (see Fig. 5(A)). At this time, the gate insulating layer 118 is also formed on the bulk transistor and becomes a part of the interlayer insulating film.

[0101] Here, the oxide semiconductor ( Since the gate oxide semiconductor (highly purified oxide semiconductor) is extremely sensitive to the interface state and interface charge, The interface between the gate insulating layer and the highly purified oxide semiconductor is important. The insulating layer (GI) is required to be of high quality.

[0102] For example, high-density plasma CVD using microwaves (2.45 GHz) produces dense, highly insulating materials. This is preferable because it allows the formation of a high-quality insulating layer with high pressure. The close contact between the gate insulating layer and the semiconductor substrate reduces the interface state density and improves the interface characteristics. Of course, it is possible to form a high-quality insulating layer as a gate insulating layer. If so, other film formation methods such as sputtering and plasma CVD can be applied. In addition, the film quality of the gate insulating layer and the interface characteristics with the oxide semiconductor are improved by heat treatment after film formation. In any case, the film quality as the gate insulating layer must be good. Of course, it is necessary to reduce the interface state density with the oxide semiconductor and form a good interface. That's good.

[0103] Furthermore, at 85°C, 2 × 10 6 V / cm, 12-hour gate bias and thermal stress test (B In the T test, when impurities are added to an oxide semiconductor, The bond with the main component of is broken by a strong electric field (B: bias) and high temperature (T: temperature), and the generated The dangling bonds induce a shift in the threshold voltage (Vth). In one embodiment of the present invention, impurities, particularly hydrogen, water, and the like, are removed as much as possible from an oxide semiconductor. By improving the interface characteristics with the gate insulating layer, a stable thin film transistor can be obtained even when a BT test is performed.

[0104] In this embodiment, the gate insulating layer 118 is formed by a high-density plasma CVD apparatus using microwaves (2.45 GHz). Here, the high-density plasma CVD apparatus refers to an apparatus capable of achieving a plasma density of 1×10 / cm 1×10 11 / cm 3 or higher. For example, plasma is generated by applying microwave power of 3 kW to 6 kW, and the insulating layer is formed.

[0105] Monosilane gas (SiH4), nitrous oxide (N2O), and a rare gas are introduced into the chamber as material gases, and high-density plasma is generated under a pressure of 10 Pa to 30 Pa to form an insulating layer on the substrate. Thereafter, the supply of monosilane gas may be stopped, and nitrous oxide ( N2O) and a rare gas may be introduced without exposure to the atmosphere to perform plasma treatment on the surface of the insulating layer. The plasma treatment performed on the surface of the insulating layer by introducing at least nitrous oxide (N2O) and a rare gas is performed after the formation of the insulating layer. The insulating layer obtained through the above process has a thin film thickness, for example, less than 100 nm and is an insulating layer capable of ensuring reliability.

[0106] When forming the gate insulating layer 118, the flow rate ratio of monosilane gas (SiH4) to nitrous oxide (N2O) introduced into the chamber is in the range of 1:10 to 1:200. Further, as the rare gas introduced into the chamber, helium, argon, krypton, xenon, etc. can be used , but it is preferable to use argon, which is inexpensive among them.

[0107] ​​​​​​​In addition, the insulating layer obtained by the high-density plasma CVD apparatus can form a layer with a constant thickness and thus has excellent step coverage. Also, the insulating layer obtained by the high-density plasma CVD apparatus can precisely control the thickness of a thin layer.

[0108] The insulating layer obtained through the above process is significantly different in film quality from the insulating layer obtained by a conventional parallel-plate PECVD apparatus. When comparing the etching rates using the same etchant, the etching rate of the insulating layer obtained by the parallel-plate PECVD apparatus is 10% or more, or 20% or more slower. The insulating layer obtained by the high-density plasma CVD apparatus can be said to be a dense layer. In this embodiment, as the gate insulating layer 118, a silicon oxynitride layer (SiO N

[0109] also referred to as, where x > y > 0) with a film thickness of 10 0 nm obtained by a high-density plasma CVD apparatus is used. x N y (also referred to as, provided that x > y > 0) is used.

[0110] As another method, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer can be formed singly or in a stacked manner using a plasma CVD method, a sputtering method, or the like. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 118, it is also preferable to form the gate insulating layer 118 by a sputtering method. When forming a silicon oxide layer by a sputtering method, a silicon target or a quartz target is used as the target, and oxygen or a mixed gas of oxygen and argon is used as the sputtering gas. When forming the gate insulating layer 118 by a sputtering method, it is also preferable. When forming a silicon oxide layer by a sputtering method, a silicon target or a quartz target is used as the target, and oxygen or a mixed gas of oxygen and argon is used as the sputtering gas. It is performed using a mixed gas of oxygen and argon as the sputtering gas.

[0111] The gate insulating layer 118 is separated from the source electrode 104 and the drain electrode 106 by a silicon oxide layer A structure in which silicon nitride layers are stacked can also be used. For example, as the first gate insulating layer a silicon oxide layer (SiO x (x>0)) with a film thickness of 5 nm or more and 300 nm or less is formed, and on the first gate insulating layer, as the second gate insulating layer, a silicon nitride layer (SiN with a film thickness of 50 nm or more and 200 y (y>0)) is stacked by sputtering to form a gate insulating layer with a film thickness of 100 nm.

[0112] Next, a resist mask is formed by a fourth photolithography process, and selective etching is performed to remove a part of the gate insulating layer 118 to form openings reaching the n-type regions 132a and 132b that will become the source region or the drain region of the bulk transistor (see Fig. 5( B)). ).

[0113] Next, after forming a conductive layer on the gate insulating layer 118 with openings formed therein, a fifth photolithography process is used to form the gate electrode 108 and the wiring layers 152 and 153. Note that the resist mask may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0114] Also, the gate electrode 108 and the wiring layers 152 and 153 can be formed as a single layer or stacked using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, or an alloy material having these as the main components. For example, as a stacked structure having two layers for the gate electrode 108 and the wiring layers 152 and 153, a two-layer stacked structure in which a molybdenum layer is stacked on an aluminum layer, or a molybdenum layer is stacked on a copper layer

[0115] For example, as a stacked structure having two layers for the gate electrode 108 and the wiring layers 152 and 153, a two-layer stacked structure in which a molybdenum layer is stacked on an aluminum layer, or a molybdenum layer is stacked on a copper layer, or A two-layer structure formed by laminating layers, or a two-layer structure formed by laminating a titanium nitride layer or tantalum nitride on a copper layer, is preferably a two-layer structure formed by laminating a titanium nitride layer and a molybdenum layer. As the three-layer laminated structure, it is preferably a laminate formed by laminating a tungsten layer or a tungsten nitride layer, an alloy of aluminum and silicon or an alloy of aluminum and titanium, and a titanium nitride layer or a titanium layer. In addition, a gate electrode can be formed using a conductive layer having translucency. Examples of the conductive layer having translucency include translucent conductive oxides.

[0116] In this embodiment, a titanium film with a film thickness of 150 nm is formed as the gate electrode 108 and the wiring layers 152 and 153 by sputtering.

[0117] Next, a second heat treatment (preferably at 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower) is performed in an inert gas atmosphere or an oxygen gas atmosphere. In this embodiment, a second heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere. Also, the second heat treatment may be performed after forming a protective insulating layer or a planarizing insulating layer on the thin film transistor and the bulk transistor.

[0118] Furthermore, heat treatment may be performed in the atmosphere at 100°C or higher and 200°C or lower for 1 hour or more and 30 hours or less. This heat treatment may be performed while maintaining a constant heating temperature, or may be repeated multiple times with a temperature increase from room temperature to a heating temperature of 100°C or higher and 200°C and a temperature decrease from the heating temperature to room temperature. Also, this heat treatment may be performed under reduced pressure before forming the oxide insulating layer. Performing the heat treatment under reduced pressure can shorten the heating time.

[0119] In the above process, an oxide semiconductor layer with reduced concentrations of hydrogen, moisture, hydrides, and hydroxides can be obtained. A thin film transistor can be formed (see Fig. 5(C)). Here, the thin film transistor can be applied as the transfer transistor 101, and the bulk transistor can be applied as the amplification transistor 131.

[0120] In addition, a protective insulating layer 142 or a planarization insulating layer (not shown) for planarization may be provided on the thin film transistor and the bulk transistor. For example, as the protective insulating layer 142, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer can be formed as a single layer or by lamination.

[0121] As the planarization insulating layer, a heat-resistant organic material such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane-based resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. Note that a planarization insulating layer may be formed by laminating a plurality of insulating films formed of these materials.

[0122] The siloxane-based resin corresponds to a resin containing an Si-O-Si bond formed using a siloxane-based material as a starting material. The siloxane-based resin may use an organic group (e.g., an alkyl group or an aryl group) as a substituent. Further, the organic group may have a fluoro group.

[0123] The method for forming the planarization insulating layer is not particularly limited, and depending on the material, a sputtering method, a SOG method, ​​​​​​​​​​​Spin coating, dip coating, spray coating, droplet ejection (inkjet, screen Printing methods such as inkjet printing, offset printing, etc., doctor knife, roll coater, A tool such as a ten coater or a knife coater can be used.

[0124] When the oxide semiconductor film is formed as described above, residual moisture in the atmosphere is removed, The concentrations of hydrogen and hydride in the oxide semiconductor film can be reduced. This makes it possible to stabilize the compound semiconductor film.

[0125] As described above, in a semiconductor device having a thin film transistor using an oxide semiconductor layer, It is possible to provide a semiconductor device having stable electrical characteristics and high reliability.

[0126] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0127] (Embodiment 2) One embodiment of the present invention is a method for manufacturing a semiconductor device that functions as a carrier donor (or acceptor) in an oxide semiconductor. By removing all possible impurities to extremely low levels, the resulting semiconductor is intrinsic or substantially intrinsic. The present embodiment is a conductor, and the oxide semiconductor is applied to a thin film transistor. In this embodiment, the measured values ​​of the off-state current in an evaluation element (also called a TEG) will be described below.

[0128] In Fig. 6, 200 thin-film transistors with L / W = 3 μm / 50 μm are connected in parallel. The initial characteristics of a 3μm / 10000μm thin-film transistor are shown. A top view of the above is shown in FIG. 7(A), and a partially enlarged view of the above is shown in FIG. 7(B). The area enclosed by the dotted line is a thin-film transistor with L / W=3μm / 50μm and Lov=1.5μm. It is a transistor. To measure the initial characteristics of the thin-film transistor, the substrate temperature was set to room temperature, and the source-drain voltage (hereinafter referred to as the drain voltage or Vd) was set to 10V, and the source-gate voltage (hereinafter referred to as the gate voltage or Vg) was changed from -20V to +20V. The change characteristics of the source-drain current (hereinafter referred to as the drain current or Id), that is, the Vg-Id characteristics, were measured. In FIG. 7, Vg is shown in the range from -20V to +5V. The source-drain voltage (hereinafter referred to as the drain voltage or Vd) was set to 10V, and the source-gate voltage (hereinafter referred to as the gate voltage or Vg) was changed from -20V to +20V. The source-drain voltage (hereinafter referred to as the drain voltage or Vd) was set to 10V, and the source-gate voltage (hereinafter referred to as the gate voltage or Vg) was changed from -20V to +20V. The change characteristics of the source-drain current (hereinafter referred to as the drain current or Id), that is, the Vg-Id characteristics, were measured. In FIG. 7, Vg is shown in the range from -20V to +5V. In FIG. 7, Vg is shown in the range from -20V to +5V.

[0129] As shown in FIG. 6, for the thin-film transistor with a channel width W of 10000μm, the off-current is 1×10 [A] or less at Vd of 1V and 10V, and is below the resolution (1 -13 [A]) of the measuring instrument (semiconductor parameter analyzer, Agilent 4156C; manufactured by Agilent). The source-drain voltage (hereinafter referred to as the drain voltage or Vd) was set to 10V, and the source-gate voltage (hereinafter referred to as the gate voltage or Vg) was changed from -20V to +20V. The source-drain voltage (hereinafter referred to as the drain voltage or Vd) was set to 10V, and the source-gate voltage (hereinafter referred to as the gate voltage or Vg) was changed from -20V to +20V.

[0130] That is, the above thin-film transistor exhibits normally-off electrical characteristics, and at a drain voltage of 1V to 10 V, the off-current per 1μm of channel width is 100aA / μm or less, preferably 10aA / μm or less, and more preferably 1aA / μm or less. That is, the above thin-film transistor exhibits normally-off electrical characteristics, and at a drain voltage of 1V to 10 V, the off-current per 1μm of channel width is 100aA / μm or less, preferably 10aA / μm or less, and more preferably 1aA / μm or less.

[0131] The manufacturing method of the measured thin-film transistor will be described.

[0132] First, a silicon nitride layer was formed as an underlayer on a glass substrate by CVD method, and a silicon oxynitride layer was formed on the silicon nitride layer. A tungsten layer was formed as a gate electrode on the silicon oxynitride layer by sputtering method. Here, the tungsten layer was selectively etched to form the gate electrode. First, a silicon nitride layer was formed as an underlayer on a glass substrate by CVD method, and a silicon oxynitride layer was formed on the silicon nitride layer. A tungsten layer was formed as a gate electrode on the silicon oxynitride layer by sputtering method. Here, the tungsten layer was selectively etched to form the gate electrode. First, a silicon nitride layer was formed as an underlayer on a glass substrate by CVD method, and a silicon oxynitride layer was formed on the silicon nitride layer. A tungsten layer was formed as a gate electrode on the silicon oxynitride layer by sputtering method. Here, the tungsten layer was selectively etched to form the gate electrode. First, a silicon nitride layer was formed as an underlayer on a glass substrate by CVD method, and a silicon oxynitride layer was formed on the silicon nitride layer. A tungsten layer was formed as a gate electrode on the silicon oxynitride layer by sputtering method. Here, the tungsten layer was selectively etched to form the gate electrode.

[0133] Next, a silicon oxynitride layer with a thickness of 100 nm was formed as a gate insulating layer on the gate electrode by CVD method. The layer was formed.

[0134] Next, an In-Ga-Zn-O based metal oxide target (mole ratio, In2O3:Ga2O3:ZnO = 1:1:2) was used on the gate insulating layer by sputtering method, and an oxide semiconductor layer with a thickness of 50 nm was formed. Here, the oxide semiconductor layer was selectively etched to form an island -shaped oxide semiconductor layer. The layer was formed.

[0135] Next, the oxide semiconductor layer was heat-treated in a clean oven under a nitrogen atmosphere at 450 °C for 1 hour for the first time.

[0136] Next, a titanium layer (thickness 150 nm ) was formed as a source electrode and a drain electrode on the oxide semiconductor layer by sputtering method. Here, by selectively etching the titanium layer, the source electrode and the drain electrode were formed, and the channel length L of one thin film transistor was 3 μm, and the channel width W was 50 μm. By arranging 200 in parallel, L / W = 3 μm / 10000 μm was achieved.

[0137] Next, a silicon oxide layer was formed with a film thickness of 300 nm as a protective insulating layer by reactive sputtering method so as to be in contact with the oxide semiconductor layer. Here, the silicon oxide layer as a protective layer was selectively etched to form openings on the gate electrode, the source electrode and the drain electrode. Then, a second heat treatment was performed at 250 °C for 1 hour under a nitrogen atmosphere. The treatment was performed.

[0138] And before measuring the Vg-Id characteristics, heating was performed at 150 °C for 10 hours.

[0139] Through the above processes, a bottom-gate type thin film transistor was fabricated.

[0140] As shown in Fig. 6, the off-current of the thin film transistor is about 1×10 -13 [A], because the hydrogen concentration in the oxide semiconductor layer could be sufficiently reduced in the above fabrication process. The hydrogen concentration in the oxide semiconductor layer is 5×10 19 atoms / cm 3 or less, preferably 5×10 18 atoms / cm 3 or less, more preferably 5×10 17 atoms / cm 3 or less, or less than 1×10 16 / cm 3 . Note that the measurement of the hydrogen concentration in the oxide semiconductor layer is performed by secondary ion mass spectrometry (SIMS). Secondary Ion Mass Sp ectroscopy).

[0141] In addition, although an example using an In-Ga-Zn-O based oxide semiconductor was shown, it is not particularly limited, and other oxide semiconductor materials, for example, In-Sn-Zn-O based, Sn-Ga-Zn-O based, Al -Ga-Zn-O based, Sn-Al-Zn-O based, In-Zn-O based, In-Sn-O based, Sn-Zn-O based, Al-Zn-O based, In-O based, Sn-O based, Zn-O based, etc. can be used. In addition, as the oxide semiconductor material, an In-Al-Zn-O based with 2.5 to 10 wt% of Al mixed in or an In-Zn-O based with 2.5 to 10 wt% of Si mixed in can also be used.

[0142] In addition, the carrier concentration of the oxide semiconductor layer measured by a Hall measurement instrument is 5×10 14 / cm 3 or less, preferably 5×1012 / cm 3 Hereinafter, more preferably, the carrier concentration of silicon is 1.45×10 10 / cm 3 or less. That is, the carrier concentration of the oxide semiconductor layer can be made as close to zero as possible.

[0143] Also, it is possible to set the channel length L of the thin film transistor to be 10 nm or more and 1000 nm or less. This can increase the operating speed of the circuit, and since the off-current value is extremely small, further reduction in power consumption can be achieved.

[0144] In addition, in the off state of the thin film transistor, the oxide semiconductor layer can be regarded as an insulator and circuit design can be performed.

[0145] Subsequently, the temperature characteristics of the off-current of the thin film transistor fabricated in this embodiment were evaluated. The temperature characteristics are important in considering the environmental resistance of the final product in which the thin film transistor is used and the maintenance of performance. Naturally, the smaller the change amount, the more preferable, and the degree of freedom in product design increases.

[0146] For the temperature characteristics, using a thermostat, the substrate on which the thin film transistor was formed was set to a constant temperature at each of -30°C, 0°C, 25°C, 40°C, 60°C, 80°C, 100 °C, and 120°C, and the drain voltage was set to 6V, and the gate voltage was changed from -20V to +20V to obtain the Vg-Id characteristics. Fig. 8(A) shows the Vg-Id characteristics measured at the respective temperatures described above overlaid,

[0147] and Fig. 8(B) shows an enlarged view of the off-current region surrounded by the dotted line. The arrows in the figure indicate... The curve at the right end shown was obtained at -30°C, and the curve at the left end was obtained at 120°C. The curves obtained at other temperatures are located in between. Almost no temperature dependence of the on-current is observed. On the other hand, as is also clear in Fig. 8(B) of the enlarged view, the off-current is near 1×10 below the resolution of the measuring instrument at all temperatures except when the gate voltage is near 20V, and there is also no temperature dependence. That is, even at a high temperature of 120°C, the off-current remains at 1×10 below. Considering that the channel width W is 10,000 μm, it can be seen that the off-current is very small. [A] -12 [A] For a thin-film transistor using a highly purified oxide semiconductor, almost no temperature dependence of the off-current appears. This is because, as shown in the band diagram of Fig. 10(A), when the oxide semiconductor is highly purified, the conductivity type approaches the intrinsic type infinitely, and the Fermi level is located at the center of the forbidden band, so it can be said that temperature dependence is not shown. Also, this is due to the fact that the energy of the oxide semiconductor is 3 eV or more, and thermally excited carriers are extremely few. In addition, since the source region and the drain region are in a degenerate state, this is a factor that temperature dependence does not appear. The operation of the thin-film transistor is mostly due to carriers injected from the degenerate source region into the oxide semiconductor. Since there is no temperature dependence of the carrier density, the above characteristics (no temperature dependence of the off-current) can be explained. Also, the extremely low off-current will be explained below using a band diagram. -12 below and maintains below. Considering that the channel width W is 10,000 μm, it can be seen that the off-current is very small.

[0148] For a thin-film transistor using a highly purified oxide semiconductor (purified Oxide Semiconduct or), almost no temperature dependence of the off-current appears. This is because, as shown in the band diagram of Fig. 10(A), when the oxide semiconductor is highly purified, the conductivity type approaches the intrinsic type infinitely, and the Fermi level is located at the center of the forbidden band, so it can be said that temperature dependence is not shown. Also, this is due to the fact that the energy of the oxide semiconductor is 3 eV or more, and thermally excited carriers are extremely few. In addition, since the source region and the drain regions are in a degenerate state, this is a factor that temperature dependence does not appear. The operation of the thin-film transistor is mostly due to carriers injected from the degenerate source region into the oxide semiconductor. Since there is no temperature dependence of the carrier density, the above characteristics (no temperature dependence of the off-current) can be explained. Also, regarding this extremely low off-current, it will be explained below using a band diagram.

[0149] FIG. 9 is a longitudinal sectional view of an inverted staggered thin film transistor using an oxide semiconductor. Gate An oxide semiconductor layer (OS) is provided on the gate electrode (GE1) via a gate insulating film (GI), and a source electrode (S) and a drain electrode (D) are provided thereon.

[0150] FIG. 10 is an energy band diagram (schematic diagram) in the A-A' cross section shown in FIG. 9. FIG. 1 0(A) shows the case where the voltage between the source and the drain is set to an equipotential (VD = 0 V), and FIG. 1 0(B) shows the case where a positive potential (VD> 0) is applied to the drain.

[0151] FIG. 11 is an energy band diagram (schematic diagram) in the B-B' cross section in FIG. 9. FIG. 11(A) shows a state where a positive potential (+ VG) is applied to the gate (G1), and between the source and the drain, it shows an on state in which carriers (electrons) flow. Further, FIG. 11(B) shows a state where a negative potential (-VG) is applied to the gate (G1), and an off state (minority carriers do not flow).

[0152] FIG. 12 shows the relationship M between the vacuum level and the work function (φ ) of the metal and the electron affinity (χ) of the oxide semiconductor.

[0153] Conventional oxide semiconductors are generally n-type, and in that case, the Fermi level (EF) is away from the intrinsic Fermi level (Ei) located at the center of the band gap and is located closer to the conduction band . Note that in the oxide semiconductor, a part of hydrogen becomes a donor, and it is known that this is one of the factors for n-type conversion . This is known.

[0154] On the other hand, the oxide semiconductor according to one aspect of the present invention uses hydrogen, which is an n-type impurity, as an oxide semiconductor Removed from the body and purified to a high purity so that impurities are not contained as much as possible other than the main component of the oxide semiconductor. This is made to be intrinsic (type i) or an attempt is made to make it intrinsic type. That is, instead of adding impurities to make it type i, impurities such as hydrogen and water are removed as much as possible, resulting in high purity purification, and it is characterized by obtaining an i-type (intrinsic) semiconductor that has been purified or approaching it. By doing so the Fermi level (EF) can be brought to the same level as the intrinsic Fermi level (Ei).

[0155] When the band gap (Eg) of the oxide semiconductor is 3.15 eV, the electron affinity (χ) is said to be 4.3 eV. The work function of titanium (Ti) that constitutes the source electrode and the drain electrode is substantially equal to the electron affinity (χ) of the oxide semiconductor. In this case, at the metal-oxide semiconductor interface, a Schottky-type barrier is not formed for electrons.

[0156] That is, when the work function of the metal (φ M ) and the electron affinity (χ) of the oxide semiconductor are equal, when the two come into contact, an energy band diagram (schematic diagram) as shown in Fig. 10(A) is shown.

[0157] In Fig. 10(B), the black circles (●) indicate electrons. When a positive potential is applied to the drain, the electrons cross the barrier (h) and are injected into the oxide semiconductor and flow toward the drain. In this case the height of the barrier (h) changes depending on the gate voltage and the drain voltage, but when a positive drain voltage is applied, the height of the barrier in Fig. 10(A) without voltage application, that is, the band gap (Eg) is smaller than half of the height of the barrier (h).

[0158] At this time, the electrons injected into the oxide semiconductor flow in the oxide semiconductor as shown in Fig. 11(A). Also, in Fig. 11(B), when a negative potential is applied to the gate electrode (G1), since the number of minority carriers, holes, is substantially zero, the current ceases to flow.

[0159] For example, even for a device with a channel width W of 1×10 4 μm and a channel length L of 3 μm, the off-current at room temperature is 10 -13 A or less, and a subthreshold swing value (S value) of 0.1 V / dec. (gate insulating film thickness 100 nm) can be obtained.

[0160] The intrinsic carrier density of the silicon semiconductor is 1.45×10 10 / cm 3 (at 300 K), and carriers exist even at room temperature. This means that thermally excited carriers exist even at room temperature. Furthermore, since the bandgap of the silicon semiconductor is 1.12 e V, the off-current of a transistor using a silicon semiconductor varies greatly depending on temperature. Therefore, instead of simply applying an oxide semiconductor with a wide bandgap to a transistor, by highly purifying the oxide semiconductor so that it contains as few impurities as possible other than the main components,

[0161] the carrier concentration is made 1×10 / cm or less, preferably 1×10 14 / cm 3 or less, 12 / cm 3 so that there are almost no thermally excited carriers at practical operating temperatures, and the transistor can be operated only by the electrons injected from the source side. Thereby, the off-current is 1×10 the off-current can be reduced to 1×10 A or less.-13 Lower it to below A, and obtain a transistor that operates extremely stably with almost no change in the off-current due to temperature changes.

[0162] The technical idea in one aspect of the present invention is to purify the oxide semiconductor itself by removing impurities such as water and hydrogen that are inadvertently present inversely without adding impurities to the oxide semiconductor. That is, it is characterized by removing water or hydrogen that creates donor levels, and at the same time replenishing oxygen to the oxide semiconductor that has become oxygen-deficient, thereby purifying the oxide semiconductor itself. That is, by removing water or hydrogen that creates donor levels, and further replenishing oxygen to the oxide semiconductor that has become oxygen-deficient at the same time, the oxide semiconductor itself is purified.

[0163] Even immediately after film formation, hydrogen at a level of 10 20 / cm 3 is observed by SIMS (secondary ion mass spectrometry). As one of the technical ideas, the oxide semiconductor is purified by intentionally removing water or hydrogen that creates donor levels, and further replenishing oxygen that decreases simultaneously with the removal of water or hydrogen, thereby making it an electrically i-type (intrinsic) semiconductor.

[0164] As a result, the smaller the amount of hydrogen, the better, and the smaller the carriers in the oxide semiconductor, the better. The oxide semiconductor, rather than intentionally having carriers as current carriers when used in a thin-film transistor, conversely has no carriers in the oxide semiconductor and functions as a path for carriers (electrons) supplied from the source to pass through, that is, a so-called highly purified i-type (intrinsic) semiconductor.

[0165] As a result, by making the carriers in the oxide semiconductor absent or extremely small, T ​​​​​​​​​​​The technical idea in one aspect of the present invention is that the off-current of the FT is reduced. That is to say, as an index, the hydrogen concentration is 5×10 19 / cm 3 or less, preferably 5×10 18 / c m 3 or less, more preferably 5×10 17 / cm 3 or less, or 1×10 16 / cm 3 or less, and the carrier density is 1×10 14 / cm 3 or less, preferably 1×10 12 / cm 3 is required.

[0166] As a result, the oxide semiconductor functions as a path, and the oxide semiconductor itself is highly purified into an i-type (intrinsic) that does not supply or hardly supplies carriers, and carriers are supplied by the source and drain.

[0167] Therefore, the smaller the off-current, the better. In the transistor characteristics when a drain voltage between 1 and 10 V is applied, it is characterized in that it is 100 aA / μm (current per channel width W = 1 μm) or less, preferably 10 aA / μm or less, and more preferably 1 aA / μ m or less.

[0168] When a memory circuit (memory element) is fabricated using such a thin film transistor with an extremely small off-current, since the off-current is small and there is almost no leakage, the potential holding time is long, and it becomes possible to hold memory data for a long time.

[0169] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is as follows.

[0170] (Embodiment 3) The operation of a solid-state imaging device including a thin-film transistor according to an aspect of the present invention will be described.

[0171] A CMOS (Complementary Metal Oxide Semiconductor) image sensor, which is a solid-state imaging device, holds a potential in a signal charge storage section and outputs the potential to a vertical output line via an amplification transistor. In a general CMOS image sensor, if there is a leakage current in the reset transistor and / or the transfer transistor, charging or discharging occurs due to the leakage current, and the potential of the signal charge storage section changes. When the potential of the signal charge storage section changes, the potential of the amplification transistor also changes, resulting in a deviation from the original potential and a problem that the captured video deteriorates.

[0172] In this embodiment, the effects of the operation when the thin-film transistors shown in Embodiments 1 and 2 are applied to the transfer transistors of a CMOS image sensor will be described. As described in Embodiment 1, in one aspect of the present invention, the reset transistor can be omitted. Also, either a thin-film transistor or a bulk transistor can be applied to the amplification transistor.

[0173] FIG. 29 is a diagram showing an example of the pixel configuration of a conventional CMOS image sensor. The pixel is composed of a photodiode 1002, which is a photoelectric conversion element, a transfer transistor 1004, a reset transistor 1006, an amplification transistor 1008, and various wirings, and a plurality of them are arranged in a matrix to form a sensor.

[0174] Here, the photodiode 1002 is connected to the source side of the transfer transistor 1004 and a signal charge accumulation section 1010 (also called a floating diffusion, FD) is formed on the drain side of the transfer transistor 1004. The source of the reset transistor 1006 and the gate of the amplification transistor 1008 are connected to the signal charge accumulation section 1010 As another configuration, a selection transistor may be connected to the amplification transistor .

[0175] Next, the operation will be described using the timing chart of FIG. 30. First, a power supply voltage is supplied to the power supply terminal . Subsequently, a reset pulse is input to the gate of the reset transistor 1006, turning on the reset transistor 1006. The signal charge accumulation section 1010 is charged to the potential of the reset power supply . Thereafter, the reset transistor 1006 turns off and the signal charge accumulation section 1010 is held at the potential of the reset power supply. Next, when the transfer transistor 1004 turns on, current flows from the signal charge accumulation section 1010 to the photodiode, and the potential of the signal charge accumulation section 1010 decreases . When the transfer transistor 1004 turns off, the potential at the time of turning off is held in the signal charge accumulation section 1010. Then, it is output to the vertical output line 1120 via the amplification transistor 1008 . Thereafter, the supply of the power supply voltage to the power supply terminal is interrupted . The signal is output in such an order . . . .

[0176] FIG. 13 is a diagram showing an example of the pixel configuration of a CMOS image sensor in one aspect of the present invention . The pixel is composed of a photodiode 1002, which is a photoelectric conversion element, a transfer transistor 1004 , an amplification transistor 1008, and various wirings, and a plurality of them are arranged in a matrix​​ which constitutes a sensor. Further, a selection transistor electrically connected to the amplification transistor 1008 may be provided. One aspect of the present invention is characterized by omitting the reset transistor.

[0177] Here, the photodiode 1002 is connected to the source side of the transfer transistor 1004, and a signal charge accumulation section 1010 is formed on the drain side of the transfer transistor 1004. The gate of the amplification transistor 1008 is connected to the signal charge accumulation section 1010.

[0178] Next, the operation will be described using the timing chart of FIG. 14. First, a power supply voltage is supplied to the power supply terminal. Subsequently, when the potential (RST1) of the reset signal line 1040 becomes high level, the photodiode 1002 becomes forward-biased, and the cathode of the photodiode 1002 becomes a potential lower by the forward voltage (Vf) of the photodiode 1002 than the high level potential of the reset signal line. Next, when the potential of the transfer switch line 1050 becomes high level and the transfer transistor 1004 is turned on, the potential (FD) of the signal charge accumulation section 1010 becomes the potential of the cathode of the photodiode 1002 (period T1). Next, when the potential (RST1) of the reset signal line 1040 becomes low level, the anode of the photodiode 1002 becomes low level, and the photodiode 1002 is in a state of being reverse-biased. Here, a current corresponding to the light irradiated on the photodiode 1002 flows through the photodiode 1002 and the transfer transistor 1004, and the potential of the signal charge accumulation section 1010 decreases (period T2). When the potential of the transfer switch line 1050 becomes low level and the transfer transistor When stage 1004 is turned off, the potential at the time of turning off is held in the signal charge storage unit 1010 (period T3). Here, if almost no leakage current flows through the transfer transistor 1004, the potential (FD) of the signal charge storage unit 1010 is held until the operation of the next transistor. Then, it is output to the vertical output line 1120 via the amplification transistor 1008. After that, the supply of the power supply voltage to the power supply terminal is cut off. The signal is output in such an order. That is, the operation can be performed with a configuration in which the reset transistor is omitted, and by applying the thin film transistor of the oxide semiconductor having an extremely low off-current shown in Embodiments 1 and 2 to the transfer transistor 1004, almost no leakage current through the thin film transistor from the signal charge storage unit 1010 can be eliminated, and an extremely high potential holding function can be made to act during the holding period of the above period T3.

[0179] Next, the operation of the photodiode 1002 will be described with reference to FIG. 15. The photodiode exhibits the same voltage-current characteristics as a normal diode when not irradiated with light (curve A shown in FIG. 15). When irradiated with light, particularly when a reverse bias is applied, a larger current flows compared to when there is no light irradiation (curve B shown in FIG. 15). The movement of the operating point of the photodiode will be described in accordance with the operation of the pixel in FIG. 13. When the reset signal line 1040 and the transfer transistor 1004 are in the off state, since there is no current path to the photodiode 1002, even when irradiated with light, the cathode of the photodiode 1002 is located at point c in FIG. 15. When the potential of the reset signal line 1040 becomes high level, the photodiode 1002 becomes forward biased, and the photodiode 1002 becomes forward biased, and the photodiode 1002 becomes forward biased,

[0180] Next, the operation of the photodiode 1002 will be described with reference to FIG. 15. The photodiode exhibits the same voltage-current characteristics as a normal diode when not irradiated with light (curve A shown in FIG. 15). When irradiated with light, particularly when a reverse bias is applied, a larger current flows compared to when there is no light irradiation (curve B shown in FIG. 15). The photodiode exhibits the same voltage-current characteristics as a normal diode when not irradiated with light (curve A shown in FIG. 15). When irradiated with light, particularly when a reverse bias is applied, a larger current flows compared to when there is no light irradiation (curve B shown in FIG. 15). When irradiated with light, particularly when a reverse bias is applied, a larger current flows compared to when there is no light irradiation (curve B shown in FIG. 15). The movement of the operating point of the photodiode will be described in accordance with the operation of the pixel in FIG. 13. When the reset signal line 1040 and the transfer transistor 1004 are in the off state, since there is no current path to the photodiode 1002, even when irradiated with light, the cathode of the photodiode 1002 is located at point c in FIG. 15. When the potential of the reset signal line 1040 becomes high level, the photodiode 1002 becomes forward biased, Since there is no current path to the photodiode 1002, even when irradiated with light, the cathode of the photodiode 1002 is located at point c in FIG. 15. When the potential of the reset signal line 1040 becomes high level, the photodiode 1002 becomes forward biased, When the potential of the reset signal line 1040 becomes high level, the photodiode 1002 becomes forward biased, The cathode of the diode is lower than the reset potential by the forward voltage of the photodiode. When the transfer transistor 1004 is turned on, the signal charge storage unit 1010 becomes the same potential as the cathode of the photodiode 1002. When the potential of the reset signal line 1040 becomes low here, the photodiode 1002 becomes reverse-biased and becomes point d in FIG. 15. When light is irradiated on the photodiode 1002, a discharge current flows from the signal charge storage unit 1010 through the transfer transistor 1004 to the photodiode 1002, and the potential of the signal charge storage unit 1010 decreases. When the transfer transistor 1004 is turned off, the discharge stops. If the operating point at that time in FIG. 15 is e, the potential difference between the operating point d and the operating point e becomes the potential difference of the signal obtained by the discharge of the photodiode 1002. Next, the operation when the amplification transistor and each signal line are shared by a plurality of pixels will be described. FIG. 16 shows a basic form in which there is one transfer transistor, one amplification transistor, and one photodiode in each pixel, and the reset signal line, transfer switch line, and vertical output line are connected to the pixel. The operation of the basic form will be described according to the timing chart of FIG. 17. For the drive of the first line, first, when the potential (RST1) of the first reset signal line 1240 becomes high, the first photo

[0181] diode 1212 becomes forward-biased, and the cathode of the first photodiode 1212 is lower than the high-level potential of the first reset signal line 1240 by the forward voltage of the photodiode ( Vf). Next, when the potential (TRF) of the first transfer switch line 1250 becomes high, the first transfer transistor 1220 is turned on, and the potential of the signal charge storage unit 1230 becomes the same as the cathode of the first photodiode 1212.

[0182] Next, the operation when the amplification transistor and each signal line are shared by a plurality of pixels will be described. For the drive of the first line, first, when the potential (RST1) of the first reset signal line 1240 becomes high, the first photo diode 1212 becomes forward-biased, and the cathode of the first photodiode 1212 is lower than the high-level potential of the first reset signal line 1240 by the forward voltage of the photodiode ( Vf). Next, when the potential (TRF) of the first transfer switch line 1250 becomes high, the first transfer transistor 1220 is turned on, and the potential of the signal charge storage unit 1230 becomes the same as the cathode of the first photodiode 1212. When 1) becomes high level, the first transfer transistor 1214 is turned on, and the signal charge storage section The potential (FD) of 1210 becomes the same as the cathode of the first photodiode 1212. Next, when the potential (RST1) of the first reset signal line 1240 becomes low level, At this time, the anode of the first photodiode 12 is at a low level potential. The first photodiode 1212 is reverse biased. A current according to the first photodiode 1212 and the first transfer transistor 1214 The potential (FD) of the signal charge storage section 1210 is lowered by the discharge. When the potential (TRF1) of the switch line 1250 becomes low level, the first transfer transistor 121 4 is turned off and the current path is cut off, so the potential (FD) of the signal charge storage section 1210 is maintained. This potential is output to the vertical output line 1220 via the first amplification transistor 1218. Then, the second line is driven, and so on.

[0183] Figure 18 differs from the basic form above in that it has an amplifier transistor, a reset transistor, and a The figure shows a vertical 4-pixel shared type configuration that uses the same signal line. This allows for miniaturization by reducing the pixel area, and noise reduction by expanding the light receiving area of ​​the photodiode. The drain side of the transfer transistor of each of the four vertical pixels is electrically The signal charge storage section 1410 is connected to the amplifier. The gate of transistor 1408 is connected.

[0184] The operation of the vertical 4-pixel sharing type will be described with reference to the timing chart in FIG. The driving process starts when the potential (RST1) of the first reset signal line 1461 becomes high level. The first photodiode 1412 becomes forward-biased, and the cathode of the first photodiode 1412 is at a potential that is lower than the high-level potential of the first reset signal line 1461 by the forward voltage (Vf) of the photodiode. Next, when the potential (TRF1) of the first transfer switch line 1451 becomes high level, the first transfer transistor 1414 turns on, and the potential (FD1) of the signal charge storage unit 1410 becomes the same as the cathode of the first photodiode 1412. Next, when the potential (RST1) of the first reset signal line 1461 becomes low level, the anode of the photodiode becomes low-level potential. At this time, the first photodiode 1412 becomes reverse-biased. Here, a current corresponding to the light irradiated on the first photodiode 1412 flows through the first photodiode 1412 and the first transfer transistor 1414, and the potential (FD1) of the signal charge storage unit 1410 decreases due to discharge. When the potential (TRF1) of the first transfer switch line 1451 becomes low level, the first transfer transistor 1414 turns off, and the current path is blocked, so the potential (FD1) of the signal charge storage unit 1410 is held. This potential is output to the vertical output line 1470 through the first amplification transistor 1408. When the potential (TRF1) of the first transfer switch line 1451 becomes low level, the first transfer transistor 1414 turns off, and the current path is blocked, so the potential (FD1) of the signal charge storage unit 1410 is held. This potential is output to the vertical output line 1470 through the first amplification transistor 1408. is held. This potential is output to the vertical output line 1470 through the first amplification transistor 1408. FD1) is held. This potential is output to the vertical output line 1470 through the first amplification transistor 1408.

[0185] For the driving of the second line, first, when the potential (RST1) of the first reset signal line 1461 becomes high level, the second photodiode 1422 becomes forward-biased, and the cathode of the second photodiode 1422 is at a potential that is lower than the high-level potential of the first reset signal line 1461 by the forward voltage (Vf) of the photodiode. Next, when the potential (TRF1) of the first transfer switch line 1451 is at a potential that is lower than the high-level potential of the first reset signal line 1461 by the forward voltage (Vf) of the photodiode. Next, when the potential (TRF1) of the second transfer switch becomes high level, the second transfer transistor 1424 turns on, and the potential (FD2) of the signal charge storage unit 1420 becomes the same as the cathode of the second photodiode 1422. ​​​​When the potential of line 1452 (TRF2) becomes high level, the second transfer transistor 1424 turns on, and the potential of the signal charge accumulation section 1410 (FD1) becomes the same potential as the cathode of the second photodiode 1422 . Next, when the potential of the first reset signal line 1461 (RST1) becomes low level, the anode of the photodiode becomes low level potential. At this time, the second photodiode 1422 is reverse-biased. Here, the current corresponding to the light irradiated on the second photodiode 1 422 flows through the second photodiode 1422 and the second transfer transistor 1424, and the potential of the signal charge accumulation section 1410 (FD1) decreases due to discharge . When the potential of the second transfer switch line 1452 (TRF2) becomes low level, the second transfer transistor 1424 turns off, and the current path is cut off, so the potential of the signal charge accumulation section 14 10 (FD1) is held. This potential is output to the vertical output line 1470 through the first amplification transistor 1408 .

[0186] For the driving of the third line, first, when the potential of the first reset signal line 1461 (RST1) becomes high level , the third photodiode 1432 becomes forward-biased, and the cathode of the third photodiode 1432 becomes a potential lower than the high level potential of the first reset signal line 1461 by the forward voltage (Vf) of the photodiode. Next, when the potential of the third transfer switch line 1453 (TRF3) becomes high level, the third transfer transistor 1434 turns on, and the potential of the signal charge accumulation section 1410 (FD1) becomes the same potential as the cathode of the third photodiode 1432 . Next, when the potential of the first reset signal line 1461 (RST1) becomes low level, the anode of the photodiode becomes low level potential. At this time, the third photodiode 1432 becomes reverse-biased. At this time, the current corresponding to the light irradiated on the third photodiode 1432 flows through the third photodiode 1432 and the third transfer transistor 1434, and the potential of the signal charge accumulation section 1410 (FD1) decreases due to discharge. When the potential of the third transfer switch line 1453 (TRF3) becomes low level, the third transfer transistor 1434 turns off, and the current path is cut off, so the potential of the signal charge accumulation section 1410 (FD1) is held. This potential is output to the vertical output line 1470 through the first amplification transistor 1408. The third photodiode 1432 is reverse-biased. Here, a current corresponding to the light irradiated on the third photodiode 1 432 flows through the third photodiode 1432 and the third transfer transistor 1434, and the potential (FD1) of the signal charge accumulation unit 1410 decreases due to discharge. When the potential (TRF3) of the third transfer switch line 1453 becomes low level, the third transfer transistor 1434 turns off and the current path is cut off, so the potential (FD1) of the signal charge accumulation unit 14 10 is held. This potential is output to the vertical output line 1470 via the first amplification transistor 1408.

[0187] For the driving of the fourth line, first, when the potential (RST1) of the first reset signal line 1461 becomes high level, the fourth photodiode 1442 becomes forward-biased, and the cathode of the fourth photodiode 1442 becomes a potential lower by the forward voltage (Vf) of the photodiode than the high-level potential of the first reset signal line 1461. Next, when the potential (TRF4) of the fourth transfer switch line 1454 becomes high level, the fourth transfer transistor 1444 turns on, and the potential (FD1) of the signal charge accumulation unit 1410 becomes the same potential as the cathode of the fourth photodiode 1442. Next, when the potential (RST1) of the first reset signal line 1461 becomes low level, the anode of the photodiode becomes low-level potential. At this time, the fourth photodiode 1442 becomes reverse-biased. Here, a current corresponding to the light irradiated on the fourth photodiode 1 442 flows through the fourth photodiode 1442 and the fourth transfer transistor 1444, and the potential (FD1) of the signal charge accumulation unit 1410 discharges. It decreases due to electricity. When the potential (TRF4) of the fourth transfer switch line 1454 becomes low level the fourth transfer transistor 1444 turns off and the current path is interrupted, so the potential (FD1) of the signal charge storage section 1410 is held. This potential is output to the vertical output line 1470 via the first amplification transistor 1408 For the driving from the fifth line to the eighth line the potential of the second reset signal line becomes high level and it is driven sequentially in the same way.

[0188] Figure 20 has a pixel sharing configuration different from that of Figure 18, and is a vertical and horizontal four-pixel sharing type that also serves as a reset signal line and an amplification transistor. For four pixels adjacent vertically and horizontally the drain sides of the transfer transistors of each pixel are electrically connected, a signal charge storage section 1510 is formed, and the gate of the amplification transistor 1508 is connected to the signal charge storage section 1510. Similar to the vertical four-pixel sharing type, by reducing transistors and wiring, miniaturization due to reduction of pixel area and noise can be reduced by expanding the light receiving area of the photodiode. For four adjacent pixels vertically and horizontally the drain sides of the transfer transistors of each pixel are electrically connected and a signal charge storage section 1510 is formed, and the gate of the amplification transistor 1508 is connected to the signal charge storage section 1510. The operation of the vertical and horizontal four-pixel sharing type will be described according to the timing chart of Figure 21. For the driving of the first line

[0189] First, when the potential (RST1) of the first reset signal line 1561 becomes high level the first photodiode 1512 becomes forward-biased, and the cathode of the first photodiode 15 12 becomes a potential that is lower than the high level potential of the first reset signal line 1561 by the forward voltage (Vf) of the photodiode. Next, when the potential (TRF1) of the first transfer switch line 1551 becomes high level, the first transfer transistor 1514 turns on and when the potential (TRF1) of the first transfer switch line 1551 becomes high level, the first transfer transistor 1514 turns on, The potential (FD1) of the signal charge accumulation unit 1510 is the same as the cathode of the first photodiode 1512. It becomes the same potential.

[0190] Next, when the potential (RST1) of the first reset signal line 1561 becomes low level, the anode of the photodiode drops to the low level potential. At this time, the first photodiode 15 12 becomes reverse biased. Here, the current corresponding to the light irradiated on the first photodiode 1512 flows through the first photodiode 1512 and the first transfer transistor 1514 and the potential (FD1) of the signal charge accumulation unit 1510 decreases due to discharge. When the potential (TRF1) of the first transfer switch line 1551 becomes low level, the first transfer transistor 15 14 turns off and the current path is blocked, so the potential (FD1) of the signal charge accumulation unit 1510 is maintained. This potential is output to the vertical output line 1570 through the first amplification transistor 1508 . When the potential (TRF1) of the first transfer switch line 1551 becomes low level, the first transfer transistor 15 14 turns off and the current path is blocked, so the potential (FD1) of the signal charge accumulation unit 1510 is maintained. This potential is output to the vertical output line 1570 through the first amplification transistor 1508 and output to the vertical output line 1570 through the first amplification transistor 1508. Output.

[0191] Next, when the potential (RST1) of the first reset signal line 1561 becomes high level again, the second photodiode 1522 becomes forward biased and the cathode of the second photodiode 1522 is at a potential lower than the high level potential of the first reset signal line 1561 by the forward voltage (Vf) of the photodiode. Next, when the potential of the second transfer switch line 1552 (TRF2) becomes high level, the second transfer transistor 1524 turns on and the potential (FD1) of the signal charge accumulation unit 1510 becomes the same as the cathode of the second photodiode 1522 . Next, when the potential of the second transfer switch line 1552 (TRF2) becomes high level, the second transfer transistor 1524 turns on and the potential (FD1) of the signal charge accumulation unit 1510 becomes the same as the cathode of the second photodiode 1522 and the potential of the signal charge accumulation unit 1510 becomes the same as the cathode of the second photodiode 1522. It becomes the same potential.

[0192] Next, when the potential (RST1) of the first reset signal line 1561 becomes low level, the photo The anode of the diode becomes the low-level potential. At this time, the second photodiode 152 2 is reverse-biased. Here, the current corresponding to the light irradiating the second photodiode 1522 flows through the second photodiode 1522 and the second transfer transistor 1524, and the potential (FD1) of the signal charge storage unit 1510 decreases due to discharge. When the potential (TRF2) of the second transfer switch line 1552 becomes low level, the second transfer transistor 1524 turns off and the current path is blocked, so the potential (FD1) of the signal charge storage unit 1510 is held. This potential is output to the vertical output line 1570 via the first amplification transistor 1508. When the potential (TRF2) of the second transfer switch line 1552 becomes low level, the second transfer transistor 1524 turns off and the current path is blocked, so the potential (FD1) of the signal charge storage unit 1510 is held. This potential is output to the vertical output line 1570 via the first amplification transistor 1508. This potential is output to the vertical output line 1570 via the first amplification transistor 1508. Through these two operations, the outputs of the pixels in the first line are sequentially output to the vertical output line 1570. Through these two operations, the outputs of the pixels in the first line are sequentially output to the vertical output line 1570.

[0193] For the driving of the second line, first, when the potential (RST1) of the first reset signal line 1561 becomes high level, the third photodiode 1532 becomes forward-biased, and the cathode of the third photodiode 1532 becomes a potential lower than the high-level potential of the first reset signal line 1561 by the forward voltage (Vf) of the photodiode. Next, when the potential (TRF3) of the third transfer switch line 1553 becomes high level, the third transfer transistor 1534 turns on, and the potential (FD1) of the signal charge storage unit 1510 becomes the same potential as the cathode of the third photodiode 1532. For the driving of the second line, first, when the potential (RST1) of the first reset signal line 1561 becomes high level, the third photodiode 1532 becomes forward-biased, and the cathode of the third photodiode 1532 becomes a potential lower than the high-level potential of the first reset signal line 1561 by the forward voltage (Vf) of the photodiode. Next, when the potential (TRF3) of the third transfer switch line 1553 becomes high level, the third transfer transistor 1534 turns on, and the potential (FD1) of the signal charge storage unit 1510 becomes the same potential as the cathode of the third photodiode 1532. Next, when the potential (TRF3) of the third transfer switch line 1553 becomes high level, the third transfer transistor 1534 turns on, and the potential (FD1) of the signal charge storage unit 1510 becomes the same potential as the cathode of the third photodiode 1532. Next, when the potential (TRF3) of the third transfer switch line 1553 becomes high level, the third transfer transistor 1534 turns on, and the potential (FD1) of the signal charge storage unit 1510 becomes the same potential as the cathode of the third photodiode 1532.

[0194] Next, when the potential (RST1) of the first reset signal line 1561 becomes low level, the anode of the photodiode drops to the low-level potential. At this time, the third photodiode 15 32 becomes reverse-biased. Here, the light irradiating the third photodiode 1532 Next, when the potential (RST1) of the first reset signal line 1561 becomes low level, the anode of the photodiode drops to the low-level potential. At this time, the third photodiode 15 A current corresponding thereto flows through the third photodiode 1532 and the third transfer transistor 1534 and the potential (FD1) of the signal charge storage unit 1510 decreases due to discharge. When the potential (TRF3) of the third transfer switch line 1553 becomes low level, the third transfer transistor 15 34 turns off and the current path is interrupted, so the potential (FD1) of the signal charge storage unit 1510 is maintained. This potential is output to the vertical output line 1570 through the first amplification transistor 1508 . . .

[0195] Next, when the potential (RST1) of the first reset signal line 1561 becomes high level again, the fourth photodiode 1542 becomes forward-biased, and the cathode of the fourth photodiode 1542 is at a potential lower than the high level potential of the first reset signal line 1561 by the forward voltage (Vf) of the photodiode. Next, when the potential (TRF4) of the fourth transfer switch line 1554 becomes high level, the fourth transfer transistor 1544 turns on, and the potential (FD1) of the signal charge storage unit 1510 becomes the same potential as the cathode of the fourth photodiode 1542 . . . . . .

[0196] Next, when the potential (RST1) of the first reset signal line 1561 becomes low level, the anode of the photodiode becomes low level potential. At this time, the fourth photodiode 154 2 becomes reverse-biased. Here, a current corresponding to the light irradiated on the fourth photodiode 1542 flows through the fourth photodiode 1542 and the fourth transfer transistor 1544, and the potential (FD1) of the signal charge storage unit 1510 decreases due to discharge. When the potential (TRF4) of the fourth transfer switch line 1554 becomes low level, the fourth transfer transistor 154 . . . 4 turns off When 4 is turned off and the current path is interrupted, the potential (FD1) of the signal charge storage unit 1510 is held. This potential is output to the vertical output line 1570 via the first amplification transistor 1508. Through these two operations, the outputs of the pixels on the second line are sequentially output to the vertical output line 1570. Next, the potential of the second reset signal line becomes high level, and driving is performed sequentially in the same manner.

[0197] FIG. 22 is a transfer switch line sharing type that doubles as a reset signal line, a transfer switch line, and an amplification transistor for two pixels each in the vertical and horizontal directions. It further shares the transfer switch line in addition to the pixel sharing type described above. By reducing the transistors and wiring, miniaturization due to the reduction of the pixel area and noise reduction by expanding the light receiving area of the photodiode can be achieved. For four adjacent pixels in the vertical and horizontal directions, the drain sides of the transfer transistors of each pixel are electrically connected to form a signal charge storage unit, and the gate of the amplification transistor is connected to the signal charge storage unit. Also, this configuration is characterized in that two transfer transistors located in the vertical direction share the transfer switch line, so there are transistors that move simultaneously not only in the horizontal direction but also in the vertical direction.

[0198] The operation of the transfer switch line sharing type will be described according to the timing chart of FIG. 23. For the first line and the second line of driving, first, when the potential (RST1) of the first reset signal line 1665 and the potential (RST2) of the second reset signal line 1666 become high level, the first photodiode 1612 and the third photodiode 1632 become forward-biased, and the cathodes of the first photodiode 1612 and the third photodiode 1632 are connected to the first reset. ​ The potential will be lower than the high-level potential of the signal line 1665 and the second reset signal line 1666 by the forward voltage (Vf) of the photodiode. It becomes a potential that is lowered by the forward voltage (Vf) of the photodiode.

[0199] Next, when the potential (TRF1) of the first transfer switch line 1751 becomes high level, the first transfer transistor 1614 turns on, and the potential (FD1) of the first signal charge storage unit 1610 becomes the same potential as the cathode of the first photodiode 1612, and the potential (FD2) of the second signal charge storage unit 1 620 becomes the same potential as the cathode of the third photodiode 1612. . Next, when the potential (RST1) of the first reset signal line 1665 and the potential (RST2) of the second reset signal line 16 66 become low level, the anode of the photodiode becomes low level potential. At this time, the first photodiode 1612 and the third photodiode 1 632 are reverse-biased. Here, the current corresponding to the light irradiated on the first photodiode 1612 and the third photodiode 1 flows through the first photodiode 1612, the third photodiode 1632, the first transfer transistor 1614, and the third transfer transistor 1 634, and the potential (FD1) of the first signal charge storage unit 1610 and the second potential (FD2) of the signal charge storage unit 1620 decreases due to discharge. When the potential (TRF1) of the first transfer switch line 1751 becomes low level, the first transfer transistor 1614 and the third transfer transistor 1634 turn off, and since the current path is cut off, the potential (FD1) of the first signal charge storage unit 1610 and the potential (FD2) of the second signal charge storage unit 1620 are maintained. These potentials are passed through the first amplification transistor 1618 to the first vertical output line 1 via Output to 675 and output to the second vertical output line 1676 via the second amplification transistor 1628. Output.

[0200] Next, when the potential (RST1) of the first reset signal line 1665 and the potential (RST2) of the second reset signal line 1666 become high level, the second photodiode 1622 and the fourth photodiode 1642 are forward-biased, and the cathodes of the second photodiode 162 2 and the fourth photodiode 1642 are at a potential lower than the high-level potential of the first reset signal line 1665 and the second reset signal line 1666 by the forward voltage (V f) of the photodiode.

[0201] Next, when the potential (TRF2) of the second transfer switch line 1572 becomes high level, the second transfer transistor 1624 and the fourth transfer transistor 1644 turn on, and the potential (FD1) of the first signal charge accumulation section 1610 becomes the same potential as the cathode of the second photodiode 1622, and the potential (FD2) of the second signal charge accumulation section 1620 becomes the same potential as the cathode of the fourth photodiode 1642. Next, when the potential (RS T1) of the first reset signal line 1665 and the potential (RST2) of the second reset signal line 1666 become low level, the anode of the photodiode becomes low level. At this time, the second photodiode 1 622 and the fourth photodiode 1642 are reverse-biased. Here, the current corresponding to the light irradiated on the second photodiode 1622 and the fourth photodiode 1642 flows through the second photodiode 1622, the fourth photodiode 1642, the second transfer transistor 1624 and the fourth transfer transistor 1644, and flows into the first signal charge accumulation section 1610. 1610. The potential of the first signal charge storage unit 1610 (FD1) and the potential of the second signal charge storage unit 1620 (FD2) decrease due to discharge. When the potential of the second transfer switch line 1572 (TRF2) becomes low level, the second transfer transistor 1624 and the fourth transfer transistor 1644 turn off, and the current path is blocked, so the potential of the first signal charge storage unit 1610 (FD1) and the second signal charge storage unit 1620 (FD2) are held. These potentials are output to the first vertical output line 1675 via the first amplification transistor 1618, and output to the second vertical output line 1676 via the second amplification transistor 1628. Through these two operations, the outputs of the pixels in the first row and the second row are sequentially output to the first vertical output line 1675 and the second vertical output line 1676.

[0202] Next, the driving of the third row and the fourth row will be described. First, when the potential of the third reset signal line 1667 (RST3) and the potential of the fourth reset signal line 1668 (RST4) become high level, the fifth photodiode 1652 and the seventh photodiode 1672 become forward-biased, and the cathodes of the fifth photodiode 1652 and the seventh photodiode 167 2 become the potential that is lower than the high level potential of the third reset signal line 1667 and the fourth reset signal line 1668 by the forward voltage (Vf) of the photodiode.

[0203] Next, when the potential of the third transfer switch line 1753 (TRF3) becomes high level, the fifth transfer transistor 1654 and the seventh transfer transistor 1674 turn on, and the potential of the second signal charge storage unit 1620 (FD2) and the potential of the third signal charge storage unit 1630 (FD3) The same as the cathodes of the fifth photodiode 1652 and the seventh photodiode 1672 becomes the potential. Next, when the potential of the third reset signal line 1667 (RST3) and the potential of the fourth reset signal line 1668 (RST4) become low level, the anodes of the photodiodes become low level potential. At this time, the fifth photodiode 1652 and the seventh photodi ode 1672 are reverse-biased. Here, a current corresponding to the light irradiated on the fifth photodiode 1652 and the seventh photodiode 1672 flows through the fifth photodi ode 1652, the seventh photodiode 1672, the fifth transfer transistor 1654 and the seventh transfer transistor 1674, and the potential (FD2) of the second signal charge accumulation section 1620 and the potential (FD3) of the third signal charge accumulation section 1630 decrease due to discharge. When the potential of the third transfer switch line 1753 (TRF3) becomes low level, the fifth transfer transist or 1654 and the seventh transfer transistor 1674 turn off, and the current path is cut off, so the potential (FD2) of the second signal charge accumulation section 1620 and the potential of the third signal charge accumulation section 1630 (FD3) are held. This potential is output to the second vertical output line 1676 via the second amplification transistor and output to the first vertical output line 1675 via the third amplification transistor .

[0204] Next, when the potential of the third reset signal line 1667 (RST3) and the potential of the fourth reset signal line 1668 (RST4) become high level, the sixth photodiode 1662 and the eighth photodiode 1682 become forward-biased, and the cathodes of the sixth photodiode 166 2 and the eighth photodiode 1682 are the third reset signal line 1667 and the ​The potential will be lower than the high-level potential of the reset signal line 1668 of 4 by the forward voltage (Vf ) of the photodiode.

[0205] Next, when the potential of the fourth transfer switch line 1754 (TRF4) becomes high level, the sixth transfer transistor 1664 and the eighth transfer transistor 1684 turn on, and the potential (FD2) of the second signal charge accumulation unit 1620 and the potential (FD3) of the third signal charge accumulation unit 1630 become the same as the cathodes of the sixth photodiode 1662 and the eighth photodiode 1682. Next, when the potential (RST3) of the third reset signal line 1667 and the potential (RST4) of the fourth reset signal line 1668 become low level, the anodes of the photodiodes fall to the low-level potential. At this time, the sixth photodiode 1662 and the eighth photodiode 1682 are reverse-biased. Here, a current corresponding to the light irradiated on the sixth photodiode 1662 and the eighth photodiode 1682 flows through the sixth photodiode 1662, the eighth photodiode 1682, the sixth transfer transistor 1664 and the eighth transfer transistor 1684, and the potential (FD2 ) of the second signal charge accumulation unit 1620 and the potential (FD3) of the third signal charge accumulation unit 1630 decrease due to discharge. When the potential (TRF4) of the fourth transfer switch line 1754 becomes low level, the sixth transfer transistor 1664 and the eighth transfer transistor 1684 turn off, and the current path is blocked, so the potential (FD2) of the second signal charge accumulation unit 1620 and the potential ( FD3) of the third signal charge accumulation unit 1630 are held. This potential is output to the second vertical output line 1 676 via the second amplification transistor and output to the first vertical output line 1675 via the third amplification transistor. FD3) is output to the first vertical output line 1675 via the third amplification transistor. ​ 。In these two operations, the outputs of the pixels on the third and fourth lines are sequentially output to the second vertical output line 167 6 and the first vertical output line 1675. Subsequently, the operations are performed in this manner sequentially.

[0206] FIG. 24 is a diagram of the entire CMOS image sensor. Reset terminal drive circuits 2020 and transfer terminal drive circuits 2040 are arranged on both sides of the pixel matrix 2100 having a pixel section 2000. In FIG. 24, the drive circuits are arranged on both sides of the pixel matrix 2100, but the drive circuits may be arranged on one side as well. Further, a vertical output line drive circuit 2060 is arranged in the vertical direction with respect to the wiring for outputting signals from the drive circuits. Since the reset terminal drive circuit 2020 and the transfer terminal drive circuit 2040 are drive circuits for binary outputs of low and high, they can be driven by a combination of a shift register 2200 and a buffer circuit 2300 as shown in FIG. 25 . These drive circuits can be composed of bulk transistors or thin film transistors, but it is preferable to use bulk transistors using a silicon semiconductor capable of forming complementary transistors . The vertical output line drive circuit 2060 can be composed of a shift register 2210, a buffer circuit 2310, and an analog switch 2400 as shown in FIG. 26. Each vertical output line 2120 is selected by the analog switch 2400, and a video signal is output to the video output line 2500 . The analog switch 2400 is sequentially selected by the shift register 2210 and the buffer circuit 2310. The vertical output line drive circuit 2060 can be composed of bulk transistors or thin film transistors, but a silicon semiconductor capable of forming complementary transistors

[0207] is used. The vertical output line drive circuit 2060 can be configured by a shift register 2210, a buffer circuit 2310, and an analog switch 2400. Each vertical output line 2120 is selected by the analog switch 2400, and a video signal is output to the video output line 2500 . The analog switch 2400 is sequentially selected by the shift register 2210 and the buffer circuit 2310. The vertical output line drive circuit 2060 can be composed of bulk transistors or thin film transistors, but a silicon semiconductor capable of forming complementary transistors is used. It is preferable to use a bulk transistor using a recon semiconductor.

[0208] Fig. 27 shows an example of a shift register and a buffer circuit. Shown in Fig. 27 is an example of a shift register 2220 composed of clocked inverters and a buffer circuit 2320 composed of inverters. The shift register and the buffer circuit are not limited to this circuit, and the reset terminal drive circuit 2020, the transfer terminal drive circuit 2040, and the vertical output line drive circuit 2060 are also not limited to the above configuration.

[0209] The solid-state imaging device according to the above embodiment can be applied to various electronic devices (including gaming machines). For example, it can be used in electronic devices having means for acquiring image information, such as digital cameras, digital video cameras, mobile phones, portable game machines, and portable information terminals.

[0210] This embodiment can be implemented in appropriate combination with other embodiments.

Explanation of Reference Numerals

[0211] 100 Single-crystalline silicon substrate 101 Transfer transistor 102 Oxide semiconductor layer 104 Source electrode 106 Drain electrode 108 Gate electrode 110 Photoelectric conversion element 114 p-type region 116 Signal charge accumulation section 118 Gate insulating layer 131 Amplification transistor 136 Gate insulating layer 138 Gate electrode 140 Insulating film 142 Protection insulating layer ​​​​​​​152 Wiring layer 154 Wiring 132a n-type region 138a Conductive layer 138b Conductive layer 201 Transistor 204 Source electrode 210 Photoelectric conversion element 301 Transistor 304 Source electrode 305 Buffer layer 306 Drain electrode 310 Photoelectric conversion element 112 n-type region 450 Under nitrogen atmosphere 501 Transfer transistor 510 Photoelectric conversion element 516 Signal charge storage section 531 Amplification transistor 540 Capacitance electrode 541 Insulating film 600 Lens 602 Color filter 604 Wiring layer 606 Interlayer insulating film 608 Photoelectric conversion element 610 Lens 612 Color filter 618 Photoelectric conversion element 1002 Photodiode 1004 Transfer transistor 1006 Reset transistor 1008 Amplification transistor 1010 Signal charge storage section 1040 Reset signal line 1050 Transfer switch line 1120 Vertical output line 1210 Signal charge storage section 1212 Photodiode 1214 Transfer transistor 1218 Amplification transistor 1220 Vertical output line 1240 Reset signal line 1250 Transfer Switch Line 1408 Amplifying Transistor 1410 Signal Charge Accumulation Section 1412 Photodiode 1414 Transfer Transistor 1422 Photodiode 1424 Transfer Transistor 1432 Photodiode 1434 Transfer Transistor 1442 Photodiode 1444 Transfer Transistor 1451 Transfer Switch Line 1452 Transfer Switch Line 1453 Transfer Switch Line 1454 Transfer Switch Line 1461 Reset Signal Line 1470 Vertical Output Line 1508 Amplifying Transistor 1510 Signal Charge Accumulation Section 1512 Photodiode 1514 Transfer Transistor 1522 Photodiode 1524 Transfer Transistor 1532 Photodiode 1534 Transfer Transistor 1542 Photodiode 1544 Transfer Transistor 1551 Transfer Switch Line 1552 Transfer Switch Line 1553 Transfer Switch Line 1554 Transfer Switch Line 1561 Reset Signal Line 1570 Vertical Output Line 1572 Transfer Switch Line 1610 Signal Charge Accumulation Section 1612 Photodiode 1614 Transfer Transistor 1618 Amplifying Transistor 1620 Signal Charge Accumulation Section 1622 Photodiode 1624 Transfer Transistor 1628 Amplification Transistor 1630 Signal Charge Accumulation Section 1632 Photodiode 1634 Transfer Transistor 1642 Photodiode 1644 Transfer Transistor 1652 Photodiode 1654 Transfer Transistor 1662 Photodiode 1664 Transfer Transistor 1665 Reset Signal Line 1666 Reset Signal Line 1667 Reset Signal Line 1668 Reset Signal Line 1672 Photodiode 1674 Transfer Transistor 1675 Vertical Output Line 1676 Vertical Output Line 1682 Photodiode 1684 Transfer Transistor 1751 Transfer Switch Line 1753 Transfer Switch Line 1754 Transfer Switch Line 2000 Pixel Section 2020 Reset Terminal Drive Circuit 2040 Transfer Terminal Drive Circuit 2060 Vertical Output Line Drive Circuit 2100 Pixel Matrix 2120 Each Vertical Output Line 2200 Shift Register 2210 Shift Register 2220 Shift Register 2300 Buffer Circuit 2310 Buffer Circuit 2320 Buffer Circuit 2400 Analog Switch 2500 Video Output Line

Claims

[Claim 1] 1. A semiconductor device comprising: a photoelectric conversion element portion embedded in a silicon semiconductor; a transfer transistor electrically connected to the photoelectric conversion element portion; a signal charge accumulation portion electrically connected to the transfer transistor; and an amplifying transistor electrically connected to the signal charge accumulation portion, wherein a channel formation region of the transfer transistor is formed from an oxide semiconductor; and the channel formation region of the amplifying transistor has a pixel portion formed from the silicon semiconductor.

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