Communication device

Abstract

To provide a communication device in which control can be continued as long as possible even if an abnormality occurs.SOLUTION: An ECU 15 includes a plurality of microcomputers 21, 23, and driver components 701 to 704. The microcomputers 21, 23 have at least one computation core. The driver components 701 to 704 are provided corresponding to the microcomputers 21, 23, and are connected with the microcomputers 21, 23 so as to be able to perform digital communication. When a combination of the microcomputers 21, 23 and the driver components 701 to 704 correspondingly provided is defined as a control system, and a communication line connecting the microcomputers 21, 23 and the driver components 701 to 704 corresponding to each other is defined as an intra-system communication line, system-to-system communication lines of different control systems, an intra-system communication line and a driver component of another control system, or the driver components 701, 703 of different control systems are connected via a system-to-system communication line 25.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a communication device.

Background Art

[0002] Conventionally, a motor control device for controlling a motor having two sets of motor windings is known. For example, in Patent Document 1, it has a two-system configuration in which an inverter circuit and a control unit are provided corresponding to the motor windings.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Document 1, when a further failure occurs during control continuation at the time of one failure, there is a possibility that the driving of the motor cannot be continued.

[0005] The present invention has been made in view of the above problems, and an object thereof is to provide a communication device capable of continuing control as much as possible even when an abnormality occurs.

Means for Solving the Problems

[0006] The communication device of the present invention includes a plurality of control units (21 to 24) and a plurality of electronic components (31, 33, 36, 38, 66 to 69, 701 to 707, 73, 801 to 804, 811, 812). The control unit has at least one arithmetic circuit (211, 212, 231, 233). The electronic components are provided corresponding to the control units and are digitally communicably connected to the control units. When the combination of the control unit and the electronic component provided corresponding to each other is defined as a control system and the communication line connecting the corresponding control unit and the electronic component is defined as an in-system communication line, between different in-system communication lines of the control system, between an in-system communication line and an electronic component of another control system, or between different electronic components of the control system, they are connected by inter-system connection lines (25, 251 to 253, 256 to 258). Thereby, the possibility of continuing control in case of failure can be enhanced with a relatively simple configuration.

Brief Description of the Drawings

[0007]

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Mode for Carrying Out the Invention

[0008] Hereinafter, a communication device according to the present invention will be described with reference to the drawings. Hereinafter, in a plurality of embodiments, substantially the same configurations will be denoted by the same reference numerals and the description thereof will be omitted.

[0009] (First Embodiment) The first embodiment is shown in FIGS. 1 to 27. As shown in FIG. 1, the drive device 10 includes a motor 11 and an ECU 15 as a communication device, and is applied to an electric power steering device 5 which is a steering device for assisting a steering operation of a vehicle, for example. FIG. 1 shows the overall configuration of a steering system 90 including the electric power steering device 5. The steering system 90 includes a steering wheel 91 as a steering member, a steering shaft 92, a pinion gear 96, a rack shaft 97, wheels 98, and the electric power steering device 5 and the like.

[0010] The steering wheel 91 is connected to the steering shaft 92. A torque sensor 93 for detecting a steering torque is provided on the steering shaft 92. A pinion gear 96 is provided at the tip of the steering shaft 92. The pinion gear 96 meshes with the rack shaft 97. A pair of wheels 98 are connected to both ends of the rack shaft 97 via tie rods or the like.

[0011] When the driver rotates the steering wheel 91, the steering shaft 92 connected to the steering wheel 91 rotates. The rotational motion of the steering shaft 92 is converted into a linear motion of the rack shaft 97 by the pinion gear 96. The pair of wheels 98 are steered at an angle corresponding to the displacement amount of the rack shaft 97.

[0012] The electric power steering device 5 includes a drive device 10 and a reduction gear 6 or the like as a power transmission unit that decelerates the rotation of the motor 11 and transmits it to the rack shaft 97. The electric power steering device 5 of the present embodiment is a so-called "rack assist type", but it may be a so-called "column assist type" or the like that transmits the rotation of the motor 11 to the steering shaft 92.

[0013] The drive device 10 has an ECU 15 integrally provided on one side in the axial direction of the motor 11 and is a so-called "mechatronic type". The ECU 15 has a connector 16 and is connected to the vehicle power supply 7, the vehicle communication network 8, and the torque sensor 93 via the connector 16. The vehicle power supply 7 includes power supplies 501 and 502 described later. The vehicle communication network 8 is, for example, a CAN (Controller Area Network) and is described as "CAN" in the figure.

[0014] The ECU 15 is arranged coaxially with the motor 11 on the side opposite to the output shaft of the motor 11. Here, "coaxial" means that, for example, errors and misalignments related to assembly and design are allowed. Hereinafter, the axial direction of the motor 11 is regarded as the axial direction of the drive device 10 and is simply referred to as the "axial direction". The same applies to the "radial direction" and the "circumferential direction".

[0015] As shown in FIG. 2, the motor 11 is, for example, a three-phase brushless motor and has four motor windings 121 to 124. The motor 11 outputs part or all of the torque required for steering, is driven by the electric power supplied from the power supplies 501 and 502, and rotates the reduction gear 6 forward and backward.

[0016] The ECU 15 includes a microcomputer 21, 23, power supply ICs 31, 33, communication units 36, 38, oscillators 41, 43, driver circuits 51 to 54, pre-driver ICs 61 to 64, and position sensors 66 to 69, etc. Note that the descriptions with subscripts such as "1", "2", "1A", "2A", "1B", "2B", etc. indicate that they are provided correspondingly, and for the components that can be identified by subscripts, the symbols are appropriately omitted. Each component constituting the ECU 15 is mounted on a substrate 75 provided substantially parallel to one end face in the axial direction of the motor 11 (see FIG. 1). In FIG. 1, one substrate 75 is shown, but it may be a plurality of substrates.

[0017] The microcomputer 21 has arithmetic cores 211, 212 with lockstep. The microcomputer 23 has arithmetic cores 231, 232 with lockstep. The microcomputers 21, 23 are provided so as to be able to transmit and receive information to and from each other by inter-microcomputer communication via an inter-microcomputer isolator 289 (see FIG. 57). In the present embodiment, the microcomputers 21, 23 are similarly configured, but their performance and configuration details may be different. The details of the microcomputers 21, 23 will be described later.

[0018] The microcomputer 21 is supplied with power from the power supply IC 31, and the microcomputer 23 is supplied with power from the power supply IC 33. The power supply ICs 31, 33 are power management ICs (PMIC). In the present embodiment, the components above the dashed-dotted line in FIG. 2 are supplied with power from the power supply 501, and the components below the dashed-dotted line are supplied with power from the power supply 502. That is, the drive device 10 of the present embodiment is a "two-power-supply system" supplied with power from two power supplies 501, 502.

[0019] The communication units 36, 38 are used for transmitting and receiving various information. The communication units 36, 38 are connected to the vehicle communication network 8 and acquire vehicle signals from the vehicle communication network 8. The oscillators 41, 43 are clock sources such as crystal oscillators or ceramic oscillators.

[0020] As shown in FIG. 3, the driver circuit 51 has six switching elements 511 to 516 and is provided corresponding to the winding 121. The driver circuit 52 has six switching elements 521 to 526 and is provided corresponding to the winding 122. The driver circuit 53 has six switching elements and is provided corresponding to the winding 123. The driver circuit 54 has six switching elements and is provided corresponding to the winding 124. Motor relays 131 to 134 are provided between the driver circuits 51 to 54 and the windings 121 to 124 (see FIG. 39).

[0021] In the driver circuit 51, the switching elements 511 to 513 are provided on the high potential side, the switching elements 514 to 516 are provided on the low potential side, and they are bridge-connected. The switching elements 511 and 514 are connected to the U phase of the winding 121, the switching elements 512 and 515 are connected to the V phase of the winding 121, and the switching elements 513 and 516 are connected to the W phase of the winding 121.

[0022] Also, in the driver circuit 52, the switching elements 521 to 523 are provided on the high potential side, the switching elements 524 to 526 are provided on the low potential side, and they are bridge-connected. The switching elements 521 and 524 are connected to the U phase of the winding 122, the switching elements 522 and 525 are connected to the V phase of the winding 122, and the switching elements 523 and 526 are connected to the W phase of the winding 122. Hereinafter, the switching element on the high potential side is appropriately referred to as the upper arm element, and the switching element on the low potential side is referred to as the lower arm element. The switching element in this embodiment is a MOSFET, but it may be an IGBT, a bipolar transistor, or the like.

[0023] The driver circuits 51 and 52 are connected to the power supply 501. Between the power supply 501 and the driver circuit 51, a power relay 551, a reverse connection protection relay 556, a choke coil 562, and a capacitor 566 are provided. The choke coil 561 and the capacitor 566 constitute a filter circuit. Between the power supply 501 and the driver circuit 52, a power relay 552, a reverse connection protection relay 557, a choke coil 562, and a capacitor 567 are provided. The choke coil 562 and the capacitor 567 constitute a filter circuit. The driver circuits 53 and 54 are connected to the power supply 502. The circuit configurations of the driver circuits 53 and 54 and the power relays, reverse connection protection relays, and filter circuits provided between the power supply 502 and the driver circuits 53 and 54 are the same as those of the driver circuits 51 and 52, the power relays 551 and 552, etc., and thus the description thereof is omitted.

[0024] Returning to FIG. 2, the pre-driver ICs 61 to 64 are provided corresponding to the driver circuits 51 to 54. The pre-driver ICs 61 and 62 are provided so as to be digitally communicable with the microcomputer 21, and the pre-driver ICs 63 and 64 are provided so as to be digitally communicable with the microcomputer 23. The microcomputers 21 and 23 transmit the three-phase drive commands of the motor 11 as a set of digital signals to each of the pre-driver ICs 61 to 64.

[0025] Specifically, the pre-driver IC 61 is communicably connected to the arithmetic core 211, the pre-driver IC 62 is communicably connected to the arithmetic core 212, the pre-driver IC 63 is communicably connected to the arithmetic core 231, and the pre-driver IC 64 is communicably connected to the arithmetic core 232. Further, the communication lines connecting the pre-driver ICs 61 to 64 and the arithmetic cores 211, 212, 231, and 232 are connected by the inter-system connection line 25.

[0026] By digitizing the communication between the microcomputer and the pre-driver and providing the inter-system connection line 25, even if an abnormality occurs in one arithmetic core, for example, it is possible to continue issuing commands from other normal arithmetic cores to all the pre-driver ICs 61 to 64. Note that the inter-system connection line 25 means that the four connection lines connecting the core and the pre-driver IC are connected so as to be at the same potential. Therefore, even if a disconnection occurs at the location indicated by the arrow mid in FIG. 2, for example, it is possible to exchange signals between the arithmetic cores 1A, 1B and the pre-drivers 2A, 2B.

[0027] An isolator 28 (not shown in FIG. 2) is provided in the inter-system connection line 25. The isolator 28 may be provided at any location on the inter-system connection line 25. Also, the same effect can be obtained by imparting an isolator function to necessary components.

[0028] The position sensors 66 to 69 detect the rotation of the motor 11. The position sensors 66 to 69 are respectively connected to the arithmetic cores 211, 212, 231, 232. The communication lines connecting the position sensors 66 to 69 and the microcomputers 21, 23 are connected by the inter-system connection line 256. The communication lines connecting the power supply ICs 31, 33 and the microcomputers 21, 23 are connected by the inter-system connection line 257, and the communication lines connecting the communication units 36, 38 and the microcomputers 21, 23 are connected by the inter-system connection line 258. Note that the inter-system connection lines 256 to 258 may be omitted.

[0029] The pre-driver IC will be described with reference to FIG. 4. Here, the pre-driver IC 61 will be described as an example. As shown in FIG. 4, the pre-driver IC 61 includes a three-phase pre-driver circuit 611 that transmits a gate signal to the switching elements constituting the driver circuit 51. The pre-driver IC 61 also includes a current detection circuit 612, a temperature detection circuit 613, an abnormality detection unit 614, a relay driver circuit 621, and the like.

[0030] The pre-driver circuit 611 outputs a gate signal as a drive signal to the switching elements 511 to 516 based on a drive command from the microcomputer 21. The current detection circuit 612 detects the motor current based on the detection values of the current detection elements 517 to 519. The current detection elements 517 to 519 in the present embodiment are current sense MOSs, which are built in a low-side chip 713 described later. The current sense MOS may be built in a high-side chip 712, or may be a chip separate from the upper and lower arm elements.

[0031] Also, as shown in FIG. 5, the current detection element 531 may be a shunt resistor provided in each phase arm. In the example of FIG. 5, a shunt resistor is provided on the low potential side of the lower arm element, but it may be provided on the high potential side of the upper arm element. Furthermore, as shown in FIG. 6, the current detection element 532 may be a Hall element provided between the connection point of the upper and lower arm elements and the motor winding. In FIGS. 5 and 6, the current detection elements 531 and 532 are described as being provided in the driver component 701 described later, but they may be provided outside the driver component 701. Note that the description of the motor relay 131 is omitted in FIG. 6.

[0032] Returning to FIG. 4, the temperature detection circuit 613 detects the temperature of the driver circuit 50 and the pre-driver IC 60 itself based on the detection value of a temperature detection element (not shown). The abnormality detection unit 614 monitors the abnormality of the driver circuit 50 based on the potential difference between the gate and source of the elements constituting the driver circuit 50, the potential difference between the drain and source, and the drive command from the microcomputer 21. For example, the abnormality detection unit 614 monitors abnormalities such as short circuits and terminal open circuits based on the potential difference. Also, the abnormality detection unit 614 monitors overheat abnormalities based on temperature information and abnormalities of the pre-driver IC 61 itself.

[0033] The relay driver circuit 621 outputs a gate signal as a drive signal to the power relay 551, the reverse connection protection relay 556, and the motor relay 131 based on a drive command from the microcomputer 21.

[0034] The pre-driver IC 61 transmits the current detection value, temperature information, and abnormality information to the microcomputer 21. The information transmission from the pre-driver IC 61 to the microcomputer 21 may be digital communication or analog communication.

[0035] In this embodiment, the provided driver circuits 51 to 54 and the pre-driver ICs 61 to 64 are provided in the same package as one driver component 701 to 704. In FIGS. 7 and 8, the driver component 701 having the driver circuit 51 and the pre-driver IC 61 is illustrated. In FIG. 7, the sealing portion 749 is omitted for the purpose of explaining the inside of the component, and in FIG. 8, the hatching of the sealing portion 749 is omitted.

[0036] As shown in FIGS. 7 and 8, the driver component 701 includes a control chip 711, a high-side chip 712, a low-side chip 713, an intermediate clip 715, a ground clip 716, a lead frame 72, etc., and is sealed with a sealing portion 749. The sealing portion 749 is formed in a substantially rectangular shape in plan view, and terminals are formed along the outer edge. Regardless of the terminal arrangement and shape, it may be a non-lead type or may be formed to protrude outside the sealing portion 749. Further, a temperature detection element such as a temperature-sensitive diode is provided in the driver component 701. The temperature detection element may be incorporated in the high-side chip 712 or the low-side chip 713, similar to the current detection elements 517 to 519.

[0037] The lead frame 72 includes a control land 721, a power land 722, an output land 723, and a ground land 724. The back side of the lead frame 72 is exposed from the sealing portion 749 and is electrically connected to the wiring pattern of the substrate 75 by soldering or the like. Note that not all lands need to be connected to the back side of the substrate 75. Hereinafter, the region on the control land 721 side is defined as the IC region Ric, and the region on the power land 722 side is defined as the drive element region Rd. Also, in the driver component 701, the end on the power land 722 side (the upper side on the paper surface of FIG. 7) is defined as the element side end, and the end on the control land 721 side (the lower side on the paper surface of FIG. 7) is defined as the IC side end.

[0038] The control chip 711 constitutes the pre-driver IC 61 and is arranged on the control land 721. In this embodiment, the control land 721 on which the control chip 711 is mounted is at the ground potential. However, when using a case where the back side of the control chip 711 is insulated, the potential of the control land 721 may be a potential other than the ground potential, such as the power supply potential.

[0039] The control terminal, which is a terminal provided in the control region Rc, is connected to the microcomputer 21, the power supply IC 31, and other pre-driver ICs 62 to 64, etc. The control terminal includes a clock signal terminal, a PWM frequency synchronization terminal, a sample hold terminal, etc. Also, when the communication between the microcomputer 21 and the pre-driver IC 61 is, for example, SPI communication, it includes a chip select terminal, a MISO terminal, a MOSI terminal, etc.

[0040] Each of the three high-side chips 712 incorporates an upper arm element for each phase, and each of the three low-side chips 713 incorporates a lower arm element for each phase. Also, the low-side chips 713 incorporate current detection elements 517 to 519.

[0041] The three high-side chips 712 are arranged on the power land 722, which is at the power supply potential. The high-side chips 712 are arranged side by side horizontally such that the gate electrodes face the control chip 711 side and are along the long side of the control chip 711. The source electrodes of the high-side chips 712 face upward, and the drain electrodes provided on the back side are connected to the power land 722. On the upper side of the high-side chips 712, an intermediate clip 715, a low-side chip 713, and a ground clip 716 are stacked in this order from the high-side chip 712 side, forming a stack structure.

[0042] The intermediate clip 715 is a conductive metal plate formed of, for example, copper or the like, and is provided for each of the three high-side chips 712. The intermediate clip 715 is connected to the source electrode of the high-side chip 712 on the lower surface side, and is connected to the drain electrode of the low-side chip 713 on the upper surface side. The intermediate clip 715 is arranged so as to be shifted to such an extent that the signal line 718 can be connected on the control chip 711 side of the high-side chip 712. The end portion of the intermediate clip 715 on the side opposite to the control chip 711 is bent downward and connected to the output land 723. The output land 723 is connected to the motor terminal and is connected to each phase of the motor winding 121 via the substrate wiring or the like.

[0043] When the direction in which the high-side chips 712 are adjacent to each other is defined as the width direction (in the figure, "first direction"), the intermediate clip 715 is spaced apart in the width direction to such an extent that insulation can be ensured from the adjacent frames, and is formed wider than the high-side chips 712. The area of the intermediate clip 715 is formed larger than that of the high-side chips 712. By forming the area of the intermediate clip 715 as large as possible, the heat dissipation efficiency is enhanced.

[0044] The ground clip 716 is a conductive plate formed of, for example, copper or the like, and is provided across the three low-side chips 713. The ground clip 716 is arranged so as to be shifted to such an extent that the signal line 718 can be connected on the control chip 711 side of the low-side chip 713. The ground clip 716 is bent downward on one side in the width direction and connected to the ground land 724. In the present embodiment, the ground clip 716 is provided in the sealing portion 749, but the top surface side may be exposed from the sealing portion 749.

[0045] The high-side chip 712 and the low-side chip 713 are connected to the control chip 711 via the signal line 718. In this embodiment, although the high-side chip 712 and the low-side chip 713 are stacked, they are shifted and stacked in a stepped manner to ensure a non-overlapping area that does not overlap with the components provided on the upper side. Therefore, the signal line 718 can be connected in the non-overlapping area. The connection end of the signal line 718 on the control chip 711 side is aggregated on one side of the control chip 711. The signal line 718 includes those for gate driving, current detection, and temperature detection. Thereby, inside the driver component 701, the drive element region Rd where a large current is energized and the IC region Ric can be regionally separated.

[0046] The component layout on the substrate 75 is shown in FIGS. 9 to 11. FIGS. 9 and 11 show the surface of the substrate 75 on the motor 11 side, and FIG. 10 shows the surface of the substrate 75 opposite to the motor 11. Note that FIG. 11 schematically shows the layout of the driver components 701 to 704 and the motor windings 121 to 124 on the substrate 75, and the corresponding pre-driver ICs 61 to 64 and driver circuits 51 to 54 are numbered in parentheses for the control chip 711, the high-side chip 712, and the low-side chip 713. The same applies to FIG. 42 and the like.

[0047] As shown in FIGS. 9 and 11, the driver components 701 to 704 are mounted on the substrate 75. The four driver components 701 to 704 are provided on the surface of the substrate 75 on the motor 11 side. The four driver components 701 to 704 are arranged on concentric circles at approximately equal intervals. Also, the driver components 701, 702 and the driver components 703, 704 are arranged symmetrically with respect to the substrate partition line D1. The substrate partition line D1 is a partition line that divides regions with different supply powers.

[0048] The driver components 701 to 704 are arranged such that the end portions on the element side face radially outward. The motor windings 121 to 124 are connected to the substrate 75 on the radially outer side of the driver components 701 to 704. That is, they are arranged in the order of the control chip 711, the high-side chip 712, the low-side chip 713, and the motor wire connection portion from the radially inner side. The lead wires of the motor windings 121 to 124 are arranged substantially parallel to the end portions on the element side of the driver components 701 to 704 so as to correspond to the phase arrangement of the switching elements in the driver components 701 to 704. Note that the phase arrangement shown in FIG. 11 is an example and may be different. In FIGS. 9 to 11, the winding connection locations to which the lead wires of the motor windings are connected are numbered as the motor windings 121 to 124. The same applies to the power terminals and the signal terminals.

[0049] On the surface of the substrate 75 on the motor 11 side, a rotation detection unit 65 is mounted at a position facing a magnet provided at the end of a shaft (not shown) of the motor 11. In the present embodiment, the rotation detection unit 65 is mounted at the center of the substrate 75. The rotation detection unit 65 includes position sensors 66 to 69.

[0050] The power terminals 761 and 763 are connected to a region on the outer edge side of the substrate 75 that straddles the substrate center line D2 orthogonal to the substrate partition line D1. The power terminals 761 and 763 include a power supply terminal and a ground terminal. Power from the power supply 501 is supplied to the power terminal 761, and power from the power supply 502 is supplied to the power terminal 763. On the substrate center line D2 of the substrate 75, between the rotation detection unit 65 and the power terminals 761 and 763, power supply ICs 31 and 33 are mounted. The power supply ICs 31 and 33 may be arranged at locations other than on the substrate center line D2 as long as they are locations where they can be easily connected to the power terminals 761 and 763 and the microcontrollers 21 and 23. Also, a signal terminal 77 is connected to a region on the outer edge side of the substrate 75 that straddles the substrate partition line D1.

[0051] As shown in FIG. 10, on the surface opposite to the motor 11, on the substrate partition line D1, microcontrollers 21 and 23 are mounted on both sides with the substrate center line D2 interposed therebetween. The microcontroller 21 is supplied with power from the power terminal 761, and the microcontroller 23 is supplied with power from the power terminal 763, and a wiring pattern is formed accordingly. The microcontrollers 21 and 23 are communicably connected, and an isolator 28 is mounted at the connection point of the microcontrollers 21 and 23. In the present embodiment, the isolator 28 is provided at the center of the substrate. Further, on the surface opposite to the motor 11, components such as capacitors and coils constituting the filter circuit are mounted.

[0052] In the present embodiment, the drive device 10 is applied to the electric power steering device 5. Not limited to the electric power steering device 5, for example, when the drive device 10 is applied to a main motor or a brake motor, various components may be made redundant so that safety can be ensured even if a part of the components fails.

[0053] In FIGS. 12 to 15, the communication configuration between the microcontroller and the components is conceptually shown. As shown in FIG. 12, assuming that the combination of the microcontrollers (or arithmetic cores) M1 and M2 and the components P1 and P2 communicably connected by the communication lines C1 and C2 is a control system, if a failure occurs in the microcontroller M1 or the component P1, which is the first control system, the microcontroller M2 and the component P2, which are the second control system, can continue to operate with 50% of the functions remaining. Here, if a failure occurs at any point in the second control system, control cannot be continued. In the present embodiment, the communication lines C1 and C2 correspond to the "intra-system communication lines".

[0054] As shown in FIG. 13, as a further redundancy, for example, when the control system is made into three systems, it is possible to continue operating with 66% of the functions remaining at the first failure, and even if a further failure occurs during the operation with one failure and two control systems, it is possible to continue operating with 33% of the functions remaining in the remaining one control system. However, increasing the number of control systems increases the number of components.

[0055] Here, as shown in FIGS. 14(a) and 14(b), assume that microcontrollers M1 and M2 correspond to microcontrollers 21 and 23, and components P1 and P2 correspond to driver components 701 and 703. The driver components 701 and 703 include pre-driver ICs 61 and 63 that control driver circuits 51 and 53, and output drive signals for driving the driver circuits 51 and 53 according to commands transmitted from the microcontrollers 21 and 23. Also, current detection values, driver outputs, abnormal information, temperature information, etc. are transmitted from the driver components 701 and 703 to the microcontrollers 21 and 23 side.

[0056] As shown in FIG. 14(a), when the driver components 701 and 703 are capable of digital communication, by connecting the first communication line C1 and the second communication line C2 with the inter-system connection line 25, for example, when a failure occurs in the microcontroller 21, the microcontroller 23 commands the driver components 701 and 703. Thereby, control can be continued. Also, if the second failure occurs in either of the driver components 701 and 703, control can be continued with the normal microcontroller and driver component. Thereby, even for two control systems, the possibility of continuing operation during a failure can be increased. Also, as shown in FIG. 14(b), the driver components 701 and 703 may be connected with the inter-system connection line 25.

[0057] The communication between the microcontrollers 21 and 23 and the components 701 and 703 is, for example, SPI communication, but communication methods other than SPI such as PSI5, SENT, CAN, Ethernet, Flexray, etc. may also be used, or wireless communication may be used. Also, in FIGS. 14 etc., one communication line is described, but the number of communication lines and terminals can be arbitrarily set according to the communication method etc.

[0058] As shown in FIG. 14(a), when the communication lines C1 and C2 are connected with the inter-system connection line 25, if the communication line is connected to a power supply or ground and the voltage is fixed, there is a failure mode in which all connected microcontrollers and components cannot operate. Also, when the microcontrollers M1 and M2 are connected to different power supplies, there is a risk of failure due to a high voltage being applied to the normal system or a large current flowing into the normal system due to a failure in one control system.

[0059] Therefore, as shown in FIG. 15, an isolator 28 as a system separation component is provided at a location where simultaneous failures are not desired to occur. Note that the description of the isolator 28 is omitted in FIG. 2 and the like. In the example of FIG. 15, the isolator 28 is provided in the inter-system connection line 25, but it may be provided, for example, inside the microcontrollers M1 and M2 or the components P1 and P2. As a configuration for separating between systems, it is only necessary that information can be transmitted while maintaining the potential difference. For example, an optical insulation method, a magnetic insulation method, or a capacitive insulation method can be used. Further, as the system separation component, instead of the isolator, a passive element such as a resistor or a buffer may be provided. Further, by making the communication wireless communication, co-trip failures may not occur. The same applies to the isolators 281 to 283 in the embodiments described later.

[0060] Specific examples of the communication configuration are shown in FIGS. 16 and 17. In FIGS. 16 and 17, for simplicity, the signal lines of the two cores of each microcontroller are described together, and the inter-system connection lines are omitted. As shown in FIG. 16, the microcontrollers 21 and 23 can transmit a common clock signal SCLK and MOSI signal to the driver components 701 to 704 provided correspondingly, and can transmit a chip select signal CS_A to the driver components 701 and 703 and a chip select signal CS_B to the driver components 702 and 704. From each of the driver components 701 to 704, an MISO signal can be transmitted to the correspondingly provided microcontrollers 21 and 23.

[0061] The microcontrollers 21 and 23 are provided so as to enable communication between the microcontrollers, and perform synchronization of PWM, synchronization of duty update timing, and synchronization of sample hold timing with respect to the four driver components 701 to 704. The microcontrollers 21 and 23 perform PWM update confirmation using the PWM reflection value and the current detection value by the MISO signal. Further, by configuring to return the driver output from the driver components 701 to 704 to the microcontrollers 21 and 23, PWM update confirmation may be performed. When the driver output is not returned to the microcontrollers 21 and 23 side, the terminals and wirings for returning the driver output can be omitted.

[0062] As shown in FIG. 17, the microcomputer 21, the driver components 701, and the driver component 702 may be connected in a so-called "daisy chain connection" in which communication lines are connected in a ring. Similarly, the microcomputer 23, the driver components 703, and the driver component 704 may be connected in a daisy chain connection.

[0063] Specifically, signals from the microcomputers 21 and 23 are transmitted to the driver components 701 and 703, and the signals are transmitted from the driver components 701 and 703 to the driver components 702 and 704. Then, MISO signals are transmitted from the driver components 702 and 704 to the microcomputers 21 and 23. In this case, the chip select signal and the sample hold may be made common. As a result, the number of terminals and the number of wirings can be reduced.

[0064] In this embodiment, since the communication lines of each control system are connected by the inter-system connection line 25, in the microcomputers 21 and 23, so that data does not mix on the communication line, when communication from other microcomputers starts, the microcomputers do not issue commands, or a command is output after a predetermined time has elapsed from the response from the driver components 701 and 703 side. Also, for commands from the microcomputers 21 and 23 side, the command destination may be specified by chip select, ID assignment, or the like.

[0065] FIG. 18 illustrates an example of data transmission and reception. In this embodiment, the microcomputers 21 and 23 output an ID and a command to specify the component to be driven. For example, the component to be driven is specified by the ID, and a current command value or an on-duty is transmitted to the component side via MOSI. In the ID method, the component to be driven is specified by the ID, but it is also possible to set an ID for simultaneously commanding a plurality of components. As a result, for example, the timing of current detection of a plurality of components can be made uniform. The specification of the component to be driven may be by the chip select method.

[0066] The driver components 701 and 703 transmit the current value and status information to the microcontrollers 21 and 23. Since the data transmission from the driver components 701 and 703 is performed via MISO, information can be transmitted even during the command transmission from the microcontrollers 21 and 23. However, in order to prevent the data transmission timings from different driver components from overlapping, for example, when the transmission from the driver component 701 is completed, the transmission from the driver component 703 is set to start. Also, data arbitration may be performed by setting, for example, to transmit in the order of ID.

[0067] Figures 19 and 20 schematically show the arrangement of the motor windings, and the three-phase wiring is described by a single line. In a concentrated winding motor, there are a plurality of windings in the stator, and a three-phase motor having three input terminals is formed by connecting the plurality of windings. Depending on the way of connecting the windings, it is possible to form a set of three-phase windings, or it is also possible to form a plurality of sets of three-phase windings. Figure 19 shows an example in the case of forming two sets of three-phase windings. When connecting the windings facing each other at 180°, the wiring related to the connection of the plurality of windings and the configuration of the bus bar responsible for the wiring tend to become complicated.

[0068] In this embodiment, it has a configuration of two power supplies and four motor windings. As shown in Figure 20, for example, when forming four sets of three-phase windings with a concentrated winding motor using a stator of 14 poles and 18 slots, 10 poles and 12 slots, or 8 poles and 12 slots, the connection between the windings arranged opposite to each other becomes unnecessary, so the wiring can be simplified.

[0069] In this embodiment, the substrate 75 is provided on one side in the axial direction of the motor 11, and the configurations corresponding to the respective power supplies are intensively arranged in the regions partitioned by the substrate partition lines D1 (see FIGS. 1, 9 to 11). Further, four sets of motor windings 121 to 124 are assigned to two power supplies 501 and 502 and two microcontrollers 21 and 23. When driving the motor 11 with the four sets of motor windings 121 to 124, the winding sets facing each other at 180° are often driven in the same phase. If the winding sets driven in the same phase are assigned to the same power supply, there is a risk of an increase in size due to the complexity of the members for bundling the wiring, a deterioration in layout due to the cross arrangement of the wiring on the substrate 75, and a common cause failure due to a wiring short circuit.

[0070] Therefore, windings with different driving phases arranged adjacent to each other in the stator are assigned to one power supply system. Specifically, it is configured such that power is supplied from the power supply 501 to the windings 121 and 122, and power is supplied from the power supply 502 to the windings 123 and 124. In this embodiment, since the inter-system connection line 25 is provided, a command to the windings assigned to other power supplies can also be output with one core. Therefore, even if two windings arranged adjacent to each other in the stator and having different driving phases are assigned to the same power supply and arranged, the drivers driven in the same phase can be operated by commands from the same core.

[0071] Further, since the energization phases of the windings assigned to the same power supply are different, the timing at which the drawing current becomes maximum during motor driving is shifted. As a result, compared with the case where a driver circuit driven in the same phase is assigned to the same power supply, the power consumption in the driver circuit can be smoothed, and for example, the smoothing capacitor can be miniaturized. Also, it is possible to achieve the intensification of the components assigned to the same power supply system on one side of the substrate, the improvement of the layout, and the reduction of the occurrence of common cause failures due to wiring shorts. In FIG. 20, the windings 121 and 123 energized in the same phase are shown in white, and the windings 122 and 124 energized in the same phase with a phase different from that of the windings 121 and 123 are shown in embossed pattern.

[0072] The communication between the arithmetic cores 211, 212, 231, 232 and the pre-driver ICs 61 to 64 will be described based on FIG. 21. In the description of the communication, for simplicity, the arithmetic core 211 is referred to as "core 1A", the arithmetic core 212 is referred to as "core 1B", the arithmetic core 231 is referred to as "core 2A", the arithmetic core 232 is referred to as "core 2B", the pre-driver IC 61 is referred to as "pre-driver 1A", the pre-driver IC 62 is referred to as "pre-driver 1B", the pre-driver IC 63 is referred to as "pre-driver 2A", and the pre-driver IC 64 is referred to as "pre-driver 2B".

[0073] In this embodiment, windings 121 and 123 provided corresponding to pre-drivers 1A and 2A are wound around the stator facing each other and energized in the same phase. Windings 122 and 124 provided corresponding to pre-drivers 1B and 2B are wound around the stator facing each other and energized in the same phase. The energization phases of windings 121 and 123 and the energization phases of windings 122 and 124 are different. It is assumed that the amplitudes of the currents flowing through windings 121 to 124 are equal.

[0074] As shown in FIG. 21, cores 1A and 2A transmit command signals such as duty command values and various drive permission signals to pre-drivers 1A and 2A that are driven in the same phase. The pre-drivers 1A and 2A transmit current detection values and status information (such as driver output, abnormality information, and temperature information) to cores 1A and 2A. Also, cores 1B and 2B transmit command signals such as duty command values and various drive permission signals to pre-drivers 1B and 2B that are driven in the same phase. The pre-drivers 1B and 2B transmit current detection values and status information to cores 1B and 2B.

[0075] In this embodiment, cores 1A and 2A send drive commands to pre-drivers 1A and 2A, and do not send drive commands to pre-drivers 1B and 2B. Here, the pre-drivers 1B and 2B may be configured to also send current detection values and status information to the cores 1A and 2A that have not received drive commands. Similarly, the pre-drivers 1A and 2A may be configured to also send current detection values and status information to the cores 1B and 2B that have not received drive commands. Thereby, in each core, the control state of the entire drive device 10 can be grasped.

[0076] Cores 1A and 2A alternately send commands to pre-drivers 1A and 2A. Similarly, cores 1B and 2B alternately send commands to pre-drivers 1B and 2B. Thereby, the computational load of each core can be reduced.

[0077] As shown in FIG. 22, when one core fails, even if the processing is not changed from the normal state, although the update period is extended, the control can be continued without causing a fatal impact. Specifically, for example, when core 2A fails, in group A, the information at the update timing by the command of core 2A is not updated, and the update period is extended. In this case, the previous command value is held at the update timing of core 2A. By using the estimated value from past data at the update timing of core 2A, the influence of the failure can be reduced.

[0078] At the command update timing of the failed core 2A, commands may be sent from the normal core 1A instead of core 2A. Thereby, a performance degradation including the update period can be prevented. Also, the pre-drivers 1B and 2B that do not use the commands of core 2A can continue control without being affected by the failure of core 2A.

[0079] As shown in FIG. 23, the inter-system connection line 25 may be divided between the A group and the B group that are driven in the same phase. In FIG. 23, the inter-system connection line of the A group is designated as "25A", and the inter-system connection line of the B group is designated as "25B". By dividing the communication lines for each phase, the amount of information on the communication lines can be suppressed. In addition, since a common failure mode on the communication lines can be avoided, control can be continued even when an abnormality occurs in one of the communication lines.

[0080] Next, the driving of the power relay and the reverse connection protection relay will be described. As shown in FIG. 24, in the present embodiment, the power relays 551 to 554 and the reverse connection protection relays 556 to 559 are provided for each of the driver circuits 51 to 54, and are driven by receiving individual commands from the relay driver circuits 621 to 624 of the corresponding driver circuits 51 to 54 during normal operation. In FIG. 24, the reverse connection protection relay and the reverse connection protection relay are collectively referred to as "power / reverse connection relay", and the description of the arithmetic core in the microcomputer is omitted. Also, in FIG. 24, although it is described as if the inter-system connection line is divided between the A group and the B group as in FIG. 23, the inter-system connection lines may be grouped together as in FIG. 2.

[0081] When an abnormality occurs in the pre-driver IC 61, the power relay 551, or the reverse connection protection relay 556, the pre-driver IC 61 side is configured to be in a pull-down (off side) state, and driving by the other pre-driver ICs 62 to 64 is not performed. The same applies when an abnormality occurs in other pre-driver ICs, power relays, reverse connection protection relays, or motor relays (not shown in FIG. 24).

[0082] Also, when an abnormality occurs in the microcomputer 21, the microcomputer 23 commands the relay driver circuits 621 and 622 in the pre-driver ICs 61 and 62 to drive the power relays 551 and 552 and the reverse connection protection relays 556 and 557. Similarly, when an abnormality occurs in the microcomputer 23, the microcomputer 21 commands the relay driver circuits 623 and 624 in the pre-driver ICs 63 and 64 to drive the power relays 553 and 554 and the reverse connection protection relays 558 and 559. Thereby, even when an abnormality occurs in one of the microcomputers, the driving of the motor 11 can be continued by driving the relays according to the command from the other microcomputer.

[0083] Next, the redundant configuration in the microcomputer will be described with reference to FIG. 25. Here, the microcomputer 21 will be described as an example. The microcomputer 21 includes arithmetic cores 211 and 212, a power control unit 213, a clock control unit 217, and the like.

[0084] The power control unit 213 includes a power supply monitoring unit 214. The power control unit 213 is connected to a plurality of power supply circuits PM1 to PM3. The power supply circuits PM1 and PM2 correspond to the power supply IC 31, and the power supply circuit PM3 corresponds to the power supply IC 33. The power supply IC 31 has, for example, a core power supply voltage output (e.g., about 1.2 [V]) and a power supply output different from the core power supply voltage (e.g., 5 [V]). The core power supply corresponds to the power supply circuit PM1, and the 5V power supply corresponds to the power supply circuit PM2. Although the power supply circuits PM1 and PM2 correspond to the same power supply IC 31, different voltages are generated inside the power supply IC 31, and they can be regarded as "different power sources". That is, it can be said that the power control unit 213 of the present embodiment has a redundant configuration in which power is supplied from three different power sources.

[0085] The power supply circuit PM1 is input to the power control unit 213 at the original voltage and is used by the arithmetic cores 211 and 212. The power from the power supply circuit PM2 is stepped down by the built-in step-down circuit 215, input to the power control unit 213, and used for core arithmetic operations. The power from the power supply circuit PM3 is stepped down by the step-down circuit 216 outside the microcomputer and input to the power control unit 213. Note that the power supply circuit PM2 may be supplied with power from a separate power source such as a power supply IC33 etc. different from the power supply IC31, or may be configured to step down the voltage with a step-down circuit outside the microcomputer. The power supply monitoring unit 214 monitors the voltages supplied from each power supply circuit.

[0086] The clock control unit 217 has a clock monitoring unit 218. The clock control unit 217 acquires a clock signal from the oscillator 41 via the phase-locked loop (PLL) 411. Also, the clock control unit 217 acquires clock signals from the built-in clock circuit 415 and the external clock circuit. In this embodiment, the external clock circuit is another system microcomputer 23, and a clock signal is acquired from the microcomputer 23. Note that the external clock circuit is not limited to another system microcomputer and may be a separately provided clock circuit.

[0087] That is, it can be said that the clock control unit 217 of this embodiment has a redundant configuration in which clocks are supplied from three different clock sources. Hereinafter, the clock signal acquired from the oscillator 41 via the phase-locked loop 411 is referred to as "PLL clock", the clock signal acquired from the built-in clock circuit 219 is referred to as "built-in clock", and the clock signal acquired from the external clock circuit is referred to as "external clock".

[0088] The clock monitoring process of this embodiment will be described based on the flowchart of FIG. 26. Here, the process in the microcomputer 21 will be described, but the same process is also performed in the microcomputer 23. Each process in the microcomputers 21 and 23 may be software processing by executing a program stored in advance in a physical memory device such as a ROM (i.e., a readable non-transitory tangible recording medium) by the CPU, or may be hardware processing by a dedicated electronic circuit. Hereinafter, the "step" such as step S101 will be omitted and simply denoted by the symbol "S".

[0089] In S101, the clock monitoring unit 218 determines whether the PLL clock and the built-in clock match. Note that a deviation within an allowable error range is permitted and it is determined that they match. The same applies to other match determinations. If it is determined that the PLL clock and the built-in clock match (S101: YES), the process proceeds to S104. If it is determined that the PLL clock and the built-in clock do not match (S101: NO), the process proceeds to S102.

[0090] In S102, the clock monitoring unit 218 determines whether the built-in clock and the external clock match. If it is determined that the built-in clock and the external clock match (S102: YES), the process proceeds to S105. If it is determined that the built-in clock and the external clock do not match (S102: NO), the process proceeds to S103.

[0091] In S103, the clock monitoring unit 218 determines whether the PLL clock and the external clock match. If it is determined that the PLL clock and the external clock match (S103: YES), the process proceeds to S104. If it is determined that the PLL clock and the external clock do not match (S103: NO), the process proceeds to S106.

[0092] In S104, which is the step to proceed when the PLL clock matches the built-in clock or the external clock, the clock control unit 217 operates the arithmetic cores 211 and 212 using the PLL clock.

[0093] In S105 which is executed when the PLL clock and the built-in clock do not match and the built-in clock and the external clock match, the clock control unit 217 operates the arithmetic cores 211 and 212 using the built-in clock. That is, the PLL clock is used during normal operation, but when the PLL clock is abnormal, it is switched to the built-in clock as a backup clock. At this time, the switched clock is output to the microcomputer of another control system, and the arithmetic operation is performed synchronously with the clock received by the other system microcomputer. Also, the abnormality monitoring by comparing the built-in clock and the external clock is continued.

[0094] In S106 which is executed when none of the PLL clock, the built-in clock, and the external clock match, the clock control unit 217 stops the operations of the arithmetic cores 211 and 212 and notifies the external IC of the clock abnormality.

[0095] The power supply monitoring process will be described based on the flowchart of FIG. 27. In S201, the power supply monitoring unit 214 determines whether the core power supply voltage supplied from the power supply circuit PM1 is normal. If it is determined that the core power supply voltage from the power supply circuit PM1 is normal (S201: YES), the process proceeds to S202, and the arithmetic cores 211 and 212 are operated with the core power supply voltage from the power supply circuit PM1. If it is determined that the core power supply from the power supply circuit PM1 is not normal (S201: NO), the process proceeds to S203, and the power supply used for the core operation is switched from the power supply circuit PM1 to the power supply circuit PM2 or the power supply circuit PM3. Here, the case of switching to the power supply circuit PM2 as a backup power source will be described as an example. For the case of switching to the power supply circuit PM3, since the power supply circuit PM2 can be replaced with the power supply circuit PM3, the description will be omitted.

[0096] In S204, the power supply monitoring unit 214 determines whether the core power supply voltage supplied from the power supply circuit PM2 via the step-down circuit is normal. When it is determined that the core power supply voltage derived from the power supply circuit PM2 is normal (S204: YES), the process proceeds to S205, and the arithmetic cores 211 and 212 are operated with the core power supply voltage derived from the power supply circuit PM2. When it is determined that the core power supply voltage derived from the power supply circuit PM2 is not abnormal (S204: NO), the process proceeds to S206, the operations of the arithmetic cores 211 and 212 are stopped, and the core power supply voltage abnormality is notified to the external IC. Thus, even when a core power supply abnormality occurs in the power supply circuit PM1, the operations of the arithmetic cores 211 and 212 can be continued by using the power supply circuits PM2 and PM3 as backup core power supplies.

[0097] As described above, the ECU15 includes a plurality of microcontrollers 21 and 23, and driver components 701 to 704. The microcontrollers 21 and 23 each have at least one arithmetic core. In this embodiment, the microcontroller 21 has arithmetic cores 211 and 212, and the microcontroller 23 has arithmetic cores 231 and 232.

[0098] The driver components 701 to 704 are provided corresponding to the microcontrollers 21 and 23, and are digitally communicably connected to the microcontrollers 21 and 23. Specifically, the driver components 701 to 704 are provided corresponding to the arithmetic cores 211, 212, 231, and 232, and are digitally communicably provided.

[0099] The combinations of the corresponding microcontrollers 21 and 23 and the driver components 701 to 704 are defined as control systems, and the communication lines connecting the corresponding microcontrollers 21 and 23 and the driver components 701 to 704 are defined as in-system communication lines C1 and C2. Different in-system communication lines between control systems, or between different driver components 701 and 703 of the control systems, are connected by an inter-system connection line 25. Thereby, the possibility of continuing control in case of a failure can be enhanced with a relatively simple configuration. Note that the same effect can be obtained by connecting the inter-system connection lines between the driver components.

[0100] The driver components 701 to 704 have pre-driver ICs 61 to 64 that transmit drive signals to the switching elements that constitute the driver circuits 51 to 54 related to the drive of the motor 11. The arithmetic cores 211, 212, 231, and 232 digitally transmit drive commands for the switching elements to the pre-driver ICs 61 to 64. The drive command is, for example, a duty command value. The pre-driver ICs 61 to 64 transmit drive information including at least one of a current detection value, temperature information, and abnormality information to the microcontrollers 21 and 23. Thereby, the drive of the motor 11 can be appropriately controlled.

[0101] The arithmetic cores 211, 212, 231, and 232 calculate drive commands for some of the driver circuits and obtain drive information from the pre-driver ICs corresponding to the driver circuits for which they do not calculate drive commands themselves. For example, the arithmetic core 211 calculates drive commands for the driver circuits 51 and 53, and also obtains drive information from the pre-driver ICs 62 and 64 corresponding to the driver circuits 52 and 54 for which it does not calculate drive commands itself. Thereby, each of the arithmetic cores 211, 212, 231, and 232 can appropriately grasp the current drive state.

[0102] The arithmetic cores 211, 212, 231, and 232 transmit drive commands at a timing when the arithmetic cores of other control systems connected by the inter-system connection line 25 are not outputting drive commands. Thereby, it is possible to prevent data from being mixed on the communication line.

[0103] The plurality of driver components 701 to 704 hold detection values at the same timing according to commands from the microcontrollers 21 and 23, and sequentially transmit the detection values to the microcontrollers 21 and 23. Thereby, it is possible to appropriately perform control calculations using the detection values obtained at the same timing.

[0104] The plurality of arithmetic cores 211 and 231 send drive commands to the pre-driver ICs 61 and 63 in turn for each arithmetic cycle. Also, the plurality of arithmetic cores 212 and 232 send drive commands to the pre-driver ICs 62 and 64 in turn for each arithmetic cycle. Thereby, the arithmetic load on the arithmetic cores 211, 212, 231, and 232 can be reduced. Also, even when an abnormality occurs in some of the arithmetic cores, the control arithmetic can be continued. Further, for example, it is possible to promptly shift to a command at a normal arithmetic core.

[0105] When an abnormality occurs in some of the plurality of arithmetic cores 211 and 231 that send drive signals to the same pre-driver ICs 61 and 63, a normal arithmetic core substitutes for the transmission of the drive command. Also, when an abnormality occurs in some of the plurality of arithmetic cores 212 and 232 that send drive signals to the same pre-driver ICs 62 and 64, a normal arithmetic core substitutes for the transmission of the drive command. Thereby, even when an abnormality occurs in some of the arithmetic cores, it is possible to prevent a performance degradation from the normal state, including the command update cycle.

[0106] The load of the present embodiment is a motor 11 having four sets of motor windings 121 to 124, which are wound around the stator so as to be adjacent in the order of the motor winding 121, the motor winding 122, the motor winding 123, and the motor winding 124. In other words, the motor winding 121 and the motor winding 123 are arranged to face each other, and the motor winding 122 and the motor winding 124 are arranged to face each other (see FIG. 20). Here, "arranged to be adjacent" means that it may be arranged so as to be an adjacent region when viewed as a whole, and for example, some slots may be shared.

[0107] The first driver circuit 51 provided corresponding to the motor winding 121 and the third driver circuit 53 provided corresponding to the motor winding 123 are driven by drive commands of the same phase. The second driver circuit 52 provided corresponding to the motor winding 122 and the fourth driver circuit 54 provided corresponding to the motor winding 124 are of the same phase and are driven by drive commands of a phase different from that of the pre-driver ICs 61 and 63.

[0108] In the present embodiment, since the inter-system connection line 25 is provided, it is possible to relatively easily transmit commands of the same phase from the same arithmetic core to the opposing winding sets. Therefore, even if winding sets with different energization phases are assigned to the same microcomputer or power supply system, the board design and motor design become easier. Further, by assigning winding sets energized in different phases to the same power supply system, the maximum value of the drawn current can be reduced.

[0109] The in-system communication line connecting the first pre-driver IC 61 provided corresponding to the first driver circuit 51 and the first arithmetic core 211 and the in-system communication line connecting the third pre-driver IC 63 provided corresponding to the third driver circuit 53 and the third arithmetic core 231 are connected by the first inter-system connection line 25A. The in-system communication line connecting the second pre-driver IC 62 provided corresponding to the second driver circuit 52 and the second arithmetic core 212 and the in-system communication line connecting the fourth pre-driver IC 64 provided corresponding to the fourth driver circuit 54 and the fourth arithmetic core 232 are connected by a second inter-system connection line 25B different from the first inter-system connection line 25A. By separating the inter-system connection lines for each phase, the amount of information of each communication line can be suppressed. Further, a common failure mode in the communication line can be avoided.

[0110] The microcomputers 21 and 23 have a plurality of arithmetic cores 211, 212, 231, and 232, and in-system communication lines connecting to driver components are assigned to each of the arithmetic cores 211, 212, 231, and 232. Thereby, even when some of the arithmetic cores 211, 212, 231, and 232 fail, control can be continued.

[0111] The system connection line 25 connects the control systems via an isolator 28 that enables information transmission while maintaining the potential difference. This allows the communication line to be properly connected even when there is a potential difference between the connected control systems. Also, even if an abnormality occurs in one of the control systems, simultaneous failures due to the application of high voltage or the inflow of current can be prevented.

[0112] (Second Embodiment, Third Embodiment) The second embodiment is shown in FIG. 28. FIG. 28 is a diagram corresponding to FIG. 24 of the first embodiment, and the power relays and reverse connection protection relays are different from those in the above embodiment. In this embodiment, the power relays 551, 553 and the reverse connection protection relays 556, 558 are provided for each power supply. The power relay 551 and the reverse connection protection relay 556 are shared by the driver circuits 51, 52, and the power relay 553 and the reverse connection protection relay 558 are shared by the driver circuits 53, 54.

[0113] The relay driver circuits 621, 622 drive the power relay 551 and the reverse connection protection relay 556 via the arbitration circuit 571. The relay driver circuits 623, 624 drive the power relay 553 and the reverse connection protection relay 558 via the arbitration circuit 573. By providing the arbitration circuits 571, 573, the number of relays can be reduced.

[0114] During normal operation, the arbitration circuit 571 receives the same commands from the relay driver circuits 621, 622, and drives the power relay 551 and the reverse connection protection relay 556 after taking consistency. When one of the relay driver circuits 621, 622 is abnormal, the arbitration circuit 571 drives the power relay 551 and the reverse connection protection relay 556, giving priority to the signal from the normally operating side because the signals received from the relay driver circuits 621, 622 are different.

[0115] During normal operation, the arbitration circuit 573 receives the same commands from the relay driver circuits 623 and 624, coordinates, and drives the power relay 553 and the reverse connection protection relay 558. When one of the relay driver circuits 623 and 624 is abnormal, the arbitration circuit 573 receives different signals from the relay driver circuits 623 and 624, and thus preferentially drives the power relay 553 and the reverse connection protection relay 558 with the signal from the normally operating side.

[0116] The third embodiment is shown in Fig. 29. In this embodiment, power relays 551 to 554 and reverse connection protection relays 556 to 559 are provided for each of the driver circuits 51 to 54. In addition, arbitration circuits 571 to 574 are provided.

[0117] The arbitration circuit 571 receives commands from the relay driver circuits 621 and 622 and drives the power relay 551 and the reverse connection protection relay 556. The arbitration circuit 572 receives commands from the relay driver circuits 621 and 622 and drives the power relay 552 and the reverse connection protection relay 557. The arbitration circuit 573 receives commands from the relay driver circuits 623 and 624 and drives the power relay 553 and the reverse connection protection relay 558. The arbitration circuit 574 receives commands from the relay driver circuits 623 and 624 and drives the power relay 554 and the reverse connection protection relay 559. The operations of the arbitration circuits 571 to 574 are generally the same as those in the second embodiment. Thereby, the operation of the motor 11 can be continued even in a wider range of failure modes. Also, the same effects as those in the above embodiment are achieved.

[0118] (Fourth to Eighth Embodiments) Embodiments 4 to 8 are variations of the redundant configuration. In the description of the redundant system, the power supply, vehicle signal input, and torque signal input are collectively referred to as the "external input system" as appropriate, the power supply IC, communication unit, and oscillator are collectively referred to as the "microcontroller input system", and the pre-driver IC and driver circuit are collectively referred to as the "driver system". The external input system corresponds to the input from connector 16. Also, the oscillator and inter-system connection lines are omitted as appropriate. FIG. 30 shows a simplified configuration of the first embodiment. When not referring to the number of cores in the microcontroller, the microcontroller is assumed to have one arithmetic core with lockstep.

[0119] As shown in FIG. 31, in the fourth embodiment, four microcontrollers each having one arithmetic core with lockstep are provided. Other configurations are generally the same as those of the first embodiment. As shown in FIG. 32, in the fifth embodiment, four external input systems are provided, and all of the power supply, microcontroller, driver, and motor windings are quadrupled. By quadrupling the power supply, microcontroller, and driver, it is easy to combine with a four-phase motor. Also, when adopting a two-power supply configuration, it is easy to divide it into two power supply lines.

[0120] By providing three or more of all components, control can be continued even if two of the same components fail. Also, as described in the first embodiment, by connecting the signal lines with inter-system connection lines, the same output as in the normal state can be obtained as long as it is not a failure on the driving side. When providing inter-system connection lines, it is preferable to insert isolators as appropriate to avoid common cause failures.

[0121] Also, it is not limited to even numbers such as two or four systems, and it may be an odd number of systems, or a mixture of components with an odd number and an even number of components. The sixth embodiment shown in FIG. 33 is an example of a three-system configuration in which three each of the external input system, microcontroller input system, driver system, and motor windings are provided. As shown in FIG. 34, when the driver system is three systems, by making the motor windings also three systems, wiring can be performed efficiently.

[0122] On the other hand, when redundancy is achieved by providing a plurality of components, there are concerns about an increase in the number of components, an increase in size, and an increase in the arithmetic processing load. In that case, it is possible to use three or four systems of components that are relatively prone to failure and two systems of components that are relatively less prone to failure. For example, when the driver circuit is most prone to failure, as in the seventh embodiment shown in FIG. 35, the driver system may have four systems and the others may have two systems.

[0123] Also, as in the eighth embodiment shown in FIG. 36, the ECU 15 is provided with four power supply ICs 31 to 34 and four oscillators 41 to 44, and a plurality (two in FIG. 36) of power supply ICs and oscillators may be provided for one microcomputer. In this embodiment, a total of four arithmetic cores are provided, and each arithmetic core uses a different power supply IC as a power source and a different oscillator as a clock source. Even with this configuration, the same effects as those of the above-described embodiments can be obtained.

[0124] (Ninth Embodiment) The ninth embodiment is shown in FIGS. 37 and 38. In the above-described embodiments, the arithmetic core has been described as having lockstep. When the arithmetic core has lockstep, redundant arithmetic is performed by the lockstep core, and abnormal detection is performed by comparing the arithmetic results. On the other hand, when the arithmetic core does not have a lockstep core, arithmetic errors cannot be detected. In the seventh embodiment, it is an example in which the arithmetic core does not have a lockstep core, and the microcomputers 21 and 23 each have three arithmetic cores, and abnormal monitoring is performed by a majority vote of the arithmetic results.

[0125] As shown in FIG. 38, the three arithmetic cores 261 to 263 can operate independently and can operate simultaneously based on a common clock. In this case, for example, when momentary noise is input, the operations in the three arithmetic cores 261 to 263 may be affected in the same way. Therefore, by shifting the operation timing using the clock delay device 265, it is possible to prevent the simultaneous occurrence of operation errors. Since the comparator 267 that compares the operation results needs to compare the operation results at the same timing, the delay amounts among the multiple cores are made uniform. By dynamically comparing using the comparator 267, a determination can be made at high speed. Also, instead of comparing with the comparator 267, data may be stored for a certain period of time and compared collectively by the arithmetic cores 261 to 263. Even with such a configuration, the same effects as those of the above-described embodiment can be obtained.

[0126] (Embodiment 10) Embodiment 10 is shown in FIGS. 39 to 41. In Embodiment 10, the operation method in the redundant configuration will be described. For example, in the case of a configuration in which four microcontrollers and four motor windings are provided (see FIG. 32), the four microcontrollers may be evenly driven, and the output per set of motor windings may be 25% each.

[0127] Also, two microcontrollers and two sets of motor windings are used as the drive system, and the remaining two are used as the backup system. During normal operation, the motor windings are driven by the drive system so that the output per set of motor windings is 50% each. Also, when an abnormality occurs in the drive system, the drive is switched to the backup system.

[0128] FIG. 39 shows an example in which there are four microcontrollers 21 to 24 and driver circuits 51 to 54, and two sets of motor windings 121 and 123. The microcontrollers 21 and 22 and the driver circuits 51 and 52 are connected to the motor winding 121, and the microcontrollers 23 and 24 and the driver circuits 53 and 54 are connected to the motor winding 123. A motor relay 131 is provided between the driver circuit 51 and the motor winding 121, a motor relay 132 is provided between the driver circuit 52 and the motor winding 122, a motor relay 133 is provided between the driver circuit 53 and the motor winding 123, and a motor relay 134 is provided between the driver circuit 54 and the motor winding 124. Each of the motor relays 131 to 134 includes three switching elements corresponding to each phase. In the figure, the motor relay is described as "SW".

[0129] As shown in FIG. 40, during normal operation, by turning on the motor relays 131 and 133, the driver circuits 51 and 53 are used to energize the motor windings 121 and 123 to drive the motor 11. When an abnormality occurs in the microcontroller 21, by turning off the motor relay 131 and turning on the motor relay 132 from off, the driver circuit 52 is used instead of the driver circuit 51 to energize the motor winding 121. If the microcontroller 23 is normal, the motor relay 133 remains on and the motor relay 134 remains off.

[0130] Similarly, when an abnormality occurs in the microcontroller 23, by turning off the motor relay 133 and turning on the motor relay 134 from off, the driver circuit 54 is used instead of the driver circuit 53 to energize the motor winding 123. If the microcontroller 21 is normal, the motor relay 131 remains on and the motor relay 132 remains off. Thus, even when abnormalities occur in the microcontrollers 21 and 23, the motor 11 can be continuously driven in the same state as before the abnormalities occurred.

[0131] As shown in FIG. 41, the components related to the energization of the motor winding 121 are intensively arranged on one side of the substrate 75 (the left side of the paper in the example of FIG. 41), and the components related to the energization of the motor winding 123 are intensively arranged on the other side of the substrate 75 (the right side of the paper in the example of FIG. 41).

[0132] On the substrate 75, the power terminals are arranged line-symmetrically with respect to the substrate partition line D1. Also, the lead wires of the motor windings 121 and 123, the driver components 73, and the motor relays 131 to 134 between the motor wires and the driver components are arranged line-symmetrically with respect to the substrate partition line D1 in the configuration corresponding to the motor winding 121 and the configuration for the motor winding 123, and the phase arrangements are arranged in reverse order.

[0133] The driver component 73 has a high-side chip 712, a low-side chip 713, and a control chip 711 in which a corresponding pre-driver IC is incorporated, each corresponding to each phase, integrally sealed. The six driver components 73 are arranged side by side with the element-side end facing the motor windings 121 and 123 and the IC-side end facing the substrate partition line D1.

[0134] Inside the driver component 73, they are arranged in the order of the low-side chip 713, the high-side chip 712, and the control chip 711 from the motor windings 121 and 123 side. The low-side chip 713 may be laminated with a shift with respect to the high-side chip 712, or may be placed flat without lamination, or the control chip 711 may be separate. Also, the driver components 701 to 704 of the above embodiment in which a total of six switching elements are modularized may be used. In this case, for the phase arranged in the middle (the V phase in the example of FIG. 41), the elements of the drive system and the elements of the backup system are assigned to different modules.

[0135] In Fig. 41, the components of the drive system are shown by solid lines, and the components of the backup system are shown by two-dot chain lines. The driver components of the drive system and the driver components of the backup system corresponding to each phase are adjacent to each other and arranged alternately. Therefore, the high-side chip 712 and the low-side chip 713 used for driving in the same phase are arranged adjacent to each other. As a result, it is easy to wire the driver component 73 and the motor windings 121 and 123, and the mounting area of the power section on the substrate can be suppressed. Even with such a configuration, the same effects as those of the above-described embodiment can be obtained.

[0136] (Embodiments 11 to 13) Embodiments 11 to 13 are variations in the power terminal arrangement and connection. When four external input systems are provided as in the 11th embodiment shown in Fig. 42 (see Fig. 32), the power terminals 761 to 764 corresponding to the four connectors are evenly arranged at 90° intervals.

[0137] As in the 12th embodiment shown in Figs. 43 and 44, on the outer edge side of the substrate 75, the power terminal 761 and the power terminal 762, and the power terminal 763 and the power terminal 763 may be arranged side by side at two locations on both sides with the substrate partition line D1 interposed therebetween. When four sets of power terminals 761 to 764 corresponding to the four connectors are provided for the two power ICs 31 and 33, the two sets of power terminals 76 are connected to the respective power ICs 31 and 33 via the diodes 781 to 784. By electrically connecting between a plurality of power inputs, even when an abnormality of the connector or disconnection of the harness occurs, power supply can be appropriately continued.

[0138] Also, as in the 13th embodiment shown in Figs. 45 to 47, switching elements 786 to 789 may be provided between the connector and the power IC instead of the diodes 781 to 784. The switching elements 786 and 787 are connected to the power IC 31, and the switching elements 788 and 789 are connected to the power IC 33.

[0139] As shown in FIG. 46, during normal operation, both switching elements 786 and 787 are turned on. When an abnormality occurs in power supply 1A, the switching element 786 on the side where the abnormality occurs is turned off. When an abnormality occurs in power supply 1B, the switching element 787 is turned off. By turning on both switching elements 786 and 787 during normal operation, the power supply to be used can be quickly switched when an abnormality occurs.

[0140] Also, as shown in FIG. 47, during normal operation, the switching element 786 is turned on and the switching element 787 is turned off so that power is supplied from one power supply (for example, power supply 1A). When an abnormality in power supply 1A is detected, the switching element 786 is turned off, and a wake-up signal is sent from the normal microcontroller to the switching element 787 to turn on the switching element 787. Thereby, the current consumption during normal operation can be suppressed. The control of the switching elements 788 and 789 connected to the power supply IC 33 is the same. Even with this configuration, the same effects as those of the above-described embodiment can be obtained.

[0141] (14th Embodiment, 15th Embodiment) The 14th embodiment and the 15th embodiment are variations in the substrate arrangement. In the first embodiment, the motor windings 121 to 124 are provided on the radially outer side of the driver components 701 to 704 (see FIG. 11). In the 14th embodiment shown in FIG. 48, the motor windings 121 to 124 are provided on the radially inner side of the driver component 701.

[0142] Also, in the 15th embodiment shown in FIG. 49, the driver components 701 and 702 are arranged symmetrically with respect to the substrate center line D2 such that the pre-driver ICs 61 and 62 face the power terminal 76 side. Also, the driver components 703 and 704 are arranged symmetrically with respect to the substrate center line D2 such that the pre-driver ICs 63 and 64 face the power terminal 76 side. The motor windings 121 to 124 are provided on the driver circuit 51 to 54 sides of the driver components 701 to 704. Even with this configuration, the same effects as those of the above-described embodiment can be obtained.

[0143] (16th Embodiment) Embodiments 16 to 18 are modification examples of the driver component. Embodiment 16 is shown in FIGS. 50 to 52. FIG. 50 is a diagram corresponding to FIG. 7, showing each component in a simplified manner. In the driver component 705 of this embodiment, the stacked structure of the chips 712 and 713 is generally the same as that of the first embodiment.

[0144] The ground land 724 of the lead frame 725 is provided on both sides of the power land 722. The ground clip 741 is bent downward on both sides in the width direction and is connected to the ground land 724.

[0145] As shown in FIG. 52, the control land 726 where the control chip 711 is arranged is exposed from the back side of the sealing portion 749 at the middle portion in the width direction and is not exposed from the sealing portion 749 on the outer side in the width direction. In other words, as shown by the dashed square, a part of the control land 726 is in a state of floating from the substrate 75. Thereby, the substrate routing property of the high-side chip 712 and the power line can be ensured. Also, since the power + line and the GND line are in a straight line, it becomes easier to arrange noise prevention elements such as a snubber element (not shown). Also, the noise loop can be reduced. Also, the same effects as those of the above embodiment are achieved.

[0146] (17th Embodiment) Embodiment 17 is shown in FIGS. 53 to 55. In the driver component 706 of this embodiment, the control chip 711 is not built in, and the lead frame 727 does not have the control land 726. The stacked structure of the chips 712 and 713 is generally the same as that of the first embodiment. Note that the control chip 711 may also be built in this embodiment. Also, in embodiments such as the first embodiment, the control chip 711 may be provided separately without being built in the driver component.

[0147] In this embodiment, the ground land 724 is divided for each phase and is arranged on the side opposite to the output land 723 with the power land 722 interposed therebetween. The ground clip 742 is provided for each phase. The ground clip 742 is provided above each low-side chip 713 and is bent downward to be connected to the ground land 724. Notches 743 are formed in the ground clip 742 so that a part of the high-side chip 712 and the low-side chip 713 is exposed on the top surface side. Thereby, a non-overlapping region is secured, and the high-side chip 712 and the low-side chip 713 can be connected to the signal lines.

[0148] By dividing the ground clip 742 for each phase and detecting the voltage at both ends on the side of the low-side chip 713 and the side of the ground land 724, the motor current can be detected. That is, in this embodiment, the ground clip 742 also functions as a current detection element. Thereby, the motor current can be detected with a relatively simple configuration.

[0149] (Embodiment 18) Embodiment 18 is shown in FIG. 56. In the driver component 707 of this embodiment, the high-side chip 712 and the low-side chip 713 are not stacked but are placed flat. In this embodiment, from one side, the control chip 711, the high-side chip 712, and the low-side chip 713 are arranged in this order.

[0150] The lead frame 728 of this embodiment has a control land 721, a power land 722, an output land 729, and a ground land 724, and the low-side chip 713 is arranged on the output land 729. The intermediate clip 715 is provided above each high-side chip 712, and one end side is bent downward to be connected to the output land 729.

[0151] In this embodiment, since the high-side chip 712 is arranged between the low-side chip 713 and the control chip 711, it is difficult to directly connect the gate electrode of the low-side chip 713 to the control chip 711. Therefore, in this embodiment, bonding pads are provided on the high-side chip 712, and the gate terminal of the low-side chip 713 and the control chip 711 are connected via the bonding pads of the high-side chip 712. By relaying the high-side chip 712 provided therebetween, the control chip 711 and the low-side chip 713 can be appropriately connected. Also, the same effects as those of the above embodiment are achieved.

[0152] (Embodiment 19) Embodiment 19 is shown in FIGS. 57 to 62. In Embodiments 19 to 24, the communication between the microcomputer and the driver components, or between the driver components, will be mainly described. In the following embodiments, for the sake of simplicity of explanation, it will be described assuming that two microcomputers, two driver components, and two motor windings are provided, but it is also applicable to the configurations of the above embodiments.

[0153] As shown in FIG. 57, in the first control system, the microcomputer 201 and the driver component 801 are connected, and in the second control system, the microcomputer 202 and the driver component 802 are connected. The microcomputers 201, 202 and the driver components 801, 802 are generally the same as the microcomputers 21, 23 and the driver components 701, 703 of the above embodiment except for the communication configuration. For the reference numerals of the configurations other than the microcomputer, the driver component, and the isolator, those of the above embodiment are appropriately incorporated.

[0154] Hereinafter, the combination of the microcomputer 201 and the driver component 801 is defined as the "first control system", and the combination of the microcomputer 202 and the driver component 802 is defined as the "second control system". Also, in the embodiments described later, the combination of the microcomputer 201 and the driver components 803 and 811 is defined as the "first control system", and the combination of the microcomputer 202 and the driver components 804 and 812 is defined as the "second control system". In the figures and the like, in order to distinguish the systems, the subscript "1" is appropriately attached to the components and signals of the first control system, and the subscript "2" is appropriately attached to the components and signals of the second control system. Also, when the systems are not distinguished, the subscripts "1", "2", etc. are omitted from the description.

[0155] The microcomputers 201 and 202 are provided with a terminal for outputting a clock signal CLK, a MISO signal terminal to which a signal from the driver side is input, a MOSI signal terminal for outputting a signal to the driver side, a terminal for outputting a chip select signal CS, and a terminal for outputting an enable signal EN. The driver components 801 and 802 have a terminal to which a clock signal CLK is input, a MISO signal terminal for outputting a signal to the microcomputer side, a MOSI terminal to which a signal from the microcomputer side is input, and a terminal to which a chip select signal CS is input. In this embodiment, the driver components 801 and 802 are provided with a set of communication ports used for communication between the microcomputer and the driver.

[0156] The chip select signals CS11 and CS12 are signals output from the microcomputer 201. The chip select signal CS11 is a signal for selecting the driver component 801, and the chip select signal CS12 is a signal for selecting the driver component 802. The chip select signals CS21 and CS22 are signals output from the microcomputer 202. The chip select signal CS21 is a signal for selecting the driver component 802, and the chip select signal CS22 is a signal for selecting the driver component 801. The chip select signals CS12 and CS22 for selecting the driver components on the other system side are output to the other system side via the isolators 281 and 282, respectively.

[0157] The enable signal EN1 is a signal output from the microcomputer 201 to the isolator 281, and the enable signal EN2 is a signal output from the microcomputer 202 to the isolator 282.

[0158] The inter-system connection line 251 connects the in-system communication lines C1 and C2, and is mainly used for signal transmission between the microcomputer 201 and the driver component 802. Specifically, the inter-system connection line 251 includes a clock signal output from the microcomputer 201 and a signal line for outputting the MOSI signal to the second control system side. The inter-system connection line 251 also includes a signal line for outputting the MISO signal output from the driver component 802 to the first control system side. An isolator 281 is provided on the inter-system connection line 251.

[0159] The inter-system connection line 252 connects the in-system communication lines C1 and C2, and is mainly used for signal transmission between the microcomputer 202 and the driver component 801. Specifically, the inter-system connection line 252 includes a clock signal output from the microcomputer 202 and a signal line for transmitting the MOSI signal to the first control system side. The inter-system connection line 252 also includes a signal line for transmitting the MISO signal output from the driver component 801 to the second system side. An isolator 282 is provided on the inter-system connection line 252.

[0160] The enable signal EN1 from the microcomputer 201 is input to the isolator 281, and the enable signal EN2 from the microcomputer 202 is input to the isolator 282. That is, the isolators 281 and 282 of the present embodiment have an enable function of switching the validity / invalidity of signals based on the enable signals EN1 and EN2 from the microcomputers 201 and 202, in addition to the system separation function that enables signal transmission and reception while maintaining the potential difference. The enable function may be configured to switch the validity / invalidity by the enable signal for each signal line, or may be configured to output one enable signal collectively for a plurality of signal lines to switch the validity / invalidity.

[0161] As shown in FIG. 58, the isolator 281 determines an output signal using a logic operation or a switching element based on the relationship between the input signal and the enable signal. For example, as shown in FIG. 59, when the input signal is "H" and the enable signal is "permitted", the output signal is set to "H", and when the input signal is "L" and the enable signal is "permitted", the output signal is set to "L". Also, when the enable signal is "not permitted", regardless of the input signal, the output signal is set to "indeterminate" or "H fixed" or "L fixed". The same applies to the isolator 282.

[0162] In this embodiment, during normal operation, the microcontrollers 201 and 202 perform microcontroller-driver intercommunication with the driver components 801 and 802 of their own systems respectively. When the microcontroller 202 is abnormal, the microcontroller 201 communicates with the driver components 801 and 802. When the microcontroller 201 is abnormal, the microcontroller 202 communicates with the driver components 801 and 802.

[0163] In the microcontroller-driver intercommunication, the information transmitted from the microcontrollers 201 and 202 includes the duty command values Du1 and Du2 which are inverter control commands, and the information transmitted from the driver components 801 and 802 includes the current detection values I1 and I2 and the driver abnormality information E1 and E2.

[0164] FIG. 60 is a flowchart for explaining the communication process of this embodiment. This process is assumed to be executed synchronously at a predetermined period by the microcontrollers 21 and 23. Here, taking the process in the microcontroller 21 as an example, the first control system is the own system and the second control system is the other system for explanation. The process in the microcontroller 23 may be appropriately read with the second control system as the own system and the first control system as the other system. The same applies to the flowcharts according to the embodiments described later.

[0165] In S301, the microcontroller 201 determines whether the own-system microcontroller is normal. If it is determined that the own-system microcontroller is not normal (S301: NO), the process proceeds to S308 and the own-system microcontroller stop process is performed. If it is determined that the own-system microcontroller is normal (S301: YES), the process proceeds to S302.

[0166] In S302, the microcomputer 201 determines whether the microcomputer 202, which is a microcomputer of another system, is normal. Here, for example, the determination is made based on information obtained through communication between microcomputers. If it is determined that the microcomputer of another system is not normal (S302: NO), the process proceeds to S304. If it is determined that the microcomputer of another system is normal (S302: YES), the process proceeds to S303.

[0167] In S303, where the process proceeds when it is determined that both the own system and the other system are normal, the microcomputer 201 disables the enable signal EN1 to the isolator 281 in the state where the driver component 801 has selected the chip select signal CS11, and conducts communication between the microcomputer 201 and the driver component 801 within the own system. At the same time, on the side of the second control system, which is the other system, communication between the microcomputer 202 and the driver component 802 is carried out.

[0168] Specifically, on the side of the first control system, the chip select signal CS11 is in the selected state, the chip select signal CS12 is in the non - selected state, and the enable signal EN1 is disabled. Also, on the side of the second control system, the chip select signal CS21 is in the selected state, the chip select signal CS22 is in the non - selected state, and the enable signal EN2 is disabled. That is, here, by disabling the enable signals EN1 and EN2, information transmission and reception in each control system are carried out simultaneously and in parallel.

[0169] In S304, where the process proceeds when it is determined that the microcomputer of another system is not normal (S302: NO), the microcomputer 201 determines whether the microcomputer of another system has stopped. If it is determined that the microcomputer of another system has already stopped (S304: YES), S305 is skipped and the process proceeds to S306. If it is determined that the microcomputer of another system has not stopped (S304: NO), the process proceeds to S305, where the process of stopping the microcomputer of another system is carried out, and then the process proceeds to S306.

[0170] In S306, the microcomputer 201 and the driver component 801 perform information transmission and reception. At this time, the chip select signal CS11 is in the selected state, the chip select signal CS12 is in the non-selected state, and the enable signal EN1 is disabled.

[0171] In S307, the microcomputer 201 and the driver component 802 perform information transmission and reception. At this time, the chip select signal CS11 is in the non-selected state, the chip select signal CS12 is in the selected state, and the enable signal EN1 is enabled.

[0172] The communication process of this embodiment will be described based on the time charts of FIGS. 61 and 62. In FIGS. 61 and 62, a common time axis is used as the horizontal axis, and various signals output from the microcomputer 201 or the driver component 801 in the first control system are shown on the upper side, and various signals output from the microcomputer 202 or the driver component 802 in the second control system are shown on the lower side.

[0173] Here, regarding the enable signal EN, the case of permission is described as H and the case of non-permission is described as L, but it is only necessary to be able to distinguish permission / non-permission, and H may be non-permission and L may be permission. Also, an example where the data frame length is 8 bits is shown, but the frame length is arbitrary. The same applies to the time charts for describing the communication process according to the embodiments described later.

[0174] As shown in FIG. 61, when both microcomputers 201 and 202 are normal, both enable signals EN1 and EN2 are disabled, data transmission and reception are performed between the microcomputer 201 and the driver component 801 within the first control system, and data transmission and reception are performed between the microcomputer 202 and the driver component 802 within the second control system. In this embodiment, the signal lines between the microcomputer and the driver are connected by the inter-system connection lines 251 and 252, but the isolators 281 and 282 have an enable function, and by disabling the enable signal EN, communication within each control system can be performed in parallel. Thereby, compared with the case where communication is sequentially performed for each control system, the time difference in data acquisition between systems can be reduced.

[0175] Figure 62 shows an example when the microcomputer 202 malfunctions. When the microcomputer 202 malfunctions, the microcomputer 201 communicates with the driver components 801 and 802. As shown in the lower part of the drawing, the clock signal CKL2 and the SPI signals (MISO2, MOSI2) of the microcomputer 202 are both at L level, the chip select signals CS21 and CS22 are not selected, and the enable signal EN2 is in a non-permitted state.

[0176] As shown in the upper part of the drawing, in the microcomputer 201, a timer is used to communicate with the driver components 801 and 802 alternately. As shown on the left side of the upper part of the drawing, the communication between the microcomputer 201 and the driver component 801 is the same as the normal example in Figure 61. As shown on the right side of the upper part of the drawing, when communicating between the microcomputer 201 and the driver component 802, the chip select signal CS11 is in a non-selected state, the chip select signal CS12 is in a selected state, and the enable signal EN1 is permitted. Thereby, information can be transmitted and received between the microcomputer 201 and the driver component 802 via the inter-system connection line 251.

[0177] When the microcomputer 201 malfunctions, the microcomputer 202 communicates with the driver components 801 and 802 alternately instead of the microcomputer 201. When communicating between the microcomputer 202 and the driver component 801, the chip select signal CS21 is in a non-selected state, the chip select signal CS22 is in a selected state, and the enable signal EN2 is permitted. Thereby, information can be transmitted and received between the microcomputer 202 and the driver component 801 via the inter-system connection line 252.

[0178] Note that communication can be established only by the chip select. However, when the chip select signal fluctuates due to external interference or the like, incorrect communication may occur. Therefore, during the period when communication with the other system side is not performed, the enable signal EN is set to non-permitted by the enable function. Also, here, an example of a microcomputer failure has been described. However, when a driver failure occurs, it is preferable to isolate the driver side.

[0179] In this embodiment, the inter-system connection lines 251 and 252 connect the control systems via isolators 281 and 282 that enable information transmission while maintaining a potential difference. The isolators 281 and 282 can receive enable signals EN1 and EN2 from the microcontrollers 201 and 202. When the enable signals EN1 and EN2 are in an allowed state, communication between the systems is permitted. When the enable signals EN1 and EN2 are in a non-allowed state, communication between the systems is prohibited.

[0180] In this embodiment, the inter-system connection lines 251 and 252 connect the intra-system communication lines C1 and C2, and the intra-system communication lines C1 and C2 are shared for intra-system communication and inter-system communication. Therefore, by using the enable signals EN1 and EN2, intra-system communication and inter-system communication can be appropriately performed.

[0181] When the microcontroller 202 of the other system is normal, the microcontroller 201 communicates with the driver component 801 of its own system. When the microcontroller 202 of the other system is abnormal, the microcontroller 201 communicates with the driver component 801 of its own system and the driver component 802 of the other system. Also, when the microcontroller 201 of the other system is normal, the microcontroller 202 communicates with the driver component 802 of its own system. When the microcontroller 201 of the other system is abnormal, the microcontroller 202 communicates with the driver component 802 of its own system and the driver component 801 of the other system. The communication data includes duty command values, current detection values, abnormality information, etc. Thereby, even when an abnormality occurs in one of the microcontrollers, the driving of the motor 11 using the two sets of motor windings 121 and 123 can be continued, and the same effects as those of the above embodiment are achieved.

[0182] (20th Embodiment) The 20th embodiment is shown in FIGS. 63 and 64. The communication process of this embodiment will be described based on the flowchart of FIG. 63. FIG. 63 is different from FIG. 60 in that S309 and S310, which are to be shifted to next after S303, are added.

[0183] Both the self-system and the other system are normal. In S309, which is executed after performing parallel communication within each system in S303, communication is carried out between the microcomputer 201 and the driver component 802. In S310, communication is carried out between the microcomputer 202 and the driver component 801. S309 and S310 may have their processing order swapped. The microcomputers 201 and 202 synchronize the timers through inter-microcomputer communication or the like, and perform communication with the other system side in sequence.

[0184] The communication process of this embodiment will be described based on the time chart of FIG. 64. The left side of the paper of FIG. 64 corresponds to S303. The enable signals EN1 and EN2 are turned off, and within each system, communication between the microcomputer and the driver is performed. The state of the signals is the same as that in FIG. 61.

[0185] The center of the paper of FIG. 64 corresponds to S309, and communication is carried out between the microcomputer 201 and the driver component 802. When communicating between the microcomputer 201 and the driver component 802, the chip select signal CS12 is in the selected state, the other chip select signals CS11, CS21, CS22 are in the non-selected state, the enable signal EN1 is permitted, the enable signal EN2 is not permitted, and SPI communication is carried out between the microcomputer 201 and the driver component 802.

[0186] The right side of the paper of FIG. 64 corresponds to S310, and communication is carried out between the microcomputer 202 and the driver component 801. When communicating between the microcomputer 202 and the driver component 801, the chip select signal CS22 is in the selected state, the other chip select signals CS11, CS12, CS21 are in the non-selected state, the enable signal EN2 is permitted, the enable signal EN1 is not permitted, and SPI communication is carried out between the microcomputer 202 and the driver component 801. The communication in case of microcomputer abnormality is the same as that in the 19th embodiment.

[0187] In this embodiment, even when both the microcomputers 201 and 202 are normal, communication is carried out with the driver components 802 and 801 on the other system side using the inter-system connection lines 251 and 252. Thereby, the inter-microcomputer communication load can be reduced. Alternatively, the inter-microcomputer communication can be omitted. Even with such a configuration, the same effects as those of the above embodiment can be achieved.

[0188] (21st Embodiment) The 21st embodiment is shown in FIGS. 65 to 67. In the 19th embodiment, the inter-system connection line 251 is connected to the in-system communication line C2 of the second control system via the isolator 281, and the inter-system connection line 252 is connected to the in-system communication line C2 of the first control system via the isolator 282.

[0189] In contrast, in this embodiment, as shown in FIG. 65, the driver components 803 and 804 have communication ports that are connected to the other system side via the isolators 281 and 282, in addition to the communication ports used for communication with the own-system microcomputer. The inter-system connection line 251 is directly connected to the driver component 804 via the isolator 281, and the inter-system connection line 252 is directly connected to the driver component 803 via the isolator 282. Thereby, communication between the microcomputer 201 and the driver component 804 and communication between the microcomputer 202 and the driver component 803 can be performed simultaneously.

[0190] The communication process of this embodiment will be described based on the flowchart of FIG. 66. In FIG. 66, the difference is that it is S311 instead of S309 and S310 in FIG. 63. In S311, which is entered after parallel communication within each system is performed in S303 and both the own system and the other system are normal, the microcomputer 201 communicates with the driver component 804 on the other system side. At the same time, the microcomputer 202 communicates with the driver component 803.

[0191] The communication process of this embodiment will be described based on the time chart of FIG. 67. The left side of the paper in FIG. 67 corresponds to S303, where the enable signals EN1 and EN2 are disabled and microcomputer-driver communication is performed within each system. The state of the signals is the same as in FIG. 61.

[0192] The right side of the paper of FIG. 67 corresponds to S311, and the communication between the microcomputer 201 and the driver component 804 and the communication between the microcomputer 202 and the driver component 803 are performed in parallel. The microcomputer 201 sets the chip select signal CS11 to the non-selected state, the chip select signal CS12 to the selected state, and the enable signal EN1 to the permitted state, and performs SPI communication with the driver component 804. The microcomputer 202 sets the chip select signal CS21 to the non-selected state, the chip select signal CS22 to the selected state, and the enable signal EN2 to the permitted state, and performs SPI communication with the driver component 803.

[0193] In this embodiment, since the ports for communication within the system and the ports for communication with other systems are provided separately, by controlling the chip select signal CS and the enable signal EN, the microcomputers 201 and 202 can perform communication with the driver components 804 and 803 of other systems in parallel. As a result, the time difference of the data acquired by the microcomputers 201 and 202 from the driver side can be reduced. Also, the communication time can be reduced.

[0194] In this embodiment, the inter-system connection line 251 connects the in-system communication line C1 and the driver component 804 of another control system, and the inter-system connection line 252 connects the in-system communication line C2 and the driver component 803 of another control system. In the driver components 803 and 804, the communication ports to which the inter-system connection lines 251 and 252 are connected are provided separately from the ports to which the in-system communication lines C1 and C2 are connected. Thereby, the microcomputer-driver communication with other systems can be performed in parallel. Also, the same effects as the above embodiment are achieved.

[0195] (22nd Embodiment) The 22nd embodiment is shown in FIG. 68. In this embodiment, the mounting positions of the isolators are different from those in the 21st embodiment. As shown in FIG. 68, the isolators 281 and 282 of this embodiment are built in the driver components 803 and 804. By building the isolators 281 and 282 in the driver components 803 and 804, the component layout and wiring of the substrate 75 can be simplified. Note that the communication processing and the like are the same as those in the 21st embodiment. Also, the same effects as those in the above embodiment are achieved.

[0196] (23rd Embodiment) The 23rd embodiment is shown in FIGS. 69 to 76. In the 23rd embodiment and the 24th embodiment, the driver components 811 and 812 are connected by the inter-system connection line 253, and the isolator 283 is provided on the inter-system connection line 253. Thereby, communication can be performed between the driver components 811 and 812 without passing through the microcontrollers 201 and 202. In the example of FIG. 69, the isolator 283 is provided on the inter-system connection line 253, but the isolator 283 may be built in at least one of the driver components 811 and 812 as in the 22nd embodiment. The same applies to the 24th embodiment. Also, the isolator 283 may have an enable function as in the above embodiment.

[0197] The driver components 811 and 812 include a driver abnormality detection unit 813 and the like. The driver abnormality detection unit 813 detects abnormalities in its own system such as internal voltage abnormality, communication abnormality, and output voltage abnormality. Information related to the driver abnormal state is transmitted to the microcontroller of its own system and the driver components of other systems. When a driver abnormality is notified, the microcontrollers 201 and 202 perform abnormal handling.

[0198] The driver component 811 transmits the duty command value Du1 and the current detection value I1 of its own system to the driver component 812 of the other system via inter-driver communication, and receives the duty command value Du2 and the current detection value I2 of the other system from the driver component 812. The driver component 812 transmits the duty command value Du2 and the current detection value I2 of its own system to the driver component 811 of the other system via inter-driver communication, and receives the duty command value Du1 and the current detection value I1 of the other system from the driver component 811. The driver components 811 and 812 update the duty command values, current detection values, and driver abnormal states of both systems at any time.

[0199] The data flows in the microcontrollers 201 and 202 and the driver components 811 and 812 are shown in FIGS. 70 and 71. In FIG. 70, for the communication between the microcontroller and the driver and the communication between the drivers, the MISO signal is shown as a solid line and the MOSI signal is shown as a dashed-dotted line. Note that the signal lines in other parts are shown as solid lines, but this does not mean that they are MISO signals. Also, in FIGS. 71 and 72, the communication between the microcontroller and the driver is shown as a white-block arrow, the communication between the drivers is shown as a hatched-block arrow, and the values used for motor drive are shown as double lines. Also, the driver circuits 51 and 53 are described as "INV1" and "INV2".

[0200] In the communication between the microcontroller and the driver within the system, SPI communication is performed with the microcontrollers 201 and 202 as masters and the driver components 811 and 812 as slaves, respectively. In the inter-driver communication, an example is shown here where the driver component 811 communicates with the driver component 812 as the master and the driver component 812 as the slave, but the driver component 812 may also be the master and the driver component 811 may be the slave.

[0201] In driver-to-driver communication, driver component 811 receives the current detection value I2 and driver abnormality information E2 of the second control system, and the duty command value Du1 related to the first control system from driver component 812 via MISO_d. Also, driver component 811 transmits the current detection value I1 and driver abnormality information E1 of the first control system, and the duty command value Du2 related to the second control system via MOSI_d.

[0202] In microcontroller-to-driver communication, microcontroller 201 transmits the duty command values Du1 and Du2 of its own system and the other system to driver component 811 via MOSI_1. Also, microcontroller 201 receives the current detection values I1 and I2 and driver abnormality information E1 and E2 of its own system and the other system from driver component 811 via MISO_1.

[0203] Microcontroller 202 transmits the duty command values Du2 and Du1 of its own system and the other system to driver component 812 via MOSI_2. Also, microcontroller 202 receives the current detection values I2 and I1 and driver abnormality information E2 and E1 of its own system and the other system from driver component 812 via MISO_2. When the microcontrollers 201 and 202 of its own system are normal, driver components 811 and 812 control driver circuits 51 and 53 using the duty command values Du1 and Du2 transmitted from the microcontrollers 201 and 202 of its own system, and control the energization of motor windings 121 and 123.

[0204] Note that in FIGS. 70 and 71, regardless of the states of microcontrollers 201 and 202, information of its own system and the other system is transmitted and received in microcontroller-to-driver communication. However, when the microcontroller on the other system side is normal, it may not be necessary to transmit and receive information related to the other system. Also, the duty command value to be sent to the other system side in driver-to-driver communication may be calculated by driver components 811 and 812 from the duty command value of its own system (see Equation (1)). In the equation, "D * self" is the duty command value of its own system, "D * other" is the duty command value of the other system, and K is an offset value corresponding to the phase difference of the motor windings.

[0205] D * He = D * Self + K ···(1)

[0206] The case where one microcomputer (here, microcomputer 202) is abnormal will be described with reference to FIG. 72. When microcomputer 202 is abnormal, communication between microcomputers and microcomputer-driver communication between microcomputer 202 and driver component 812 cannot be performed. In FIG. 72, those that cannot be transmitted and received due to the abnormality of microcomputer 202 are indicated by broken lines. Here, only the characteristic parts during abnormality will be described, and the description of the parts common to the normal state will be omitted as appropriate.

[0207] When microcomputer 202 is abnormal, driver component 812 transmits the current detection value I2 of its own system and abnormality information E2 to driver component 811 at MISO_d. Driver component 811 transmits, in addition to its own current detection value I1 and driver abnormality information E1, the current detection value I2 of the second control system side and driver abnormality information E2 to microcomputer 201 at MISO_1.

[0208] In microcomputer 201, a duty command value Du2 is calculated based on the current detection value I2 of the second control system side. For example, the duty command values Du1 and Du2 may be calculated based on the current detection values I1 and I2 by control such as addition and subtraction. The same applies to the normal state. The duty command value Du2 calculated by microcomputer 201 is transmitted to driver component 801 at MOSI_1. Driver component 801 transmits the duty command value Du2 to driver component 802 at MOSI. In driver component 802, the duty command value Du2 received from the first control system side is used to control driver circuit 53 and control the energization of motor winding 123.

[0209] When microcomputer 201 is abnormal, the duty command value Du2 calculated by microcomputer 202 is transmitted to driver component 811 through microcomputer-driver communication and then transmitted from driver component 811 to driver component 812 through driver-driver communication. Thereby, even when one of microcomputers 201 and 202 becomes abnormal, motor driving in two systems can be continued.

[0210] In addition, when the driver component 811 malfunctions, the output of the motor drive signal to the driver circuit 51 is stopped, and single-system drive on the second system side is performed. When the driver component 812 malfunctions, the output of the motor drive signal to the driver circuit 53 is stopped, and single-system drive on the first system side is performed. The stop command for the motor drive signal may be output from any of the self-system microcomputer, the other-system driver, or the other-system microcomputer that has acquired information related to the driver abnormality. As a configuration for stopping the motor drive signal, for example, a relay may be provided at the output sections of the pre-driver ICs 61 and 63 to cut off the signal, or the pre-driver ICs 61 and 63 may be provided with a function that can stop the output from the outside.

[0211] The communication process between the microcomputer and the driver in this embodiment is shown in the flowchart of FIG. 73. FIG. 71 is the same as FIG. 60 except that S307 is omitted. That is, in this embodiment, an inter-system connection line 253 is provided between the drivers, and the microcomputer 201 acquires the information of the driver component 812, which is the other-system driver, via the driver component 811, which is the self-system driver, and thus does not directly transmit and receive information with the driver component 812.

[0212] The communication process between the drivers is shown in the flowchart of FIG. 74. The communication frequency of the communication between the drivers is higher than the communication frequency of the communication between the microcomputer and the driver. Here, the process of the driver component 811 will be described, but the same process is performed for the driver component 812.

[0213] In S351, the driver component 811 determines whether both the driver component 811 and the driver component 812 are normal. If it is determined that both the driver component 811 and the driver component 812 are normal (S351: YES), the process proceeds to S352, and communication between the drivers is performed. If it is determined that at least one of the driver component 811 and the driver component 812 is abnormal (S351: NO), the process proceeds to S353.

[0214] In S353, the driver component 811 determines whether the driver component 811 is abnormal and whether the driver component 812 is normal. If it is determined that the driver component 811 is abnormal and the driver component 812 is normal (S353: YES), the process proceeds to S354 and the driver component 811 is stopped. If it is determined that the driver component 811 is abnormal and the driver component 812 is not normal (S353: NO), the process proceeds to S355.

[0215] In S355, the driver component 811 determines whether the driver component 811 is normal and whether the driver component 812 is abnormal. If it is determined that the driver component 811 is normal and the driver component 812 is abnormal (S355: YES), the process proceeds to S356 and the driver component 812 is stopped. If it is determined that both the driver components 811 and 812 are abnormal (S355: NO), the process proceeds to S366 and the driver components 811 and 812 are stopped.

[0216] The communication process of this embodiment will be described based on the time charts of FIGS. 75 and 76. In FIGS. 75 and 76, the communication between the microcomputer 201 and the driver component 811 is shown in the upper part of the paper surface, the communication between the microcomputer 202 and the driver component 812 is shown in the middle part of the paper surface, and the communication between the driver components 811 and 812 is shown in the lower part of the paper surface. The same applies to FIG. 80 described later.

[0217] As shown in FIG. 75, when both the microcomputers 201 and 202 are normal, the communication between the microcomputer 201 and the driver component 811, the communication between the microcomputer 202 and the driver component 812, and the communication between the driver components 811 and 812 are carried out in parallel. In FIG. 75, the frequency of the communication between the drivers is three times that of the microcomputer-driver communication, but the communication frequency can be set arbitrarily.

[0218] As shown in FIG. 76, when the microcomputer 202 is abnormal, communication between the microcomputer 202 and the driver component 812 is not performed. Communication between the microcomputer 201 and the driver component 811, and communication between the driver components 811 and 812 are the same as in the normal state. The microcomputer 201 transmits the duty command values Du1 and Du2 of its own system and other systems to the driver component 811, and receives the current detection values I1 and I2 of its own system and other systems and the driver abnormality information E1 and E2 from the driver component 811.

[0219] In this embodiment, since the inter-system connection line 253 for performing communication between drivers is provided independently of the intra-system communication lines C1 and C2, communication between the microcomputer and the driver within each control system and communication between the drivers can be executed in parallel. As a result, the simultaneity of data between the drivers is improved due to the high-speed communication.

[0220] The inter-system connection line 253 connects the driver components 811 and 812 of different control systems. The microcomputer 201 can transmit the duty command value Du2 to the driver component 812 of the other system via the driver component 811 of its own system, and can receive the current detection value I2 which is sensor data and the driver abnormality information E2 of the other system from the driver component 812 of the other system. The microcomputer 202 can transmit the duty command value Du1 to the driver component 811 of the other system via the driver component 812 of its own system, and can receive the current detection value I1 which is sensor data and the driver abnormality information E1 of the other system from the driver component 811 of the other system.

[0221] In this embodiment, between the driver components 811 and 812, information of its own system and other systems is continuously updated. As a result, the microcomputers 201 and 202 can appropriately communicate with the other system side via the driver components 811 and 812 of their own systems. Also, the same effects as in the above embodiment are achieved.

[0222] (24th Embodiment) The 24th embodiment is shown in FIGS. 77 to 80. As shown in FIG. 77, the driver components 811 and 812 are provided with two sets of inter-system connection lines 253, and isolators 283 are provided for each of them. One of the two sets of inter-system connection lines 253 is a communication line with the driver component 811 as the master and the driver component 812 as the slave, and the other is a communication line with the driver component 812 as the master and the driver component 811 as the slave.

[0223] In the 23rd embodiment, the driver-driver communication is always carried out. In contrast, in this embodiment, when an inter-system access command is issued from the microcomputer side and received by the driver component side, the communication between the drivers is carried out. Hereinafter, the case where the driver component 811 is the master and the driver component 812 is the slave will be described as an example. The microcomputer 201 is configured to be able to transmit two commands to the driver component 811, namely, a command for reading and writing (hereinafter referred to as "R / W") only the own system, and a command for performing R / W on the own system and other systems. The command for performing R / W on the own system and other systems corresponds to the "inter-system access command".

[0224] The data flow of this embodiment will be described based on FIG. 78. When the driver component 811 receives the R / W commands for the own system and other systems from the microcomputer 201, during period [1], in the microcomputer-driver communication, the microcomputer 201 transmits the duty command value Du2 of the other system to the driver component 811, and the driver component 811 transmits the current detection value I1 of the own system to the microcomputer 201.

[0225] During period [2], in the microcontroller-driver communication, the microcontroller 201 transmits the duty command value Du1 of its own system to the driver component 811, and the driver component 811 transmits the abnormality information E1 of its own system driver to the microcontroller 201. Also, while the driver component 811 is returning the data of its own system to the microcontroller 201, it concurrently performs driver-to-driver communication. Specifically, in the driver-to-driver communication, the driver component 811 transmits the duty command value Du2 to the driver component 812, and the driver component 812 transmits the current detection value I2 to the driver component 811. Further, following the current detection value I2, the driver component 812 transmits the driver abnormality information E2 of the second control system to the driver component 811.

[0226] During period [3] after the reception of the current detection value I2 is completed, the driver component 811 transmits the current detection value I2 of the other system to the microcontroller 201, and during period [4] after the reception of the driver abnormality information E2 of the second control system is completed, it transmits the abnormal state of the other system to the microcontroller 201.

[0227] The microcontroller-driver communication process of this embodiment will be described based on the flowchart of FIG. 79. The processes of S301 to S305 and S308 are the same as those in FIG. 73. In S320 which proceeds when both the microcontrollers 201 and 202 are normal (S301: YES and S302: YES), the microcontroller 201 transmits a command for performing R / W only on its own system to the driver component 811. The process of S321 is the same as that of S303, and the microcontroller 201 communicates with the driver component 811. At the same time, on the second control system side which is the other system, the microcontroller 202 communicates with the driver component 812. Note that even when both the microcontrollers 201 and 202 are normal and communication is also performed with the other system side, it may be configured to proceed to S322 after a positive determination in S302.

[0228] In S322 which proceeds after the other-system microcontroller, the microcontroller 202, becomes abnormal and the other-system microcontroller stops, the microcontroller 201 transmits R / W commands for its own system and the other system to the driver component 811.

[0229] In S323, the microcomputer 201 performs communication between the driver component 811 and the microcomputer-driver. At this time, the driver components 811 and 812 perform communication between drivers, and the microcomputer 201 transmits and receives the duty command value Du2, the current detection value I2, and the driver abnormality information E2 via the driver component 811.

[0230] The communication process of this embodiment will be described based on the time chart of FIG. 80. The left side of the paper of FIG. 80 shows the case where the driver component 811 is the master in the communication between drivers, and the right side of the paper shows the case where the driver component 812 is the master in the communication between drivers. Here, the description will focus on the information communication with the other system, and the description of the information communication within the system will be omitted.

[0231] As shown on the left side of the paper, when the driver component 811 is the master, the R / W commands of the own system and the other system, and the duty command value Du2 of the other system are transmitted from the microcomputer 201 to the driver component 811. After recognizing the command, the driver component 811 performs communication between drivers, transmits the duty command value Du2 to the driver component 812, and receives the current detection value I2 and the driver abnormality information E2 of the other system from the driver component 812. In addition, the driver component 811 transmits the current detection value I2 and the driver abnormality information E2 received from the driver component 812 to the microcomputer 201.

[0232] As shown on the right side of the paper, when the driver component 812 is the master, the R / W commands of the own system and the other system, and the duty command value Du1 of the other system are transmitted from the microcomputer 202 to the driver component 812. After recognizing the command, the driver component 812 performs communication between drivers, transmits the duty command value Du1 to the driver component 811, and receives the current detection value I1 and the driver abnormality information E1 of the other system from the driver component 811. In addition, the driver component 812 transmits the current detection value I1 and the driver abnormality information E1 received from the driver component 811 to the microcomputer 202. Thereby, even when an abnormality occurs in one of the microcomputers 201 and 202, the motor drive in the two systems can be continued.

[0233] In this embodiment, the driver components 811 and 812 communicate with the driver components 812 and 811 of other systems in response to commands from the microcontrollers 201 and 202 of their own system. Even with such a configuration, communication between systems can be appropriately performed. Also, the same effects as those of the above embodiment are achieved.

[0234] In the embodiment, the motor 11 corresponds to the "load", the ECU 15 corresponds to the "communication device", the motor winding 121 corresponds to the "first winding set", the motor winding 122 corresponds to the "second winding set", the motor winding 123 corresponds to the "third winding set", the motor winding 124 corresponds to the "fourth winding set", the microcontrollers 21 to 24 correspond to the "control unit", the driver components 701 to 704, 801 to 804, 811, 812, the power supply ICs 31, 33, the communication units 36, 38, and the position sensors 66 to 69 correspond to the "electronic components", and the isolators 28, 281 to 283 correspond to the "system separation components". Also, the arithmetic cores 211, 212, 231, 233 correspond to the "arithmetic circuits", the arithmetic core 211 corresponds to the "first arithmetic circuit", the arithmetic core 212 corresponds to the "second arithmetic circuit", the arithmetic core 231 corresponds to the "third arithmetic circuit", and the arithmetic core 232 corresponds to the "fourth arithmetic circuit". Also, the duty command values Du1 and Du2 correspond to the "drive commands", and the current detection values I1 and I2 correspond to the "sensor data".

[0235] (Other embodiments) In the above embodiment, the example where the power supply system has 2 to 4 systems and the control system has 2 to 4 systems has been mainly described. In other embodiments, the number of power supply ICs, microcontrollers, arithmetic cores, pre-driver ICs, driver circuits, motor windings, etc. can be arbitrarily set according to the required redundancy, mounting space, etc. Also, the number of components that are easily broken (for example, microcontrollers and driver circuits) can be four, and the others can be three, etc., so that the number of components may be different.

[0236] In the above embodiment, the electronic component is mainly a driver component with a built-in pre-driver IC. In other embodiments, the electronic component only needs to be capable of digital communication with the microcomputer, and may be, for example, a pre-driver IC or a sensor provided separately from the driver circuit. Also, in the above embodiment, the electronic components of each system are described as being the same. In other embodiments, the electronic components of each system may have different outputs, accuracies, etc.

[0237] In the above embodiment, the duty command value, the current detection value, and the driver abnormality information are transmitted and received through the microcomputer-driver communication or the driver-driver communication. In other embodiments, as the information transmitted and received through the microcomputer-driver communication or the driver-driver communication, some of the duty command value, the current detection value, and the driver abnormality information may be omitted, or other information may be included. In the above embodiment, the duty command value is used as the drive command. In other embodiments, a value other than the duty command value may be used as the drive command. Also, in the above embodiment, the current detection value is shared as sensor data through the microcomputer-driver communication or the driver-driver communication. In other embodiments, the sensor data is not limited to the current detection value, and may be, for example, a rotation angle detection value or the like.

[0238] In the above embodiment, the control target of the ECU is the motor. In other embodiments, the control target may be an actuator other than the motor or other devices. In the above embodiment, the communication device is applied to the electric power steering device. In other embodiments, it may be applied to in-vehicle devices other than the electric power steering device, or may be applied to devices other than in-vehicle devices.

[0239] The present disclosure may also be the communication device according to any one of items 1 to 9, "The control unit has a plurality of the arithmetic circuits, and the communication line is assigned to each of the arithmetic circuits."; the communication device according to any one of items 1 to 10, "The inter-system connection line is provided with a system separation component (28, 281 to 283) capable of transmitting information while maintaining a potential difference."; the communication device according to any one of items 11 to 13, "The inter-system connection line connects the in-system communication line to the electronic component of another control system or between different electronic components of the control system, and the system separation component is built in the electronic component."; the communication device according to any one of items 11 to 14, "The inter-system connection line connects the in-system communication line to the electronic component of another control system, and in the electronic component, the communication port to which the inter-system connection line is connected is provided separately from the port to which the in-system communication line is connected."; the communication device according to any one of items 11 to 14, "The inter-system connection line connects between different electronic components of the control system, and the control unit can transmit a drive command to the electronic component of another system via the electronic component of its own system and can receive sensor data and abnormality information of the control system from the electronic component of another system."

[0240] The control unit and its method described in the present disclosure may be implemented by a dedicated computer provided by configuring a processor and a memory programmed to execute one or more functions embodied by a computer program. Alternatively, the control unit and its method described in the present disclosure may be implemented by a dedicated computer provided by configuring a processor with one or more dedicated hardware logic circuits. Or, the control unit and its method described in the present disclosure may be implemented by one or more dedicated computers configured by a combination of a processor and a memory programmed to execute one or more functions and a processor configured by one or more hardware logic circuits. Also, the computer program may be stored in a computer-readable non-transitory tangible recording medium as instructions executable by a computer. As described above, the present invention is not limited to the above embodiments and can be implemented in various forms without departing from the spirit of the invention.

Explanation of Signs

[0241] 10 ··· Drive device 11 ··· Motor (load) 15 ··· ECU (communication device) 21~24, 201, 202 ··· Microcomputer (control unit) 25, 251~253, 256~258 ··· Inter-system connection lines 211, 212, 231, 232 ··· Arithmetic cores (arithmetic circuits) 51~54 ··· Driver circuits 61~64 ··· Pre-driver ICs 701~707, 73, 801~804, 811, 812 ··· Driver components (electronic components)

Claims

1. A plurality of control units (21 to 24) each having at least one arithmetic circuit (211, 212, 231, 232); A plurality of electronic components (31, 33, 36, 38, 66 to 69, 701 to 707, 73, 801 to 804, 811, 812) provided in correspondence with the control unit and connected to the control unit so as to be capable of digital communication; Equipped with A combination of the control unit and the electronic component provided correspondingly is defined as a control system, and a communication line connecting the corresponding control unit and the electronic component is defined as an intra-system communication line. A communication device in which the intra-system communication lines of the different control systems, the intra-system communication lines and the electronic components of other control systems, or the electronic components of the different control systems are connected by inter-system connection lines (25, 251-253, 256-258).

2. The electronic component is a driver component (701-707, 73, 801-804, 811, 812) having a pre-driver IC (61-64) that transmits a drive signal to a driver circuit (51-54) related to driving a load (11), The arithmetic circuit digitally transmits a drive command for the driver circuit to the pre-driver IC, The communication device according to claim 1 , wherein the pre-driver IC transmits drive information including at least one of a current detection value, temperature information, and abnormality information to the arithmetic circuit.

3. The arithmetic circuit includes: Calculating and outputting the drive command for a part of the driver circuits, and acquiring the drive information from the pre-driver IC that has output the drive command; The communication device according to claim 2 , wherein the driving information is obtained from the pre-driver IC corresponding to the driver circuit that does not output the driving command by itself.

4. 4. The communication device according to claim 2, wherein the arithmetic circuit transmits the drive command at a timing when the arithmetic circuit of the other control system connected by the system-to-system connection line is not outputting the drive command.

5. The communication device according to claim 2 , wherein the plurality of driver parts hold detection values ​​at the same timing in response to a command from the control unit, and transmit the detection values ​​to the control unit in sequence.

6. The communication device according to claim 2 , wherein the plurality of arithmetic circuits alternately transmit the drive command to the pre-driver IC every calculation period.

7. 7. The communication device according to claim 6, wherein when an abnormality occurs in one of the plurality of arithmetic circuits that transmit the drive command to the same pre-driver IC, a normal arithmetic circuit takes over the transmission of the drive command.

8. The load is a motor having four sets of motor windings (121 to 124), wound around a stator adjacent to each other in the order of a first winding set (121), a second winding set (122), a third winding set (123), and a fourth winding set (124); a first driver circuit (51) provided corresponding to the first winding set and a third driver circuit (53) provided corresponding to the third winding set are driven by the drive commands of the same phase; 3. The communication device according to claim 2, wherein a second driver circuit (52) provided corresponding to the second winding set and a fourth driver circuit (54) provided corresponding to the fourth winding set are in phase and driven by the drive command of a different phase from that of the first driver circuit and the third driver circuit.

9. the intra-system communication line connecting a first pre-driver IC (61) provided corresponding to the first driver circuit and a first arithmetic circuit (211), and the intra-system communication line connecting a third pre-driver IC (63) provided corresponding to the third driver circuit and a third arithmetic circuit (231) are connected by a first inter-system connection line (25A); 9. The communication device according to claim 8, wherein the intra-system communication line connecting a second pre-driver IC (62) provided corresponding to the second driver circuit and a second arithmetic circuit (212), and the intra-system communication line connecting a fourth pre-driver IC (64) provided corresponding to the fourth driver circuit and a fourth arithmetic circuit (232) are connected by a second inter-system connection line (25B) different from the first inter-system connection line.

10. The communication device according to claim 1 , wherein the control unit includes a plurality of the arithmetic circuits, and the intra-system communication line is assigned to each of the arithmetic circuits.

11. 2. The communication device according to claim 1, wherein the inter-system connection lines connect the control systems via system separation components (28, 281 to 283) that enable information transmission while maintaining a potential difference.

12. The communication device according to claim 11 , wherein the system separation component is capable of receiving an enable signal from the control unit, and when the enable signal is in an enabling state, communication between the systems is permitted, and when the enable signal is in a disabling state, communication between the systems is prohibited.

13. The control unit is When the control unit of the other system is normal, the control unit communicates with the electronic component of the own system; The communication device according to claim 11 or 12, wherein, when the control unit of the other system is abnormal, the communication device communicates with the electronic component of its own system and the electronic component of the other system.

14. the inter-system connection line connects the intra-system communication line to the electronic components of the other control systems, or between the electronic components of different control systems; The communication device according to claim 11 or 12, wherein the system isolation component is built into the electronic component.

15. the inter-system connection line connects the intra-system communication line and the electronic components of the other control systems; 13. The communication device according to claim 11, wherein in the electronic component, a communication port to which the inter-system connection line is connected is provided separately from a port to which the intra-system communication line is connected.

16. the inter-system connection line connects the electronic components in different control systems, The communication device according to claim 11 or 12, wherein the control unit is capable of transmitting drive commands to the electronic components of the other system via the electronic components of its own system, and is capable of receiving sensor data and abnormality information of the control system from the electronic components of the other system.

17. The communication device according to claim 16 , wherein information on the own system and information on the other system are continuously updated between the electronic components.

18. The communication device according to claim 16 , wherein the electronic component communicates with the electronic component of another system in response to a command from the control unit of the own system.

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