Memory device and method for erasing and verifying the same

Abstract

To provide a memory device capable of increasing channel discharge time for avoiding false error verification and a method for erasing and verifying the same.SOLUTION: A memory device includes a plurality of memory blocks and a control circuit. The memory block selected from among the plurality of memory blocks includes an upper selection gate, a lower selection gate, a plurality of word lines, a common source line, and a P well. The control circuit executes an erasure and verification method, and the erasure and verification method includes: a step of erasing the selected memory block during an erasing stage; and a step of performing maintenance in a manner such that the lower selection gate is turned on during a maintenance period before the upper selection gate is turned on during a verifying stage.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present invention relates to a memory device and a method for erasing and verifying the same, and more particularly, to a memory device capable of increasing a channel discharge time to avoid false error verification and a method for erasing and verifying the same.

Background Art

[0002] Semiconductor memories are widely used in various electronic devices such as mobile phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, and non-mobile computing devices. Non-volatile memories enable information to be stored and retained. Examples of non-volatile memories include flash memories (e.g., NAND-type and NOR-type flash memories), and Electrically Erasable Programmable Read-Only Memory (EEPROM).

[0003] Recently, ultra-high density storage devices using a three-dimensional (3D) stacked memory structure, sometimes called a Bit Cost Scalable (BiCS) architecture, have been proposed. For example, a 3D NAND stacked flash memory device can be formed from an array of alternating conductive and dielectric layers. Memory holes are drilled in the layers to define a number of memory layers simultaneously. Then, NAND strings are formed by filling the memory holes with an appropriate material. Control gates of memory cells are provided by the conductive layers.

[0004] Each planar NAND memory consists of an array of memory cells connected by a plurality of word lines and bit lines. Data is programmed into, or read from, the planar NAND memory on a page-by-page basis, and erased from the planar NAND memory on a block-by-block basis, i.e., a block is the unit of a conventional erase operation, and a page is the unit of a conventional programming operation.

[0005] In the case of an existing three-dimensional (3D) NAND flash structure, a verification stage is required after the erase stage to verify whether the erase is successful or not. However, in 3D NAND flash, false errors may occur during the verification stage. SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION

[0006] Therefore, it is an object of the present invention to provide a memory device capable of increasing the channel discharge time to avoid false error verification, as well as an erase and verification method thereof. MEANS FOR SOLVING THE PROBLEMS

[0007] The present invention discloses a memory device. This memory device includes a plurality of memory blocks and a control circuit. A selected memory block among the plurality of memory blocks includes an upper select gate, a lower select gate, a plurality of word lines, a common source line, and a P well. The control circuit executes an erase and verification method, and this erase and verification method includes a step of erasing the selected memory block during an erase stage, and a step of maintaining the lower select gate to be turned on during a maintenance period before the upper select gate is turned on during a verification stage.

[0008] The present invention discloses an erasing and verifying method for a memory device, wherein a selected memory block among a plurality of memory blocks of the memory device includes an upper selection gate, a lower selection gate, a plurality of word lines, a common source line, and a P-well. The erasing and verifying method includes erasing the selected memory block during an erasing stage, and maintaining the lower selection gate to be turned on during a maintenance period before the upper selection gate is turned on during a verifying stage.

[0009] These and other objects of the present invention will become apparent to those skilled in the art upon reading the following detailed description of the preferred embodiments shown in the various figures and drawings.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5A

Figure 5B

Figure 6A

Figure 6B

Figure 7

Modes for Carrying Out the Invention

[0011] In the following detailed description, reference is made to the accompanying drawings, which illustrate specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, the specific features, structures, or characteristics described herein in connection with one embodiment may be implemented within other embodiments without departing from the spirit and scope of the invention. In addition, it is to be understood that the position or arrangement of the individual elements within each disclosed embodiment may be changed without departing from the spirit and scope of the invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the invention is defined only by the appended claims, appropriately construed in light of the full scope of equivalents to which the claims are entitled. In the drawings, the same numbers refer to the same or similar functions throughout the several views.

[0012] In the following description and in the claims, the terms "comprising" and "including" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to." Also, the term "coupled" is intended to mean either an indirect or a direct electrical connection. Thus, if one device is electrically coupled to another device, that connection may be by a direct electrical connection or by an indirect electrical connection through other devices and connections. "Approximately" means within an acceptable error range, which means that one of ordinary skill in the art can solve the technical problem within a certain error range and basically achieve the technical effect.

[0013] FIG. 1 is a top view showing a NAND string according to an embodiment of the present invention. FIG. 2 is a diagram showing an equivalent circuit thereof. In a flash memory system using a NAND structure, a plurality of transistors are arranged in series and sandwiched between two select gates, and these are called a NAND string. The NAND string shown in FIGS. 1 and 2 includes four transistors 101 to 104 connected in series and sandwiched between an upper select gate SG_T and a lower select gate SG_B (source side), and a substrate Sub, and the substrate Sub includes a P well. The upper select gate SG_T is arranged to connect the NAND string to a bit line via a bit line contact and can be controlled by applying an appropriate voltage to the select gate line SGTL. The lower select gate SG_B is arranged to connect the NAND string to a common source line CSL and can be controlled by applying an appropriate voltage to the select gate line SGBL. The common source line CSL penetrates the stacked structure. Each of the transistors 101 to 104 includes a control gate and a floating gate. For example, transistor 101 includes a control gate CG1 and a floating gate FG1, transistor 102 includes a control gate CG2 and a floating gate FG2, transistor 103 includes a control gate CG3 and a floating gate FG3, and transistor 104 includes a control gate CG4 and a floating gate FG4. The control gate CG1 is connected to the word line WL1, the control gate CG2 is connected to the word line WL2, the control gate CG3 is connected to the word line WL3, and the control gate CG4 is connected to the word line WL4.

[0014] For the sake of explanation, FIGS. 1 and 2 show four memory cells in the NAND string. In other embodiments, the NAND string may include eight memory cells, sixteen memory cells, thirty-two memory cells, sixty-four memory cells, one hundred and twenty-eight memory cells, and the like. However, the number of memory cells in the NAND string does not limit the scope of the present invention.

[0015] A general architecture of a flash memory system using a NAND structure includes several NAND strings. Each NAND string is connected to a common source line CSL by its lower select gate SG_B controlled by a select line SGBL, and is connected to its associated bit line by its upper select gate SG_T controlled by a select line SGTL. Each bit line and each (one or more) NAND string connected to that bit line via a bit line contact includes a column of an array of memory cells. The bit lines are shared among multiple NAND strings. Generally, the bit lines pass above the NAND strings in a direction orthogonal to the word lines and are connected to one or more sense amplifiers.

[0016] FIG. 3 is a diagram showing an exemplary structure of a memory device 30 according to an embodiment of the present invention. The memory device 30 includes a memory array 302 and a control circuit 304. The control circuit 304 is utilized to perform read, write, erase, and verify operations on the memory array 302 and may include a word line driver, a bit line driver, a column decoder, a sensing circuit, a data buffer, program verification logic, and an erase verification circuit. The memory array 302 is divided into a plurality of memory blocks of memory cells indicated by BLOCK1 to BLOCK I where I is a positive integer and is generally equal to a large number. The blocks include a set of NAND strings accessed via a common set of bit lines BL1 to BL M and word lines WL1 to WL N . However, M and N are integers greater than 1. One terminal of the NAND string is connected to the corresponding bit line via an upper select gate (connected to a select gate line SGTL), and the other terminal is connected to the common source line CSL via a lower select gate (connected to a select gate line SGBL). Each block is generally divided into several pages indicated by dotted lines. In one embodiment, the block is the unit of a conventional erase operation and the page is the unit of a conventional programming operation. However, other units of erase / program may also be used.

[0017] When the control circuit 304 performs an erase operation in units of blocks, in order to avoid data remanence or metastability, which causes the shortening of the life of the 3D NAND flash memory, a corresponding verification operation must be performed to ensure that the corresponding memory cells are erased.

[0018] More specifically, in the verification stage, the corresponding memory cells are conducted in order to examine whether the corresponding memory cells are "strong" logic 1 or "weak" logic 1 by measuring the threshold voltage of the corresponding memory cells. If the corresponding memory cells are not "strong" enough, or if the threshold voltage of the corresponding memory cells does not meet a predetermined threshold, the bit cell may change from logic 1 to logic 0 during aging, and the reliability of the 3D NAND flash decreases. Therefore, after the erase stage, it is necessary to examine the bit cell to determine whether the threshold voltage of the corresponding memory cell meets a predetermined threshold. However, false errors may occur in the verification stage.

[0019] Specifically, refer to FIG. 4, which is a timing chart of a conventional erase and verification process. However, T1 is when the verification stage starts, T2 is when the voltage of the upper selection gate SG_T begins to reach the turn-on voltage Von, and T3 is when the verification stage ends. As shown in FIG. 4, memory blocks BLOCK1 to BLOCK IWhen a selected memory block among them is selected to be erased, taking one NAND string as an example, the upper select gate SG_T, the lower select gate SG_B, and the common source line CSL are in a floating state, the word line is grounded, and the P-well is supplied with an erase voltage Ve in the erase stage (i.e., the voltage of the P-well rises, is maintained as the erase voltage Ve for a certain time period, and then drops to zero). Therefore, the electrons trapped in the floating gate of the corresponding memory cell are attracted by the high erase voltage Ve of the P-well, leave the floating gate, and the corresponding memory cell comes to be erased.

[0020] Next, in the verification stage, the word line is supplied with a verification voltage Vv (e.g., 2.2V), then the upper select gate SG_T and the lower select gate SG_B are supplied with a turn-on voltage Von, and finally the word line is supplied with the verification voltage Vv again to check whether the threshold voltage of the corresponding memory cell satisfies a predetermined threshold. If the threshold voltage of the corresponding memory cell does not satisfy the predetermined threshold, i.e., the verification during the verification stage fails, another erase stage and another verification stage are performed until the threshold voltage of the corresponding memory cell satisfies the predetermined threshold, or if the verification stage in which the verification fails is performed a predetermined number of times, an error message is generated.

[0021] However, since the upper selection gate SG_T and the lower selection gate SG_B are in a floating state during the erasure stage, when the voltage of the P-well drops to zero, the voltages of the upper selection gate SG_T and the lower selection gate SG_B drop accordingly, and then reach the turn-on voltage Von, and (as shown by the dotted line in FIG. 5B) the lower selection gate SG_B is turned off, thus the channel stops discharging and enters a floating state. Next, when the voltage of the word line rises to the verification voltage Vv during the verification stage (between T1 and T2), the potential of the channel is coupled with the voltage of the word line and remains at a higher potential. Thereafter, when the upper selection gate SG_T and the lower selection gate SG_B are turned on during the verification stage (after T2), the channel is connected to the P-well, and thus is grounded, and the potential of the channel drops rapidly, and accordingly the voltage of the word line is coupled and drops. As a result, a false error occurs in the first verification stage, which requires another erasure stage and another verification stage, and thus the corresponding memory cell is over-erased at a lower threshold voltage than required.

[0022] For example, if the corresponding memory cell is erased to a strong logic 1 but is determined to be a weak logic 1, another erasure stage is required to ensure that the erasure is successful. However, since the corresponding memory cell is logically strong enough, erasing the corresponding memory cell having a strong logic 1 is a redundant step. As a result, more false errors occur during a longer period of the erasure stage and the verification stage, reducing the reliability and programming performance of the memory device 30.

[0023] In comparison, in the erasure and verification processes of the present invention, for memory blocks BLOCK1 to BLOCK IWhen a selected memory block among them is selected to be erased, the control circuit 304 maintains the lower selection gate SG_B to be turned on during the maintenance period before the upper selection gate SG_T is turned on during the verification stage. As a result, by maintaining the lower selection gate SG_B to be turned on during the maintenance period before the upper selection gate SG_T is turned on during the verification stage, the present invention increases the channel discharge time to avoid the voltage drop of the word line and subsequent false error verification.

[0024] More specifically, refer to FIGS. 5A and 5B. FIG. 5A is a timing chart of an erase and verification process according to an embodiment of the present invention, and FIG. 5B is a schematic diagram of the channel potential of a conventional erase and verification process and an erase and verification process according to an embodiment of the present invention. As can be seen from FIG. 5A, when a selected memory block among memory blocks BLOCK1 to BLOCK I is selected to be erased, taking one NAND string as an example, the lower selection gate SG_B is switched from the floating state so as to be maintained at the turn-on voltage Von (for example, 6.5V) during the maintenance period Pm before the upper selection gate SG_T changes. However, the maintenance period Pm is from when the voltage of the lower selection gate SG_B drops to the turn-on voltage Von as the voltage of the P-well drops until the upper selection gate SG_T is turned on during the verification stage.

[0025] Under such circumstances, the common source line CSL and the channel can be connected during the maintenance period Pm. Therefore, compared with the conventional erasing and verifying processes, which have problems of higher channel potential due to word line coupling and voltage drop of the word line due to channel discharge coupling in the above description, the channel maintains a discharged state to zero potential at the initial verification stage (after T1), as shown by the solid line in FIG. 5B of the present invention, thereby increasing the channel discharge time and avoiding the voltage drop of the word line as shown in FIG. 5A. Other operations of the erasing and verifying processes can be derived by referring to the above description of the conventional erasing and verifying processes. For example, the lower selection gate is in a floating state during the erasing stage except for the maintenance period Pm and will not be described below for simplicity. As a result, the present invention increases the channel discharge time to avoid subsequent false error verification and improves the efficiency of the erasing and verifying processes.

[0026] In particular, the gist of the present invention is to maintain the lower selection gate SG_B being turned on during the maintenance period before the upper selection gate SG_T is turned on during the verification stage in order to increase the channel discharge time to avoid the voltage drop of the word line due to channel discharge coupling. Those skilled in the art can make changes or modifications, which still fall within the scope of the present invention. For example, the maintenance period during which the lower selection gate SG_B is turned on is not limited to the maintenance period Pm shown in FIG. 5A, and can be other time intervals as long as there is a maintenance period before the upper selection gate SG_T is turned on during the verification stage.

[0027] For example, refer to FIGS. 6A and 6B which are timing charts of an erasure and verification process according to another embodiment of the present invention. As shown in FIG. 6A, the hold period Pm' is within the verification stage, that is, from near the midpoint between T1 and T2 until the upper select gate SG_T is turned on. Under such circumstances, as shown by the dotted line in FIG. 5B for a conventional erasure and verification process, the channel potential can become higher due to word line coupling, but the channel is still discharged and can reach zero potential rapidly even starting from the midpoint between T1 and T2 (refer to the solid line in FIG. 5B, the channel can be rapidly discharged). As a result, even when the hold period Pm' is shorter than the hold period Pm, the embodiment of FIG. 6A can also increase the channel discharge time to avoid the voltage drop of the word line due to channel discharge coupling.

[0028] On the other hand, as shown in FIG. 6B, the hold period Pm'' is from the start of the erasure stage until the upper select gate SG_T is turned on. Under such circumstances, the channel is made conductive to release electrons as fast as possible.

[0029] In particular, the default value of the 3D NAND flash is logic 1 in the above embodiment. However, in other embodiments, the default value of the 3D NAND flash may be logic 0, and the erasure operation is to change the memory cell from 1 to 0. In one embodiment, a high voltage (e.g., 1.1 volts) represents logic 1, and in one embodiment, logic 1 may be represented by, but not limited to, a low voltage (e.g., 0 volts). Further, the predefined threshold between a strong logic 1 and logic 0 may vary between process techniques. For example, the threshold may be 0.7 volts in 22nm ultra-low power (22ULP) technology. Those skilled in the art may make appropriate changes or modifications, which are not limited in this specification.

[0030] Furthermore, the present invention avoids false error verification. However, if the threshold voltage of the corresponding memory cell does not meet a predetermined threshold, that is, if the verification during the verification stage fails, another erase stage and another verification stage are performed until the threshold voltage of the corresponding memory cell meets the predetermined threshold, or if the verification stage in which the verification fails is performed a predetermined number of times, an error message is generated. The criteria for determining the failure of the erase and verification processes are not limited, but may be based on a threshold time, a threshold number, or a combination thereof for performing the erase and verification processes on 3D NAND flash. In addition, the threshold time or the threshold number may be determined in advance or fixed by calibration, may be a number mapped in a table, or may be adjusted appropriately according to the actual scenario. Those skilled in the art may make changes to the determination rules and corresponding modifications, which are not limited in this specification.

[0031] In addition, the erase and verification processes may be changed such that the verification stage sequentially follows a plurality of erase stages. For example, the 3D NAND flash erase and verification process may include a first erase stage, a second erase stage, and a verification stage. In one embodiment, in order to increase the channel discharge time and thus avoid the voltage drop of the word line caused by channel discharge coupling, each of the erase and verification processes should include a holding period during which the lower select gate SG_B is turned on.

[0032] In particular, the embodiments described above are used to explain the concept of the present invention. Those skilled in the art may make appropriate changes and modifications, which are not limited in this specification. Therefore, as long as the lower select gate SG_B is turned on before the upper select gate SG_T is turned on during the verification stage, the requirements of this application are met and it is within the scope of this application.

[0033] FIG. 7 is a schematic diagram of an erasure and verification process 70 according to an embodiment of the present invention. As shown in FIG. 7, the 3D NAND flash erasure and verification process 70 includes the following steps. Step 700: Start. Step 702: Erase the selected memory block during the erasure stage. Step 704: Maintain the lower select gate SG_B turned on during the hold period before the upper select gate SG_T is turned on during the verification stage. Step 706: End.

[0034] The detailed operation of the erasure and verification process 70 can be derived by referring to the above description and will not be described below for the sake of brevity.

[0035] In summary, by maintaining the lower select gate SG_B turned on during the hold period before the upper select gate SG_T is turned on during the verification stage, the present invention increases the channel discharge time to avoid voltage drop of the word line and false error verification caused by channel discharge coupling.

[0036] Those skilled in the art will readily notice that numerous changes and modifications can be made to the devices and methods while maintaining the teachings of the present invention. Therefore, the above disclosure should be construed as being limited only by the boundaries and limitations of the appended claims.

Description of the Reference Numerals

[0037] 30 Memory device 101 Transistor 102 Transistor 103 Transistor 104 Transistor 302 Memory array 304 Control circuit

Claims

1. 1. A memory device comprising: a plurality of memory blocks, a selected memory block of the plurality of memory blocks comprising an upper select gate, a lower select gate, a plurality of word lines, a common source line, and a P-well; 1. A control circuit configured to perform an erase and verify method, the erase and verify method comprising: erasing the selected memory block during an erase phase; maintaining the lower select gate turned on for a sustain period before the upper select gate is turned on during a verify phase; A control circuit including: A memory device comprising:

2. The memory device of claim 1 , wherein the voltage of the bottom select gate is maintained at a turn-on voltage during the sustain period.

3. 2. The memory device of claim 1, wherein the sustain period is from when the voltage of the lower select gate drops to a turn-on voltage as the voltage of the P-well drops to when the upper select gate is turned on during the verify phase.

4. The memory device of claim 1 , wherein the maintenance period is within the verify phase.

5. The memory device of claim 1 , wherein the sustain period is from the beginning of the erase phase until the top select gate is turned on.

6. 2. The memory device of claim 1, wherein the P-well is supplied with an erase voltage during the erase phase, the upper select gate is floating, and the lower select gate is floating during the erase phase except during the sustain period.

7. 10. The memory device of claim 1, wherein the plurality of word lines are supplied with a verify voltage and then the top select gate and the bottom select gate are supplied with a turn-on voltage during the verify phase.

8. The memory device of claim 1 , wherein if verification during the verify phase is unsuccessful, another erase phase and another verify phase are performed.

9. 10. The memory device of claim 8, wherein an error message is generated if a predetermined number of verification steps result in a failed verification.

10. 1. An erase and verify method for a memory device, wherein a selected memory block of a plurality of memory blocks of the memory device comprises an upper select gate, a lower select gate, a plurality of word lines, a common source line, and a P-well, the erase and verify method comprising: erasing the selected memory block during an erase phase; maintaining the lower select gate turned on for a sustain period before the upper select gate is turned on during a verify phase; 2. An erasure and verification method, comprising:

11. maintaining the voltage of the lower select gate at a turn-on voltage during the sustain period.

11. The erase and verify method of claim 10, further comprising:

12. 11. The erase and verify method of claim 10, wherein the sustain period is from when the voltage of the lower select gate drops to a turn-on voltage as the voltage of the P-well drops until the upper select gate is turned on during the verify phase.

13. 11. The erase and verify method of claim 10, wherein the sustain period is within the verify phase.

14. 11. The erase and verify method of claim 10, wherein the sustain period is from the beginning of the erase phase until the top select gate is turned on.

15. providing an erase voltage to the P-well during the erase phase and floating the upper select gate; floating the lower select gate during the erase phase except for the sustain period; 11. The erase and verify method of claim 10, further comprising:

16. applying a verify voltage to the plurality of word lines and then applying a turn-on voltage to the upper select gate and the lower select gate during the verify phase.

11. The erase and verify method of claim 10, further comprising:

17. if verification during said verification step is unsuccessful, performing another erase step and another verification step.

11. The erase and verify method of claim 10, further comprising:

18. generating an error message if a verification step has been performed a predetermined number of times that verification has failed.

20. The erase and verify method of claim 17, further comprising:

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