System and method for increasing power during low frequency cycles using binning

Abstract

To provide a method and a controller for achieving uniformity in etch rate.SOLUTION: A method includes receiving a voltage signal from an output of a matching portion and determining a positive crossing point 122 and a negative crossing point 124a of the voltage signal for each cycle of the voltage signal. The negative crossing point of each cycle is contiguous with the positive crossing point of the cycle. The method also includes dividing a time interval of each cycle of the voltage signal into a number of bins and adjusting a frequency of a radio frequency generator to achieve uniformity in the etch rate for one or more of the number of bins associated with the positive crossing point or one or more of the number of bins associated with the negative crossing point.SELECTED DRAWING: Figure 1B-1

Description

Technical Field

[0001] This embodiment relates to a system and method for increasing power during a low-frequency cycle using binning.

Background Art

[0002] A plasma tool includes a radio frequency generator (RFG), an impedance matching network, and a plasma chamber. The RFG generates power that is provided to the plasma chamber via the impedance matching network. When power is being provided, a process gas is supplied to the plasma chamber to process a wafer placed within the plasma chamber. When the process gas is supplied, plasma is generated within the plasma chamber. The wafer is etched by the generated plasma.

[0003] The embodiments described in this disclosure arise in this context.

[0004] The description of the background provided herein is for the purpose of generally presenting the content of this disclosure. The research by the inventors named at the present time within the scope described in this background art section, as well as aspects of the description that cannot be separately regarded as prior art at the time of filing, are not recognized as prior art against this disclosure, whether explicitly or implicitly.

Summary of the Invention

[0005] Embodiments of this disclosure provide a system, apparatus, method, and computer program for increasing power during a low-frequency cycle using binning. It should be understood that these embodiments can be implemented by various means, such as a process, apparatus, system, device, or method on a computer-readable medium. Some embodiments are described below.

[0006] A low frequency (LF) radio frequency (RF) generator and a high frequency (HF) RF generator are used to process a substrate. The LF RF generator and the HF RF generator generate RF signals that are used to generate plasma and a plasma sheath within a plasma chamber. The voltage of the plasma sheath periodically repeats between a low level and a high level. During a period when the plasma sheath is at a low level, the amount of influence of the first voltage of the plasma sheath generated based on the HF RF generator on the second voltage of the plasma sheath generated based on the LF RF generator becomes greater. This influence is greater than the amount of influence of the first voltage on the second voltage during a period when the plasma sheath is at a high level. As this influence increases, it becomes difficult to control the uniformity when processing the substrate. The systems and methods described herein facilitate achieving uniformity during a period when there is an increase in the amount of influence.

[0007] Some advantages of the systems and methods described herein include achieving a level of uniformity in substrate processing, such as an etching rate or a deposition rate of the substrate. The level of uniformity is achieved by dividing a portion of the positive cycle of the voltage measured at the output of the impedance matching circuit into a predetermined number of bins. For example, a portion of the cycle between the positive intersection and the negative intersection of the cycle is divided into a predetermined number of bins. For each bin, the frequency of the HF RF generator is controlled to control the power transmitted by the HF RF generator. For example, the frequency of the HF RF generator is increased or decreased to increase the transmitted power. By controlling the frequency for a predetermined number of bins, the HF RF generator can be controlled in detail to achieve a level of uniformity.

[0008] In one embodiment, a method for achieving uniformity in etching rate is described. This method includes receiving a voltage signal from the output of a matching unit, and determining the positive and negative intersections of the voltage signal for each cycle of the voltage signal. The negative intersection of each cycle is consecutive with the positive intersection of the cycle. This method further includes dividing the time interval of each cycle of the voltage signal into a plurality of bins. For one or more of the plurality of bins associated with the positive intersection, or for one or more of the plurality of bins associated with the negative intersection, this method includes adjusting the frequency of a radio frequency generator to achieve uniformity in etching rate.

[0009] In one embodiment, a method for achieving uniformity in etching rate is described. This method includes receiving a voltage signal from the output of a matching unit, and determining the positive and negative intersections of the voltage signal for each cycle of the voltage signal. The negative intersection of each cycle is consecutive with the positive intersection of the cycle. This method further includes dividing the time interval of each cycle of the voltage signal, starting from the time close to the positive intersection and ending at the time close to the negative intersection, into a plurality of bins. For one or more of the plurality of bins, this method includes adjusting the frequency of a radio frequency generator to achieve uniformity in etching rate.

[0010] In one embodiment, a controller for achieving uniformity in etching rate is described. The controller includes a processor that receives a voltage signal from the output of a matching unit. The processor determines the positive and negative intersections of the voltage signal for each cycle of the voltage signal. The negative intersection of each cycle is consecutive with the positive intersection of the cycle. The processor divides the time interval of each cycle of the voltage signal, starting from the time close to the positive intersection and ending at the time close to the negative intersection, into a plurality of bins. For one or more of the plurality of bins, the processor adjusts the frequency of a radio frequency generator to achieve uniformity in etching rate. The controller includes a memory device coupled to the processor.

[0011] Other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings.

Brief Description of the Drawings

[0012] Embodiments can be best understood by reference to the following description taken in conjunction with the accompanying drawings.

[0013]

Figure 1A

[0014]

Figure 1B-1

[0015]

Figure 1B-2

[0016]

Figure 1C

[0017]

Figure 1D-1

[0018]

Figure 1D-2

[0019]

Figure 2

[0020]

Figure 3A

[0021]

Figure 3B

[0022]

Figure 3C

[0023]

Figure 4

[0024]

Figure 5

[0025]

Figure 6A

[0026]

Figure 6B

DETAILED DESCRIPTION OF THE INVENTION

[0027] In the following embodiments, a system and method for increasing power during a low frequency cycle using binning will be described. It will be apparent that these embodiments can be implemented without some or all of these specific details. In other instances, well-known operations are not described in detail so as not to unnecessarily obscure these embodiments.

[0028] Figure 1A is an embodiment of graph 100, showing the voltage (V) of the plasma sheath versus time t. This plasma sheath is the lower plasma sheath, which is formed near the power supply electrode that is the lower electrode, compared to the upper plasma sheath. The upper plasma sheath is formed near the upper electrode, compared to the lower plasma sheath. In graph 100, the voltage of the plasma sheath is plotted on the Y-axis and time t is plotted on the X-axis. Graph 100 includes a plot 102 of the first part of the voltage of the plasma sheath, and the first part is created as a result of a radio frequency (RF) signal generated by a low frequency (LF) RF generator. An example of the LF RF generator is provided below. Plot 102 is shown using a solid line. Graph 100 further includes a plot 104 of the second part of the voltage of the plasma sheath, and the second part is created based on an RF signal generated by a high frequency (HF) RF generator. An example of the HF RF generator is provided below. Plot 104 is shown using a dotted line.

[0029] As shown in Figure 1A, in plot 102, a low voltage level V1 and a high voltage level V2 are periodically repeated. An example of the low voltage level V1 is a low voltage point such as a low voltage amplitude, and an example of the high voltage level V2 is a high voltage point such as a high voltage amplitude. Plot 102 remains at a level approximately at the low voltage level V1 from time t0 to time t1, transitions from the level at time t1, reaches the high voltage level V2 between time t1 and time t2, and transitions from the high voltage level V2 to reach a level approximately at the low voltage level V1 at time t2. Also, plot 102 is at a level approximately at the low voltage level V1 from approximately time t2 to time t3, transitions from the level at time t3, reaches the high voltage level V2 between time t3 and time t4, and reaches a level approximately at the low voltage level V1 at approximately time t4. An example of the level approximately at the low voltage level V1 is a level within a predetermined range such as within ±10% from the low voltage level V1.

[0030] Note that between time t1 and time t2, plot 102 is either transitioning between the low voltage level V1 and the high voltage level V2 or is at the high voltage level V2. Due to the high voltage level V2, the plasma sheath becomes thicker, and the effect of the second part (plot 104) of the plasma sheath voltage on the first part (plot 102) of the plasma sheath voltage becomes smaller. When the second part of the voltage affects the first part during the period from time t1 to time t2, the plasma sheath voltage reaches the highest voltage point such as the highest voltage amplitude. The highest voltage point is the highest among the total voltage amplitudes of the plasma sheath during the period from time t1 to time t3. Since the effect becomes smaller, generally, a level of uniformity in the etching rate across the entire surface of the substrate is achieved. Also, the control of the impedance matching network is sufficient between time t1 and time t2 to minimize the power reflected from the plasma chamber through the impedance matching network towards the LF and HF RF generators. However, between time t2 and time t3, a level approximately at the low voltage level V1 is maintained. Between time t2 and time t3, due to the low voltage level V1, the plasma sheath becomes thinner, and the effect of the second part (plot 104) of the plasma sheath voltage on the first part (plot 102) of the plasma sheath voltage becomes larger. When the second part of the voltage affects the first part during the period from time t2 to time t3, the plasma sheath voltage reaches the lowest voltage point such as the lowest voltage amplitude. The lowest voltage point is the lowest among the total voltage amplitudes of the plasma sheath during the period from time t1 to time t3. As a result of the larger effect, the uniformity in the etching rate decreases. For example, the RF signal output from the HF RF generator causes harmonics in the plasma chamber, and the harmonics cause standing waves. The standing waves decrease the uniformity in the etching rate.

[0031] FIG. 1B-1 is an embodiment of a graph 110 showing a voltage 112 applied to a radio frequency (RF) rod of an RF transmission line to achieve the voltage shown in FIG. 1A in a plasma sheath. FIG. 1B-2 is a continuation of graph 110. In graph 110, the voltage 112 measured by a sensor coupled to the output of an impedance matching circuit (IMC) described with respect to FIG. 2 is plotted. The voltage 112 is plotted against the time t shown in FIG. 1A. The voltage 112 is plotted on the Y-axis and the time t is plotted on the X-axis. The voltage 112 is a voltage signal that is repeated over a plurality of cycles such as cycle 1 and cycle 2. Cycle 2 is continuous with cycle 1. As an example, the voltage signal of graph 110 is a sine wave signal.

[0032] The voltage 112 has a direct current (DC) offset 114 or the DC offset 114 is applied. The DC offset 114 is applied by an impedance matching circuit and a blocking capacitor (not shown) of the plasma system described herein.

[0033] The voltage 112 has an orthogonal point for each cycle of the voltage 112 and a negative intersection point for each cycle of the voltage 112. For example, the voltage 112 has an orthogonal point 122 during cycle 1 and a negative intersection point 124a during cycle 1. The negative intersection point 124a indicates the start of cycle 1. The orthogonal point of each cycle of the voltage 112 is continuous with the negative intersection point of the cycle. For example, there are no other intersection points between the orthogonal point 122 and the negative intersection point 124a of cycle 1. The orthogonal point and the negative intersection point are further described below.

[0034] The negative intersection point of the cycle is at the start of the cycle and at the edge of the cycle. For example, cycle 1 has a negative intersection point 124a indicating the start of cycle 1 and another negative intersection point 124b indicating the end of cycle 1. The other negative intersection point 124b that is continuous with the orthogonal point 122 of cycle 1 belongs to cycle 1 of the voltage 112. The other negative intersection point 124b is at the edge of cycle 1. Also, the negative intersection point 124b at the end of cycle 1 belongs to cycle 2.

[0035] Each cycle of voltage 112 is divided into a plurality of bins, such as segments or intervals or divided time intervals, etc., by a processor described below with reference to FIG. 2. For example, the first half 112A of the period of cycle 1 is divided into bins 1m, 2m, etc. up to bin Mm, where M is an integer and m is a variable indicating the first half of each cycle of voltage 112. Also, the second half 112B of the period of cycle 1 is divided into bins 1n, 2n, etc. up to bin Nn, where N is an integer and n is a variable indicating the second half of each cycle of voltage 112. As another example, referring to FIG. 1B-2, the first half of the period of cycle 2 is divided into bins 1m, 2m, etc. up to bin Mm. Also, the second half of the period of cycle 2 is divided into bins 1n, 2n, etc. up to bin Nn.

[0036] Each bin of cycle 1 has the same period or time interval. For example, bin 1m of cycle 1 extends from time tNn at the end of cycle 0 to time t1m of cycle 1, and bin 2m of cycle 1 extends from time t1m of cycle 1 to time t2m of cycle 1, and bin Mm of cycle 1 extends from time t(M-1)m to time tMm of cycle 1. Cycle 1 is continuous with cycle 0 of voltage 112. The time interval between time Nn of cycle 0 and time t1m of cycle 1 is equal to the time interval between time t1m of cycle 1 and time t2m of cycle 1, and is equal to the time interval between time t(M-1)m of cycle 1 and time tMm of cycle 1. Similarly, bin 1n of cycle 1 extends from time tMm of cycle 1 to time t1n of cycle 1, and bin 2n of cycle 1 extends from time t1n of cycle 1 to time t2n of cycle 1, and bin Nn extends from time t(N-1)n of cycle 1 to time tNn, which is the end of the cycle and the start time of cycle 2. The time interval between time tMm of cycle 1 and time t1n of cycle 1 is equal to the time interval between time t1n of cycle 1 and time t2n of cycle 1, and is equal to the time interval between time t(N-1)n of cycle 1 and time tNn, which is the end of cycle 1 and the start time of cycle 2.

[0037] Similarly, each bin of each remaining cycle, such as cycle 2 of voltage 112, has the same period or time interval. For example, bin 1m of cycle 2 extends from time tNn of cycle 2 to time t1m of cycle 2, and bin 2m of cycle 2 extends from time t1m of cycle 2 to time t2m of cycle 2, and bin Mm of cycle 2 extends from time t(M - 1)m of cycle 2 to time tMm of cycle 2. Similarly, bin 1n of cycle 2 extends from time tMm of cycle 2 to time t1n of cycle 2, and bin 2n of cycle 2 extends from time t1n of cycle 2 to time t2n of cycle 2, and bin Mm extends from time t(N - 1)n of cycle 2 to time tNn, which is the end of cycle 2 and the start time of cycle 3 of voltage 112. Cycle 3 is continuous with cycle 2 of voltage 112.

[0038] As shown by plot 102 and voltage 112 of FIGS. 1A, 1B-1, and 1B-2, during the period between time t1 and time t2 when voltage 112 is high, for example, significantly negative, the voltage of the plasma sheath increases. Also, during the period between time t2 and time t3 when voltage 112 is low, for example, the positive potential is small or not significantly negative, the voltage of the plasma sheath decreases. As an example, a large amount of voltage 112 is more negative compared to a small amount of voltage 112. To explain, a large amount of voltage 112 has a negative amplitude larger than the amplitude of a small amount of voltage 112. More specifically, a large amount of voltage 112 has no positive potential, and a small amount of voltage 112 has a positive potential. The low voltage 112 corresponds to P 正 corresponding. The relatively positive amount of power during the period between time t2 and time t3 is more positive compared to the amount of power based on voltage 112 between time t1 and time t2. The amount of power between time t1 and time t2 is relatively negative compared to the amount of power between time t2 and time t3. The relatively negative amount of power between time t1 and time t2 is shown as P 負 as shown.

[0039] Also, the voltage 112 between time t1 and time t2 corresponds to the high voltage duty cycle (HVDC) of the voltage 112, and the voltage 112 between time t2 and time t3 corresponds to the low voltage duty cycle (LVDC) of the voltage 112. The high voltage is more negative compared to the low voltage.

[0040] As further shown by the plots 102 and the voltage 112 in FIGS. 1A, 1B-1, and 1B-2, the second half of each cycle of the voltage 112 coincides with the period during which the voltage of the plasma sheath is lower compared to the voltage of the plasma sheath during the first half of the cycle, and the first half of each cycle of the voltage 112 coincides with the period during which the voltage of the plasma sheath is higher compared to the voltage of the plasma sheath during the second half of the cycle. For example, the second half 112B coincides with the period between time t2 and time t3 during which the voltage of the plasma sheath is lower compared to the voltage of the plasma sheath during the first half 112A, and the first half 112A coincides with the period between time t1 and time t2 during which the voltage of the plasma sheath is higher compared to the voltage of the plasma sheath during the second half 112B. More specifically, the period between time t1 and time t2 of the plot 102 is included within the period during which the first half 112A of cycle 1 of the voltage 112 occurs, and most of the period between time t2 and time t3 of the plot 102 is included within the period during which the second half 112B of cycle 1 of the voltage 112 occurs.

[0041] During the first half of cycle 1 in each bin of 112A, the processor determines the operating frequency of the HF RF generator to control the amount of power sent by the output of the HF RF generator. For example, during the time interval of bin 1m in cycle 1, the processor determines the operating frequency of the HF RF generator at which the amount of power sent by the output of the HF RF generator is increased, decreased, or maintained to achieve a predetermined level of uniformity. The amount of power sent is increased, decreased, or maintained compared to the amount of power sent by the output of the HF RF generator during bin 1m of the previous cycle, such as cycle 0 of voltage 112. As another example, during the time interval of bin 2m in cycle 1, the processor determines the operating frequency of the HF RF generator at which the amount of power sent by the output of the HF RF generator is increased, decreased, or maintained to achieve a predetermined level of uniformity. The amount of power sent is increased, decreased, or maintained compared to the amount of power sent by the output of the HF RF generator during bin 2m of the previous cycle, such as cycle 0 of voltage 112.

[0042] During cycle 2 of voltage 112, the processor applies the operating frequency previously determined during the first half of cycle 1 of voltage 112. For example, the processor increases or decreases the operating frequency of the HF RF generator during bin 1m of cycle 2 to achieve the frequency previously determined during bin 1m of cycle 1. As another example, the processor increases or decreases the operating frequency of the HF RF generator during bin 2m of cycle 2 to achieve the frequency previously determined during bin 2m of cycle 1.

[0043] Similarly, in each bin of the second half 112B of Cycle 1, the processor determines the operating frequency of the HF RF generator so as to control the amount of power transmitted by the output of the HF RF generator. For example, during the time interval of bin 1n of Cycle 1, the processor determines the operating frequency of the HF RF generator at which the amount of power transmitted by the output of the HF RF generator increases, decreases, or remains the same. The amount of power transmitted increases, decreases, or is maintained compared to the amount of power transmitted by the output of the HF RF generator during bin 1n of the previous cycle, such as Cycle 0 of voltage 112. As another example, during the time interval of bin 2n of Cycle 1, the processor determines the operating frequency of the HF RF generator at which the amount of power transmitted by the output of the HF RF generator increases, decreases, or remains in the same state. The amount of power transmitted increases, decreases, or is maintained compared to the amount of power transmitted by the output of the HF RF generator during bin 2n of the previous cycle, such as Cycle 0 of voltage 112.

[0044] During Cycle 2 of voltage 112, the processor applies the operating frequency previously determined during the second half 112B of Cycle 1 of voltage 112. For example, the processor increases or decreases the operating frequency of the HF RF generator during bin 1n of Cycle 2 so as to achieve the frequency previously determined during bin 1n of Cycle 1. As another example, the processor increases or decreases the operating frequency of the HF RF generator during bin 2n of Cycle 2 so as to achieve the frequency previously determined during bin 2n of Cycle 1.

[0045] Note that it is beneficial to control the operating frequency during the second half of Cycle 2 compared to the first half of Cycle 2. This is because the low voltage of the plasma sheath between time t2 and time t3 causes a decrease in the uniformity of the etching rate. By controlling the operating frequency during the second half of Cycle 2, the transmitted power at the output of the HF RF generator increases and the uniformity improves.

[0046] In one embodiment, the first half 112A of the period of cycle 1 is divided into a different number of bins than the second half 112B of the period of cycle 1. For example, the first half 112A of the period of cycle 1 is divided into 10 bins, and the second half 112B of the period of cycle 1 is divided into 15 bins.

[0047] In one embodiment, after cycle 1 of voltage 112, the processor controls the operating frequency of the HF RF generator during the second half of each cycle such as cycle 2 or cycle 3, but does not control the operating frequency of the HF RF generator during the first half of the cycle of voltage 112. For example, the processor controls the operating frequency during the second half of cycle 2, but does not control the frequency during the first half of cycle 2. To explain, when the processor ignores a predetermined level of uniformity, the processor does not control the operating frequency. More specifically, while adjusting the operating frequency, the processor does not target a predetermined level of uniformity. As another explanation, since the processor does not control the operating frequency, it does not modify the operating frequency.

[0048] In one embodiment, the processor controls the operating frequency of the HF RF generator during the first half of each cycle of voltage 112, but does not control the operating frequency of the HF RF generator during the second half of the cycle. For example, the processor controls the operating frequency of the HF RF generator during the first half 112A of cycle 1 of voltage 112, but does not control the operating frequency of the HF RF generator during the second half 112B of cycle 1 of voltage 112. As another example, the processor controls the operating frequency of the HF RF generator during the first half 112A of cycle 2 of voltage 112, but does not control the operating frequency of the HF RF generator during the second half 112B of cycle 2 of voltage 112.

[0049] In one embodiment, the processor determines the operating frequency of the HF RF generator for the bins of voltage 112 during a plurality of cycles of voltage 112, and applies the operating frequency during subsequent cycles of voltage 112. The subsequent cycles are consecutive with the plurality of cycles of voltage 112. For example, the processor determines the operating frequency of the HF RF generator in bin 1n of a plurality of cycles such as cycles 1 and 2 of voltage 112, and controls the HF RF generator to achieve the same operating frequency in bin 1n of cycle 3 of voltage 112. Cycle 3 is consecutive with cycle 2.

[0050] Note that in one embodiment, the operating frequency of the HF RF generator changes for the same bin after the first set of cycles of voltage 112, and this change in operating frequency is calculated based on achieving a level of uniformity. Once the frequency changes, the processor maintains the frequency without change for the same bin of the second set of cycles. The first set of cycles precedes the second set of cycles.

[0051] In one embodiment, the processor applies the operating frequency of the HF RF generator determined for a bin during a cycle of voltage 112 to the same bin during a plurality of consecutive cycles of voltage 112. For example, the processor applies the operating frequency of the HF RF generator determined for bin 1n during cycle 1 of voltage 112 to bin 1n during cycles 2 and 3 of voltage 112.

[0052] In one embodiment, the processor determines the operating frequency of the HF RF generator for a bin during a cycle of voltage 112, and then applies this determined operating frequency to the bin during the same cycle. For example, the operating frequency is determined in a portion of bin 1n of cycle 1 and applied in the remaining portion of bin 1n of cycle 1.

[0053] In one embodiment, the DC offset 114 is not applied to voltage 112, and voltage 112 oscillates with respect to the X-axis on which time t is plotted. For example, the voltage of the DC offset 114 is zero.

[0054] The voltage 112 shown in FIG. 1B-1 is a sine waveform or an envelope. In one embodiment, the voltage 112 has another shape, for example, a sawtooth shape, or a pulse shape, or an arbitrary shape.

[0055] FIG. 1C is one embodiment of the graph 100.

[0056] FIG. 1D-1 is one embodiment of the graph 120 for showing the binning around the ortho-point 122 of the cycle of the voltage 112. FIG. 1D-2 is a continuation of the graph 120. The ortho-point is the intersection of the voltage 112 where the voltage changes from a larger negative potential on one side of the DC offset 114 to a smaller negative potential on the opposite side of the DC offset 114. As an example, the ortho-point is the point at which the value of the voltage 112 coincides with the potential of the DC offset 114 and the voltage 112 transitions from a larger negative potential to a smaller negative potential. The ortho-point 122 occurs at the time tMm or approximately the time tMm during each cycle of the voltage 112. Examples of the time that is approximately the time tMm are times within a preset range, such as ±10% from the time tMm. In the graph 120, the voltage 112 is plotted against the time t. The voltage 112 is plotted on the Y-axis of the graph 120, and the time t is plotted on the X-axis of the graph 120.

[0057] Negative intersections such as the negative intersection 124a or 124b are intersections of the voltage 112 where the voltage changes from a smaller negative potential on one side of the DC offset 114 to a larger negative potential on the opposite side of the DC offset 114. As an example, the negative intersection is the point at which the value of the voltage 112 coincides with the potential of the DC offset 114 and the voltage 112 transitions from a smaller negative potential to a larger negative potential. Negative intersections such as the negative intersection 124a or 124b occur at the time tNn or approximately the time tNn during each cycle of the voltage 112. Examples of the time that is approximately the time tNn are times within a preset range, such as ±10% from the time tNn.

[0058] Voltage 112 is divided from bin 1m to 1n in the same manner as above, except that bin 1n is offset along the X-axis from bin 1m such that bin 1n of each cycle of voltage 112 extends before and after the positive intersection point 122 of the cycle, and bin 1m extends before and after the negative intersection point such as negative intersection points 124a or 124b of the cycle. For example, bin 1m to 1n is shifted to the left compared to bin 1m to 1n shown in FIG. 1B-1. Bin 1m starts at the time tRr of the previous cycle such as cycle 0 and ends at the time t1q of the current cycle such as cycle 1, where R is an integer and r is a variable indicating the second half of each cycle of voltage 112. The time tNn of the current cycle is between the time tRr of the previous cycle and the time t1q of the current cycle. The previous cycle precedes the current cycle. Also, bin 1n starts at the time tQq of the current cycle and ends at the time t1r of the current cycle, where Q is an integer and q is a variable indicating the first half of each cycle of voltage 112. The time tMm of the current cycle is between the time tQq of the current cycle and the time t1r of the current cycle.

[0059] In graph 120, voltage 112 is plotted against time t. Instead of binning, such as dividing each cycle of voltage 112 from bin 1m to Nn such that bin 1m starts at the negative intersection point of the cycle and bin Nn ends at the positive intersection point of the cycle (FIG. 1B-1), the processor divides the cycle of voltage 112 from bin 1m to Nn such that bin 1n extends at a first predetermined time interval before the positive intersection point 122 and at a second predetermined time interval after the positive intersection point 122, and bin 1m extends at a third predetermined time interval before the negative intersection point 124a and at a fourth predetermined time interval after the negative intersection point 124a.

[0060] That is, the positive intersection point 122 and the negative intersection point 124a do not occur at the edge of the bin (i.e., either the start or the end), but instead occur in the central portion of the bin. For example, the processor divides the time interval around the negative intersection point 124a of cycle 1 to generate bin 1m of cycle 1. To explain, bin 1m of cycle 1 extends from the third predetermined time interval before the time tNn of cycle 1 at which the negative intersection point 124a occurs to the fourth predetermined time interval after the time tNn. The time tRr is in the third predetermined time interval before the time tNn and falls within cycle 0 of voltage 112, and the time t1q is in the fourth predetermined interval after the time tNn and falls within cycle 1 of voltage 112. In one explanation, the third predetermined time interval is equal to the fourth predetermined time interval. As another explanation, the third predetermined time interval is greater than or less than the fourth predetermined time interval. As yet another explanation, each of the first predetermined time interval, the second predetermined time interval, the third predetermined time interval, and the fourth predetermined time interval is equal. The processor determines the operating frequency of the HF RF generator for bin 1m and controls the operating frequency of the HF RF generator to achieve the determined operating frequency within bin 1m of cycle 2 of voltage 112.

[0061] As another example, instead of using the positive intersection point 122 and the negative intersection point 124a as the two ends to divide the first half 112A of cycle 1 of voltage 112 into a preset number of bins from 1m to Mm, the processor divides a part of cycle 0 of voltage 112, the first half 112A of cycle 1, and a part of the second half 112B of cycle 1 into a preset number of bins from 1m to 1n. To explain, instead of ending bin Mm at time tMm which is the end of the first half 112A of cycle 1, bin 1n starts at a first predetermined interval before time tMm and ends at a second predetermined interval after time tMm. In this explanation, the first predetermined time interval is equal to the second predetermined time interval. As another explanation, the first predetermined time interval is greater than or less than the second predetermined time interval. Bin 1n starts at time tQq and ends at time t1r. Time t1r is within cycle 1 and time tQq is within cycle 1. Also, time tQq occurs after time t(M - 1)m (FIG. 1B - 1) of cycle 1 and time t1r occurs before time t1n (FIG. 1B - 1) of cycle 1. Since time tQq occurs after time t(M - 1)m (FIG. 1B - 1) and time t1r occurs before time t1n, the positive intersection point 122 occurs during the period of the bin instead of at the start or end of the bin.

[0062] Thereby, the processor can control the operating frequency of the HF RF generator during the time interval when the positive intersection point 122 occurs. For example, when determining the operating frequency of the HF RF generator for bin 1n of cycle 1, the processor applies that operating frequency during bin 1n of cycle 2 of voltage 112. Bin 1n of cycle 2 extends from time tQq of cycle 2 to time t1r of cycle 2. During bin 1n of cycle 2 of voltage 112, the positive intersection point 122 occurs and the operating frequency of the HF RF generator is controlled by the processor 214 at the positive intersection point 112.

[0063] As another example, instead of dividing the second half 112B of cycle 1 of voltage 112 into a preset number of bins 1n to Nn such that bin 1n starts at the positive intersection point 122 of cycle 1 and bin Nn ends at the negative intersection point 124b of cycle 2, the processor divides a part of the first half 112A of cycle 1 of voltage 112, the second half 112B of cycle 1, and a part of the first half 112A of cycle 2 into a preset number of bins 1n to Nn. To explain, bin 1n starts at a first predetermined interval before time tMm and ends at a second predetermined interval after time tMm.

[0064] Similarly, the processor divides the time interval around the negative intersection point 124b of cycle 2 to generate bins 1m of cycle 2. As an example, bin 1m of cycle 2 extends from a third predetermined time interval before time tNn of cycle 1 at which the negative intersection point 124b occurs to a fourth predetermined time interval after time tNn.

[0065] FIG. 2 is an embodiment of a plasma system 200 for explaining the application of the operating frequency of an HF RF generator to a plurality of bins. The plasma system 200 includes an LF RF generator, an HF RF generator, an impedance matching circuit (IMC) 202, a host computer 212, a plasma chamber 220, a voltage sensor 204, a control system 222, and a power sensor 224. The LF RF generator is a radio frequency generator that operates in a low frequency range, for example, in the kilohertz (kHz) frequency range. For example, the LF RF generator is a 400 kHz RF generator having a frequency tuning range of 330 kHz to 440 kHz. As another example, the LF RF generator is a 100 kHz RF generator having a frequency tuning range of 50 kHz to 150 kHz. The HF RF generator is a radio frequency generator that operates in a high frequency range, for example, in the megahertz (MHz) frequency range. As an example, the HF RF generator is a 60 MHz RF generator having a frequency tuning range of 54 MHz to 63 MHz. As another example, the HF RF generator operates at a frequency in the range of 20 MHz to 30 MHz, or in the range of 12 MHz to 14 MHz, or in the range of 1 MHz to 3 MHz.

[0066] As an example of IMC202, a network of electrical components such as capacitors and inductors can be cited. For example, IMC202 includes a plurality of inductors and a plurality of capacitors, and the inductors and capacitors are coupled to each other. Examples of capacitors include fixed capacitors and variable capacitors, and examples of inductors include fixed inductors and variable inductors. IMC202 has two branch circuits including a first branch circuit and a second branch circuit.

[0067] The host computer 212 includes a processor 214 and a memory device 216. The processor 214 is coupled to the memory device 216. By way of example, the processor is a controller, or an application specific integrated circuit (ASIC), or a programmable logic device (PLD), or a central processing unit (CPU), or a microcontroller, or a microprocessor, and these terms are used interchangeably herein. Examples of memory devices used herein include random access memory (RAM), read only memory (ROM), and combinations thereof.

[0068] As an example of the control system 222, a combination of a drive system and a motor system can be cited. The drive system includes one or more drive devices such as one or more transistors, and the motor system includes one or more motors such as one or more electric motors. The drive system is coupled to the motor system, and the motor system is coupled to IMC202 via one or more connection parts such as a combination of one or more rods or a plurality of rods and one or more gears. For example, the electric motor is coupled to the plate of the capacitor of IMC202 via two rods and a gear, and the gear is coupled between the two rods.

[0069] The processor 214 is coupled to the LF RF generator via the transfer cable 236A and to the HF RF generator via another transfer cable 236B. As an example, the processor 214 is connected to the digital signal processor (DSP) of the LF RF generator via the transfer cable 236A and to the DSP of the HF RF generator via the transfer cable 236B. Examples of transfer cables include serial transfer cables, parallel transfer cables, and universal serial bus (USB) cables.

[0070] Also, the processor 214 is coupled to the voltage sensor 204 via the transfer cable 236C and to the power sensor 224 via the transfer cable 236D. The processor 214 is also coupled to the drive system of the control system 222.

[0071] The plasma chamber 106 is a capacitively coupled plasma (CCP) chamber and includes a chuck 226 and an upper electrode 228. The upper electrode 228 has a lower surface facing the upper surface of the chuck 226. An example of the chuck 226 is an electrostatic chuck (ESC). The chuck 226 includes a lower electrode made of a metal such as aluminum or an aluminum alloy. The upper electrode 228 is coupled to the ground potential and is made of silicon.

[0072] The output 230A of the LF RF generator is coupled to the input 232A of the IMC202 via the RF cable 234A. The input 232A is coupled to the first branch circuit of the IMC202. Also, the output 230B of the HF RF generator is coupled to another input 232B of the IMC202 via another RF cable 234B. The input 232B is coupled to the second branch circuit of the IMC202. The first branch circuit and the second branch circuit of the IMC202 are coupled to each other at a connection point, and the connection point is coupled to the output 206 of the IMC202. As an example, the output 206 is an output port of the housing or enclosure of the IMC202, and the RF transmission line 210 extends out of the matching unit from the output port. The output 206 of the IMC202 is coupled to the lower electrode of the chuck 226 via the RF transmission line 210 and the input 208 of the plasma chamber 220. The input 208 is a point on the RF transmission line 210. To explain, the input 208 is a port of the housing or enclosure of the plasma chamber 220, and the RF transmission line extends into the housing or enclosure from this port. Examples of the RF transmission line 210 include an RF rod and an RF cylinder. The RF rod is coupled to an RF cylinder located in the plasma chamber. The RF rod is surrounded by the RF tunnel of the RF transmission line 210 and the RF sheath of the RF transmission line 210. The RF sheath surrounds the RF tunnel, and the RF tunnel includes an insulator material to insulate the RF rod from the RF sheath.

[0073] The power sensor 224 is coupled to the output 230B of the HF RF generator, and the voltage sensor 204 is coupled to the output 206 of the IMC202. For example, the power sensor 224 is coupled to the output 230B of the HF power supply of the HF RF generator, and the voltage sensor 204 is coupled to the connection point of the first branch circuit and the second branch circuit of the IMC202. The power sensor 224 measures the transmitted power, which is the difference between the power supplied at the output 230B and the power reflected back to the output 230B. The power reflected back to the output 230B is reflected from the plasma chamber 220, through the RF sheath and housing of the IMC202, the RF sheath of the RF cable 234B, and the output 230B, back to the HF RF generator.

[0074] The processor 214 provides set points of parameters such as frequency and power to the LF RF generator via the transfer cable 236A, and provides the set points of the parameters to the HF RF generator via the transfer cable 236B. Upon receiving the set points of the parameters, the LF RF generator generates an RF signal 218A and transmits the RF signal 218A to the first branch circuit via the output 230A, the RF cable 234A, and the input 232A. Similarly, upon receiving the set points of the parameters, the HF RF generator generates an RF signal 218B and transmits the RF signal 218B to the second branch circuit via the output 230B, the RF cable 234B, and the input 232B.

[0075] The first branch circuit of the IMC 202 matches the impedance of the load coupled to the output 206 with the impedance of the source coupled to the input 232A and outputs a first corrected RF signal at the connection of the IMC 202. Examples of the load coupled to the output 206 include the RF transmission line 210 and the plasma chamber 220. Examples of the source coupled to the input 232A include the RF cable 234A and the LF RF generator. Similarly, the second branch circuit of the IMC 202 matches the impedance of the load coupled to the output 206 with the impedance of the source coupled to the input 232B and outputs a second corrected RF signal at the connection of the IMC 202. Examples of the source coupled to the input 232B include the RF cable 234B and the HF RF generator. The first corrected RF signal and the second corrected RF signal are combined, such as being added, at the connection of the IMC 202, and a corrected RF signal 238 is output at the connection.

[0076] The corrected RF signal 238 is provided from the connection point to the output 206 and further provided to the lower electrode of the chuck 226 via the RF transmission line 210. In addition to supplying the power of the corrected RF signal 238 to the lower electrode of the chuck 226, when one or more types of process gases such as an oxygen-containing gas or a fluorine-containing gas are supplied to the plasma chamber 220, plasma is collided or maintained in the plasma chamber 220 to process the substrate S placed on the upper surface of the chuck 226. Examples of the substrate S include a semiconductor wafer and a substrate stack.

[0077] While the corrected RF signal 238 is being supplied to the lower electrode, the voltage sensor 204 measures the voltage 112 (FIGS. 1B-1 and 1D-1) at the output 206, generates a measured value of the voltage 112, and provides this measured value to the processor 214 via the transfer cable 236C. In addition, the voltage sensor 204 provides the time at which the measurement was made to the processor 214 via the transfer cable 236C. Upon receiving the measured value of the voltage 112 and the time at which the measurement was made, the processor 214 identifies the positive and negative intersection points of each cycle of the voltage 112 and divides the voltage 112 from bin 1m to Nm. For example, the processor 214 determines or identifies from the measured value the time when the voltage 112 is at a predetermined value, such as the value of the DC offset 114 (FIG. 1B-1) or zero with no DC offset at all. The processor 214 further determines from the measured value that the value of the voltage 112 increases after the time when the voltage 112 is at the predetermined value compared to the time before the voltage 112 is at the predetermined value. To explain, the processor 214 determines that the value of the voltage 112 in the time interval between the time tMm and the time t1n (FIG. 1B-1) is greater than the value of the voltage 112 in the time interval between the time t(M-1)m and the time tMm (FIG. 1B-1). As another explanation, the processor 214 determines that the value of the voltage 112 in the time interval between the time tMm and the time t1r (FIG. 1D-1) is greater than the value of the voltage 112 in the time interval between the time tQq and the time tMm (FIG. 1D-1). When it is determined that the value of the voltage 112 increases after the time when the voltage 112 is at the predetermined value compared to the time before the voltage 112 is at the predetermined value, the processor 214 determines that the time at which the predetermined value occurred is the positive intersection point.

[0078] As another example, the processor 214 determines or identifies from the measured value the time during which the voltage 112 is at a predetermined value, such as the value of the DC offset 114 (FIG. 1B-1) or a zero value with no DC offset at all. The processor 214 further determines from the measured value that the value of the voltage 112 decreases after the time when the voltage 112 is at the predetermined value as compared to the time before the voltage 112 is at the predetermined value. Specifically, the processor 214 determines that the value of the voltage 112 in the time interval (FIG. 1B-1) between the time tNn and the time t1m is smaller than the value of the voltage 112 in the time interval (FIG. 1B-1) between the time t(N-1)n and the time tNn.

[0079] As another explanation, the processor 214 determines that the value of the voltage 112 in the time interval (FIG. 1D-1) between the time tNn and the time t1q is smaller than the value of the voltage 112 in the time interval (FIG. 1D-1) between the time tRr and the time tNn. When it is determined that the value of the voltage 112 decreases after the time when the voltage 112 is at the predetermined value as compared to the time before the voltage 112 is at the predetermined value, the processor 214 determines that the time when the predetermined value occurs is a negative intersection point.

[0080] As another example, the processor 214 divides the time interval of the second half 112B of each cycle of the voltage 112 (FIGS. 1B-1 and 1D-1) into bins 1n to Nn. Specifically, the processor 214 divides the time interval from time tMm to time tNn into bins 1n to Nn (see FIG. 1B-1) such that bin 1n starts at the positive intersection 122 and bin Nn ends at the negative intersection 124b. As another explanation, the processor 214 divides the time interval from time tQq (FIG. 1D-1) to time tRr into bins 1n to Nn, where R is an integer. The time tQq is close to the time tMm of the positive intersection 122 of cycle 1, and the time tRr is close to the time tNn of the negative intersection 124b of cycle 2 (FIG. 1D-1). For example, the time tQq is within a predetermined range from the time tMm of the positive intersection 122 of cycle 1, and the time tRr is within a predetermined range from the time tNn of the negative intersection 124b of cycle 2. The predetermined ranges associated with each intersection of the voltage 112 are stored in the memory device 216. In this example, the processor 214 does not divide the time interval of the first half 112A of each cycle of the voltage 112 (FIGS. 1B-1 and 1D-1) into bins 1m to Mm.

[0081] As another example, the processor 214 divides the time interval of the first half 112A of each cycle of the voltage 112 from bin 1m to Mm. In this example, the processor 214 does not divide the time interval of the second half 112B of each cycle of the voltage 112 from bin 1n to Nn. To explain, the processor 214 divides the time interval from time tNn to time tMm such that bin 1m starts at the negative intersection 124a and bin Mm ends at the positive intersection 122, from bin 1m to Mm (FIG. 1B-1). As another explanation, the processor 214 divides the time interval from time tRr (FIG. 1D-1) to time tQq from bin 1m to Mm. Time tRr is close to the time tNn of the negative intersection 124a of cycle 1, and time tQq is close to the time tMm of the positive intersection 122 of cycle 1 (FIG. 1D-1). For example, time tRr is within a predetermined range from the time tNn of the negative intersection 124a of cycle 1, and time tQq is within a predetermined range from the time tMm of the positive intersection 122 of cycle 1. In this example, the processor 214 does not divide the time interval of the second half 112B of each cycle of the voltage 112 (FIG. 1B-1 and FIG. 1D-1) from bin 1n to Nn.

[0082] As another example, the processor 214 divides the time interval of each cycle of the voltage 112 into bins 1m through Nn. Specifically, the processor 214 identifies the negative crossing point 124a (FIG. 1D-1) of cycle 1 of the voltage 112 from the measured values, and identifies the successive negative crossing points 124b (FIG. 1D-1) of cycle 1 or cycle 2 of the voltage 112 from the measured values. The processor 214 determines the period taken by the voltage sensor 204 to obtain the measured values between two successive negative crossing points 124a and 124b. The processor 214 divides that period into a predetermined number of time intervals so as to generate bins 1m through Nn. The period for obtaining the measured values of the voltage 112 for each cycle of the voltage 112 is transmitted to the processor 214 together with the measured values from the voltage sensor 204 via the transfer cable 236C. The predetermined number of time intervals is stored in the memory device 216 and is received as an input from the user via a user interface including an input device such as a mouse, keyboard, or keypad, a display device, a display screen, or a combination thereof. The input device is coupled to the processor 214. As another example, the processor 214 divides a portion of the time interval of each cycle of the voltage 112 into a pre-stored number of bins. Examples of the pre-stored number of bins are provided below.

[0083] Also, the processor 214 receives, via the transfer cable 236D, the measured value of the transmitted power from the power sensor 224 and the time at which the measured value was generated by the power sensor 224. The time at which the measured value of the transmitted power is acquired by the power sensor 224 for each cycle of the voltage 112 is transmitted from the power sensor 224 to the processor 214 via the transfer cable 236D together with the measured value. To generate the measured value of the transmitted power, the transmitted power at the output 230B is measured by the power sensor 224. The processor 214 associates the measured value of the transmitted power with the bins 1m to Nn. For example, the processor 214 determines that the first set of measured values or the first measured value of the transmitted power corresponds to the period of the bin 1n, and that the second set of measured values or the second measured value of the transmitted power corresponds to the period of the bin 2n. The measured value of the transmitted power includes one value of the transmitted power, and the set of measured values of the transmitted power includes multiple values of the transmitted power. When receiving multiple values regarding the transmitted power in a bin, the processor 214 calculates the average or median of those values to determine a single measured value of the transmitted power for that bin.

[0084] For each of the bins from bin 1m to bin Nn that stores a pre - memorized number, the processor 214 determines a frequency level, which is the amount of the operating frequency of the HF RF generator, to achieve a predetermined level UNFM, such as uniformity, a value, or a range of consecutive values. For example, the processor 214 determines that by increasing the frequency level of the HF RF generator from the set - point value to level HF1m in bin 1m, the transmitted power will be increased from the measured level, such as the measured value for bin 1m, to level PR1m for bin 1m, and further achieve the level UNFM. The measured level of the transmitted power for bin 1m is received from the power sensor 224 by the above - mentioned method. The processor 214 controls the HF RF generator in bin 1m of cycle 1 of voltage 112 to achieve the frequency level HF1m, receives the measured value of power level PR1m from the power sensor 224, and determines that by increasing the frequency level from the set - point value to level HF1m, the transmitted power will be increased from the measured level to level PR1m. The transmitted power increases to level PR1m and achieves or exceeds the uniformity level UNFM. The correspondence between level PR1m and level UNFM is stored in table 240 of the memory device 216. The processor 214 stores the determined frequency level as corresponding to bin HF1m in table 240.

[0085] As another example, the processor 214 determines that by increasing the frequency level of the HF RF generator from the set - point value to level HF1m in bin 1m, instead of increasing the transmitted power, the transmitted power will be decreased from the measured level for bin 1m to level PR1m for bin 1m.

[0086] As yet another example, the processor 214 determines that by decreasing the frequency level of the HF RF generator from the set - point value to level HF1m in bin 1m instead of increasing it, the transmitted power will be increased from the measured level for bin 1m to level PR1m for bin 1m.

[0087] As yet another example, the processor 214 determines that by decreasing the frequency level of the HF RF generator from the set point value to level HF1m in bin 1m, the transmitted power will be decreased from the measured level for bin 1m to level PR1m for bin 1m instead of being increased.

[0088] Similarly, as another example, the processor 214 determines that by increasing the frequency level of the HF RF generator from HF1m of bin 1m to level HF2m, the transmitted power will be increased from the measured level for bin 2m to level PR2m for bin 2m, and further achieve level UNFM. The measured level of the transmitted power for bin 2m is received from the power sensor 224 by the above method. The processor 214 controls the HF RF generator in bin 2m during cycle 1 of voltage 112 to achieve the frequency level HF2m, and receives the measured value of power level PR2m from the power sensor 224, and determines that by increasing the frequency level to level HF2m, the transmitted power will be increased from the measured level to level PR2m. The transmitted power increases to level PR2m to achieve the level of uniformity UNFM. The correspondence between level PR2m and level UNFM is stored in table 240 of the memory device 216. The processor 214 stores the determined frequency level HF2m as corresponding to bin 2m of table 240.

[0089] As another example, the processor 214 determines that by increasing the frequency level of the HF RF generator from level HF1m to level HF2m in bin 2m, the transmitted power will be decreased from the measured level for bin 2m to level PR2m for bin 2m instead of being increased.

[0090] As yet another example, the processor 214 determines that by decreasing the frequency level of the HF RF generator to level HF2m in bin 2m instead of increasing it, the transmitted power will be increased from the measured level for bin 2m to level PR2m for bin 2m.

[0091] As yet another example, the processor 214 determines that by lowering the frequency level of the HF RF generator to level HF2m in bin 2m, instead of increasing the transmitted power, the transmitted power will be decreased from the measured level for bin 2m to level PR2m for bin 2m.

[0092] As another example, the processor 214 determines that by raising the frequency level of the HF RF generator to level HFMm in bin Mm, the transmitted power will be increased from the measured level for bin Mm to level PRMm for bin Mm, and further achieve level UNFM. The frequency level is raised from the frequency level HF(M-1)m for bin (M-1)m to level HFMm. The measured level of the transmitted power for bin Mm is received from the power sensor 224 by the above method. The processor 214 controls the HF RF generator in bin Mm of cycle 1 of voltage 112 to achieve the frequency level HFMm, receives the measured value of power level PRMm from the power sensor 224, and determines that by raising the frequency level to level HFMm, the transmitted power will be increased from the measured level to level PRMm. The transmitted power increases to level PRMm to achieve the level of uniformity UNFM. The correspondence between level PRMm and level UNFM is stored in table 240. The processor 214 stores the determined frequency level HFMm as corresponding to bin Mm in table 240.

[0093] As another embodiment, the processor 214 determines that by raising the frequency level of the HF RF generator from the frequency level HF(M-1)m to level HFMm in bin Mm, instead of increasing the transmitted power, the transmitted power will be decreased from the measured level for bin Mm to level PRMm for bin Mm.

[0094] As yet another example, the processor 214 determines that by lowering the frequency level to level HFMm in bin Mm instead of raising it, the transmitted power will be increased from the measured level for bin Mm to level PRMm for bin Mm.

[0095] As yet another example, the processor 214 determines that by lowering the frequency level of the HF RF generator to level HFMm in bin Mm, instead of increasing the transmitted power, the measured level for bin Mm will be decreased to level PRMm for bin Mm.

[0096] As yet another example, the processor 214 determines that by increasing the frequency level of the HF RF generator from level HFMm to level HF1n in bin 1n, the transmitted power will be increased from the measured level for bin 1n to level PR1n for bin 1n, further achieving level UNFM. The measured level of the transmitted power for bin 1n is received from the power sensor 224 in the above manner. The processor 214 controls the HF RF generator in bin 1n during cycle 1 of voltage 112 to achieve the frequency level HF1n, and receives the measured value of power level PR1n from the power sensor 224, and determines that by increasing the frequency level to level HF1n, the transmitted power will be increased from the measured level to level PR1n. The transmitted power increases to level PR1n, achieving the level of uniformity UNFM. The correspondence between level PR1n and level UNFM is stored in table 242 of the memory device 216. The processor 214 stores the determined frequency level HF1n as corresponding to bin 1n in table 242.

[0097] As another example, the processor 214 determines that by increasing the frequency level of the HF RF generator from level HFMm to level HF1n in bin 1n, instead of increasing the transmitted power, the measured level for bin 1n will be decreased to level PR1n for bin 1n.

[0098] As yet another example, the processor 214 determines that by decreasing the frequency level to level HF1n in bin 1n instead of increasing it, the transmitted power will be increased from the measured level for bin 1n to level PR1n for bin 1n.

[0099] As yet another example, the processor 214 determines that by lowering the frequency level of the HF RF generator to level HF1n in bin 1n, instead of increasing the transmitted power, the transmitted power will be decreased from the measured level for bin 1n to level PR1n for bin 1n.

[0100] Similarly, as another example, the processor 214 determines that by raising the frequency level of the HF RF generator from level HF1n to level HF2n in bin 2n, the transmitted power will be increased from the measured level for bin 2n to level PR2n for bin 2n, and further achieve the level UNFM. The measured level of the transmitted power for bin 2n is received from the power sensor 224 by the above method. The processor 214 controls the HF RF generator in bin 2n of cycle 1 of voltage 112 to achieve the frequency level HF2n, receives the measured value of power level PR2n from the power sensor 224, and determines that by raising the frequency level to level HF2n, the transmitted power will be increased from the measured level to level PR2n. The transmitted power increases to level PR2n to achieve the level of uniformity UNFM. The correspondence between level PR2n and level UNFM is stored in table 242 of the memory device 216. The processor 214 stores the determined frequency level HF2n as corresponding to bin 2n in table 240.

[0101] As another example, the processor 214 determines that by raising the frequency level of the HF RF generator from frequency level HF1n to level HF2n in bin 2n, instead of increasing the transmitted power, the transmitted power will be decreased from the measured level for bin 2n to level PR2n for bin 2n.

[0102] As yet another example, the processor 214 determines that by lowering the frequency level to level HF2n in bin 2n instead of raising it, the transmitted power will be increased from the measured level for bin 2n to level PR2n for bin 2n.

[0103] As yet another example, the processor 214 determines that by lowering the frequency level of the HF RF generator to level HF2n in bin 2n, instead of increasing the transmitted power, the transmitted power will be decreased from the measured level for bin 2n to level PR2n for bin 2n.

[0104] As another example, the processor 214 determines that by raising the frequency level of the HF RF generator to level HFNn in bin Nn, the transmitted power will be increased from the measured level for bin Nn to level PRNn for bin Nn. To further achieve level UNFM, the frequency level is raised from the frequency level HF(N - 1)n for bin (N - 1)n to level HFNn for bin Nn. The measured level of the transmitted power for bin Nn is received from the power sensor 224 by the above method. The processor 214 controls the HF RF generator in bin Nn of cycle 1 of voltage 112 to achieve the frequency level HFNn, and receives the measured value of power level PRNn from the power sensor 224, and determines that by raising the frequency level to level HFNn, the transmitted power will be increased from the measured level to level PRNn. The transmitted power increases to level PRNn to achieve the level of uniformity UNFM. The correspondence between level PRNn and level UNFM is stored in table 240. The processor 214 stores the determined frequency level HFNn as corresponding to bin Nn of table 240.

[0105] As another example, the processor 214 determines that by raising the frequency level of the HF RF generator from frequency level HF(N - 1)n to level HFNn in bin Nn, instead of increasing the transmitted power, the transmitted power will be decreased from the measured level for bin Nn to level PRNn for bin Nn.

[0106] As yet another example, the processor 214 determines that by lowering the frequency level of the HF RF generator to level HFNn in bin Nn instead of raising it, the transmitted power will be increased from the measured level for bin Nn to level PRNn for bin Nn.

[0107] As yet another example, the processor 214 determines that it will decrease the transmit power from the measured level for bin Nn to level PRNn for bin Nn by lowering the frequency level of the HF RF generator to level HFNn in bin Nn, instead of increasing it.

[0108] In one embodiment, the uniformity level is achieved when a predetermined value of uniformity is reached, or when a value within a preset range from the predetermined value of uniformity is reached. An example of the preset range is a range of ±5% from the predetermined value. The preset range and the predetermined value of uniformity are stored in the memory device 216.

[0109] Examples of uniformity include the uniformity of the etching rate across the surface of the substrate or the uniformity of the deposition rate across the surface of the substrate. As an example, the uniformity level is a statistical value such as the average or median of the etching rates across the surface of the substrate. As another example, the uniformity level is the maximum or minimum value among all the etching rates across the surface of the substrate.

[0110] Examples of the pre-stored number of bins out of bins 1m to Nn include the number of bins 1m to Mm for the first half 112A of cycle 1 of voltage 112.

[0111] Another example of the pre-stored number of bins out of bins 1m to Nn includes the number of bins 1n to Nn for the second half 112B of cycle 1 of voltage 112.

[0112] Yet another example of the pre-stored number of bins includes all, one, or more of bins 1m to Nn of the cycle of voltage 112.

[0113] As yet another example of bins of a number stored in advance out of bins 1m to Nn, there are bins 1n to Nn for the first quarter or the second quarter or the third quarter or the fourth quarter of cycle 1 of voltage 112. The second quarter of cycle 1 is consecutive with the first quarter of cycle 1. Similarly, the third quarter of cycle 1 is consecutive with the second quarter of cycle 1, and the fourth quarter of cycle 1 is consecutive with the third quarter of cycle 1.

[0114] As yet another example of bins of a number stored in advance, there are a predetermined number of bins associated with the orthogonality point 122. To explain, the predetermined number of bins associated with the orthogonality point 122 includes bin 1n (FIGS. 1B-1 and 1D-1) or bin Mm (FIG. 1B-1) including the time tMm of the orthogonality point 122.

[0115] As another explanation, the predetermined number of bins associated with the orthogonality point 122 includes bin 1n or bin Mm (FIG. 1B-1), and a predetermined number of additional bins adjacent to bin 1n or bin Mm. The predetermined number of additional bins is stored in the memory device 216. As an example, bins 2n and Mm are adjacent to bin 1n (FIG. 1B-1), and bins (M-1)m and 1n are adjacent to bin Mm (FIG. 1B-1).

[0116] Also, as yet another example, bins 2n, bin 3n (FIG. 1B-1), bins (M-1)m and Mm are adjacent to bin 1n (FIG. 1B-1), and bins (M-2)m (FIG. 1B-1), bins (M-1)m, and bins 1n and 2n (FIG. 1B-1) are adjacent to bin Mm. One or more bins are adjacent to additional bins when there are no other bins at all between such one or more bins and the additional bins.

[0117] As yet another example, the bins within the second quarter and within the third quarter of cycle 1 of voltage 112 are examples of a predetermined number of bins associated with the orthogonality point 122.

[0118] As yet another explanation, the predetermined number of bins associated with the orthogonality point 122 includes the bin 1n (FIG. 1D-1) and a predetermined number of additional bins adjacent to the bin 1n. The bins 2n and Mm are adjacent to the bin 1n (FIG. 1D-1). Also, the bins 2n and 3n (FIG. 1D-1), and the bins (M-1)m and Mm are adjacent to the bin 1n (FIG. 1D-1).

[0119] In one embodiment, it should be noted that the predetermined number of bins associated with one cycle of the orthogonality point 122 is less than the number of bins for half of the cycle. For example, the predetermined number of bins associated with the orthogonality point 122 of cycle 1 is less than the number of bins in the first half 112A or the second half 112B of cycle 1.

[0120] As another example of the number of bins stored in advance, there is a predetermined number of bins associated with the negative intersection point 124a. To explain, the predetermined number of bins associated with the negative intersection point 124a includes the bin Nn including the time tNn of the negative intersection point 124a or the bin 1m (FIGS. 1B-1 and 1D-1).

[0121] As yet another explanation, the predetermined number of bins associated with the negative intersection point 124a includes the bin Nn or the bin 1m (FIG. 1B-1) and a predetermined number of additional bins adjacent to the bin Nn or the bin 1m. As an example, the bins (N-1)n and 1m are adjacent to the bin Nn (FIG. 1B-1), and the bins 2m and Nn are adjacent to the bin 1m (FIG. 1B-1).

[0122] Also, as another example, the bins (N-1)n, the bins (N-2)n (FIG. 1B-1), and the bins 1m and 2m are adjacent to the bin Nn (FIG. 1B-1), and the bins (N-1)n and Nn, and the bins 2m and 3m (FIG. 1B-1) are adjacent to the bin 1m.

[0123] As yet another example, the bins that are within the fourth quarter of cycle 0 of the voltage 112 and within the first quarter of cycle 1 are examples of the predetermined number of bins associated with the negative intersection point 124a.

[0124] As yet another explanation, a predetermined number of bins associated with the negative intersection point 124a includes the bin 1m (FIG. 1D-1) and a predetermined number of additional bins adjacent to the bin 1m. The bins 2m and Nn are adjacent to the bin 1m (FIG. 1D-1). Also, the bins 2m and 3m (FIG. 1D-1), and the bins (N-1)n and Nn are adjacent to the bin 1m (FIG. 1D-1).

[0125] In one embodiment, it should be noted that a predetermined number of bins associated with a negative intersection point such as the negative intersection point 124a or 124b of a cycle is less than the number of bins for half of the cycle. For example, a predetermined number of bins associated with the negative intersection point 124a of cycle 1 is less than the number of bins in the second half of cycle 0 or the first half 112A of cycle 1.

[0126] In one embodiment, after obtaining a measured value of the transmission power for a pre-stored number of bins of cycle 1 of the voltage 112, the processor 214 determines whether a predetermined statistical power value of the transmission power for the pre-stored number of bins of cycle 1 is achieved. Examples of the statistical power value of the transmission power for the pre-stored number of bins include the average value or the median value of a plurality of values of the transmission power for the pre-stored number of bins. If it is determined that the predetermined statistical power value is not achieved, the processor 214 corrects one or more of the frequency levels for one or more of the pre-stored number of bins. The processor 214 continues to correct one or more of the frequency levels until a predetermined statistical power value of the transmission power for the pre-stored number of bins of cycle 1 is achieved.

[0127] For example, after obtaining the measured value of the transmission power for bins 1m to Mm of cycle 1 of voltage 112 from power sensor 224, processor 214 determines whether a predetermined statistical power value of the transmission power for bins 1m to Mm of cycle 1 is achieved by the frequency level for bins 1m to Mm. For example, processor 214 obtains the measured values of the transmission power for bins 1m to Mm and calculates the average value of these measured values to determine the average transmission power level for bins 1m to Mm of cycle 1. Processor 214 further determines whether the average transmission power level for bins 1m to Mm of cycle 1 is greater than a predetermined average transmission power level stored in memory device 216 for bins 1m to Mm. The predetermined average transmission power level for the first half 112A is received by processor 214 from the user via a user interface including an input device. If it is determined that the average transmission power level for bins 1m to Mm is greater than the predetermined average transmission power level for bins 1m to Mm, processor 214 does not modify one or more of the frequency levels for bins 1m to Mm. On the other hand, if it is determined that the average transmission power level for bins 1m to Mm is not greater than the predetermined average transmission power level for bins 1m to Mm, processor 214 changes one or more of the frequency levels for bins 1m to Mm. Processor 214 continues to change one or more of the frequency levels for bins 1m to Mm until the average transmission power level for bins 1m to Mm is greater than the predetermined average transmission power level for bins 1m to Mm. The frequency level for bins 1m to Mm is modified to frequency levels HF1m to HFMm.

[0128] In one embodiment, instead of changing one or more of the frequency levels for bins 1m to Mm within bins 1m to Mm of cycle 1 of voltage 112, processor 214 changes one or more of the frequency levels for bins 1m to Mm within bins 1m to Mm of a plurality of consecutive cycles of voltage 112 until the average transmission power level for bins 1m to Mm is greater than the predetermined average transmission power level for bins 1m to Mm.

[0129] As another example, after the processor 214 obtains the measured values of the transmission power for bins 1n to Nn of cycle 1 of the voltage 112 from the power sensor 224, the processor 214 determines whether a predetermined statistical power value of the transmission power for bins 1n to Nn of cycle 1 is achieved by the frequency level for bins 1n to Nn. For example, the processor 214 obtains the measured values of the transmission power for bins 1n to Nn and calculates the average value of these measured values to determine the average transmission power level for bins 1n to Nn of cycle 1. The processor 214 further determines whether the average transmission power level for bins 1n to Nn of cycle 1 is greater than a predetermined average transmission power level stored in the memory device 216 for bins 1n to Nn. The predetermined average transmission power level for the second half 112B is received by the processor 214 from the user via a user interface including an input device. When it is determined that the average transmission power level for bins 1n to Nn is greater than the predetermined average transmission power level for bins 1n to Nn, the processor 214 does not correct one or more of the frequency levels for bins 1n to Nn. On the other hand, when it is determined that the average transmission power level for bins 1n to Nn is not greater than the predetermined average transmission power level for bins 1n to Nn, the processor 214 changes one or more of the frequency levels for bins 1m to Mm. The processor 214 continues to change one or more of the frequency levels for bins 1n to Nn until the average transmission power level for bins 1n to Nn is greater than the predetermined average transmission power level for bins 1n to Nn. The frequency level for bins 1n to Nn is corrected to frequency levels HFn1 to HFnN.

[0130] In one embodiment, instead of changing one or more of the frequency levels for bins 1n through Nn in cycle 1 of voltage 112, processor 214 changes one or more of the frequency levels for bins 1n through Nn in a plurality of consecutive cycles of voltage 112 until the average transmit power level for bins 1n through Nn is greater than a predetermined average transmit power level for bins 1n through Nn.

[0131] In one embodiment, after obtaining a measurement of the transmit power for a pre - stored number of bins in cycle 1 of voltage 112, processor 214 determines whether a predetermined statistical power value of the transmit power for the entire cycle 1 of voltage 112 is achieved. Examples of the statistical power value of the transmit power for a cycle of voltage include the average value or the median value of a plurality of values of the transmit power for all bins of the cycle. If it is determined that the predetermined statistical power value is not achieved, processor 214 modifies one or more of the frequency levels for one or more of the pre - stored number of bins. Processor 214 continues to modify one or more of the frequency levels until a predetermined statistical power value of the transmit power for cycle 1 is achieved. The frequency levels for bins 1m through Nn are modified to frequency levels HFn1 through HFnN.

[0132] As used herein, a predetermined statistical power value of the transmit power for a pre - stored number of bins corresponds to a uniformity level UNFM. For example, when a predetermined statistical power value is achieved for a pre - stored number of bins, the uniformity level UNFM is achieved.

[0133] In one embodiment, instead of a predetermined statistical power value of the transmit power, a predetermined ratio of the transmit power is used. Examples of the ratio of the transmit power include the ratio of the average transmit power for bins 1n through Nn to the average transmit power for bins 1m through Mm.

[0134] As another example of the ratio of the transmitted power, there is a ratio of the average transmitted power from bin 1m to Mm and the average transmitted power from bin 1n to Nn. For example, the processor 214 determines whether a predetermined ratio of the transmitted power is achieved from the frequency level of bin 1m to Nn during cycle 1. If it is determined that the predetermined ratio of the transmitted power is not achieved, the processor 214 modifies one or more of the frequency levels of bin 1m to Nn. The processor 214 continues to modify one or more of the frequency levels of bin 1m to Nn until the predetermined ratio of the transmitted power is achieved. The predetermined ratio of the transmitted power corresponds to the uniformity level UNFM. For example, when the predetermined ratio of the transmitted power is achieved for cycle 1, the uniformity level UNFM is achieved.

[0135] The processor 214 generates a table 240 including the correspondence between each of bins 1m to Mm and the corresponding ones among the frequency values HF1m to HFMm, the corresponding ones among the power levels PR1m to PRMm, a predetermined statistical power value of the transmitted power for a pre-stored number of bins, and the uniformity level UNFM, and stores the table 240 in the memory device 216. Similarly, the processor 214 generates a table 242 including the correspondence between each of bins 1n to Nn and the corresponding ones among the frequency values HF1n to HFNn, the corresponding ones among the power levels PR1n to PRNn, a predetermined statistical power value of the transmitted power for a pre-stored number of bins, and the uniformity level UNFM, and stores the table 242 in the memory device 216.

[0136] The processor 214 applies the high-frequency levels in tables 240 and 242 during one or more subsequent cycles of voltage 112. For example, when the high-frequency level is determined during cycle 1 of voltage 112, the processor 214 applies the high-frequency levels in tables 240 and 242 during cycle 2 of voltage 112.

[0137] As another example, when the high-frequency level is determined during cycle 1 of voltage 112, the processor 214 applies the high-frequency levels in tables 240 and 242 during cycles 2 and 3 of voltage 112.

[0138] As another example, when the high-frequency level is determined during cycles 1 and 2 of voltage 112, the processor 214 applies the high-frequency levels of tables 240 and 242 during cycle 3 of voltage 112.

[0139] As another example, the processor 214 applies the high-frequency level HF1n determined in bin 1n of cycle 1 of voltage 112. The high-frequency level HF1n is applied during bin 1n, such as from the start time of bin 1n to the end time of bin 1n in cycle 2 of voltage 112. Examples of the start time of bin 1n include time tMm (FIG. 1D-1) or time tQq (FIG. 1D-1). Examples of the end time of bin 1n include time t1n (FIG. 1D-1) or time t1r (FIG. 1D-1).

[0140] As yet another example, the processor 214 applies the high-frequency level HFNn determined in bin Nn of cycle 1 of voltage 112. The high-frequency level HFNn is applied during bin Nn, such as from the start time of bin Nn to the end time of bin Nn in cycle 2 of voltage 112. Examples of the start time of bin Nn include time t(N-1)n (FIG. 1B-1) or time t(R-1)r (FIG. 1D-1). Examples of the end time of bin Nn include time tNn (FIG. 1B-1) or time tRr (FIG. 1D-1).

[0141] As another example, the processor 214 applies the high-frequency level HF1m determined in bin 1m of cycle 1 of voltage 112, and the high-frequency level HF1m is applied during bin 1m of cycle 2 of voltage 112.

[0142] As yet another example, the processor 214 applies the high-frequency level HF1m determined in bin Mm of cycle 1 of voltage 112, and the high-frequency level HF1m is applied during bin Mm of cycle 2 of voltage 112.

[0143] As another example, during bin 1n of cycle 2 of voltage 112, processor 214 transmits a data signal having a frequency value HF1n to the HF RF generator via transfer cable 236B. When receiving a data signal having a frequency value HF1n during the period of bin 1n of cycle 2, the HF RF generator generates an RF signal 218B having a high frequency level HF1n.

[0144] Similarly, during bin Nn of cycle 2 of voltage 112, processor 214 transmits a data signal having a frequency value HFNn to the HF RF generator via transfer cable 236B. When receiving a data signal having a frequency value HFNn during the period of bin Nn of cycle 2, the HF RF generator generates an RF signal 218B having a high frequency level HFNn.

[0145] As yet another example, during bin 1m of cycle 2 of voltage 112, processor 214 transmits a data signal having a frequency value HF1m to the HF RF generator via transfer cable 236B. When receiving a data signal having a frequency value HF1m during the period of bin 1m of cycle 2, the HF RF generator generates an RF signal 218B having a high frequency level HF1m.

[0146] Similarly, during bin Mm of cycle 2 of voltage 112, processor 214 transmits a data signal having a frequency value HFMm to the HF RF generator via transfer cable 236B. When receiving a data signal having a frequency value HFMm during the period of bin Mm of cycle 2, the HF RF generator generates an RF signal 218B having a high frequency level HFMm.

[0147] It should be noted that the processor 214 determines the change of the voltage 112 from one cycle to another based on the clock signal generated by the clock generator and the value of the voltage 112 received from the voltage sensor 204. For example, the processor 214 determines that the value of the voltage 112 repeats during a second period consecutive to the first period. When the processor 114 determines that the value of the voltage 112 starts to repeat, it determines that a change regarding the cycle has occurred, such as from cycle 1 to cycle 2. As another example, the processor 214 determines that a certain type of intersection, such as consecutive positive intersections or consecutive negative intersections, has occurred continuously during the previous cycle of the voltage 112 in order to determine that a change has occurred from the previous cycle to the consecutive cycle.

[0148] The first and second periods are part of the clock signal generated by the clock generator coupled to the processor 214. The clock generator provides the processor 214 with a clock signal including the first and second periods. In one embodiment, the clock generator is part of the processor 214. In one embodiment, the processor 214 obtains the clock signal from a computer network such as the Internet.

[0149] In one embodiment, the processor 214 applies some, but not all, of the high-frequency levels in the tables 240 and 242 during one or more subsequent cycles of the voltage 112. For example, the processor 214 applies the high-frequency levels HF1n to HFNn determined during the second half 112B of cycle 1 of the voltage 112 to bins 1n to Nn of cycle 2 of the voltage 112, but does not apply the high-frequency levels HF1m to HFMm determined during the first half 112A of cycle 1 of the voltage 112 to bins 1m to Mm of cycle 2 of the voltage 112.

[0150] As another example, the processor 214 applies high-frequency levels HF1m to HFMn determined during the first half 112A of cycle 1 of voltage 112 to bins 1m to Mm of cycle 2 of voltage 112, but does not apply high-frequency levels HF1n to HFNn determined during the second half 112B of cycle 1 of voltage 112 to bins 1n to Mn of cycle 1 of voltage 112.

[0151] As yet another example, the processor 214 applies high-frequency levels for a pre-stored number of bins of cycle 2 of voltage 112 to the pre-stored number of bins.

[0152] As yet another example, the processor 214 applies high-frequency levels HF1n to HF(N / 2)n determined during the third quarter of cycle 1 of voltage 112 to bins 1n to (N / 2)n of cycle 2 of voltage 112, but does not apply high-frequency levels HF1m to HFMm determined during the first half 112A of cycle 1 of voltage 112 to bins 1m to Mm of cycle 2, and does not apply high-frequency levels HF((N / 2)+1)n to HFNn determined during the fourth quarter of cycle 1 of voltage 112 to bins 1n to ((N / 2)+1)n of cycle 2 of voltage 112.

[0153] In one embodiment, a frequency level such as a high-frequency level includes one or more frequency values. For example, the frequency level includes a single frequency value. As another example, the frequency level includes a plurality of frequency values, and the frequency values of one frequency level exclude, are different from, are not the same as, or do not match the frequency values of another frequency level.

[0154] In one embodiment, instead of the power sensor 224, a voltage sensor (not shown) is used. When the voltage sensor is used instead of the power sensor 224, the processor 214 receives a measured value of voltage from the voltage sensor and calculates power based on the measured value.

[0155] Figure 3A is a schematic diagram of an embodiment of a system 300 for explaining the operation of an HF RF generator. The system 300 includes a host computer 212 and an HF RF generator. The HF RF generator includes a digital signal processor (DSP) and a power controller PWR. As an example, the controller includes memory devices such as a processor and registers. The processor is coupled to the registers.

[0156] The HF RF generator further includes an automatic frequency tuner (AFT) for bins 1n to Nn. Examples of the AFT used herein include a controller including a processor and a memory device. An example of the memory device of the AFT is a register. The HF RF generator includes an automatic frequency tuner AFTbin1m for bin 1m, an automatic frequency tuner AFTbin2m for bin 2m, and so on up to an automatic frequency tuner AFTbinMm for bin Mm. The HF RF generator includes an automatic frequency tuner AFTbin1n for bin 1n, an automatic frequency tuner AFTbin2n for bin 2n, and so on up to an automatic frequency tuner AFTbinNn for bin Nn.

[0157] The HF RF generator includes an HF power supply (PS) that is an RF oscillator. The RF oscillator is an electronic oscillator that generates an electronically oscillating signal such as a sine wave.

[0158] The DSP of the HF RF generator is coupled to the power controller PWR and is coupled to the automatic frequency tuners AFTbin1m to AFTbinNn of the HF RF generator. The power controller PWR and the automatic frequency tuners AFTbin1m to AFTbinNn are coupled to the HF power supply of the HF RF generator. The HF power supply is coupled to an RF cable 234B. The DSP is coupled to the processor 214 via a transfer cable 236B.

[0159] The processor 214 accesses the high-frequency levels HF1m to HFNn from Tables 240 and 242 (Figure 2) and transmits the high-frequency levels HF1m to HFNn to the DSP via the transfer cable 236B. Further, the processor 214 generates a digital pulse signal that is pulsed according to bins 1m to Mm during each cycle of the voltage 112, and transmits the digital pulse signal to the DSP via the transfer cable 236B. An example of the digital pulse signal is the digital pulse signal 310 shown in Figure 3B. Figure 3B is one embodiment of a graph 312 that plots the logic level of the digital pulse signal 310 against time t.

[0160] The digital pulse signal 310 has logic levels for each of bins 1m to Nn shown in Figure 1B-1. For example, the digital pulse signal 310 has a logic level L(N-1)n for bin (N-1)n in Figure 1B-1, another logic level LN for bin Nn in Figure 1B-1, another logic level L1m for bin 1m in Figure 1B-1, another logic level L2m for bin 2m in Figure 1B-1, and so on up to a logic level LM for bin Mm in Figure 1B-1. The logic level L(N-1)n occurs during the period between time t(N-2)n and time t(N-1)n.

[0161] Similarly, the logic level LNn occurs during the period between time t(N-1)n and time tNn, the logic level L1m occurs during the period between time tNn and time t1m, the logic level L2m occurs during the period between time t1m and time t2m, the logic level L3m occurs during the period between time t2m and time t3m, and the logic level L Mm occurs during the period between time t(M-1)m and time tMm. The logic levels L1m to LNn repeat during each cycle of the voltage 112. Each logic level during the cycle of the voltage 112 is a horizontal level and has a value different from another logic level during the cycle.

[0162] Another example of the digital pulse signal is the digital pulse signal 320 shown in Figure 3C. Figure 3C is one embodiment of a graph 322 that plots the logic level of the digital pulse signal 320 against time t.

[0163] The digital pulse signal 322 has logic levels for each of bins 1m to Nn shown in FIG. 1D-1. For example, the digital pulse signal 322 has a logic level L(N-1)n for bin (N-1)n in FIG. 1D-1, a logic level LN for bin Nn in FIG. 1D-1, a logic level L1m for bin 1m in FIG. 1D-1, a logic level L2m for bin 2m in FIG. 1D-1, and so on up to a logic level LM for bin Mm in FIG. 1D-1. The logic level L(N-1)n occurs during the period between time t(R-1)r and time tRr.

[0164] Similarly, the logic level LNn occurs during the period between time tRr and time t1q, the logic level L1m occurs during the period between time t1q and time t2q, the logic level L2m occurs during the period between time t2q and time t3q, the logic level L3m occurs during the period between time t3q and time t4q, and the logic level LMm occurs during the period between time t(Q-1)q and time tQq. The logic levels from L1m to LNn repeat during each cycle of voltage 112.

[0165] Referring back to FIG. 3A, the processor 214 also transmits information identifying the cycle of voltage 112 to the DSP via the transfer cable 236B. For example, the processor 214 transmits information identifying whether the cycle of voltage 112 is cycle 0, or cycle 1, or cycle 2. Further, the processor 214 transmits an instruction indicating the number of cycles of voltage 112 to which one or more of the frequency values HF1m to HFNn for a pre-stored number of bins are to be applied.

[0166] The DSP receives the high frequency levels HF1m to HFNn and transmits each of the high frequency levels HF1m to HFNn to the corresponding one of the automatic frequency tuners AFTbin1m to AFTbinNn. The DSP receives information identifying the cycle of voltage 112, an instruction indicating the number of cycles to which one or more of the frequency values HF1m to HFNn for a pre-stored number of bins are to be applied, and the digital pulse signal from the processor 214.

[0167] The DSP transmits the frequency levels HF1m through HFNn to the corresponding automatic frequency tuners AFT1m through AFTNn for storage. For example, the DSP transmits the frequency level HF1m to the automatic frequency tuner AFT1m to store it in the memory device of the automatic frequency tuner AFT1n, transmits the frequency level HFMm to the automatic frequency tuner AFTMm to store it in the memory device of the automatic frequency tuner AFTMm, and transmits the frequency level HFTNn to the automatic frequency tuner AFTNn to store it in the memory device of the automatic frequency tuner AFTNn.

[0168] Upon receiving information regarding the digital pulse signal and the cycle of voltage 112, the DSP determines the logic level of the digital pulse signal and identifies the cycle of the voltage. For example, the DSP determines whether there is a match between the logic level LN and a previously stored logic level, which is also LN, in the memory device of the DSP. If there is a match, the DSP determines that the logic level of the digital pulse signal is LN. As another example, the DSP determines whether there is a match between the logic level LM and a previously stored logic level, which is also LM, in the memory device of the DSP. If there is a match, the DSP determines that the logic level of the digital pulse signal is LM.

[0169] After determining the logic level and identifying the cycle of voltage 112, the DSP transmits a control signal to the corresponding AFT of the HF RF generator during the period of the logic level for the number of cycles received in the instruction from the processor 214. For example, the DSP transmits a control signal to the automatic frequency tuner AFT1m during bin 1m of cycle 2, and transmits another control signal to the automatic frequency tuner AFTMm during bin Mm of cycle 2. Similarly, the DSP transmits a control signal to the automatic frequency tuner AFT1n during bin 1n of cycle 2, and transmits a control signal to the automatic frequency tuner AFTNn during bin Nn of cycle 2.

[0170] From the automatic frequency tuner AFT1m to AFTNn, each provides a corresponding value among the high-frequency values HF1m to HFNn to the HF power supply in the corresponding bin among bins 1m to Nn. For example, in response to a control signal from the DSP, the automatic frequency tuner AFT1m provides the high-frequency level HF1m to the HF power supply in bin 1m of cycle 2, and the automatic frequency tuner AFTMm provides the high-frequency level HFMm to the HF power supply in bin Mm of cycle 2. Also, in response to a control signal from the DSP, the automatic frequency tuner AFT1n provides the high-frequency level HF1n to the HF power supply in bin 1n of cycle 2, and the automatic frequency tuner AFTNn provides the high-frequency level HFNn to the HF power supply in bin Nn of cycle 2.

[0171] The HF power supply generates an RF signal 218B having each of the frequencies from 1m to Nn during the period of the corresponding bin among bins 1m to Nn. For example, when receiving the high-frequency level HF1m in bin 1m of cycle 2, the HF power supply generates a part of the RF signal 218B in bin 1m of cycle 2 of voltage 112, and that part of the RF signal 218B has the high-frequency level HF1m.

[0172] Similarly, when receiving the high-frequency level HFMm in bin Mm of cycle 2, the HF power supply generates a part of the RF signal 218B in bin Mm of cycle 2 of voltage 112, and that part of the RF signal 218B has the high-frequency level HFMm.

[0173] Also, when receiving the high-frequency level HF1n in bin 1n of cycle 2, the HF power supply generates a part of the RF signal 218B in bin 1n of cycle 2 of voltage 112, and that part of the RF signal 218B has the high-frequency level HF1n.

[0174] Similarly, when receiving the high-frequency level HFNn in bin Nn of cycle 2, the HF power supply generates a part of the RF signal 218B in bin Nn of cycle 2 of voltage 112, and that part of the RF signal 218B has the high-frequency level HFNn.

[0175] Also, the DSP receives one or more power levels from the processor 214 via the transfer cable 236B and transmits the one or more power levels to the power controller PWR. The power controller PWR provides the one or more power levels to the HF power supply. Upon receiving the one or more power levels, the HF power supply generates an RF signal 218B having the one or more power levels.

[0176] In one embodiment, one or more of the automatic frequency tuners AFT1m through AFTNn are integrated into a single automatic frequency tuner. In one embodiment, one or more of the automatic frequency tuners AFT1m through AFTNn are part of the DSP.

[0177] FIG. 4 is a schematic diagram of one embodiment of a system 400 for explaining the control of an auxiliary capacitor C3 of an impedance matching circuit (IMC) for modifying a frequency within a high frequency range to control the power transmitted by an HF RF generator. The system 400 includes an LF RF generator, an HF RF generator, a power sensor 224, a processor 214, an IMC, a motor 1, a motor 2, a motor 3, a drive system 1, a drive system 2, a drive system 3, and a voltage divider 402. The LF RF generator includes an LF power supply (PS) that is an RF oscillator. The LF power supply is coupled to an RF cable 234A (FIG. 2).

[0178] Examples of each of the motors 1, 2, and 3 include an electric motor including a stator and a rotor. Examples of each of the drive systems described herein include one or more transistors.

[0179] The IMC includes a main circuit and an auxiliary matching circuit. The main matching circuit includes branch circuit 406A and branch circuit 406B. Branch circuit 406A includes one or more electrical components including capacitor C1, and branch circuit 406B includes one or more electrical components including capacitor C2. Each of capacitors C1 and C2 is a series capacitor. Branch circuit 406A is an example of a first branch circuit, and branch circuit 406B is an example of a second branch circuit. Also, the auxiliary matching circuit includes one or more electrical components including capacitor C3. Each of capacitors C1 to C3 is a variable capacitor.

[0180] Each motor is connected to the corresponding capacitor of the IMC by a corresponding connection part such as one or more rods or a combination of a plurality of rods and one or more gears. For example, motor 1 is connected to the plate of capacitor C1 via connection part 404A, motor 2 is connected to the plate of capacitor C2 via connection part 404B, and motor 4 is connected to the plate of capacitor C3 via connection part 404C.

[0181] Voltage divider 402 is an example of voltage sensor 204 (Figure 2). Voltage divider 402 includes resistor R1 and resistor R2, and the two resistors R1 and R2 are coupled in series with each other.

[0182] Before dividing voltage 112 into bins, processor 214 sets the capacitance values of capacitors C1 and C2. For example, based on a predetermined capacitance of capacitor C1, processor 214 transmits a control signal to drive system 1. When drive system 1 receives the control signal, it generates a current signal and transmits this current signal to motor 1. Motor 1 operates to change the capacitance of capacitor C1 to the predetermined capacitance. Motor 1 operates to move the plate of capacitor C1 relative to the opposing plate of capacitor C1 to achieve the predetermined capacitance.

[0183] Similarly, as another example, the processor 214 transmits a control signal to the drive system 2 based on a predetermined capacitance of the capacitor C2. When receiving the control signal, the drive system 2 generates a current signal and transmits the current signal to the motor 2. The motor 2 operates to change the capacitance of the capacitor C2 to the predetermined capacitance. The motor 2 operates to move the plate of the capacitor C2 relative to the facing plate of the capacitor C2 to achieve the predetermined capacitance.

[0184] When the predetermined capacitances of the capacitors C1 and C2 are set, the processor 214 divides the voltage 112 into bins, determines the frequency values for the bins, and further controls the transmitted power in the output 230B of the HF RF generator.

[0185] Also, the processor 214 controls the capacitor C3 of the auxiliary matching circuit to control the transmitted power in the output 230B of the HF RF generator. For example, the processor 214 receives a measured value of the transmitted power in the output 230B from the power sensor 224 via the transfer cable 236D. The processor 214 determines the statistical power value of the transmitted power for a pre-stored number of bins from the measured value in the same manner as above, compares the statistical power value with a predetermined statistical power value, and determines that the predetermined statistical power value of the transmitted power for the pre-stored number of bins is not achieved. If it is determined that it is not achieved, the processor 214 transmits a control signal to the drive system 3. When receiving the control signal, the drive system 3 generates a current signal and transmits the current signal to the motor 3. The motor 3 operates to change the capacitance of the capacitor C1. The motor 3 operates to move the plate of the capacitor C3 relative to the facing plate of the capacitor C3 to achieve the capacitance. The processor 214 continues to control the capacitor C3 in such a manner until the predetermined statistical power value of the transmitted power for the pre-stored number of bins is achieved.

[0186] Note that the capacitance of capacitor C3 is controlled simultaneously while controlling the HF RF generator to operate at the high frequency values in Tables 240 and 242. By controlling capacitor C3 to achieve a predetermined statistical power value of the transmitted power for a pre-stored number of bins, the generation of the voltage at the output 206 of the IMC is facilitated. When the voltage is generated at the output 206, one or more of the frequency levels HF1m to HFNn are applied from the HF RF generator through the IMC to the plasma chamber 220 for a pre-stored number of bins, making it easier to achieve the uniformity level UNFM.

[0187] In one embodiment, the capacitance of capacitor C3 is controlled before controlling the HF RF generator to operate at the high frequency values in Tables 240 and 242. In one embodiment, the capacitance of capacitor C3 is controlled after controlling the HF RF generator to operate at the high frequency values in Tables 240 and 242.

[0188] FIG. 5 is an embodiment of a graph 500 showing the change in uniformity in the etching rate when high frequency values for a pre-stored number of bins are applied. In graph 500, the etching rate measured in angstroms (Å) per minute (min) is plotted along the Y-axis, and the radius R of the substrate S is plotted along the X-axis. Graph 500 includes a plurality of plots 502, 504, 506, and 508 for different uniformities. Plot 508 shows a higher level of uniformity than the uniformity shown by plot 506. Similarly, plot 506 shows a higher level of uniformity than the uniformity shown by plot 504, and plot 504 shows a higher level of uniformity than the uniformity shown by plot 502.

[0189] By controlling the frequency level of the HF RF generator in a pre-stored number of bins, the uniformity regarding the etching rate across the substrate S is changed from the uniformity shown by plot 502 to the uniformity shown by plot 508. For example, by controlling the frequency level of the HF RF generator to be in the range from HF1m to HFNn during the cycles 2 and later of voltage 112, the uniformity regarding the etching rate is increased from the uniformity shown by plot 502 to the uniformity shown by plot 508.

[0190] In one embodiment, the frequency level of the HF RF generator is controlled in a pre-stored number of bins so as to decrease from the uniformity shown by plot 508 to the uniformity shown by any of plots 502, 504, and 506.

[0191] FIG. 6A is one embodiment of graph 100.

[0192] FIG. 6B is one embodiment of graph 600 for showing that the transmitted power increases by applying the high-frequency values of tables 240 and 242. In graph 600, voltage is plotted on the Y-axis and time t is plotted on the X-axis. The voltage envelopes of the forward power measured by the directional coupler coupled to the output 230B of the HF RF generator (FIG. 2) are shown by plots 602A and 602B, and the voltage envelopes of the reflected power measured by the directional coupler coupled to the output 230B are shown by plots 604A and 604B. Plots 602A and 602B are those of the voltage envelopes showing the supply power at the output of the HF RF generator, and plots 604A and 604B are those of the voltage envelopes showing the reflected power at the output of the HF RF generator. As shown in FIGS. 6A and 6B, an increase in the reflected power is seen after time t2 and after time t4. The reflected power increases as a result of the voltage 112 of the LF RF generator decreasing during each cycle of voltage 112. By controlling the HF RF generator to achieve high-frequency values for a pre-stored number of bins, the reflected power at the output 230B decreases and the transmitted power at the output 230B increases.

[0193] The embodiments described in this specification may be implemented in various computer system configurations including a handheld hardware unit, a microprocessor system, a microprocessor-based or programmable household appliance, a minicomputer, a mainframe computer, and the like. The embodiments may also be implemented in a distributed computing environment where tasks are performed by remote processing hardware units linked via a network.

[0194] In some embodiments, the controller is part of the system and may be part of the above examples. Such systems include semiconductor processing apparatuses including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (such as a wafer pedestal, a gas flow system, etc.). These systems are integrated with electronics for controlling the operation of the system before, during, and after the processing of a semiconductor wafer or substrate. The electronics are referred to as a "controller", and the controller may control various components or sub-components of one or more systems. The controller is programmed to control any of the processes disclosed herein, including the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and motion settings, the loading and unloading of wafers to and from tools and other transfer tools coupled to or interlocked with the system, and / or load locks, depending on the processing requirements and / or the type of system.

[0195] In a broad sense, in various embodiments, a controller is defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, and so on. The integrated circuits include a chip that stores program instructions in the form of firmware, a digital signal processor (DSP), a chip defined as an ASIC, a PLD, and / or one or more microprocessors, or a microcontroller that executes program instructions (e.g., software). The program instructions are communicated to the controller in the form of various individual settings (or program files) and are instructions that define parameters, coefficients, variables, etc. for performing a specific process on or for a semiconductor wafer or for a system. In some embodiments, the program instructions are part of a recipe defined by a process engineer to achieve one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of the wafer.

[0196] In some embodiments, the controller is part of a computer or is coupled to a computer, and such computer is integrated with the system, coupled to the system, network-connected to the system in some other way, or coupled to the system in combinations thereof. For example, the controller is present within the "cloud" or is all or part of a fab host computer system, thereby enabling remote access to wafer processing. The computer enables remote access to the system to monitor the current progress of the fabrication operation, examine the history of past fabrication operations, or examine trends or performance metrics from multiple fabrication operations to change the parameters of the current process, set the processing steps following the current process, or initiate a new process.

[0197] In some embodiments, a remote computer (e.g., a server) provides a process recipe to the system via a network, which may include a local network or the Internet. The remote computer includes a user interface that enables the input or programming of parameters and / or settings, and such parameters and / or settings are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data, and the instructions specify parameters, coefficients, and / or variables for each processing step to be performed during one or more operations. It should be understood that the parameters, coefficients, and / or variables are specific to the type of process being performed and the type of tool that the controller is configured to interact with or control. Thus, as described above, the controller may be distributed, such as by including one or more separate controllers that are network-connected to each other and cooperate towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such a purpose is one or more integrated circuits in a chamber that are located remotely (e.g., at the platform level or as part of a remote computer) and communicate with one or more integrated circuits in the chamber to jointly control the process in the chamber.

[0198] Without limitation, in various embodiments, example systems to which the method is applied include a plasma etching chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etching chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etching (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing system related to or used in the fabrication and / or manufacture of semiconductor wafers.

[0199] In some embodiments, it should be further noted that the above operations are applicable to several types of plasma chambers, such as plasma chambers including inductively coupled plasma (ICP) reactors, transformer-coupled plasma chambers, conductor tools, dielectric tools, plasma chambers including electron cyclotron resonance (ECR) reactors, etc. For example, one or more RF generators are coupled to an inductor within an ICP reactor. Examples of the shape of the inductor include a solenoid, a dome-shaped coil, a flat-shaped coil, and the like.

[0200] As described above, depending on one or more process steps performed by a tool, the host computer communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, proximate tools, tools installed throughout the factory, a main computer, another controller, or a tool used in material handling for loading and unloading a wafer container with respect to a tool position and / or a load port in a semiconductor manufacturing factory.

[0201] With the above embodiments in mind, some of the embodiments should be understood to use various computer-implemented operations with data stored in a computer system. These operations are operations that physically manipulate physical quantities. All operations described herein that constitute part of the embodiments are useful mechanical operations.

[0202] Also, some of the embodiments relate to hardware units or devices for performing these operations. The device is specially constructed for a dedicated computer. When defined as a dedicated computer, the computer is operable for its dedicated purpose while performing other processes, program executions, or routines that are not part of its dedicated purpose.

[0203] In some embodiments, the operations may be processed by a computer selectively activated or configured by one or more computer programs stored in a computer memory, cached, or obtained via a computer network. When data is obtained via a computer network, the data may be processed by another computer on the computer network, such as a cloud of computing resources.

[0204] Also, one or more embodiments may be implemented as computer-readable code on a non-transitory computer-readable medium. The non-transitory computer-readable medium is any data storage hardware unit that stores data, such as a memory device, etc., and the data is then read by a computer system. Examples of non-transitory computer-readable media include hard drives, network-attached storage (NAS), ROM, RAM, compact disc ROM (CD-ROM), CD recordable (CD-R), CD rewritable (CD-RW), magnetic tape, and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer-readable medium includes computer-readable tangible media distributed on a network-coupled computer system such that the computer-readable code is stored and executed in a distributed manner.

[0205] Although the method operations have been described in a particular order, in various embodiments, it should be understood that other housekeeping operations are performed between each operation, or each method operation is adjusted to occur at slightly different times, or each method operation is distributed across a system that allows it to occur at various intervals, or is performed in an order different from the above order.

[0206] It should be further noted that in one embodiment, one or more features from any of the above embodiments may be combined with one or more features from any of the other above embodiments without departing from the scope described in the various embodiments described in this disclosure.

[0207] Also, in one embodiment, it should be noted that one or more features from any of the above-described embodiments may be combined with one or more features from any of the other above-described embodiments without departing from the scope described in the various embodiments described in the present disclosure.

[0208] Also, in one embodiment, it should be noted that one or more features from any of the above-described embodiments may be combined with one or more features from any of the above-described embodiments without departing from the scope described in the various embodiments described in the present disclosure.

[0209] Although the foregoing embodiments have been described in some detail for clarity of understanding, it will be apparent that certain changes and modifications can be made within the scope of the appended claims. Accordingly, the present embodiments are to be regarded as illustrative and not restrictive, and the present embodiments are not limited to the details described herein.

Claims

1. 1. A method for achieving uniformity in etch rate, comprising: receiving a voltage signal from an output of the matching section; determining positive and negative crossing points of the voltage signal for each cycle of the voltage signal, the negative crossing point of each cycle being consecutive with the positive crossing point of the cycle; dividing a time interval of each cycle of the voltage signal into a number of bins; adjusting a frequency of a radio frequency generator to achieve the uniformity in the etch rate for one or more of the plurality of bins associated with the positive intersection point and for one or more of the plurality of bins associated with the negative intersection point. The method includes:

2. 2. The method of claim 1, wherein determining the positive intersections comprises: determining a point at which the voltage signal is at a predetermined value; and determining that the value of the voltage signal increases after the voltage signal has reached the predetermined value as compared to a time before the voltage signal has reached the predetermined value; The method includes:

3. 2. The method of claim 1, wherein determining the negative intersection point comprises: determining a point at which the voltage signal is at a predetermined value; and determining that the value of the voltage signal decreases after the voltage signal has reached the predetermined value as compared to a time before the voltage signal has reached the predetermined value; The method includes:

4. 2. The method of claim 1, wherein one or more of the plurality of bins associated with the positive intersection point comprises a predetermined number of bins, one of the predetermined number of bins including the positive intersection point.

5. 2. The method of claim 1, wherein one or more of the plurality of bins associated with the negative intersection point comprises a predetermined number of bins, and one of the predetermined number of bins includes the negative intersection point.

6. 1. A method for achieving uniformity in etch rate, comprising: receiving a voltage signal from an output of the matching section; determining positive and negative crossing points of the voltage signal for each cycle of the voltage signal, the negative crossing point of each cycle being consecutive with the positive crossing point of the cycle; dividing a time interval of each cycle of the voltage signal, the time interval beginning at a time proximate the positive crossing point and ending at a time proximate the negative crossing point, into a number of bins; adjusting a frequency of a first radio frequency generator to achieve said uniformity in said etch rate for one or more of said plurality of bins. The method includes:

7. 7. The method of claim 6, wherein determining the positive intersections comprises: determining a point at which the voltage signal is at a predetermined value; and determining that the value of the voltage signal increases after the voltage signal has reached the predetermined value as compared to a time before the voltage signal has reached the predetermined value; The method includes:

8. 7. The method of claim 6, wherein determining the negative intersection point comprises: determining a point at which the voltage signal is at a predetermined value; and determining that the value of the voltage signal decreases after the voltage signal has reached the predetermined value as compared to a time before the voltage signal has reached the predetermined value; The method includes:

9. 7. The method of claim 6, wherein the time proximate to a positive intersection is the time at which the positive intersection occurs and the time proximate to a negative intersection is the time at which the negative intersection occurs.

10. 7. The method of claim 6, wherein the time proximate to the positive intersecting point is a time that is within a first predetermined range before the time the positive intersecting point occurs, and the time proximate to the negative intersecting point is a time that is within a second predetermined range after the time the negative intersecting point occurs.

11. The method of claim 6 , wherein each of the plurality of bins is of equal duration.

12. 7. The method of claim 6, wherein the voltage signal is received from a voltage sensor coupled to the output of the matching section, the output of the matching section being coupled to an input of a plasma chamber via a radio frequency transmission line.

13. 7. The method of claim 6, wherein each cycle includes an early portion and a later portion, the early portion coinciding with a period during which a voltage of a plasma sheath reaches its highest point and the later portion coinciding with a period during which the voltage of the plasma sheath reaches its lowest point.

14. 7. The method of claim 6, wherein the plurality of bins includes a first bin and a second bin, the first radio frequency generator has a higher operating frequency compared to a second radio frequency generator, the cycle corresponds to an operation of the second radio frequency generator, and adjusting the frequency comprises: varying the first value of the frequency during the first bin to achieve a second value; and Varying the second value of the frequency during the second bin to achieve a third value. A method comprising:

15. 15. The method of claim 14, wherein the cycle of the voltage signal includes a first cycle and a second cycle, the first value is changed to achieve the second value during the first bin of the second cycle, and the second value is changed to achieve the third value during the second bin of the second cycle.

16. 15. The method of claim 14, receiving a first measurement of a transmitted power, the first measurement associated with the first bin, the first measurement received from a sensor coupled to an output of the first radio frequency generator; receiving a second measurement of the delivered power, the second measurement being associated with the second bin; Varying the first value of the frequency includes increasing or decreasing the first value of the frequency to decrease the first measurement value; The method, wherein varying the second value of the frequency includes increasing or decreasing the second value of the frequency so as to decrease the second measurement value.

17. 17. The method of claim 16, wherein the decrease in the first and second measurements facilitates achieving the uniformity in the etch rate.

18. 1. A controller for achieving uniformity in etch rate, comprising:

1. A processor comprising: receiving a voltage signal from the output of the matching section; determining positive and negative crossings of the voltage signal for each cycle of the voltage signal, the negative crossings of each cycle being contiguous with the positive crossings of the cycle; Dividing a time interval of each cycle of the voltage signal, the time interval beginning at a time proximate to the positive crossing point and ending at a time proximate to the negative crossing point, into a number of bins; adjusting a frequency of a radio frequency generator to achieve said uniformity in the etch rate for one or more of said plurality of bins. A processor comprising: a memory device coupled to the processor; Including, the controller.

19. 20. The controller of claim 18, wherein to determine the negative intersection point, the processor comprises: determining a point at which the voltage signal is at a predetermined value; The controller is configured to determine an increase in value of the voltage signal a time after the voltage signal is at the predetermined value compared to a time before the voltage signal is at the predetermined value.

20. 20. The controller of claim 18, wherein to determine the negative intersection point, the processor comprises: determining a point at which the voltage signal is at a predetermined value; The controller is configured to determine that the voltage signal decreases in value a time after the voltage signal is at the predetermined value compared to a time before the voltage signal is at the predetermined value.

21. 20. The controller of claim 18, wherein the time approaching a positive crossing is a time at which the positive crossing occurs and the time approaching a negative crossing is a time at which the negative crossing occurs.

22. 20. The controller of claim 18, wherein the time approaching the positive intersecting point is a time that is within a first predetermined range before the time the positive intersecting point occurs, and the time approaching the negative intersecting point is a time that is within a second predetermined range after the time the negative intersecting point occurs.

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