Semiconductor device

Abstract

To provide a semiconductor device that can suppress leak current more.SOLUTION: A semiconductor device includes a semiconductor substrate, a first semiconductor region formed in the semiconductor substrate, a second semiconductor region surrounding the first semiconductor region in a plan view, a first conductive layer formed on the first semiconductor region, a first electrode formed on the first conductive layer, a cathode region connected to the first electrode through the first conductive layer, a second conductive layer in contact with the first semiconductor region, a second electrode formed on the second conductive layer, and a first region disposed between the cathode region and a region, out of the first semiconductor region, that is in contact with the first conductive layer in a direction along an upper surface of the semiconductor substrate and in contact with a lower surface of the second conductive layer. The depth of the first region is larger than the depth of the cathode region. Each of the semiconductor substrate, the second semiconductor region, and the first region has a first conductivity type. Each of the first semiconductor region and the cathode region has a second conductivity type opposite to the first conductivity type.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device including a Schottky barrier diode.

Background Art

[0002] A Schottky barrier diode (SBD) is a rectifying element that utilizes the Schottky barrier generated by the junction of a metal and a semiconductor. The Schottky barrier diode has lower forward voltage characteristics and faster switching speed compared to a diode that utilizes a PN junction. On the other hand, there is a problem that the leakage current of the Schottky barrier diode is larger than the leakage current of a diode that utilizes a PN junction.

[0003] Patent Document 1 discloses an SBD including a semiconductor region having a first conductivity type, an anode electrode, a guard ring having a second conductivity type formed along the periphery of the anode electrode, a separation insulating film that separates the anode electrode around the guard ring, and a mask for the anode electrode. By adopting such a configuration, it becomes possible to reduce the reverse leakage current of the SBD.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the reverse bias state of the Schottky barrier diode, not only does the electric field concentrate at the corner of the Schottky electrode, but the electric field may reach directly below the Schottky electrode. The generation of such an electric field causes a tunneling leakage current.

[0006] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0007] In the present disclosure, a semiconductor device includes a semiconductor substrate having an upper surface, a first semiconductor region formed in the semiconductor substrate, a second semiconductor region formed in the semiconductor substrate and surrounding the first semiconductor region in a plan view, a first conductive layer formed on the first semiconductor region, a first electrode formed on the first conductive layer, a cathode region formed in the first semiconductor region and connected to the first electrode via the first conductive layer, a second conductive layer formed on the first semiconductor region and in contact with the first semiconductor region, a second electrode formed on the second conductive layer, and a first region formed in the first semiconductor region and disposed between a region in contact with the second conductive layer and the cathode region of the first semiconductor region in a direction along the upper surface of the semiconductor substrate and in contact with the lower surface of the second conductive layer. When the upper surface of the semiconductor substrate is used as a reference plane, the depth of the first region is greater than the depth of the cathode region. The semiconductor substrate, the second semiconductor region, and the first region each have a first conductivity type. The first semiconductor region and the cathode region each have a second conductivity type opposite to the first conductivity type.

Advantages of the Invention

[0008] According to the present disclosure, a semiconductor device capable of further suppressing leakage current can be provided.

Brief Description of the Drawings

[0009]

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Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the specification and drawings, the same reference numerals are given to the same or corresponding components, and redundant descriptions are omitted. In the drawings, for convenience of explanation, the configuration may be omitted or simplified in some cases. Also, at least a part of each embodiment may be arbitrarily combined with each other.

[0011] In the semiconductor device of the present disclosure, the conductivity type (p-type or n-type) of components such as a semiconductor substrate, a semiconductor region, a diffusion region, and a transistor may be inverted. Therefore, when one of the n-type and p-type conductivity types is defined as the first conductivity type and the other of the n-type and p-type conductivity types is defined as the second conductivity type, the first conductivity type can be p-type and the second conductivity type can be n-type, or conversely, the first conductivity type can be n-type and the second conductivity type can be p-type.

[0012] The impurity concentration of a component included in the semiconductor device of the present disclosure refers to the peak value in the measured region of the component. Also, when comparing the impurity concentrations of two components, the description "about the same" does not only mean being exactly the same. Even if the impurity concentrations of two components differ due to manufacturing variations, if the set values of the impurity concentrations of the two components are the same, the impurity concentrations of the two components are considered to be the same as each other.

[0013] <Embodiment 1> As shown in FIG. 1, the semiconductor device 1 includes a semiconductor substrate 10 having a first conductivity type and a plurality of regions formed in and on the semiconductor substrate 10. FIGS. 2 to 4 are cross-sectional views showing modified examples of the semiconductor device 1, respectively.

[0014] Examples of the semiconductor device 1 include a semiconductor chip including a Schottky barrier diode, a semiconductor wafer, and a package in which these are mounted inside.

[0015] The semiconductor substrate 10 has an upper surface 11 and a lower surface 12. Hereinafter, unless otherwise specified, the components included in the semiconductor device 1 shown in FIG. 1 are formed on the upper surface 11 of the semiconductor substrate 10.

[0016] An embedded region 110 having a second conductivity type opposite to the first conductivity type is formed in the semiconductor substrate 10. The embedded region 110 is formed, for example, by introducing impurities indicating the second conductivity type into the semiconductor substrate 10.

[0017] A first semiconductor region 100 is formed within the semiconductor substrate 10 and above the embedded region 110. The first semiconductor region 100 includes a first semiconductor layer 101 having a second conductivity type and a second semiconductor layer 102 having a first conductivity type located below the first semiconductor layer 101. The impurity concentration of the first semiconductor region 100 is lower than, for example, the impurity concentration of the semiconductor substrate 10 and is equal to or less than the impurity concentration of the embedded region 110. Also, the impurity concentrations of the first semiconductor layer 101 and the second semiconductor layer 102 are, for example, approximately the same as each other.

[0018] A cathode region 103 having a second conductivity type is formed within the first semiconductor layer 101 of the first semiconductor region 100. The cathode region 103 is formed on the upper surface of the first semiconductor layer 101. The cathode region 103 is electrically connected to a first electrode 51 which is a contact plug formed on the cathode region 103. The impurity concentration of the cathode region 103 is, for example, higher than that of the first semiconductor layer 101.

[0019] The above-described first electrode 51 is disposed above the cathode region 103. A first conductive layer 50 is formed between the cathode region 103 and the first electrode 51, and the cathode region 103 is connected to the first electrode 51 via the first conductive layer 50.

[0020] A first region 104 is formed within the first semiconductor layer 101 of the first semiconductor region 100. The first region 104 is disposed between the region in contact with the second conductive layer 60 and the cathode region 103 in the first semiconductor region 100 in the direction along the upper surface 11 of the semiconductor substrate 10. The first region 104 is formed by introducing impurities showing a first conductivity type into the first semiconductor layer 101. The impurity concentration of the first region 104 is, for example, higher than the impurity concentration of the first semiconductor region 100 and is equal to or less than the impurity concentration of the cathode region 103. Also, when the upper surface 11 of the semiconductor substrate 10 is used as a reference plane, the depth of the first region 104 is greater than the depth of the cathode region 103. Note that even when the upper surface of the first semiconductor region 100 is used as a reference plane, the depth of the first region 104 is greater than the depth of the cathode region 103.

[0021] The second semiconductor region 120 is located within the semiconductor substrate 10 and above the buried region 110, and is formed so as to surround the first semiconductor region 100 in a plan view. The second semiconductor region 120 has a first conductivity type, and the impurity concentration of the second semiconductor region 120 is, for example, about the same as the impurity concentration of the first semiconductor region 100.

[0022] Within the second semiconductor region 120, an anode region 123 having a first conductivity type is formed. The anode region 123 is formed on the upper surface of the second semiconductor region 120. The anode region 123 is electrically connected to a second electrode 61 which is a contact plug formed on the anode region 123. The impurity concentration of the anode region 123 is, for example, higher than that of the second semiconductor region 120.

[0023] The above-described second electrode 61 is disposed on the anode region 123. Also, in a plan view, the second electrode 61 is disposed so as to overlap the anode region 123. A second conductive layer 60 is formed between the anode region 123 and the second electrode 61, whereby the anode region 123 is connected to the second electrode 61.

[0024] The second conductive layer 60 is formed on the semiconductor substrate so as to be in contact with the first semiconductor region 100 and the first region 104. Also, an insulating layer 40 is formed between the second conductive layer 60 and the first conductive layer 50. The second conductive layer 60 and the first conductive layer 50 are electrically insulated from each other by the insulating layer 40.

[0025] The third semiconductor region 130 is located within the semiconductor substrate 10 and above the buried region 110, and is formed so as to surround the first semiconductor region 100 and the second semiconductor region 120 in a plan view. The third semiconductor region 130 has a second conductivity type, and the impurity concentration of the third semiconductor region 130 is, for example, about the same as the impurity concentration of the first semiconductor region 100 and the impurity concentration of the second semiconductor region 120.

[0026] In the third semiconductor region 130, a contact region 133, which is a second region having a second conductivity type, is formed. Further, a third conductive layer 70, which is an electrode pad, is formed on the contact region 133 so as to be in contact with the contact region 133. The impurity concentration of the contact region 133 is higher than that of the third semiconductor region 130, for example. A third electrode (not shown) is formed on the third conductive layer 70, and the contact region 133 is connected to the third electrode via the third conductive layer 70.

[0027] The fourth semiconductor region 140 is formed in the semiconductor substrate 10 and is formed so as to surround the first semiconductor region 100, the second semiconductor region 120, and the third semiconductor region 130 in a plan view. The fourth semiconductor region 140 has a first conductivity type, and the impurity concentration of the fourth semiconductor region 140 is, for example, on the same order as the impurity concentration of the first semiconductor region 100, the impurity concentration of the second semiconductor region 120, and the impurity concentration of the third semiconductor region 130.

[0028] In the fourth semiconductor region 140, a ground region 143 having a first conductivity type is formed. Further, a fourth conductive layer 80, which is an electrode pad, is formed on the ground region 143 so as to be in contact with the ground region 143. The impurity concentration of the ground region 143 is higher than that of the fourth semiconductor region 140, for example.

[0029] The buried insulating layer 30 is formed in the semiconductor substrate 10. The buried insulating layer 30 is disposed between the second conductive layer 60 and the third conductive layer 70 and between the third conductive layer 70 and the fourth conductive layer 80 in a plan view. The buried insulating layer 30 is formed by forming grooves in the semiconductor substrate 10 for the conductive films that will become the first conductive layer 50, the second conductive layer 60, the third conductive layer 70, and the fourth conductive layer 80, and then embedding an insulating film in the grooves.

[0030] In the semiconductor device 1 of the first embodiment, a Schottky barrier is formed between the first semiconductor region 100 and the second conductive layer 60, and the first semiconductor region 100 and the second conductive layer 60 constitute a Schottky barrier diode having the current path 20 shown in FIG. 1. Compared with the case where the first region 104 is not formed, the current path 20 is located away from the upper surface 11 by the first region 104 formed in the first semiconductor layer 101 of the first semiconductor region 100. Therefore, the current path 20 is narrowed by the first region 104.

[0031] Thereby, it becomes possible to relax the electric field concentrated at the corner of the second conductive layer 60 which is a Schottky electrode during reverse bias, and further relax the electric field extending to directly below the second conductive layer 60, so that the tunneling leakage current can be suppressed.

[0032] Next, a modified example of the semiconductor device 1 of the first embodiment will be described. Note that the repeated description may be omitted for those that are the same as the configuration example of the first embodiment.

[0033] FIG. 2 shows a modified example of the first region 104 formed in the first semiconductor layer 101 of the first semiconductor region 100. The first region 104 surrounded by the dotted line in FIG. 2 has a first portion 105 and a second portion 106. Also, in a plan view, the first portion 105 is formed so as to surround the second portion 106.

[0034] The first portion 105 is formed by introducing impurities showing the first conductivity type, similar to the first region 104 in FIG. 1. The impurity concentration of the first portion 105 is higher than, for example, the impurity concentration of the first semiconductor region 100.

[0035] Similar to the first portion 105, the second portion 106 is formed by introducing impurities of the first conductivity type. The impurity concentration of the second portion 106 is, for example, higher than that of the first portion 105. Also, when the upper surface 11 of the semiconductor substrate 10 is used as a reference plane, the depth of the second portion 106 is greater than the depth of the cathode region 103. Note that even when the upper surface of the first semiconductor region 100 is used as a reference plane, the depth of the second portion 106 is greater than the depth of the cathode region 103. With such a configuration, the second portion 106 functions as a potential barrier, and the current path 20 can be positioned away from the upper surface of the semiconductor substrate 10 as compared with the case where the first region 104 is not formed. Therefore, the current path 20 is narrowed by the second portion 106.

[0036] Furthermore, the first portion 105 has an offset region 107 that separates the second portion 106 from the cathode region 103 in a direction along the upper surface 11 of the semiconductor substrate 10. If only the second portion 106 is formed in the first semiconductor layer 101, an electric field may concentrate at the interface between the second portion 106 and the first semiconductor layer 101. Therefore, by providing the first portion 105 having the offset region 107, it becomes possible to secure a breakdown voltage.

[0037] FIG. 3(a) shows an application example of the semiconductor device 1 shown in FIG. 1, and FIG. 3(b) shows an application example of the semiconductor device 1 shown in FIG. 2. FIGS. 3(a) and 3(b) show a layout in which the second conductive layer 60, which is a Schottky electrode, is located inside the first electrode 51, which is a cathode electrode, as compared with FIGS. 1 and 2. Even in such a configuration, it is possible to relax the electric field between the second conductive layer 60 and the first electrode 51 during reverse bias. Therefore, the semiconductor device 1 of the first embodiment is not limited to the layout of the Schottky electrode and the cathode electrode. Also, a first conductive layer 50 may be formed between the cathode region 103 and the first electrode 51.

[0038] FIG. 4 is a diagram showing the simulation results of the electric field strength distribution of the semiconductor device when a reverse bias is applied. FIG. 4(a) is a diagram showing the potential distribution of the semiconductor device 1 having no first region 104 as a comparative example. FIG. 4(b) is a diagram showing the potential distribution of the semiconductor device 1 shown in FIG. 1, and FIG. 4(c) is the potential distribution of the semiconductor device 1 shown in FIG. 2.

[0039] In the comparative example, as shown by the dotted line portion in FIG. 4(a), it can be seen that an electric field concentrated at the corner of the second conductive layer 60 which is a Schottky electrode and an electric field extending to directly below the second conductive layer 60 are observed. On the other hand, in the semiconductor device 1 of the first embodiment, as shown by the dotted line portions in FIGS. 4(b) and 4(c), it can be seen that the electric field is relaxed.

[0040] FIG. 5 is a diagram showing the correlation between the leakage current and the drive voltage. FIG. 5 shows the simulation results (TCAD) of the semiconductor device of the comparative example, the simulation results (Structure-1) of the semiconductor device of FIG. 1, and the simulation results (Structure-2) of the semiconductor device of FIG. 2. The horizontal axis of FIG. 5 indicates the drive voltage Vf, and the vertical axis of FIG. 5 indicates the leakage current Ir.

[0041] It can be seen that the leakage current Ir is suppressed in each of the semiconductor devices of FIGS. 1 and 2 as compared with the semiconductor device of the comparative example. On the other hand, in the semiconductor device of FIG. 1, it was found that the decreasing tendency of the leakage current Ir saturates in the vicinity of a drive voltage Vf of 0.4V. Further, in the semiconductor device of FIG. 2, while the leakage current Ir is suppressed, an increase in the drive voltage Vf was observed.

[0042] In order to improve the drive voltage Vf of the semiconductor device 1 in the configuration of FIG. 2, FIG. 6 shows an example in which the arrangement of the second portion 106 in the first region 104 is deformed. FIG. 6(a) shows a perspective view of a modified example of the semiconductor device 1 of the first embodiment, and FIG. 6(b) shows a plan view of a modified example of the semiconductor device 1 of the first embodiment. In the first portion 105 indicated by the dotted line in FIG. 6(b), while fixing the offset region 107, the arrangement and size of the second portion 106 were changed and simulation was performed.

[0043] FIGS. 7(a) and 7(b) show the simulation results of the correlation between the leakage current and the drive voltage of the semiconductor device 1 shown in FIGS. 6(a) and 6(b). Note that the plots in FIGS. 7(a) and 7(b) are normalized with a predetermined current value for the simulation results of the second portion 106 in a staggered lattice shape for comparison with the simulation results of the semiconductor device 1 shown in FIG. 1.

[0044] FIG. 7(a) shows the position dependence when the lower part of the second portion 106 is fixed at the right position and the upper part of the second portion 106 is arranged at left, center, and right in FIG. 6(b). From FIG. 7(a), when the width W of the first portion 105 is 0 μm, an increase in Vf was confirmed along with the suppression of Ir. On the other hand, when the width W of the first portion 105 is 0.795 μm, since the current path becomes wider, it was found that the position dependence of the second portion 106 is relaxed.

[0045] Figure 7(b) shows the dependence of the width of region 105 including the second portion 106, which is a staggered arrangement pattern when the upper part of the second portion 106 in Figure 6(b) is placed at the left position, and the width a3 of the first region 104. At Point A in Figure 7(b), a3 of the semiconductor device in the configuration of Figure 1 (structure-1) was 3.3 μm, and a3 of the semiconductor device in the configuration of Figure 6 was 1.8 μm. Therefore, the configuration of Figure 6 can reduce the leakage current Ir with a smaller Schottky barrier diode size compared to the configuration of Figure 2. A major advantage of the configuration of Figure 6 is that the drive voltage Vf and the leakage current Ir can be controlled by the width W of the first portion 105 without increasing the size of the Schottky barrier diode.

[0046] Figure 8 is a plan view of the semiconductor device 1 of Figure 6. The shape of the second portion 106 in plan view is striped or dot-shaped. When the shape of the second portion 106 is dot-shaped, the shape of the second portion 106 is not limited to a square shape, and may be any of a circular shape, an elliptical shape, a triangular shape, a rectangular shape, a trapezoidal shape, or a polygonal shape with five or more sides. Further, when the shape of the second portion 106 is dot-shaped, a staggered or linear pattern may be formed by a plurality of second portions 106. Also, the shape of the first portion 105 in plan view may have a striped or intermittent pattern, or may be a shape having a gap 108 between two adjacent first portions 105 as shown in Figure 8.

[0047] <Embodiment 2> In this Embodiment 2, a modified example of the semiconductor device 1 of Embodiment 1 will be described. Note that repeated descriptions may be omitted for those that are the same as the configuration example of Embodiment 1.

[0048] The semiconductor device 1 shown in FIG. 9 has an anode region 123 formed in the second semiconductor region 120, a contact region 133 formed in the third semiconductor region 130, and a wiring 90 formed on the semiconductor substrate 10. Further, the semiconductor device 1 has a wiring 90 formed on the semiconductor substrate 10 and connecting the anode region 123 and the contact region 133. Thereby, the second conductive layer 60 and the third conductive layer 70 are electrically connected. Also, similarly to the first embodiment, a third electrode (not shown) is formed on the third conductive layer 70, and the contact region 133 is connected to the third electrode via the third conductive layer 70. Therefore, the second electrode 61 is connected to the third electrode via the wiring 90. Thereby, it is possible to suppress the operation of the parasitic bipolar transistor and the flow of leakage current into the semiconductor substrate.

[0049] In the semiconductor device of the first embodiment, the leakage current can be suppressed without being restricted by the layout of the Schottky electrode and the cathode electrode. On the other hand, in the semiconductor device 1 of the second embodiment, from the viewpoint of reducing the area of the Schottky barrier diode, it is preferable that the first electrode 51 is disposed inside the second electrode 61 which is the anode electrode. FIG. 10(a) shows a plan view of the semiconductor device 1 of the second embodiment, and FIG. 10(b) shows a plan view of a semiconductor device in which the second electrode 61 is disposed inside the first electrode 51 as a comparative example. By disposing the first electrode 51 which is the cathode electrode inside the second electrode 61 which is the anode electrode, the area of the Schottky barrier diode can be reduced. Also, since the number of wirings can be reduced, the degree of freedom of the layout can be improved.

[0050] FIG. 11 shows a forward waveform of the electrical characteristics of the Schottky barrier diode of the semiconductor device 1 of the present embodiment. The drive voltage Vf when the on-current Ia is 1 μA is 0.39 V, and it was found to have good electrical characteristics.

[0051] Figs. 12(a) and (b) show a modified example of the semiconductor device 1 of the second embodiment. Fig. 12(a) shows a configuration in which a metal silicide layer 91 is formed on the first region 104. In the semiconductor substrate 10, an LDMOSFET (Laterally Diffused Metal Oxide Semiconductor Field Effect Transistor) may be formed in addition to the Schottky barrier diode. Since the metal silicide layer 91 can be formed using a mask for introducing a drift layer of the LDMOSFET around the Schottky barrier diode, the metal silicide layer 91 can be formed without increasing the number of masks.

[0052] Fig. 13 is a diagram showing a simulation result of the electric field strength distribution of the semiconductor device when a reverse bias is applied. In a plan view, by arranging the end portion of the metal silicide layer 91 to be located between the first region 104 and the cathode region 103, it becomes possible to relax the electric field and improve the breakdown voltage of the Schottky barrier diode.

[0053] Fig. 12(b) shows a configuration in which a buried insulating layer 92, which is an insulating region that penetrates the first region 104 and surrounds the first region 104, is formed. When the upper surface 11 of the semiconductor substrate 10 is used as a reference plane, the depth of the buried insulating layer 92 is preferably greater than the depth of the first region 104. By forming the buried insulating layer 92, the current path 20 can be narrowed. Further, the buried insulating layer 92 can be formed in the same process as the buried insulating layer 30.

[0054] Fig. 14(a) shows a forward waveform, which is the electrical characteristic of the Schottky barrier diode of the semiconductor device 1 of the second embodiment. When the on-current Ia is 1 μA, the drive voltage Vf is 0.31 V, indicating that it has good electrical characteristics.

[0055] Figure 14(b) shows the reverse direction waveform of the electrical characteristics of the Schottky barrier diode of the semiconductor device 1 according to Embodiment 2. When 25 V was applied to the Schottky barrier diode, the leakage current Ir was lower than the specification value indicated by the dotted line, and the breakdown voltage BV was 37 V. Therefore, it was found that the Schottky barrier diode of the semiconductor device 1 according to Embodiment 2 has sufficient tolerance.

[0056] In this way, by providing the configuration of Embodiment 2, it is possible to provide a semiconductor device capable of further suppressing the leakage current.

[0057] As described above, the invention made by the present inventors has been specifically described based on the embodiments. However, it goes without saying that the present disclosure is not limited to the embodiments already described, and various modifications can be made without departing from the gist thereof.

Explanation of Reference Numerals

[0058] 1 Semiconductor device 10 Semiconductor substrate 11 Upper surface 12 Lower surface 20 Current path 30 Embedded insulating layer 40 Insulating layer 50, 60, 70, 80 First to fourth conductive layers 51 First electrode 61 Second electrode 90 Wiring 91 Metal silicide layer 92 Embedded insulating layer 100 First semiconductor region 101 First semiconductor layer 102 Second semiconductor layer 103 Cathode region 104 First region 105 First part 106 Second part 107 Offset region 108 Gap 110 Embedded region 120 Second semiconductor region 123 Anode region 130 Third semiconductor region 133 Contact region 140 Fourth semiconductor region 143 Ground region

Claims

1. A semiconductor substrate having an upper surface, a first semiconductor region formed in the semiconductor substrate, a second semiconductor region formed in the semiconductor substrate and surrounding the first semiconductor region in a plan view, a first conductive layer formed on the first semiconductor region, a first electrode formed on the first conductive layer, a cathode region formed in the first semiconductor region and connected to the first electrode through the first conductive layer, a second conductive layer formed on the first semiconductor region and in contact with the first semiconductor region, a second electrode formed on the second conductive layer, a first region formed in the first semiconductor region, disposed between a region in contact with the second conductive layer and the cathode region of the first semiconductor region along a direction along the upper surface of the semiconductor substrate, and in contact with a lower surface of the second conductive layer, when the upper surface of the semiconductor substrate is used as a reference plane, a depth of the first region is greater than a depth of the cathode region, the semiconductor substrate, the second semiconductor region, and the first region each have a first conductivity type, the first semiconductor region and the cathode region each have a second conductivity type opposite to the first conductivity type, a semiconductor device.

2. The first region has a first portion and a second portion, when the upper surface of the semiconductor substrate is used as a reference plane, a depth of the second portion is greater than a depth of the cathode region and a depth of the first portion, the first portion has an offset region that separates the second portion from the cathode region in a direction along the upper surface of the semiconductor substrate, the offset region is disposed between the cathode region and the second portion, an impurity concentration of the second portion is higher than an impurity concentration of the first portion, the semiconductor device according to Claim 1.

3. The first semiconductor region and the second conductive layer constitute a Schottky barrier diode, the semiconductor device according to Claim 1.

4. The first semiconductor region, a first semiconductor layer having the second conductivity type, a second semiconductor layer having the first conductivity type and located under the first semiconductor layer, a current path of the Schottky barrier diode is formed in the first semiconductor layer and narrowed by the first region, the semiconductor device according to Claim 3.

5. a shape of the second portion in a plan view is stripe-shaped or dot-shaped, When the shape of the second portion in plan view is the dot shape, the shape of the first portion is any one of a circular shape, an elliptical shape, a triangular shape, a square shape, a rectangular shape, a trapezoidal shape, and a polygonal shape with five or more sides. The semiconductor device according to claim 2.

6. When the shape of the second portion in plan view is the dot shape, a plurality of the second portions form a staggered or linear pattern. The semiconductor device according to claim 5.

7. The shape of the first portion in plan view has a striped or intermittent pattern. The semiconductor device according to claim 5.

8. Furthermore, an embedded region formed in the semiconductor substrate, disposed under the first semiconductor region and the second semiconductor region, and having the second conductivity type; A third semiconductor region formed in the semiconductor substrate, surrounding the first semiconductor region and the second semiconductor region in plan view, and having the second conductivity type. The third semiconductor region is connected to the embedded region. The semiconductor device according to claim 1.

9. Furthermore, a third conductive layer formed on the third semiconductor region; A third electrode formed on the third conductive layer; A second region formed in the third semiconductor region and connected to the third electrode via the third conductive layer. The impurity concentration of the second region is higher than the impurity concentration of the third semiconductor region. The second electrode and the third electrode are connected to each other via a wiring. The semiconductor device according to claim 8.

10. Furthermore, having a metal silicide layer between the first electrode and the first conductive layer. The semiconductor device according to claim 9.

11. In plan view, furthermore, having an insulating region disposed so as to surround the first region. When the upper surface of the semiconductor substrate is used as a reference plane, the depth of the insulating region is greater than the depth of the first region. The semiconductor device according to claim 9.

12. An anode region formed in the second semiconductor region and connected to the second electrode via the second conductive layer; An insulating layer formed between the first conductive layer and the second conductive layer; Furthermore having. The second conductive layer is formed on the first semiconductor region and the second semiconductor region. The first region is formed so as to surround the cathode region, and is disposed under the insulating layer and under the second conductive layer. In plan view, the second electrode is disposed so as to overlap the anode region. The semiconductor device according to claim 1.

13. An anode region formed in the second semiconductor region and connected to the second electrode via the second conductive layer, An insulating layer formed between the first electrode and the second conductive layer, Further comprising, The cathode region is formed so as to surround the first region, The first region is disposed under the insulating layer and under the second conductive layer, In a plan view, the second electrode is disposed so as to overlap the anode region, The semiconductor device according to claim 1.

14. A semiconductor substrate having an upper surface, A first semiconductor region formed in the semiconductor substrate, A second semiconductor region formed in the semiconductor substrate and surrounding the first semiconductor region in a plan view, A first conductive layer formed on the first semiconductor region, A first electrode formed on the first conductive layer, A cathode region formed in the first semiconductor region and connected to the first electrode via the first conductive layer, A second conductive layer formed on the first semiconductor region and on the second semiconductor region and in contact with the first semiconductor region, A second electrode formed on the second conductive layer, An anode region formed in the second semiconductor region and connected to the second electrode via the second conductive layer, A first region formed in the first semiconductor region, disposed between the cathode region and the second semiconductor region in a direction along the upper surface of the semiconductor substrate, and in contact with the lower surface of the second conductive layer, An embedded region formed in the semiconductor substrate and disposed under the first semiconductor region and the second semiconductor region, A third semiconductor region formed in the semiconductor substrate and surrounding the first semiconductor region and the second semiconductor region in a plan view, A third conductive layer formed on the third semiconductor region, A third electrode formed on the third conductive layer, A second region formed in the third semiconductor region and connected to the third electrode via the third conductive layer, When the upper surface of the semiconductor substrate is used as a reference plane, the depth of the first region is greater than the depth of the cathode region, The semiconductor substrate, the second semiconductor region, the anode region, and the first region each have a first conductivity type, The first semiconductor region, the cathode region, the embedded region, and the third semiconductor region each have a second conductivity type opposite to the first conductivity type, The third semiconductor region is connected to the embedded region, The impurity concentration of the second region is higher than that of the third semiconductor region. The second electrode and the third electrode are connected to each other via wiring. Semiconductor device.

15. The first semiconductor region and the second conductive layer constitute a Schottky barrier diode. The semiconductor device according to claim 14.

16. The first semiconductor region includes a first semiconductor layer having the second conductivity type, and a second semiconductor layer having the first conductivity type and located under the first semiconductor layer. The current path of the Schottky barrier diode is formed in the first semiconductor layer and narrowed by the first region. The semiconductor device according to claim 15.

17. Furthermore, a metal silicide layer is provided between the first electrode and the first conductive layer. The semiconductor device according to claim 14.

18. In a plan view, further, an insulating region is provided so as to surround the first region. When the upper surface of the semiconductor substrate is used as a reference plane, the depth of the insulating region is greater than the depth of the first region. The semiconductor device according to claim 14.

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