Simulation device, modeling device, and simulation method

Abstract

To provide a simulation device, a modeling device, and a simulation method that improve accuracy of a simulation.SOLUTION: A simulation method comprises the steps of: limiting dependency of Vgs on Cgd to Vgs=0; and setting, without using Cgd (0, Vds-Vgs) which simplifies and includes Vds dependency on Cgd with an offset of "Vds-Vgs", Cgd using Cgd (Vgs, Vds) which also takes into account Vgs dependency where Vgs≠0.SELECTED DRAWING: Figure 14

Description

Technical Field

[0001] The present invention relates to a simulation device, a modeling device, and a simulation method, and more particularly to a technique effective when applied to a simulation technique for setting parasitic capacitance of a power transistor, for example.

Background Art

[0002] Circuit simulation is effective for considering optimal device and drive condition settings according to applications, margins for product variations, and the like. In order to improve the accuracy of circuit simulation, the accuracy of the device model is important, and various models have been developed.

[0003] For example, Patent Document 1 describes a method for extracting model parameters that can well reproduce the high-current region of a SiC power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Patent Document 2 describes a method for extracting capacitance.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, even if the performance of the method for extracting parameters as shown in Patent Document 1 or Patent Document 2 is good, there is a limit to improving the simulation accuracy when the expressive power of the function (referred to as the base model) from which the parameters are input is insufficient.

[0006] For example, although the gate-drain capacitance Cgd is a function not only of the drain-source voltage Vds but also of the complex Vgs, in commonly used MOSFET models, Cgd(Vgs, Vds) = Cgd(0, Vds - Vgs) is overly simplified, making it difficult to obtain simulations with sufficient accuracy.

[0007] Regarding this point, for example, in the case of a base model with very broad expressiveness such as an artificial neural network (hereafter referred to as a multi-layer perceptron (MLP)), the number of parameters to be extracted becomes very large with respect to the training data, resulting in problems such as an increase in computational resources and unintended behavior due to overfitting.

[0008] Therefore, the base model needs to have sufficient expressiveness to reproduce real-world characteristics while minimizing the number of parameters to be tuned. For this purpose, it is necessary to accurately capture the characteristics of the functions that the model should have. That is, from the perspective of improving the accuracy of simulations, a base model is desired that has sufficient expressiveness to reproduce real-world characteristics while minimizing the number of parameters to be tuned.

[0009] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0010] A simulation apparatus according to an embodiment includes a setting unit that sets the gate-drain capacitance based on Cgd(Vgs, Vds), which is a function that outputs the gate-drain capacitance when the gate-source voltage Vgs and the drain-source voltage Vds are input.

[0011] A simulation method according to an embodiment includes a step of setting the gate-drain capacitance based on Cgd(Vgs, Vds), which is a function that outputs the gate-drain capacitance when the gate-source voltage Vgs and the drain-source voltage Vds are input.

[0012] In one embodiment, the modeling device includes a first parameter determination unit that determines parameters included in Cgd(Vgs, Vds), which is a function that outputs the gate-drain capacitance when the gate-source voltage Vgs and the drain-source voltage Vds are input based on the measured switching waveform of the power transistor.

Advantages of the Invention

[0013] According to one embodiment, the accuracy of the simulation can be improved.

Brief Description of the Drawings

[0014]

Figure 1

Figure 2

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Figure 14

Embodiments for Carrying Out the Invention

[0015] In all the drawings for explaining the embodiment, the same members are basically given the same reference numerals, and the repeated explanations thereof are omitted. Note that, in order to make the drawings easy to understand, hatching may be added even to a plan view.

[0016] The technical idea in this embodiment relates to the technology of simulating the characteristics of a power transistor. For example, it is a technical idea of simulating the characteristics of a power transistor based on a function called a "base model".

[0017] In this embodiment, a power MOSFET is assumed as the power transistor. However, the technical idea in this embodiment is not limited to power MOSFETs and can be widely applied to power transistors including IGBTs (Insulated Gate Bipolar Transistors).

[0018] Hereinafter, a power MOSFET will be taken as an example for explanation.

[0019] <Process of Consideration> In power MOSFETs, power MOSFETs using a silicon (Si) substrate (Si power MOSFETs) are mainstream. However, the breakdown field strength in silicon carbide (SiC) is approximately one order of magnitude greater than that in silicon.

[0020] Therefore, in a power MOSFET using an SiC substrate (SiC power MOSFET), compared with an Si power MOSFET, the thickness of the drift layer for maintaining the breakdown voltage can be reduced to approximately 1 / 10, and the impurity concentration of the drift layer can be increased by about 100 times.

[0021] As a result, in an SiC power MOSFET, theoretically, the device resistance can be reduced by three orders of magnitude or more. Also, since the bandgap of silicon carbide is approximately three times larger than that of silicon, the SiC power MOSFET can have a lower on-resistance at the same breakdown voltage and can also operate in a high-temperature environment. For this reason, SiC semiconductor devices (SiC semiconductor devices) are expected to have performance superior to that of Si semiconductor devices (Si semiconductor devices).

[0022] As an example of the use of a power MOSFET, two power MOSFETs connected in series are connected to a load, and the potential across the load is adjusted by alternately switching the on-operation and off-operation of the two power MOSFETs. This is called a half-bridge circuit.

[0023] In one power MOSFET, current flows in the on-state but no voltage is applied, and no current flows in the off-state but a voltage is applied.

[0024] At this time, the operation of changing the gate voltage of the power MOSFET to switch between the on-state and off-state of the power MOSFET is called switching.

[0025] In a half-bridge circuit, when the power MOSFET is in the on state, the voltage is low, while when the power MOSFET is in the off state, the current is low. Therefore, the power generated in the steady state such as the on state or the off state is low.

[0026] This is because power is expressed as the product of current and voltage, and since the voltage is low in the on state and the current is low in the off state, the product of current and voltage is small in either the on state or the off state.

[0027] However, the power MOSFET in the switching state consumes a large amount of power because high voltage and large current occur simultaneously. This consumed power is called switching loss. The higher the switching frequency defined by the on-off signal frequency of the MOSFET, the better the quality of the inverter output at the application destination. On the other hand, when the switching frequency increases, the number of switching losses generated per unit time increases, so the loss becomes large. To increase the switching frequency, it is necessary to reduce the switching loss, and for this, it is effective to shorten the switching time during which high voltage and large current occur simultaneously. That is, it is necessary to increase the change rates of voltage and current (dV / dt and di / dt), and as a result, the switching period becomes short, and the switching loss can be reduced.

[0028] Therefore, the higher the switching speed, the smaller the switching loss, but when the change rates of voltage and current increase, noise, surge voltage, and surge current will increase, so there is a limit to increasing the switching speed.

[0029] For example, in a half-bridge circuit where the high-side power MOSFET and the low-side power MOSFET are connected in series, when the high-side power MOSFET is turned on while the low-side power MOSFET is in the off state, a dV / dt is generated in the low-side power MOSFET due to the turn-on of the high-side power MOSFET. As a result, in the low-side power MOSFET, an unintentional gate current i = Cgd × dV / dt is generated by the gate-drain capacitance Cgd, called the feedback capacitance, and the dV / dt.

[0030] Then, as a result of this unintentionally generated gate current being injected into the gate electrode, a gate voltage greater than the threshold voltage may be applied to the gate electrode of the low-side power MOSFET. In this case, the low-side power MOSFET in the off state may unintentionally turn on. This phenomenon is called "false arcing" or "self-turn-on". When such "false arcing" occurs, both the high-side power MOSFET and the low-side power MOSFET may simultaneously turn on, resulting in a short-circuit fault.

[0031] Regarding this point, the above-mentioned "false arcing" can be prevented by pre-applying a negative gate voltage to the gate electrode of the low-side power MOSFET so that even if a surge voltage occurs, the low-side power MOSFET will not accidentally turn on exceeding the threshold voltage. However, since the SiC power MOSFET has problems with the reliability of the gate insulating film, the absolute maximum rating of the negative gate voltage is small, and there are limitations to this countermeasure.

[0032] For example, the absolute maximum rating of the gate voltage is -30V for Si-IGBT and -4V for SiC power MOSFET. Therefore, especially in the case of SiC power MOSFET, "false arcing" is more likely to become apparent than in Si-IGBT.

[0033] Therefore, in the case of SiC power MOSFETs, in order not to generate "false turn-on arcs", it is necessary to determine switching conditions more carefully than for Si-IGBTs.

[0034] Regarding this point, circuit simulation is effective in order to consider the optimal device, drive condition setting, margin for product variations, etc. according to the application. For example, simulation techniques based on MOSFET models are being studied. Hereinafter, the MOSFET model will be described.

[0035] <MOSFET Model> FIG. 1 is a circuit diagram showing the terminals and inter-terminal capacitances of MOSFET model 100.

[0036] MOSFET model 100 includes a drain terminal D, a gate terminal G, a Kelvin source terminal KS, and a power source terminal PS. Here, the Kelvin source terminal KS and the power source terminal PS may be a single source terminal according to the structure of the package to be modeled. Also, MOSFET model 100 may include a thermal circuit terminal Tj representing the junction temperature and a thermal path terminal Tc indicating the contact point between the module and the outside. Furthermore, MOSFET model 100 may include other appropriate terminals according to the function.

[0037] MOSFET model 100 is modeled so that the current between the drain terminal D and the power source terminal PS can be controlled by Vgs between the gate terminal G and the Kelvin source terminal KS. Note that in this embodiment, an n-type MOSFET will be described, but the technical idea in this embodiment can also be applied to p-type MOSFETs.

[0038] MOSFET model 100 also includes a body diode and parasitic inductance, but since it is not directly handled in this embodiment, the description and illustration are omitted.

[0039] <Consideration of Improvement> In the MOSFET model 100 shown in FIG. 1, there are a gate-drain capacitance (feedback capacitance) Cgd, a gate-source capacitance Cgs, and a drain-source capacitance Cds, which are parasitic capacitances between terminals. These parasitic capacitances are parasitic capacitances caused by the MOS part or depletion layer of the power MOSFET and are important parameters that determine the switching characteristics.

[0040] Cgd is important for determining the drain speed with respect to the gate speed during switching and the surge voltage applied to the gate electrode, and needs to be modeled with high precision. In particular, since Cgd is a cause of "false arcing", in order to prevent "false arcing", it is desirable that Cgd can be set accurately in the simulation.

[0041] Cgd is expressed as a function Cgd(Vgs, Vds) having dependencies on Vgs and Vds. Here, since the gate voltage is changed during the switching operation, generally, the gate-source voltage Vgs≠0.

[0042] However, in the performance evaluation of general power MOSFETs, Cgd(0, Vds) with Vgs = 0 is actually measured and installed in the product specification sheet and model.

[0043] On the other hand, it is difficult to measure the state where Vgs≠0, especially when the current is conducting with Vgs>Vth exceeding the threshold voltage Vth. This is because it is difficult to measure the capacitance in the current conducting state (on state).

[0044] Therefore, in general simulations, Cgd is set using Cgd(0, Vds - Vgs) composed of a function obtained by offsetting Cgd(0, Vds) with Vgs = 0. That is, in general simulations, the Vgs dependency of Cgd is simplified by offsetting.

[0045] However, when Vds and Vgs are simultaneously applied to the power MOSFET, complex interactions occur. Therefore, from the perspective of setting Cgd with high precision, a simple offset is insufficient. Thus, the function (base model) representing Cgd used in the current simulation has room for improvement from the perspective of setting Cgd with high precision. Therefore, in this embodiment, measures are taken to realize a function capable of setting Cgd with high precision.

[0046] Hereinafter, the technical idea in the embodiment with measures taken will be described.

[0047] <Basic idea in the embodiment> The basic idea in this embodiment is not to use Cgd(0, Vds - Vgs) that limits the dependence of Vgs on Cgd to Vgs = 0 and simplifies and includes the dependence of Vds on Cgd with an offset of "Vds - Vgs", but to use Cgd(Vgs, Vds) that also considers the dependence of Vgs where Vgs ≠ 0 to set Cgd.

[0048] Cgd(Vgs, Vds) that considers the dependence of Vgs where Vgs ≠ 0 becomes a base model with sufficient expressive power to reproduce the actual Cgd compared to Cgd(0, Vds - Vgd). Therefore, according to the basic idea, Cgd can be set with high precision.

[0049] Here, it is stated that Cgd can be set with high precision as a result of Cgd(Vgs, Vds) considering the dependence of Vgs where Vgs ≠ 0. However, it is important to analyze how Cgd(Vgs, Vds) considers the dependence of Vgs where Vgs ≠ 0. That is, it is important to analyze the characteristics of Cgd(Vgs, Vds) as a function for accurately reproducing the actual Cgd. Therefore, the characteristics of Cgd(Vgs, Vds) as a function newly discovered by the inventor of the present invention will be described.

[0050] Figure 2 is a graph showing the relationship between Vds and Cgd when Vgs is greater than the voltage Vm(Isw). In Figure 2, a graph representing Cgd(0, Vds), a graph representing Cgd(0, Vds - Vgs), and a graph representing the measured value of Cgd are shown.

[0051] Here, Vm(Isw) as used in this specification is a function of the drain-source current Isw and means the gate-source voltage during the Miller period. Vm(Isw) is composed of, for example, a function that monotonically increases with respect to Isw.

[0052] In this specification, since it is premised that the switching operation starts when the drain-source current Isw (load current) is flowing, the on-state and off-state of the power MOSFET are defined by the above-described Vm(Isw) rather than the threshold voltage Vth. Specifically, in this specification, the case where Vgs < Vm(Isw) is defined as the off-state, while the case where Vgs > Vm(Isw) is defined as the on-state.

[0053] As described above, it is difficult to measure the capacitance in the current conduction state (on-state), but the inventor has measured Cgd in the on-state by a special method. Specifically, the inventor measures Cgd by monitoring the current flowing into the body region and gate electrode of the power MOSFET.

[0054] As shown in Figure 2, Cgd(0, Vds) and Cgd(0, Vds - Vgs) do not reflect the measured values. That is, in order to set Cgd in the on-state with high precision, Cgd(0, Vds) and Cgd(0, Vds - Vgs) are insufficient.

[0055] Regarding this point, if it is designed to fit Cgd(Vgs, Vds) to the measured values, it is considered that a base model capable of reproducing Cgd in the on-state with high precision can be obtained. Therefore, focusing on the measured values in Figure 2, at Vcross, the graph representing the measured values intersects with the graph representing Cgd(0, Vds - Vgs).

[0056] Therefore, in Vcross, if the functional form of Cgd(Vgs, Vds) is designed to intersect with Cgd(0, Vds - Vgs), it is considered that Cgd(Vgs, Vds) that fits the measured value can be realized.

[0057] From the above, the characteristics of Cgd(Vgs, Vds) as a function for accurately reproducing Cgd are as follows.

[0058] (A) When Vgs > Vm(Isw) and Vds < Vcross, Cgd(Vgs, Vds) takes a value intermediate between Cgd(0, Vds) and Cgd(0, Vds - Vgs).

[0059] (B) When Vgs > Vm(Isw) and Vds > Vcross, Cgd(0, Vds - Vgs) < Cgd(Vgs, Vds).

[0060] Here, Vcross is the drain-source voltage at which Cgd(0, Vds - Vgs) = Cgd(Vgs, Vds) when Vgs > Vm(Isw). Vcross(Vgs) is composed of, for example, a function that is monotonically increasing with respect to Vgs.

[0061] According to Cgd(Vgs, Vds) having such characteristics, a base model that fits the measured value with high accuracy can be provided.

[0062] Next, an embodiment that embodies the above-described basic idea will be described.

[0063] <Embodiment> <<Device Structure of Power MOSFET>> FIG. 3 is a diagram showing the device structure of a power MOSFET.

[0064] In FIG. 3, on a semiconductor substrate SUB which is an n-type semiconductor substrate, an epitaxial layer EPI composed of, for example, an n-type semiconductor layer is formed. Inside the epitaxial layer EPI, a body region BR composed of a p-type semiconductor region is formed. And inside the body region BR, a source region SR composed of an n-type semiconductor region is formed. Also, in FIG. 3, in the right region of the body region BR, a region called a JFET region 10 is formed. As shown in FIG. 3, a source electrode SE is formed so as to be in contact with the body region BR and the source region SR, and this source electrode SE is electrically connected to a source terminal S. On the other hand, as shown in FIG. 3, a gate electrode GE is formed so as to face the source region SR, the body region BR, and the JFET region 10 via a gate insulating film. This gate electrode GE is electrically connected to a gate terminal G. Also, the semiconductor substrate SUB is electrically connected to a drain terminal D.

[0065] Here, on the surface of the body region BR existing directly under the gate electrode GE, when a gate voltage equal to or higher than the threshold voltage is applied to the gate electrode GE, an inversion layer is formed, and this inversion layer becomes a channel. In the above manner, a power MOSFET is configured.

[0066] In the power MOSFET configured in this way, there are parasitic capacitances. Specifically, as shown in FIG. 3, in the power MOSFET, there are a drain-source capacitance Cds, a gate-source capacitance Cgs, and a gate-drain capacitance Cgd.

[0067] <<Physical image explaining the behavior of capacitance characteristics>> FIG. 4 is a conceptual diagram for explaining the behavior of capacitance characteristics newly found by the present inventor based on a physical image. As described above, the parasitic capacitance of the power MOSFET is caused by, for example, a depletion layer in the semiconductor region. Specifically, the amount of charge of the depletion layer generated with respect to a voltage change becomes the capacitance value. In FIG. 4, in the power MOSFET, the distribution of the depletion layer DPL in the off state with Vgs = 0 is shown.

[0068] When the drain voltage is increased, the depletion layer DPL in the semiconductor region expands. In the drain-side region where the depletion layer DPL has expanded, as shown in FIG. 4, positive fixed charges are generated by the current supplied from the drain terminal D. Here, when there is a charge, there must be a charge of the opposite polarity that terminates its electric field lines.

[0069] In FIG. 4, a part of the charge corresponding to the positive charge existing at a position close to the gate electrode GE is supplied as a negative charge from the gate electrode GE. This is the essence of the gate-drain capacitance Cgd. On the other hand, a part of the charge is supplied as a negative charge from the source electrode SE. This is the essence of the drain-source capacitance Cds.

[0070] For example, the charge corresponding to the positive charge existing at a position far from the gate electrode GE is almost entirely supplied as a negative charge from the source electrode SE. Thus, due to the electrical distribution, it is determined whether the positive charge existing in the drain-side region is preferentially terminated by the negative charge supplied from the gate electrode GE or the negative charge supplied from the source electrode SE.

[0071] From this physical image, the amount of charge stored in the drain-side region is limited. With the sum of Cds and Cgd being constant, the idea is obtained that Cds and Cgd are determined by the distribution of whether the termination of the positive charge existing in the drain-side region is carried out by the negative charge supplied from the gate electrode GE or the negative charge supplied from the source electrode SE.

[0072] Next, FIG. 5 is a diagram showing the distribution of the depletion layer DPL in the case where a gate voltage (positive voltage) equal to or higher than Vm(Isw) is applied to the gate electrode to set the current to the conductive on-state. Different from FIG. 4, in FIG. 5, the MOS interface on the surface of the JFET region 10 is in the accumulation state or the strong inversion state. Therefore, as shown in FIG. 5, the depletion layer DPL does not extend from the gate electrode GE into the JFET region 10. When the drain voltage is increased from this state, the positive charges that have advanced to the JFET region 10 side terminate the electric field lines with a MOS capacitor having a capacitance much larger than that of the depletion layer DPL. That is, the positive charges that have advanced to the JFET region 10 side reach a position where the distance from the negative charges induced in the gate electrode GE becomes shorter. As a result, Cgd in the on-state, which is the current conduction state shown in FIG. 5, becomes larger than Cgd in the off-state shown in FIG. 4.

[0073] Thus, Cgd varies significantly in capacitance value between the on-state and the off-state. In this regard, Cgd(0, Vds - Vgs) basically only considers Cgd in the off-state (Vgs = 0). In other words, Cgd(0, Vds - Vgs) does not appropriately consider Cgd in the on-state, which has a significantly different capacitance value from the off-state. For this reason, the Cgd set using Cgd(0, Vds - Vgs) does not reflect the actual Cgd. In other words, the error from the actual Cgd becomes large for the Cgd set using Cgd(0, Vds - Vgs).

[0074] By paying attention to such behavior, the inventor of the present invention has examined the error when comparing Cgd(0, Vds - Vgs) with the actual capacitance value, and believes that it is possible to create a base model that can always set a highly accurate Cgd by modifying the base model in the direction of reducing the error.

[0075] Hereinafter, based on the physical image, the characteristics of the base model incorporating the dependency on an arbitrary Vgs will be described by appropriately considering not only the off-state but also the on-state of the power MOSFET.

[0076] FIG. 6 is a diagram schematically showing the physical image of a power MOSFET when Vgs < Vm(Isw). Here, "when Vgs < Vm(Isw)" means that the power MOSFET is in the off state.

[0077] FIG. 6(a) is a diagram showing the physical image corresponding to Cgd(0, Vds - Vgs), FIG. 6(b) is a diagram showing the physical image corresponding to Cgd(Vgs, Vds), and FIG. 6(c) is a diagram showing the physical image corresponding to Cgd(0, Vds).

[0078] First, pay attention to the fact that the depletion layer DPL extends more as the voltage applied between the drain terminal D and the gate terminal G increases. Looking at FIG. 6(a) and FIG. 6(c), in FIG. 6(a), since "0V" is applied to the gate terminal G and "Vds - Vgs" is applied to the drain terminal D, the voltage applied between the drain terminal D and the gate terminal G is "Vds - Vgs". On the other hand, in FIG. 6(c), since "0V" is applied to the gate terminal G and "Vds" is applied to the drain terminal D, the voltage applied between the drain terminal D and the gate terminal G is "Vds". Therefore, in FIG. 6(c), the voltage applied between the drain terminal D and the gate terminal G is larger than that in FIG. 6(a). This means that the extension of the depletion layer DPL in FIG. 6(c) is longer than that in FIG. 6(a). In this regard, the longer the extension of the depletion layer DPL, the smaller Cgd becomes. For this reason, Cgd in FIG. 6(c) is smaller than Cgd in FIG. 6(a). That is, Cgd(0, Vds) corresponding to FIG. 6(c) is smaller than Cgd(0, Vds - Vgs) corresponding to FIG. 6(a).

[0079] Next, focusing on FIG. 6(b), in FIG. 6(b), a voltage smaller than Vm(Isw) but larger than 0V is applied to the gate terminal G, and "Vds" is applied to the drain terminal D. From this, in FIG. 6(b), the voltage applied between the drain terminal D and the gate terminal G is larger than that in FIG. 6(a) and smaller than that in FIG. 6(c). That is, in FIG. 6(b), the voltage applied between the drain terminal D and the gate terminal G takes a value between that in FIG. 6(a) and that in FIG. 6(c). Therefore, Cgd in FIG. 6(b) takes a value between Cgd in FIG. 6(a) and Cgd in FIG. 6(c). That is, Cgd(Vgs, Vds) corresponding to FIG. 6(b) is smaller than Cgd(0, Vds - Vgs) corresponding to FIG. 6(a), while being larger than Cgd(0, Vds) corresponding to FIG. 6(c).

[0080] From the above, when the power MOSFET is in the off state, the following relationship holds. Cgd(0, Vds - Vgs) > Cgd(Vgs, Vds) > Cgd(0, Vds) That is, Cgd(Vgs, Vds) takes a value intermediate between Cgd(0, Vds) and Cgd(0, Vds - Vgs).

[0081] Subsequently, FIG. 7 is a diagram schematically showing the physical image of the power MOSFET when Vgs > Vm(Isw). Here, "when Vgs > Vm(Isw)" means that the power MOSFET is in the on state.

[0082] Note that in FIG. 7, a state where Vds is low is assumed.

[0083] FIG. 7(a) is a diagram showing the physical image corresponding to Cgd(0, Vds - Vgs), FIG. 7(b) is a diagram showing the physical image corresponding to Cgd(Vgs, Vds), and FIG. 7(c) is a diagram showing the physical image corresponding to Cgd(0, Vds).

[0084] Focusing on FIGS. 7(a) and 7(b), in FIG. 7(a), the voltage applied to the drain terminal D is "Vds - Vgs". In contrast, in FIG. 7(b), the voltage applied to the drain terminal D is "Vds". Therefore, in FIG. 7(a), since the voltage applied to the drain terminal D is lower than that in FIG. 7(b), the extension of the depletion layer becomes shorter. As a result, as shown in FIGS. 7(a) and 7(b), the gate-drain facing area S1 in FIG. 7(a) is larger than the gate-drain facing area S2 in FIG. 7(b). Considering that the capacitance value is proportional to the facing area, Cgd in FIG. 7(a) becomes larger than Cgd in FIG. 7(b). That is, Cgd(0, Vds - Vgs) corresponding to FIG. 7(a) becomes larger than Cgd(Vgs, Vds) corresponding to FIG. 6(b).

[0085] Also, focusing on FIGS. 7(b) and 7(c), in FIG. 7(b), a voltage larger than the voltage Vm(Isw) is applied to the gate terminal G, and "Vds" is applied to the drain terminal D. From this, in FIG. 7(b), the voltage applied between the drain terminal D and the gate terminal G is smaller than that in FIG. 7(c). As a result, the extension of the depletion layer DPL in FIG. 7(b) becomes shorter than the extension of the depletion layer DPL in FIG. 7(c). In other words, the extension of the depletion layer DPL in FIG. 7(c) becomes longer than the extension of the depletion layer DPL in FIG. 7(b), and the gate-drain facing area S3 in FIG. 7(c) becomes smaller than the gate-drain facing area S2 in FIG. 7(b). Therefore, Cgd in FIG. 7(c) becomes smaller than Cgd in FIG. 7(b). That is, Cgd(0, Vds) corresponding to FIG. 7(c) becomes smaller than Cgd(Vgs, Vds) corresponding to FIG. 7(b).

[0086] For this reason, when the power MOSFET is in the on state (Vgs > Vm(Isw)) and Vds is low, the following relationship holds. Cgd(0, Vds - Vgs) > Cgd(Vgs, Vds) > Cgd(0, Vds) That is, Cgd(Vgs, Vds) takes a value intermediate between Cgd(0, Vds) and Cgd(0, Vds - Vgs).

[0087] Next, FIG. 8 is a diagram schematically showing a physical image of a power MOSFET when Vgs > Vm(Isw).

[0088] Note that in FIG. 8, a state where Vds is high is assumed.

[0089] FIG. 8(a) is a diagram showing a physical image corresponding to Cgd(0, Vds - Vgs), and FIG. 8(b) is a diagram showing a physical image corresponding to Cgd(Vgs, Vds).

[0090] In FIG. 8(a), as Vds is increased, the extension of the depletion layer DPL becomes longer, and the long depletion layer DPL is inserted as a series capacitance, so Cgd decreases significantly. On the other hand, in FIG. 8(b), as Vds is increased, the depletion layer DPL extends, but a gate - source voltage larger than Vm(Isw) is applied to the gate electrode GE. Therefore, unlike FIG. 8(a) where "0V" is applied to the gate electrode GE and it is in the off state, the power MOSFET is in the on state. That is, in FIG. 8(b), there is a path for current to pass through, and it is connected to the channel. From this, the depletion layer DPL existing between the gate electrode GE and the JFET region 10 is relatively thin. Therefore, in FIG. 8(b), as Vds is increased, Cgd increases.

[0091] As described above, when the power MOSFET is in the on state (Vgs > Vm(Isw)) and Vds is low, the relationship Cgd(0, Vds - Vgs) > Cgd(Vgs, Vds) > Cgd(0, Vds) holds. In this regard, as Vds is increased, in FIG. 8(a), Cgd decreases, while in FIG. 8(b), Cgd increases.

[0092] Therefore, when Vds is higher than a certain voltage Vcross, it is expected that Cgd(0, Vds - Vgs) < Cgd(Vgs, Vds) will reverse. Here, Vcross means the drain-source voltage at which Cgd(0, Vds - Vgs) = Cgd(Vgs, Vds) when Vgs > Vm(Isw).

[0093] Actually, in FIG. 2, as part of a graph showing the relationship between Vds and Cgd in the on-state of a power MOSFET, a graph representing the measured value of Cgd is shown. Looking at the relationship between this measured value and Cgd(0, Vds - Vgs) in FIG. 2, when Vds < Vcross, Cgd(0, Vds - Vgs) > the measured value, and when Vds > Vcross, Cgd(0, Vds - Vgs) < the measured value.

[0094] From this, the physical images described in FIGS. 6 to 8 can well explain the behavior of the measured value of Cgd. Therefore, by constructing Cgd(Vgs, Vds) that satisfies the conditions derived from the physical images described in FIGS. 6 to 8, the measured value of Cgd can be reproduced.

[0095] <<Parentheses>> Cgd(Vgs, Vds) in the embodiment satisfies the following conditions.

[0096] (1) When Vgs < Vm(Isw) Cgd(0, Vds) < Cgd(Vgs, Vds) < Cgd(0, Vds - Vgs). That is, Cgd(Vgs, Vds) takes a value intermediate between Cgd(0, Vds) and Cgd(0, Vds - Vgs).

[0097] (2) When Vgs > Vm(Isw) and Vds < Vcross(Vgs) Cgd(0, Vds) < Cgd(Vgs, Vds) < Cgd(0, Vds - Vgs). That is, Cgd(Vgs, Vds) takes a value intermediate between Cgd(0, Vds) and Cgd(0, Vds - Vgs).

[0098] (3) When Vgs > Vm(Isw) and Vds > Vcross(Vgs) Cgd(0, Vds - Vgs) < Cgd(Vgs, Vds).

[0099] [[Features in the Embodiment]] The characteristic point in the embodiment lies in realizing Cgd(Vgs, Vds) that takes into account the dependence of Vgs where Vgs ≠ 0. That is, it lies in realizing Cgd(Vgs, Vds) that takes into account the dependence not only in the state of Vgs = 0V (off state of the power MOSFET) but also in the state of Vgs > Vm(Isw) (on state of the power MOSFET).

[0100] And as a result of analyzing the behavior of the on - state capacitance, the inventor obtained a new finding that the magnitude relationship between Cgd(0, Vds - Vgs) and the measured value reverses with Vcross as the boundary, and another characteristic point is that it provides a guideline for determining the functional form of Cgd(Vgs, Vds) to reflect this new finding. That is, the characteristic point lies in clearly stating that if Cgd(Vgs, Vds) has a functional form that satisfies the conditions (1) to (3) listed in "<< >>", Cgd can be set with high accuracy reflecting the behavior of the measured value.

[0101] [[An Example of a Specific Functional Form]] Hereinafter, an example of a specific functional form of Cgd(Vgs, Vds) will be described.

[0102] Cgd(Vgs, Vds) includes, for example, the sum of Cgd1(Vgs, Vds) and Cgd2(Vgs, Vds) as components and satisfies the following conditions.

[0103] (1) When Vgs > 0 and Vds = 0 Cgd2(Vgs, Vds) > Cgd1(Vgs, Vds),

[0104] (2) When Vgs > 0 and Vds → ∞ Cgd2(Vgs, Vds) < Cgd1(Vgs, Vds).

[0105] Here, Cgd1(Vgs, Vds) includes a function part of A×(1 - tanh(Vdep)) + C, where A is composed of at least a function of Vgs, and C is composed of at least a function of Vgs. Vdep is a function approximating Vgd and is composed of at least functions of Vgs and Vds. In the region where Vgs > 0, Vdep is composed of a function that, for example, decreases monotonically with respect to Vgs and increases monotonically with respect to Vds.

[0106] Cgd2(Vgs, Vds) includes a function part of D×(Vepi) -E where D is a coefficient and E satisfies 0.4 ≤ E ≤ 0.6. Also, Vepi is a function approximating Vgd and is composed of at least functions of Vgs and Vds. Vepi is composed of a function that decreases monotonically with respect to Vgs and increases monotonically with respect to Vds.

[0107] Next, an example of the specific functional forms of Cgd1(Vgs, Vds) and Cgd2(Vgs, Vds) will be described.

[0108] First, the gate charge Qg is represented by the following Equation 1.

[0109]

Equation

[0110]

Equation

[0111]

Equation

[0112]

Equation

[0113] Here, Qjft included in Equation 3 is a parameter representing the amount of charge present in the JFET region 10, and Kvg1 is a parameter that becomes the coefficient of Vgs. Also, Vdep included in Equation 3 is a function approximating Vgd and is a function incorporating the steepness of depletion in the JFET region 10, and is represented by the following Equation 5.

[0114]

Equation

[0115] Furthermore, Vjft2 included in Equation 3 and Equation 5 represents the voltage at which the sweep-out of Qjft ends, and is represented by the following Equation 6. This Qjft and Vjft2 are parameters that depend on Vgs.

[0116]

Equation

[0117] Subsequently, Cdep included in Equation 4 represents the capacitance component among the capacitance components by the epitaxial layer EPI where the electric lines of force terminate at the gate electrode GE. Also, Vepi included in Equation 4 is a function approximating Vgd and is a function incorporating the potential at the end of the depletion layer DPL existing under the JFET region 10, and is represented by the following Equation 7.

[0118] [Number] Vbi and Kvg4 included in Equation 7 are parameters.

[0119] Next, Cgd1 is obtained by differentiating Q1 described above with respect to Vgd (≒ Vdep) and is represented by the following Equation 8.

[0120] [Number] On the other hand, Cgd2 is obtained by differentiating Q2 described above with respect to Vgd (≒ Vepi) and is represented by the following Equation 9.

[0121] [Number] Cgd(Vgs, Vds) = Cgd1(Vgs, Vds) + Cgd2(Vgs, Vds) obtained in this way has a small number of parameters. Therefore, in the implementation mode, a base model is realized that can suppress the number of parameters to be tuned while having sufficient expressive power to reproduce the actual Cgd.

[0122] Although an example of the specific functional form of Cgd(Vgs, Vds) has been described, this example has been derived by separately and independently considering not only Q2 resulting from the depletion of the epitaxial layer EPI but also Q1 resulting from the depletion of the JFET region 10 as components of the gate charge Qg, and this concept is important. That is, by considering Q1 separately from Q2, an example of a base model capable of accurately reproducing the actual Cgd can be derived, and thus the sharp insight of the present inventor to consider Q1 separately from Q2 has great technical significance.

[0123] In the implementation mode, as the simplest example, the dependence of Vgs is expressed by a linear equation. However, the technical idea in the implementation mode is not limited to this, and the dependence of Vgs may be expressed using a polynomial of the second degree or higher, or may be expressed by combining other elementary functions.

[0124] Also, the functional form of Cgd(Vgs, Vds) is not limited to the functional form described above, and a wide range of functional forms satisfying the conditions described in this specification can be applied.

[0125] As described above, the base model Cgd(Vgs, Vds) contains a plurality of parameters. Therefore, in order to realize a model capable of accurately reproducing the actual Cgd, it is necessary to determine the parameters included in the base model.

[0126] Here, in this specification, determining the parameters included in the base model is called modeling. Also, the modeled base model is simply called a model.

[0127] Hereinafter, a modeling device for modeling Cgd(Vgs, Vds) will be described.

[0128] <Modeling Device> <<Hardware Configuration>> First, the hardware configuration of the modeling device in the present embodiment will be described.

[0129] FIG. 9 is a diagram showing an example of the hardware configuration of the modeling apparatus 200 in the present embodiment. Note that the configuration shown in FIG. 9 is merely an example of the hardware configuration of the modeling apparatus 200, and the hardware configuration of the modeling apparatus 200 is not limited to the configuration described in FIG. 9 and may be other configurations.

[0130] In FIG. 9, the modeling apparatus 200 includes a CPU (Central Processing Unit) 101 that executes a program. This CPU 101 is electrically connected to, for example, a ROM (Read Only Memory) 102, a RAM (Random Access Memory) 103, and a hard disk device 112 via a bus 113, and is configured to control these hardware devices.

[0131] The CPU 101 is also connected to an input device and an output device via the bus 113. Examples of the input device include a keyboard 105, a mouse 106, a communication board 107, and a scanner 111. On the other hand, examples of the output device include a display 104, a communication board 107, and a printer 110. Further, the CPU 101 may be connected to, for example, a removable disk device 108 or a CD / DVD-ROM device 109.

[0132] The modeling apparatus 200 may be connected to, for example, a network. For example, when the modeling apparatus 200 is connected to other external devices via a network, a communication board 107 that constitutes a part of the modeling apparatus 200 is connected to a LAN (Local Area Network), a WAN (Wide Area Network), or the Internet.

[0133] The RAM 103 is an example of a volatile memory, and the recording media of the ROM 102, the removable disk device 108, the CD / DVD-ROM device 109, and the hard disk device 112 are examples of non-volatile memories. The storage device of the modeling device 200 is configured by these volatile and non-volatile memories.

[0134] For example, an operating system (OS) 201, a program group 202, and a file group 203 are stored in the hard disk device 112. The programs included in the program group 202 are executed by the CPU 101 while using the operating system 201. Also, at least a part of the program of the operating system 201 and application programs to be executed by the CPU 101 are temporarily stored in the RAM 103, and various data necessary for the processing by the CPU 101 are stored.

[0135] A BIOS (Basic Input Output System) program is stored in the ROM 102, and a boot program is stored in the hard disk device 112. When the modeling device 200 is started up, the BIOS program stored in the ROM 102 and the boot program stored in the hard disk device 112 are executed, and the operating system 201 is started up by the BIOS program and the boot program.

[0136] The program group 202 stores programs that realize the functions of the modeling device 200, and these programs are read and executed by the CPU 101. Also, in the file group 203, information, data, signal values, variable values, and parameters indicating the results of the processing by the CPU 101 are stored as each item of the file.

[0137] The file is recorded on a recording medium such as the hard disk device 112 or the memory. Information, data, signal values, variable values, and parameters recorded on a recording medium such as the hard disk device 112 or the memory are read by the CPU 101 into the main memory or the cache memory and used for the operations of the CPU 101 typified by extraction, search, reference, comparison, calculation, processing, editing, output, printing, and display. For example, during the operations of the CPU 101 described above, information, data, signal values, variable values, and parameters are temporarily stored in the main memory, register, cache memory, buffer memory, etc.

[0138] The functions of the modeling device 200 may be realized by the firmware stored in the ROM 102, or alternatively, may be realized by software only, hardware only typified by elements, devices, substrates, and wirings, a combination of software and hardware, or further, a combination with firmware. Firmware and software are recorded as programs on a recording medium typified by the hard disk device 112, removable disk, CD-ROM, DVD-ROM, etc. The program is read and executed by the CPU 101. That is, the program causes the computer to function as the modeling device 200.

[0139] As described above, the modeling device 200 is a computer including the CPU 101 which is a processing device, the hard disk device 112 and the memory which are storage devices, the keyboard 105, the mouse 106, the communication board 107 which are input devices, and the display 104, the printer 110, the communication board 107 which are output devices. And the functions of the modeling device 200 are realized by using the processing device, the storage device, the input device, and the output device.

[0140] <<Functional Block Configuration>> Next, the functional block configuration of the modeling device 200 will be described.

[0141] FIG. 10 is a diagram showing the functional block configuration of the modeling device 200.

[0142] In FIG. 10, the modeling device 200 includes an input unit 301, a first parameter determination unit 302, a second parameter determination unit 303, a third parameter determination unit 304, an output unit 305, and a storage unit 306.

[0143] The input unit 301 is configured to input various data. Further, the input unit 301 is configured to input, for example, the base models Cgd(Vgs, Vds), Cgd(0, Vds - Vgs), and Cgd(0, Vds). Furthermore, condition data indicating the conditions that Cgd(Vgs, Vds) should satisfy is also input to the input unit 301. After these various data, base models, and condition data are input to the input unit 301, they are stored in the storage unit 306.

[0144] The first parameter determination unit 302 is configured to determine the parameters included in Cgd(Vgs, Vds). Specifically, the first parameter determination unit 302 is configured to determine the parameters included in Cgd(Vgs, Vds), which is a function that outputs the gate-drain capacitance when Vgs and Vds are input, based on, for example, the measured switching waveform of the power transistor. More specifically, the first parameter determination unit 302 is configured to determine the parameters of Cgd(Vgs, Vds) based on the gate-drain capacitance measured by monitoring the current flowing into the body region and gate electrode of the power transistor.

[0145] However, the first parameter determination unit 302 is configured to be able to implement not only the above-described parameter determination method but also the parameter determination method described later.

[0146] The second parameter determination unit 303 is configured to determine the parameters included in Cgd(0, Vds). Specifically, the second parameter determination unit 303 is configured to determine the parameters of Cgd(0, Vds) based on, for example, the measured value data obtained by measuring the gate-drain capacitance.

[0147] The third parameter determination unit 304 is configured to determine the parameters included in Cgd(0, Vds - Vgs).

[0148] In addition, the above-described first parameter determination unit 302 is configured to determine the parameters of Cgd(Vgs, Vds) so as to satisfy the conditions defined by the conditional data stored in the storage unit 306 based on Cgd(0, Vds) whose parameters are determined by the second parameter determination unit 303 and Cgd(0, Vds) whose parameters are determined by the third parameter determination unit 304.

[0149] The output unit 305 is configured to output Cgd(Vgs, Vds) having the parameters determined by the first parameter determination unit 302. That is, the output unit 305 is configured to output a model in which parameters are substituted into Cgd(Vgs, Vds). The output unit 305 may be configured to output this model to an external device, or may be configured to output the model so as to store it in the storage unit 306.

[0150] The modeling device 200 is configured as described above.

[0151] <Modeling program> The modeling method implemented by the above-described modeling device 200 can be realized by a modeling program that causes a computer to execute the modeling process.

[0152] For example, in the modeling device 200 composed of a computer shown in FIG. 9, the modeling program according to the present embodiment can be introduced as one of the program groups 202 stored in the hard disk device 112. Then, by causing the computer, which is the modeling device 200, to execute this modeling program, the modeling method according to the present embodiment can be realized.

[0153] A modeling program that causes a computer to execute each process for creating data related to modeling processing can be recorded on a computer-readable recording medium and distributed. Examples of the recording medium include magnetic storage media typified by hard disks and flexible disks, optical storage media typified by CD-ROMs and DVD-ROMs, and hardware devices typified by non-volatile memories such as ROMs and EEPROMs.

[0154] <Simulation device> As described above, by operating the modeling device 200, Cgd(Vgs, Vds) with determined parameters can be obtained. Hereinafter, a simulation device that performs circuit simulation using Cgd(Vgs, Vds) with determined parameters will be described. In the description of the simulation device, Cgd(Vgs, Vds) with determined parameters will be simply denoted as Cgd(Vgs, Vds). That is, until now, Cgd(Vgs, Vds) has meant the base model, but in the description of the simulation device, Cgd(Vgs, Vds) is used in the sense of the base model with determined parameters, that is, the model.

[0155] <<Hardware configuration>> The hardware configuration of the simulation device is, for example, the same as the hardware configuration of the modeling device 200 shown in FIG. 9. That is, basically, the simulation device is also composed of a computer system.

[0156] <<Functional block configuration>> Next, the functional block configuration of the simulation device 300 will be described.

[0157] FIG. 11 is a diagram showing the functional block configuration of the simulation device 300.

[0158] In FIG. 11, the simulation device 300 includes an input unit 401, a setting unit 402, a circuit simulation unit 403, an output unit 404, and a storage unit 405.

[0159] The input unit 401 is configured to input various data. Also, the input unit 301 is configured to input, for example, the model Cgd(Vgs, Vds). Further, circuit data of the circuit to be simulated is also input to the input unit 301. After these various data, models, and circuit data are input to the input unit 401, they are stored in the storage unit 405.

[0160] The setting unit 402 is configured to set the gate-drain capacitance based on Cgd(Vgs, Vds) stored in the storage unit 405. Specifically, when Vgs and Vds are input, the setting unit 402 is configured to substitute the input Vgs and Vds into Cgd(Vgs, Vds). Then, the setting unit 402 is configured to set the gate-drain capacitance output from Cgd(Vgs, Vds) to, for example, the gate-drain capacitance of the power MOSFET that constitutes the circuit.

[0161] The circuit simulation unit 403 is configured to simulate the characteristics of the circuit based on the circuit data indicating the circuit. At this time, in the power MOSFET included in the circuit, the gate-drain capacitance set by the setting unit 402 is used to perform circuit simulation of the circuit including the power MOSFET.

[0162] The output unit 404 is configured to output the result of the simulation performed by the circuit simulation unit 403.

[0163] The simulation device 300 is configured as described above.

[0164] <<Simulation Operation (Simulation Method)>> Next, the operation of the simulation device 300 will be described.

[0165] In advance, circuit data and Cgd(Vgs, Vds) are stored in the storage unit 405.

[0166] First, when Vgs and Vds are input, the setting unit 402 substitutes Vgs and Vds into Cgd(Vgs, Vds). As a result, the gate-drain capacitance is output from Cgd(Vgs, Vds), and the output gate-drain capacitance is set as the gate-drain capacitance of the power MOSFET included in the circuit.

[0167] After that, the circuit simulation unit 403 simulates the characteristics of the circuit based on the circuit data indicating the circuit. In particular, in the power MOSFET included in the circuit, the gate-drain capacitance set by the setting unit 402 is used to perform circuit simulation of the circuit including the power MOSFET.

[0168] Then, the output unit 404 outputs the result of the circuit simulation performed by the circuit simulation unit 403. In this way, the simulation device 300 operates.

[0169] According to the simulation device 300, the gate-drain characteristics of the MOSFET model can be reproduced with high accuracy by a small number of parameters. As a result, according to the simulation device 300, the prediction of the operation failure of the power MOSFET can be made with high accuracy, and thereby the reliability of the power electronics circuit can be ensured.

[0170] <Simulation Program> The simulation method implemented by the above-described simulation apparatus 300 can be realized by a simulation program that causes a computer to execute simulation processing. For example, in the simulation apparatus 300 composed of a computer shown in FIG. 9, the simulation program according to the present embodiment can be introduced as one of the program groups 202 stored in the hard disk device 112. Then, by causing the computer, which is the simulation apparatus 300, to execute this simulation program, the simulation method according to the present embodiment can be realized.

[0171] A simulation program that causes a computer to execute each process for creating data related to simulation processing can be recorded on a computer-readable recording medium and distributed. The recording medium includes, for example, magnetic storage media typified by hard disks and flexible disks, optical storage media typified by CD-ROMs and DVD-ROMs, and hardware devices typified by non-volatile memories such as ROMs and EEPROMs.

[0172] <Verification of Effects> The verification results of the effects by Cgd(Vgs, Vds) in the present embodiment will be described.

[0173] FIG. 12 is a diagram showing the relationship between Cgd and Vds in the case of Vgs = 0V (off state).

[0174] In FIG. 12, the graph of the actually measured value of Cgd is shown by a dotted line, and the graph of Cgd(0, Vds - Vgs) is shown by a solid line. Regarding the actually measured value, since Vgs = 0V, capacitance measurement is possible as static characteristics, and the result is shown by the graph of the dotted line.

[0175] As shown in FIG. 12, it can be seen that when Vgs = 0V (off state), both Cgd(0, Vds - Vgs) and the actually measured value can be fitted with good accuracy.

[0176] FIG. 13 is a diagram showing the relationship between Cgd and Vds at Vgs = 2V (off state).

[0177] In FIG. 13, the graph of the measured value of Cgd is shown by a dotted line, and the graphs of Cgd(0, Vds - Vgs) and Cgd(0, Vds) are shown by solid lines. Also, Cgd(Vgs, Vds) is shown by a dashed-dotted line.

[0178] Regarding the measured value, since Vgs = 2V, it is difficult to measure the capacitance. However, the inventor has measured the measured value of Cgd by a special method. Specifically, the inventor has measured Cgd by monitoring the current flowing into the body region and the gate electrode of the power transistor, which is shown by the dotted-line graph.

[0179] As shown in FIG. 13, it can be seen that the measured value does not match either Cgd(0, Vds) or Cgd(0, Vds - Vgs), and a large error occurs. On the other hand, it can be seen that Cgd(Vgs, Vds), which is the model in this embodiment, fits well with the measured value and can reproduce the measured value with high accuracy.

[0180] FIG. 14 is a diagram showing the relationship between Cgd and Vds at Vgs = 6V (on state).

[0181] In FIG. 14, the graph of the measured value of Cgd is shown by a dotted line, and the graphs of Cgd(0, Vds - Vgs) and Cgd(0, Vds) are shown by solid lines. Also, Cgd(Vgs, Vds) is shown by a dashed-dotted line.

[0182] Regarding the measured value, since Vgs = 6V, it is difficult to measure the capacitance. However, the inventor has measured the measured value of Cgd by a special method. Specifically, the inventor has measured Cgd by monitoring the current flowing into the body region and the gate electrode of the power transistor, which is shown by the dotted-line graph.

[0183] As shown in FIG. 14, it can be seen that the measured values do not match either Cgd(0, Vds) or Cgd(0, Vds - Vgs) and deviate significantly. On the other hand, Cgd(Vgs, Vds) which is the model in this embodiment fits well with the measured values, indicating that it can reproduce the measured values with high accuracy.

[0184] From the above, it is verified that according to Cgd(Vgs, Vds) in this embodiment, even in the state where Vgs ≠ 0, the measured values can be reproduced with high accuracy.

[0185] Thereby, according to this embodiment, simulation of high-precision circuit characteristics becomes possible. For example, in the on state, the switching speed (dV / dt) is inversely proportional to Cgd corresponding to a high Vds.

[0186] Regarding this point, for example, referring to FIG. 14, at a high Vds, Cgd(0, Vds - Vgs) is half of the measured value. Therefore, when simulating the switching speed with Cgd(0, Vds - Vgs), the switching speed will become twice the actual value.

[0187] In contrast, since Cgd(Vgs, Vds) in this embodiment accurately reproduces the measured values, when simulating the switching speed with Cgd(Vgs, Vds), the switching speed can be reproduced almost accurately. Therefore, according to this embodiment, the accuracy of circuit simulation can be improved.

[0188] The invention made by the present inventor has been specifically described based on its embodiments above. Needless to say, the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof.

[0189] The above embodiments include the following forms.

[0190] (Appendix 1) A program for causing a computer to execute circuit simulation, comprising a setting process for setting the gate-drain capacitance based on the function Cgd(Vgs, Vds) that outputs the gate-drain capacitance when the gate-source voltage Vgs and the drain-source voltage Vds are input.

[0191] (Appendix 2) A program for causing a computer to execute function modeling, comprising a determination process for determining the parameters included in the function Cgd(Vgs, Vds) that outputs the gate-drain capacitance when the gate-source voltage Vgs and the drain-source voltage Vds are input based on the measured switching waveform of the power transistor.

Explanation of Symbols

[0192] BR Body region Cds Drain-source capacitance Cgd Gate-drain capacitance Cgs Gate-source capacitance D Drain terminal DPL Depletion layer EPI Epitaxial layer KS Kelvin source terminal G Gate terminal GE Gate electrode PS Power source terminal S Source terminal SE Source electrode SR Source region SUB Semiconductor substrate Tc Thermal path terminal Tj Thermal circuit terminal 10 JFET region 100 MOSFET model 101 CPU 102 ROM 103 RAM 104 Display 105 Keyboard 106 Mouse 107 Communication board 108 Removable disk device 109 CD / DVD-ROM device 110 Printer 111 Scanner 112 Hard disk device 200 Modeling device 201 Operating system 202 Program group 203 File group 300 Simulation device 301 Input section 302 First parameter determination section 303 Second parameter determination section 304 Third parameter determination section 305 Output section 306 Memory section 401 Input section 402 Setting section 403 Circuit simulation section 404 Output section 405 Memory section

Claims

1. An input unit that inputs a gate-source voltage Vgs, which is the voltage between the gate and the source of a power transistor, and a drain-source voltage Vds, which is the voltage between the drain and the source of the power transistor; A setting unit that sets a gate-drain capacitance Cgd, which is the capacitance between the gate and the drain of the power transistor, based on the gate-source voltage Vgs and the drain-source voltage Vds; A simulation device comprising: The setting unit sets the gate-drain capacitance Cgd based on Cgd(Vgs, Vds), which is a function of the gate-source voltage Vgs and the drain-source voltage Vds. A simulation device.

2. In the simulation device according to Claim 1, Assuming Cgd(0, Vds) = Cgd(Vgs = 0, Vds), And assuming Cgd(0, Vds - Vgs) = Cgd(Vgs = 0, Vds - Vgs), Cgd(Vgs, Vds) is a simulation device that satisfies the following conditions. (1) When Vgs < Vm(Isw), Cgd(Vgs, Vds) takes a value intermediate between Cgd(0, Vds) and Cgd(0, Vds - Vgs), (2) When Vgs > Vm(Isw) and Vds < Vcross(Vgs), Cgd(Vgs, Vds) takes a value intermediate between Cgd(0, Vds) and Cgd(0, Vds - Vgs), (3) When Vgs > Vm(Isw) and Vds > Vcross(Vgs), Cgd(0, Vds - Vgs) < Cgd(Vgs, Vds), Here, Vm(Isw) is a function of the drain-source current Isw, It means the gate-source voltage during the Miller period, Vcross(Vgs) is a function of Vgs, In the case where Vgs > Vm(Isw), it means the drain-source voltage at which Cgd(0, Vds - Vgs) = Cgd(Vgs, Vds).

3. In the simulation device according to Claim 2, Vm(Isw) is composed of a function that monotonically increases with respect to Isw. A simulation device.

4. In the simulation device according to Claim 2, Vcross(Vgs) is composed of a function that monotonically increases with respect to Vgs. A simulation device.

5. In the simulation device according to Claim 2, A simulation device, Cgd(Vgs, Vds), includes as a component the sum of Cgd1(Vgs, Vds) and Cgd2(Vgs, Vds) and satisfies the following conditions. (1) When Vgs > 0 and Vds = 0, Cgd2(Vgs, Vds) > Cgd1(Vgs, Vds), (2) When Vgs > 0 and Vds → ∞, Cgd2(Vgs, Vds) < Cgd1(Vgs, Vds).

6. In the simulation device according to claim 5, Cgd1(Vgs, Vds) includes a function part of A × (1 - tanh(Vdep)) + C, A is composed of at least a function of Vgs, C is composed of at least a function of Vgs, Vdep is a function approximating the gate-drain voltage Vgd and is composed of at least functions of Vgs and Vds, A simulation device.

7. In the simulation device according to claim 6, Vdep is composed of a function that monotonically decreases with respect to Vgs and monotonically increases with respect to Vds in the region where Vgs > 0. A simulation device.

8. In the simulation device according to claim 5, Cgd2(Vgs, Vds) includes a functional part of D×(Vepi) －Ｅ and includes the following functional part D is a coefficient, E satisfies 0.4 ≦ E ≦ 0.6, Vepi is a function approximating the gate-drain voltage Vgd and is composed of at least functions of Vgs and Vds, A simulation device.

9. In the simulation device according to claim 8, Vepi is composed of a function that monotonically decreases with respect to Vgs and monotonically increases with respect to Vds. A simulation device.

10. An input step of inputting a gate-source voltage Vgs, which is a voltage between the gate and the source of a power transistor, and a drain-source voltage Vds, which is a voltage between the drain and the source of the power transistor; A setting step of setting a gate-drain capacitance Cgd, which is a capacitance between the gate and the drain of the power transistor, based on the gate-source voltage Vgs and the drain-source voltage Vds; A simulation method comprising: In the setting step, the gate-drain capacitance Cgd is set based on Cgd(Vgs, Vds), which is a function of the gate-source voltage Vgs and the drain-source voltage Vds. A simulation method.

11. In the simulation method according to claim 10, Let \(C_{gd}(0, V_{ds}) = C_{gd}(V_{gs} = 0, V_{ds})\), and if \(C_{gd}(0, V_{ds}-V_{gs}) = C_{gd}(V_{gs} = 0, V_{ds}-V_{gs})\), \(C_{gd}(V_{gs}, V_{ds})\) is a simulation method that satisfies the following conditions. (1) When \(V_{gs}<V_m(I_{sw})\), \(C_{gd}(V_{gs}, V_{ds})\) takes a value intermediate between \(C_{gd}(0, V_{ds})\) and \(C_{gd}(0, V_{ds}-V_{gs})\), (2) When \(V_{gs}>V_m(I_{sw})\) and \(V_{ds}<V_{cross}(V_{gs})\), \(C_{gd}(V_{gs}, V_{ds})\) takes a value intermediate between \(C_{gd}(0, V_{ds})\) and \(C_{gd}(0, V_{ds}-V_{gs})\), (3) When \(V_{gs}>V_m(I_{sw})\) and \(V_{ds}>V_{cross}(V_{gs})\), \(C_{gd}(0, V_{ds}-V_{gs})<C_{gd}(V_{gs}, V_{ds})\), Here, \(V_m(I_{sw})\) is a function of the drain-source current \(I_{sw}\) and represents the gate-source voltage during the Miller period, \(V_{cross}(V_{gs})\) is a function of \(V_{gs}\), and when \(V_{gs}>V_m(I_{sw})\), it represents the drain-source voltage at which \(C_{gd}(0, V_{ds}-V_{gs}) = C_{gd}(V_{gs}, V_{ds})\).

12. An input unit that inputs the gate-source voltage \(V_{gs}\), which is the voltage between the gate and the source of the power transistor, and the drain-source voltage \(V_{ds}\), which is the voltage between the drain and the source of the power transistor, based on the measured switching waveform of the power transistor; A first parameter determination unit that determines the parameters included in \(C_{gd}(V_{gs}, V_{ds})\), which is a function of the gate-source voltage \(V_{gs}\) and the drain-source voltage \(V_{ds}\) and outputs the gate-drain capacitance \(C_{gd}\); A modeling device comprising: The first parameter determination unit determines the parameters included in \(C_{gd}(V_{gs}, V_{ds})\) based on the gate-source voltage \(V_{gs}\) and the drain-source voltage \(V_{ds}\) input to the input unit.

13. In the modeling device according to claim 12, Let \(C_{gd}(0, V_{ds}) = C_{gd}(V_{gs} = 0, V_{ds})\), and if \(C_{gd}(0, V_{ds}-V_{gs}) = C_{gd}(V_{gs} = 0, V_{ds}-V_{gs})\), the modeling device has a second parameter determination unit that determines the parameters of \(C_{gd}(0, V_{ds})\) and a third parameter determination unit that determines the parameters of \(C_{gd}(0, V_{ds}-V_{gs})\), and The first parameter determination unit determines the parameter of Cgd(Vgs, Vds) based on Cgd(0, Vds) whose parameter is determined by the second parameter determination unit and Cgd(0, Vds) whose parameter is determined by the third parameter determination unit, such that Cgd(Vgs, Vds) satisfies the following conditions. A modeling device. When (1) Vgs < Vm(Isw), Cgd(Vgs, Vds) takes a value intermediate between Cgd(0, Vds) and Cgd(0, Vds - Vgs), When (3) Vgs > Vm(Isw) and Vds < Vcross(Vgs), Cgd(Vgs, Vds) takes a value intermediate between Cgd(0, Vds) and Cgd(0, Vds - Vgs), When (5) Vgs > Vm(Isw) and Vds > Vcross(Vgs), Cgd(0, Vds - Vgs) < Cgd(Vgs, Vds), Here, Vm(Isw) is a function of the drain-source current Isw and represents the gate-source voltage during the Miller period. Vm(Isw) is a function of the drain-source current Isw and represents the gate-source voltage during the Miller period. Vcross(Vgs) is a function of Vgs and represents the drain-source voltage at which Cgd(0, Vds - Vgs) = Cgd(Vgs, Vds) when Vgs > Vm(Isw). Vcross(Vgs) is a function of Vgs and represents the drain-source voltage at which Cgd(0, Vds - Vgs) = Cgd(Vgs, Vds) when Vgs > Vm(Isw).

14. In the modeling device according to claim 13, The second parameter determination unit determines the parameter of Cgd(0, Vds) based on the data obtained by measuring the gate-drain capacitance. A modeling device.

15. In the modeling device according to claim 12, The first parameter determination unit determines the parameter of Cgd(Vgs, Vds) based on the gate-drain capacitance measured by monitoring the current flowing into the body region and the gate electrode of the power transistor. A modeling device.

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