Chip hybrid simulation method based on general verification methodology and image processing algorithm

Abstract

Disclosed in the present application is a chip hybrid simulation method based on general verification methodology and an image processing algorithm. The method comprises: upon receiving a chip simulation task, starting a verification platform; inputting excitation data into a design module under test, and performing simulation processing on a target chip, so as to obtain simulation output data; transmitting to an image processing model the simulation output data and the excitation data to be processed, and converting the formats thereof, so as to obtain a simulation data code stream and an excitation data code stream; processing the excitation data code stream, so as to obtain an image algorithm output data code stream; and comparing the simulation data code stream with the image algorithm output data code stream, so as to obtain a verification result. The present application solves the technical problem that chip simulation verification modes in the prior art isolate the interconnection and connectivity between image algorithm models and UVM simulation verification platforms, are thus prone to cause data errors and algorithm processing flow errors, and therefore reduce the simulation efficiency and accuracy of the UVM platforms.

Description

Chip hybrid simulation method based on general verification methodology and image processing algorithm

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 29, 2023, with application number 202311862988.8 and application name “Chip hybrid simulation method based on general verification methodology and image processing algorithm”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of chip simulation control technology, and in particular to a chip hybrid simulation method based on general verification methodology and image processing algorithm. Background Art

[0003] For consumer electronic products in the chip field (for example, computers, notebooks, tablets, monitors, TVs, etc.), more and more products need to use image processing and optimization to achieve more perfect display effects, reduce power consumption and increase refresh rate.

[0004] To ensure timely market launch of electronic products, high chip quality, high stability, and high efficiency have become the key to competitiveness and advantages of various electronic products. As display screens become increasingly larger and faster, and image processing algorithms become more complex, the efficiency and accuracy of chip front-end simulation and verification are becoming unprecedentedly challenging.

[0005] Currently, simulation verification for image processing chips generally follows this approach: Algorithm engineers develop a specific image processing algorithm, then write an algorithm model in a programming language (such as C, Python, or MATLAB) for algorithm verification and output the algorithm data. Chip verification engineers then build a UVM simulation verification platform, simulate the device under test (DUT), and output the simulation data. Finally, the two sets of data are compared one-to-one to obtain the overall design comparison results. This chip verification approach isolates the interconnectivity and connectivity between the algorithm model and the UVM simulation verification platform, resulting in data errors and errors in the algorithm processing flow, reducing the simulation efficiency and accuracy of the UVM platform and hindering the reuse and acceleration of subsequent test cases.

[0006] The method used to simulate and verify the chip in the above-mentioned related technologies isolates the interconnectivity and connectivity between the image algorithm model and the UVM simulation verification platform, which easily causes data errors and algorithm processing errors, thereby reducing the simulation efficiency and accuracy of the UVM platform. No effective solution has been proposed yet.

[0007] Summary of the Invention

[0008] The embodiment of the present application provides a chip hybrid simulation method based on a general verification methodology and an image processing algorithm, which at least solves the technical problem that the method used in the related art for simulating and verifying the chip isolates the interconnectivity and connectivity of the image algorithm model and the UVM simulation verification platform, which easily causes data errors and algorithm processing flow errors, thereby reducing the simulation efficiency and accuracy of the UVM platform.

[0009] According to one aspect of an embodiment of the present application, a chip hybrid simulation method based on a general verification methodology and an image processing algorithm is provided, comprising: after receiving a chip simulation task, generating a startup instruction based on the chip simulation task to trigger the startup of a verification platform of the general verification methodology, wherein the verification platform is integrated with an image processing model; after the simulation operating environment of the verification platform is running, inputting stimulus data into a design module to be tested, so as to use the stimulus data to simulate a target chip corresponding to the chip simulation task in the design module to be tested, and obtain simulation output data; obtaining the stimulus data and the simulation output data, and sending the stimulus data and the simulation output data to the image processing module; model, using the image processing model to analyze and process the output data to obtain a simulation result of the target chip; performing format conversion on the simulation output data and the excitation data in the image processing model to obtain a simulation data code stream and an excitation data code stream that can be recognized by the image processing algorithm in the image processing model; processing the excitation data code stream using the image processing algorithm to obtain an image algorithm output data code stream; comparing the simulation data code stream in the image processing model with the image algorithm output data code stream to obtain a verification result of the target chip according to the comparison result, wherein the verification result is used to indicate whether the actual function of the target chip is consistent with the function description information.

[0010] Optionally, before generating a startup instruction based on the chip simulation task to trigger the startup of a general verification methodology verification platform, the chip hybrid simulation method based on general verification methodology and image processing algorithm also includes: calling the logic code design of the design module to be tested to obtain the design module to be tested, wherein the logic code is a code pre-written according to the chip simulation requirements; determining the multiple components required to generate the verification platform according to the functional description information of the target chip, wherein the multiple components are components required for simulating the target chip; packaging the multiple components using the methodology architecture corresponding to the verification platform, and connecting the multiple packaged components to obtain the verification platform including the design module to be tested and the multiple packaged and connected components.

[0011] Optionally, after the simulation operating environment of the verification platform is running, the stimulus data is input into the design module to be tested, so as to use the stimulus data to simulate the target chip corresponding to the chip simulation task in the design module to be tested, and obtain simulation output data, including: triggering the top-level configuration module in the verification platform to start, so as to use the top-level configuration module to configure the registers of the design module to be tested according to the functional description information of the target chip, and using the top-level configuration module to set the simulation environment of the verification platform; triggering the scenario stimulator in the verification platform to start, so as to generate the stimulus data, and inputting the stimulus data into the design module to be tested, so as to use the stimulus data to drive the design module to be tested, simulate the target chip, and obtain the simulation output data.

[0012] Optionally, the simulation output data and the stimulus data in the image processing model are format-converted to obtain a simulation data code stream recognizable by the image processing algorithm in the image processing model, including: in the process of inputting the stimulus data into the design module to be tested so as to use the stimulus data to simulate the target chip in the design module to be tested, triggering the logic monitor of the verification platform to start up to collect the stimulus data and the simulation output data, and inputting the stimulus data and the simulation output data into the image processing model; after determining that the image processing model has received the simulation output data, using the data processing module in the image processing model to format-convert the simulation output data to obtain the simulation data code stream.

[0013] Optionally, before using the image processing algorithm to process the excitation data code stream to obtain the image algorithm output data code stream, the chip hybrid simulation method based on general verification methodology and image processing algorithm also includes: obtaining the configuration information of the register model in the verification platform and the setting information of the simulation environment in the verification platform; sending the configuration information and the setting information to the configuration module of the image processing model, so as to use the configuration module to pre-process the configuration information and the setting information, so that the configuration module is paired and integrated with the top-level configuration module of the verification platform.

[0014] Optionally, the excitation data code stream is processed using the image processing algorithm to obtain an image algorithm output data code stream, including: using the image processing algorithm and the configuration information of the register model in the verification platform to perform predetermined dimension analysis and processing on the excitation data code stream to obtain the image algorithm output data code stream, wherein the predetermined dimension includes at least one of the following: pixel depth, color temperature, contrast, color vividness, and transition smoothness.

[0015] Optionally, the simulation data code stream and the image algorithm output data code stream in the image processing model are compared to obtain a verification result of the target chip based on the comparison result, including: comparing the simulation data code stream and the image algorithm output data code stream in the image processing model to obtain a comparison result; when the comparison result indicates that the simulation data code stream is consistent with the image algorithm output data or the number of inconsistencies between the simulation data code stream and the image algorithm output data is less than a predetermined threshold, determining that the actual function of the target chip is consistent with the function description information; when the comparison result indicates that the number of inconsistencies between the simulation data code stream and the image algorithm output data is not less than a predetermined threshold, determining that the actual function of the target chip is inconsistent with the function description information.

[0016] Optionally, after comparing the simulation data code stream in the image processing model and the image algorithm output data code stream to obtain the verification result of the target chip based on the comparison result, the chip hybrid simulation method based on general verification methodology and image processing algorithm also includes: storing the verification result in a log.

[0017] According to another aspect of an embodiment of the present application, a chip hybrid simulation device based on a general verification methodology and an image processing algorithm is also provided, including: a trigger unit for generating a startup instruction based on the chip simulation task after receiving a chip simulation task, so as to trigger the startup of a verification platform of a general verification methodology, wherein the verification platform is integrated with an image processing model; a first acquisition unit for inputting stimulus data into a design module to be tested after the simulation running environment of the verification platform is running, so as to use the stimulus data to simulate the target chip corresponding to the chip simulation task in the design module to be tested to obtain simulation output data; a second acquisition unit for acquiring the stimulus data and the simulation output data, and sending the stimulus data and the simulation output data to the image processing module type, so as to analyze and process the output data by using the image processing model to obtain the simulation result of the target chip; a third acquisition unit is used to convert the format of the simulation output data and the excitation data in the image processing model to obtain a simulation data code stream and an excitation data code stream that can be recognized by the image processing algorithm in the image processing model; a fourth acquisition unit is used to process the excitation data code stream by using the image processing algorithm to obtain an image algorithm output data code stream; a fifth acquisition unit is used to compare the simulation data code stream and the image algorithm output data code stream in the image processing model to obtain a verification result of the target chip according to the comparison result, wherein the verification result is used to indicate whether the actual function of the target chip is consistent with the function description information.

[0018] Optionally, the chip hybrid simulation device based on general verification methodology and image processing algorithm also includes: a sixth acquisition unit, used to call the logic code design of the design module to be tested to obtain the design module to be tested before generating a startup instruction based on the chip simulation task to trigger the startup of the general verification methodology verification platform, wherein the logic code is a code pre-written according to the chip simulation requirements; a determination unit, used to determine the multiple components required to generate the verification platform according to the functional description information of the target chip, wherein the multiple components are components required for simulating the target chip; a seventh acquisition unit, used to package the multiple components using the methodology architecture corresponding to the verification platform, and connect the packaged multiple components to obtain the verification platform including the design module to be tested and the packaged and connected multiple components.

[0019] Optionally, the first acquisition unit includes: a first trigger module, used to trigger the startup of the top-level configuration module in the verification platform, so as to use the top-level configuration module to configure the registers of the design module to be tested according to the functional description information of the target chip, and use the top-level configuration module to set the simulation environment of the verification platform; a second trigger module, used to trigger the startup of the scenario stimulator in the verification platform to generate the stimulus data, and input the stimulus data into the design module to be tested, so as to use the stimulus data to drive the design module to be tested, simulate the target chip, and obtain the simulation output data.

[0020] Optionally, the third acquisition unit includes: a third trigger module, which is used to trigger the start-up of the logic monitor of the verification platform when inputting the stimulus data into the design module to be tested so as to simulate the target chip in the design module to be tested using the stimulus data, so as to collect the stimulus data and the simulation output data, and input the stimulus data and the simulation output data into the image processing model; a first acquisition module, which is used to convert the format of the simulation output data using the data processing module in the image processing model after determining that the image processing model has received the simulation output data, so as to obtain the simulation data code stream.

[0021] Optionally, the chip hybrid simulation device based on general verification methodology and image processing algorithm also includes: an eighth acquisition unit, used to obtain the configuration information of the register model in the verification platform and the setting information of the simulation environment in the verification platform before using the image processing algorithm to process the excitation data code stream to obtain the image algorithm output data code stream; a processing unit, used to send the configuration information and the setting information to the configuration module of the image processing model, so as to use the configuration module to pre-process the configuration information and the setting information, so that the configuration module is paired and integrated with the top-level configuration module of the verification platform.

[0022] Optionally, the fourth acquisition unit includes: a second acquisition module, used to use the image processing algorithm and the configuration information of the register model in the verification platform to analyze and process the excitation data code stream in predetermined dimensions to obtain the image algorithm output data code stream, wherein the predetermined dimension includes at least one of the following: pixel depth, color temperature, contrast, color vividness, and transition smoothness.

[0023] Optionally, the fifth acquisition unit includes: a third acquisition module, used to compare the simulation data code stream and the image algorithm output data code stream in the image processing model to obtain a comparison result; a first determination module, used to determine that the actual function of the target chip is consistent with the function description information when the comparison result indicates that the simulation data code stream is consistent with the image algorithm output data or the number of inconsistencies between the simulation data code stream and the image algorithm output data is less than a predetermined threshold; a second determination module, used to determine that the actual function of the target chip is inconsistent with the function description information when the comparison result indicates that the number of inconsistencies between the simulation data code stream and the image algorithm output data is not less than a predetermined threshold.

[0024] Optionally, the chip hybrid simulation device based on general verification methodology and image processing algorithm also includes: a storage unit compares the simulation data code stream in the image processing model and the image algorithm output data code stream to obtain a verification result of the target chip based on the comparison result, wherein the verification result is used to indicate whether the actual function of the target chip is consistent with the function description information, and then the verification result is stored in a log.

[0025] According to another aspect of an embodiment of the present application, a chip hybrid simulation system based on a general verification methodology and an image processing algorithm is also provided. The chip hybrid simulation system based on a general verification methodology and an image processing algorithm uses any of the above-mentioned chip hybrid simulation methods based on a general verification methodology and an image processing algorithm.

[0026] According to another aspect of an embodiment of the present application, a computer-readable storage medium is further provided, wherein the computer-readable storage medium includes a stored program, wherein the program executes any one of the above-mentioned chip hybrid simulation methods based on the general verification methodology and image processing algorithm.

[0027] According to another aspect of an embodiment of the present application, a processor is further provided, which is used to run a program, wherein when the program is running, any one of the above-mentioned chip hybrid simulation methods based on the general verification methodology and image processing algorithm is executed.

[0028] In an embodiment of the present application, after receiving a chip simulation task, a startup instruction is generated based on the chip simulation task to trigger the startup of a universal verification methodology verification platform, wherein the verification platform is integrated with an image processing model; after the simulation operating environment of the verification platform is running, the stimulus data is input into the design module to be tested, so as to use the stimulus data to simulate the target chip corresponding to the chip simulation task in the design module to obtain simulation output data; the stimulus data and simulation output data are obtained, and the stimulus data and simulation output data are sent to the image processing model, so as to use the image processing model to analyze and process the output data to obtain the simulation result of the target chip; the simulation output data and the stimulus data in the image processing model are processed. Perform format conversion to obtain a simulation data code stream and an excitation data code stream that are recognizable by the image processing algorithm in the image processing model; use the image processing algorithm to process the excitation data code stream to obtain an image algorithm output data code stream; compare the simulation data code stream and the image algorithm output data code stream in the image processing model to obtain a verification result of the target chip based on the comparison result, wherein the verification result is used to indicate whether the actual function of the target chip is consistent with the function description information. Through the above technical scheme, the image algorithm model and the UVM simulation verification platform are integrated together. While the target chip is simulated by the chip simulation verification platform, the input data and simulation output data used for the simulation can be input into the image processing model so that the image processing model can be used to process the input data at the algorithm level. Therefore, it is possible to comprehensively verify whether the actual function of the target chip is consistent with its function description information based on the simulation output result and the image algorithm model processing result. The image algorithm model and the UVM simulation verification platform are interconnected to avoid data errors and algorithm processing process errors, thereby improving the simulation efficiency and accuracy of the UVM platform, thereby solving the technical problem that the method used for chip simulation verification in the related art isolates the interconnectivity and connectivity of the image algorithm model and the UVM simulation verification platform, which easily causes data errors and algorithm processing process errors, thereby reducing the simulation efficiency and accuracy of the UVM platform. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0030] FIG1 is a hardware structure block diagram of a mobile terminal of an embodiment of the present application using a chip hybrid simulation method based on a general verification methodology and an image processing algorithm;

[0031] FIG2 is a flow chart of a chip hybrid simulation method based on a general verification methodology and an image processing algorithm according to an embodiment of the present application;

[0032] FIG3 is a schematic diagram of a chip simulation verification platform according to an embodiment of the present application;

[0033] FIG4 is a flow chart of an optional chip hybrid simulation method based on a general verification methodology and an image processing algorithm according to an embodiment of the present application;

[0034] FIG5 is a schematic diagram of a chip simulation verification process according to an embodiment of the present application;

[0035] FIG6 is a schematic diagram of a chip hybrid simulation device based on a universal verification methodology and an image processing algorithm according to an embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0037] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0038] As described in the background, the methods used to simulate and verify chips in related technologies isolate the interconnectivity and connectivity between the image algorithm model and the UVM simulation verification platform, which can easily lead to data errors and algorithm processing errors, thereby reducing the simulation efficiency and accuracy of the UVM platform. To address these shortcomings, an embodiment of the present application provides a hybrid chip simulation method based on a universal verification methodology and an image processing algorithm.

[0039] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application.

[0040] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a mobile terminal as an example, FIG1 is a hardware structure block diagram of a mobile terminal of a chip hybrid simulation method based on a general verification methodology and an image processing algorithm in an embodiment of the present application. As shown in FIG1 , the mobile terminal may include one or more (only one is shown in FIG1 ) processors 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the mobile terminal may also include a transmission device 106 and an input and output device 108 for communication functions. It will be understood by those skilled in the art that the structure shown in FIG1 is only for illustration and does not limit the structure of the mobile terminal. For example, the mobile terminal may also include more or fewer components than those shown in FIG1 , or have a configuration different from that shown in FIG1 .

[0041] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the chip hybrid simulation method based on the general verification methodology and image processing algorithm in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implementing the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely located relative to the processor 102, and these remote memories can be connected to the mobile terminal via a network. Examples of the above-mentioned networks include but are not limited to the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. The transmission device 106 is used to receive or send data via a network. The specific example of the above-mentioned network may include a wireless network provided by the communication provider of the mobile terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so that it can communicate with the Internet. In one example, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0042] According to an embodiment of the present application, a method embodiment of a chip hybrid simulation method based on a general verification methodology and an image processing algorithm is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0043] FIG2 is a flow chart of a chip hybrid simulation method based on a general verification methodology and an image processing algorithm according to an embodiment of the present application. As shown in FIG2 , the method includes the following steps:

[0044] Step S202 : after receiving the chip simulation task, generating a startup instruction based on the chip simulation task to trigger the startup of a universal verification methodology verification platform, wherein the verification platform is integrated with an image processing model.

[0045] Optionally, the aforementioned universal verification methodology (English name: Universal Verification Methodology, abbreviated as: UVM) is a standard verification methodology for integrated circuit design, which is derived from open verification methodology and provides a greater degree of automation.

[0046] According to the above-mentioned embodiment of the present application, before the above-mentioned step S202, that is, before generating a startup instruction based on the chip simulation task to trigger the startup of the general verification methodology verification platform, the chip hybrid simulation method based on the general verification methodology and image processing algorithm also includes: calling the logic code design of the design module to be tested to obtain the design module to be tested, wherein the logic code is a code pre-written according to the chip simulation requirements; determining the multiple components required to generate the verification platform according to the functional description information of the target chip, wherein the multiple components are the components required for simulating the target chip; packaging the multiple components using the methodology architecture corresponding to the verification platform, and connecting the multiple packaged components to obtain a verification platform including the design module to be tested and the multiple packaged and connected components.

[0047] The above embodiment of the present application is described in detail below in conjunction with Figure 3, which is a schematic diagram of a chip simulation verification platform according to an embodiment of the present application. As shown in Figure 3, before the chip simulation begins, a chip simulation verification platform based on UVM will be established. The platform mainly includes: a top-level module (test_top) and a module to be tested. The top-level environment of the top-level module includes: a top-level configuration (top_cfg), an image processing model (alg_model), a register model (reg_model), an algorithm agent (alg_agent), a logic monitor (dut_monitor), a scene exciter (video_seq), etc.; secondly, the simulation software, scripts, and file paths, etc. must be set.

[0048] The following is an explanation of the functions of each module in the chip simulation verification platform:

[0049] 1) Top-level module (test_top): Responsible for establishing the entire simulation environment by calling the logic code of the design under test (DUT) and encapsulating components such as the top-level environment (top_env), top-level configuration (top_cfg), register model (reg_model), and registers (i.e., registers in the DUT module) based on the UVM methodology architecture, and connecting various modules to form an integrated simulation environment;

[0050] 2) Top-level environment (top_env): Responsible for calling the top-level module (test_top), register model (reg_model), image processing model (alg_model), algorithm agent (alg_agent), etc., providing configuration information (including video image color depth, length, number of frames, number of pixels, register configuration bus type, rate and number of lanes, etc.), module enable, module connection, data transfer and other information to various modules, and incorporating them into the top_env module. During the simulation process, the function methods in the module are automatically called to realize the module functions;

[0051] 3) Top-level configuration (top_cfg): responsible for providing various configurations of the entire algorithm function module, including: environment configuration, process configuration, data flow configuration, register function configuration, comparison mechanism configuration, etc.

[0052] 4) Register model (reg_model): responsible for providing the register model of the entire simulation environment, realizing the reading, writing, resetting, dynamic configuration, static configuration, etc. of the register. Among them, the register model here is the UVM simulation verification platform;

[0053] 5) Image processing model (alg_model): responsible for calling the algorithm program model written in Python, and analyzing and comparing the algorithm processing data and DUT output data based on the register configuration information;

[0054] 6) Algorithm Agent (alg_agent): Responsible for instantiating the logic monitor (dut_monitor) and scene stimulator (video_seq), as well as inter-module connections. The instantiated module is embedded in the algorithm agent by directly calling the module name and trying the functions and methods inside the instantiated module;

[0055] 7) Logic Monitor (dut_monitor): responsible for monitoring the input and output data of the logic code and transmitting them to the image processing model;

[0056] 8) Scene stimulator (video_seq): Responsible for generating input stimulus data for the algorithm model and DUT. By importing the video image color depth, length, number of frames, number of pixels and other configurations of reg_model and top_cfg, it generates input signals such as bit data stream, DE, vsync, hsync, and connects to the DUT module interface.

[0057] Step S204, after the simulation running environment of the verification platform is running, the stimulus data is input into the design module to be tested, so as to simulate the target chip corresponding to the chip simulation task in the design module to obtain simulation output data using the stimulus data.

[0058] Optionally, the above simulation output data can be used as a reference to verify whether the actual function of the target chip is consistent with the functional description information.

[0059] In this embodiment, after the simulation running environment of the verification platform is running, the scenario stimulator in the verification platform can be triggered to start to generate stimulus data. The stimulus data is then used as a driver for the design module to be tested to simulate the target chip.

[0060] Fig. 4 is a flow chart of a chip hybrid simulation method based on a general verification methodology and an image processing algorithm according to an optional embodiment of the present application. As shown in Figure 4, when chip simulation starts, the version, file path, and environment variables of the simulation software are first configured; then the simulation script is run in the system terminal. At this time, a simulation verification platform based on UVM methodology will be established. The simulation platform is divided into two parts: one is the logic code DUT; the other is the environment integration component. These components mainly include top-level modules (test_top), top-level environment (top_env), top-level configuration (top_cfg), register model (reg_model), image processing model (alg_model), algorithm agent (alg_agent), etc.

[0061] Next, after the entire simulation environment is established, the simulation platform will automatically start the simulation process, perform real-time image algorithm model processing, DUT synchronous simulation and data interaction, etc.; finally, the simulation platform automatically processes data, analyzes and compares all data information, register configuration information, etc., analyzes simulation results and data content, and finally confirms the correct judgment results of the design simulation, and then ends the entire simulation process, saving simulation data log records, simulation files and waveforms, etc.

[0062] According to the above-mentioned embodiment of the present application, in the above-mentioned step S204, after the simulation operating environment of the verification platform is running, the stimulus data is input into the design module to be tested, so as to use the stimulus data to simulate the target chip corresponding to the chip simulation task in the design module to be tested, and obtain simulation output data, including: triggering the top-level configuration module in the verification platform to start, so as to use the top-level configuration module to configure the registers of the design module to be tested according to the functional description information of the target chip, and using the top-level configuration module to set the simulation environment of the verification platform; triggering the scenario stimulator in the verification platform to start, so as to generate stimulus data, and inputting the stimulus data into the design module to be tested, so as to use the stimulus data to drive the design module to be tested, simulate the target chip, and obtain simulation output data.

[0063] As shown in Figure 3 above, after the simulation running environment of the verification platform is running, the top-level configuration (top_cfg) module is started, and all registers and environment settings are configured (configuration includes: environment configuration, process configuration, data flow configuration, register function configuration, comparison mechanism configuration), and the corresponding various configuration parameters are sent to the image processing model (alg_model), algorithm agent (alg_agent) and register model (reg_model). After the algorithm agent (alg_agent) receives the configuration data, the logic monitor (dut_monitor) and scene stimuli (video_seq) are started, and the generated video_data (stimulus data) is driven to the design module under test (DUT).

[0064] It should be noted that the registers here refer to the registers in the chip and have nothing to do with UVM. Although the registers here and the register model in UVM use the same configuration, they process the data that they need to process respectively. The chip registers and UVM register models are used to jointly process data here to avoid using the same configuration data in the simulation processing and image processing algorithm. When there is a problem with the configuration data, it is easy for the simulation processing and image processing algorithm to use wrong data, which will make the verification result of the target chip invalid.

[0065] Step S206 , obtaining excitation data and simulation output data, and sending the excitation data and simulation output data to the image processing model, so as to analyze and process the output data using the image processing model to obtain simulation results for the target chip.

[0066] As shown in Figure 3 above, while the design under test (DUT) continuously receives video_data (stimulus data), the logic monitor (dut_monitor) will continue to run, constantly sampling the DUT input and output data and transmitting the data to the image processing model (alg_model). In the image processing model (alg_model), the data and input information will be processed and the comparison results will be output.

[0067] Step S208 , performing format conversion on the simulation output data and the excitation data in the image processing model to obtain a simulation data code stream and an excitation data code stream that can be recognized by the image processing algorithm in the image processing model.

[0068] When processing data, compatibility issues need to be considered. In order to ensure that subsequent steps can proceed smoothly, the obtained simulation output data and stimulus data need to be converted into a simulation data stream and stimulus data stream that can be recognized by the image processing algorithm in the image processing model (alg_model).

[0069] According to the above-mentioned embodiment of the present application, in the above-mentioned step S208, the format of the simulation output data and the excitation data in the image processing model is converted to obtain a simulation data code stream that can be recognized by the image processing algorithm in the image processing model, including: in the process of inputting the excitation data into the design module to be tested and using the excitation data to simulate the target chip in the design module to be tested, triggering the logic monitor of the verification platform to start to collect the excitation data and the simulation output data, and inputting the excitation data and the simulation output data into the image processing model; after determining that the image processing model has received the simulation output data, using the data processing module in the image processing model to convert the format of the simulation output data to obtain a simulation data code stream.

[0070] The above embodiment of the present application is described in detail below with reference to FIG5 , which is a schematic diagram of the chip simulation verification process according to the embodiment of the present application. As shown in FIG5 , after receiving the stimulus data and simulation output data, the image processing model (alg_model) transmits them to the data_pro module for integration and analysis (format conversion), and then sends them to the Comparator module (comparison module) to obtain the simulation data code stream and the stimulus data code stream.

[0071] The data_pro module here is mainly responsible for pixel extraction and packaging of the stimulus data and simulation output data output by the DUT, and saving them into the queue in byte order so that the image processing model can compare the two after processing the input data to obtain the processing results to verify whether the target chip is qualified.

[0072] Step S210: Process the excitation data code stream using an image processing algorithm to obtain an image algorithm output data code stream.

[0073] Optionally, the data code stream output by the above-mentioned image algorithm is a data code stream in a specific format required for subsequent verification of the target chip.

[0074] After obtaining the data stream in a specific format (simulation data stream and image algorithm output data stream, i.e. data_in), it is transmitted to the PYTHON algorithm model. The PYTHON algorithm model does not consume simulation time during operation, and can instantly output the ideal data after image analysis and processing, and output the data in a specific format to the comparison module of the image processing algorithm model.

[0075] It should be noted that, in the embodiments of the present application, the image processing algorithm includes but is not limited to the PYTHON algorithm, and may also be other types of algorithms.

[0076] According to the above-mentioned embodiment of the present application, before the above-mentioned step S210, that is, before using the image processing algorithm to process the excitation data code stream to obtain the image algorithm output data code stream, the chip hybrid simulation method based on the general verification methodology and the image processing algorithm also includes: obtaining the configuration information of the register model in the verification platform and the setting information of the simulation environment in the verification platform; sending the configuration information and the setting information to the configuration module of the image processing model, so as to use the configuration module to pre-process the configuration information and the setting information, so that the configuration module is paired and integrated with the top-level configuration module of the verification platform.

[0077] As shown in Figure 5 above, when the data_pro module performs format conversion on the stimulus data and simulation output data (data_out), the image processing model (alg_model) also passes the configuration information of the top-level configuration (top_cfg) and the register model (reg_model) into the cfg module for preprocessing. The cfg module mainly includes: register name, register domain value, register address, register configuration bus type, rate, and number of lanes, etc. By pairing and integrating this basic information with the top-level configuration (top_cfg) module, the required processing status configuration data can be finally obtained.

[0078] According to the above embodiment of the present application, in the above step S210, the excitation data code stream is processed using an image processing algorithm to obtain an image algorithm output data code stream, including: using the image processing algorithm and the configuration information of the register model in the verification platform to perform predetermined dimension analysis and processing on the excitation data code stream to obtain the image algorithm output data code stream, wherein the predetermined dimension includes at least one of the following: pixel depth, color temperature, contrast, color vividness, and transition smoothness.

[0079] As shown in Figure 5 above, the image processing algorithm model (alg_model) can directly call a program written in the Python programming language to perform data processing and analysis on the input image in a specific format. This processing and analysis process mainly focuses on the pixel depth, color temperature, contrast, color vividness, transition smoothness, and other processing calculations of the video image to ensure that the video data meets the chip requirements.

[0080] In addition, during the simulation process, the image processing algorithm model (alg_model) will synchronously collect the input and output data of the DUT operation (i.e., stimulus data and simulation output data), and synchronously introduce the input data (stimulus data) and register configuration data (register name, register domain value, register address, register configuration bus type, rate and number of lanes, etc.) into the PYTHON algorithm model.

[0081] Step S212 , comparing the simulation data code stream in the image processing model with the image algorithm output data code stream to obtain a verification result of the target chip based on the comparison result, wherein the verification result is used to indicate whether the actual function of the target chip is consistent with the function description information.

[0082] After the Python algorithm model outputs the data in a specific format to the comparison module of the image processing algorithm model, the simulation data code stream and the image algorithm output data code stream will be compared in the comparison module. Then, based on the comparison result, the verification result of the target chip is obtained to verify whether the actual function of the target chip is consistent with its function description information.

[0083] According to the above embodiment of the present application, in the above step S212, the simulation data code stream in the image processing model and the image algorithm output data code stream are compared to obtain the verification result of the target chip based on the comparison result, including: comparing the simulation data code stream and the image algorithm output data code stream in the image processing model to obtain a comparison result; when the comparison result indicates that the simulation data code stream and the image algorithm output data are consistent or the number of inconsistencies between the simulation data code stream and the image algorithm output data is less than a predetermined threshold, determining that the actual function of the target chip is consistent with the function description information; when the comparison result indicates that the number of inconsistencies between the simulation data code stream and the image algorithm output data is not less than a predetermined threshold, determining that the actual function of the target chip is inconsistent with the function description information.

[0084] Optionally, the predetermined threshold is used to determine whether the actual function of the target chip is consistent with the function description information. The specific value can be obtained from a large number of experiments, and no specific requirements are made for the value here.

[0085] As shown in Figure 5 above, after the Python algorithm model processes and analyzes the stimulus data stream and the simulation data stream, it transmits the analysis results to the Comparator module. The Comparator module analyzes and compares the final data to obtain the simulation verification results of the entire image processing chip.

[0086] For example, if the number of inconsistencies between the simulation data code stream and the image algorithm output data code stream exceeds 5 (the predetermined threshold is 5 as an example), it can be considered that the actual function of the target chip is inconsistent with its function description information, that is, the chip is an unqualified chip; if the number of inconsistencies between the simulation data code stream and the image algorithm output data code stream is less than 5 (the predetermined threshold is 5 as an example), it can be considered that the actual function of the target chip is consistent with its function description information, that is, the chip is a qualified chip.

[0087] According to the above-mentioned embodiment of the present application, after the above-mentioned step S212, that is, after comparing the simulation data code stream in the image processing model and the image algorithm output data code stream to obtain the verification result of the target chip based on the comparison result, the chip hybrid simulation method based on the general verification methodology and the image processing algorithm also includes: storing the verification result in a log.

[0088] The comparison module of the image processing algorithm model compares the data output by the DUT and the Python algorithm model, and prints and records the comparison results in the log directory. These output data use a unified data byte packaging format, mainly including video format data type, data depth, and pixel byte data.

[0089] It can be seen from the above that, through the above steps, after receiving the chip simulation task, a startup instruction can be generated based on the chip simulation task to trigger the startup of the general verification methodology verification platform, wherein the verification platform is integrated with an image processing model; after the simulation operating environment of the verification platform is running, the stimulus data is input into the design module to be tested, so that the target chip corresponding to the chip simulation task in the design module to be tested is simulated using the stimulus data to obtain simulation output data; the stimulus data and simulation output data are obtained, and the stimulus data and simulation output data are sent to the image processing model, so that the output data is analyzed and processed using the image processing model to obtain the simulation result of the target chip; the simulation output data and the stimulus data in the image processing model are format converted to obtain the simulation data code stream and the stimulus data code stream that can be recognized by the image processing algorithm in the image processing model; the stimulus data code stream is processed using the image processing algorithm to obtain the image algorithm Output data code stream; compare the simulation data code stream in the image processing model and the image algorithm output data code stream to obtain a verification result of the target chip according to the comparison result, wherein the verification result is used to indicate whether the actual function of the target chip is consistent with the function description information. By integrating the image algorithm model with the UVM simulation verification platform, while using the chip simulation verification platform to simulate the target chip, the input data and simulation output data used for the simulation can be input into the image processing model so that the image processing model can be used to process the input data at the algorithm level, thereby comprehensively verifying whether the actual function of the target chip is consistent with its function description information according to the simulation output result and the image algorithm model processing result. The image algorithm model and the UVM simulation verification platform are interconnected to avoid data errors and algorithm processing process errors, thereby improving the simulation efficiency and accuracy of the UVM platform.

[0090] Therefore, according to the technical solution provided in the above embodiments of the present application, the technical problem that the method used for simulating and verifying the chip in the related art isolates the interconnectivity and connectivity of the image algorithm model and the UVM simulation verification platform, which easily causes data errors and algorithm processing errors, thereby reducing the simulation efficiency and accuracy of the UVM platform is solved.

[0091] It should be noted that for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

[0092] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0093] According to an embodiment of the present application, a chip hybrid simulation device based on a universal verification methodology and an image processing algorithm is also provided for implementing the above-mentioned chip hybrid simulation method based on a universal verification methodology and an image processing algorithm. FIG6 is a schematic diagram of the chip hybrid simulation device based on a universal verification methodology and an image processing algorithm according to an embodiment of the present application. As shown in FIG6 , the device includes: a trigger unit 601, a first acquisition unit 603, a second acquisition unit 606, a third acquisition unit 607, a fourth acquisition unit 609, and a fifth acquisition unit 611. The chip hybrid simulation device based on a universal verification methodology and an image processing algorithm is described in detail below.

[0094] The trigger unit 601 is used to generate a startup instruction based on the chip simulation task after receiving the chip simulation task, so as to trigger the startup of the universal verification methodology verification platform, wherein the verification platform is integrated with an image processing model.

[0095] The first acquisition unit 603 is used to input the stimulus data into the design module to be tested after the simulation running environment of the verification platform is running, so as to use the stimulus data to simulate the target chip corresponding to the chip simulation task in the design module to obtain simulation output data.

[0096] The second acquisition unit 605 is used to acquire excitation data and simulation output data, and send the excitation data and simulation output data to the image processing model so as to analyze and process the output data using the image processing model to obtain simulation results for the target chip.

[0097] The third acquisition unit 607 is used to convert the formats of the simulation output data and the stimulation data in the image processing model to obtain simulation data code streams and stimulation data code streams that can be recognized by the image processing algorithm in the image processing model.

[0098] The fourth acquisition unit 609 is configured to process the excitation data code stream using an image processing algorithm to obtain an image algorithm output data code stream.

[0099] The fifth acquisition unit 611 is used to compare the simulation data code stream in the image processing model and the image algorithm output data code stream to obtain a verification result of the target chip based on the comparison result, wherein the verification result is used to indicate whether the actual function of the target chip is consistent with the function description information.

[0100] It should be noted here that the above-mentioned trigger unit 601, first acquisition unit 603, second acquisition unit 606, third acquisition unit 607, fourth acquisition unit 609, and fifth acquisition unit 611 correspond to steps S202 to S212 in the above-mentioned embodiments. The six units have the same instances and application scenarios implemented by the corresponding steps, but are not limited to the contents disclosed in the above-mentioned embodiments.

[0101] From the above, it can be seen that in the scheme recorded in the above embodiments of the present application, a trigger unit can be used to generate a startup instruction based on the chip simulation task after receiving the chip simulation task, so as to trigger the startup of the general verification methodology verification platform, wherein the verification platform is integrated with an image processing model; then, after the simulation running environment of the verification platform is started, the first acquisition unit is used to input the stimulus data into the design module to be tested, so as to use the stimulus data to simulate the target chip corresponding to the chip simulation task in the design module to be tested, and obtain simulation output data; then, the second acquisition unit is used to obtain the stimulus data and the simulation output data, and the stimulus data and the simulation output data are sent to the image processing model, so as to use the image processing model to analyze and process the output data to obtain the simulation result of the target chip; then, the third acquisition unit is used to convert the format of the simulation output data and the stimulus data in the image processing model, so as to obtain the simulation data code stream and the stimulus data code stream that can be recognized by the image processing algorithm in the image processing model; and then the fourth acquisition unit is used to use the image processing The image algorithm is used to process the excitation data code stream to obtain the image algorithm output data code stream; finally, the fifth acquisition unit is used to compare the simulation data code stream in the image processing model with the image algorithm output data code stream to obtain the verification result of the target chip according to the comparison result, wherein the verification result is used to indicate whether the actual function of the target chip is consistent with the functional description information. By integrating the image algorithm model with the UVM simulation verification platform, while using the chip simulation verification platform to simulate the target chip, the input data and simulation output data used for the simulation can be input into the image processing model so that the image processing model can be used to process the input data at the algorithm level, so that the actual function of the target chip can be comprehensively verified to be consistent with its functional description information according to the simulation output result and the image algorithm model processing result. The image algorithm model and the UVM simulation verification platform are interconnected to avoid data errors and algorithm processing process errors, thereby improving the simulation efficiency and accuracy of the UVM platform.

[0102] Therefore, according to the technical solution provided in the above embodiments of the present application, the technical problem that the method used for simulating and verifying the chip in the related art isolates the interconnectivity and connectivity of the image algorithm model and the UVM simulation verification platform, which easily causes data errors and algorithm processing errors, thereby reducing the simulation efficiency and accuracy of the UVM platform is solved.

[0103] Optionally, the chip hybrid simulation device based on general verification methodology and image processing algorithm also includes: a sixth acquisition unit, used to call the logic code design of the design module to be tested to obtain the design module to be tested before generating a startup instruction based on the chip simulation task to trigger the startup of the general verification methodology verification platform, wherein the logic code is a code pre-written according to the chip simulation requirements; a determination unit, used to determine the multiple components required to generate the verification platform according to the functional description information of the target chip, wherein the multiple components are the components required for simulating the target chip; a seventh acquisition unit, used to package the multiple components using the methodology architecture corresponding to the verification platform, and connect the multiple packaged components to obtain a verification platform including the design module to be tested and the multiple packaged and connected components.

[0104] Optionally, the first acquisition unit includes: a first trigger module, used to trigger the startup of the top-level configuration module in the verification platform, so as to use the top-level configuration module to configure the registers of the design module to be tested according to the functional description information of the target chip, and use the top-level configuration module to set the simulation environment of the verification platform; a second trigger module, used to trigger the startup of the scenario stimulator in the verification platform to generate stimulus data, and input the stimulus data into the design module to be tested, so as to use the stimulus data to drive the design module to be tested, simulate the target chip, and obtain simulation output data.

[0105] Optionally, the third acquisition unit includes: a third trigger module, which is used to trigger the start-up of the logic monitor of the verification platform when inputting the stimulus data into the design module to be tested so as to simulate the target chip in the design module to be tested using the stimulus data, so as to collect the stimulus data and simulation output data, and input the stimulus data and simulation output data into the image processing model; a first acquisition module, which is used to convert the format of the simulation output data using the data processing module in the image processing model after determining that the image processing model has received the simulation output data, so as to obtain a simulation data code stream.

[0106] Optionally, the chip hybrid simulation device based on general verification methodology and image processing algorithm also includes: an eighth acquisition unit, used to obtain the configuration information of the register model in the verification platform and the setting information of the simulation environment in the verification platform before using the image processing algorithm to process the excitation data code stream to obtain the image algorithm output data code stream; a processing unit, used to send the configuration information and setting information to the configuration module of the image processing model, so as to use the configuration module to pre-process the configuration information and setting information, so that the configuration module is paired and integrated with the top-level configuration module of the verification platform.

[0107] Optionally, the fourth acquisition unit includes: a second acquisition module, which is used to use the image processing algorithm and the configuration information of the register model in the verification platform to analyze and process the excitation data code stream in predetermined dimensions to obtain the image algorithm output data code stream, wherein the predetermined dimension includes at least one of the following: pixel depth, color temperature, contrast, color vividness, and transition smoothness.

[0108] Optionally, the fifth acquisition unit includes: a third acquisition module, used to compare the simulation data code stream and the image algorithm output data code stream in the image processing model to obtain a comparison result; a first determination module, used to determine that the actual function of the target chip is consistent with the function description information when the comparison result indicates that the simulation data code stream is consistent with the image algorithm output data or the number of inconsistencies between the simulation data code stream and the image algorithm output data is less than a predetermined threshold; a second determination module, used to determine that the actual function of the target chip is inconsistent with the function description information when the comparison result indicates that the number of inconsistencies between the simulation data code stream and the image algorithm output data is not less than a predetermined threshold.

[0109] Optionally, the chip hybrid simulation device based on general verification methodology and image processing algorithm also includes: the storage unit compares the simulation data code stream in the image processing model and the image algorithm output data code stream to obtain the verification result of the target chip based on the comparison result, and then stores the verification result in the log.

[0110] According to another aspect of an embodiment of the present application, a chip hybrid simulation system based on a general verification methodology and an image processing algorithm is also provided. The chip hybrid simulation system based on a general verification methodology and an image processing algorithm uses any of the above-mentioned chip hybrid simulation methods based on a general verification methodology and an image processing algorithm.

[0111] According to another aspect of an embodiment of the present application, a computer-readable storage medium is further provided, the computer-readable storage medium including a stored program, wherein the program executes any one of the above-mentioned chip hybrid simulation methods based on general verification methodology and image processing algorithm.

[0112] Optionally, in this embodiment, the computer-readable storage medium may be located in any one of the computer terminals in a computer terminal group in a computer network, or in any one of the communication devices in a communication device group.

[0113] Optionally, in this embodiment, the computer-readable storage medium is configured to store program codes for executing the following steps: after receiving a chip simulation task, generating a startup instruction based on the chip simulation task to trigger the startup of a universal verification methodology verification platform, wherein the verification platform is integrated with an image processing model; after the simulation operating environment of the verification platform is running, inputting stimulus data into the design module to be tested, so as to use the stimulus data to simulate the target chip corresponding to the chip simulation task in the design module to be tested, and obtain simulation output data; obtaining stimulus data and simulation output data, and sending the stimulus data and simulation output data to the image processing module; The method comprises the following steps: a first step is to analyze and process the output data using the image processing model to obtain a simulation result of the target chip; a second step is to convert the format of the simulation output data and the stimulation data in the image processing model to obtain a simulation data code stream and a stimulation data code stream that can be recognized by the image processing algorithm in the image processing model; a third step is to process the stimulation data code stream using the image processing algorithm to obtain an image algorithm output data code stream; a fourth step is to compare the simulation data code stream in the image processing model with the image algorithm output data code stream to obtain a verification result of the target chip according to the comparison result, wherein the verification result is used to indicate whether the actual function of the target chip is consistent with the function description information.

[0114] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for performing the following steps: calling the logic code design of the design module to be tested to obtain the design module to be tested, wherein the logic code is a code pre-written according to the chip simulation requirements; determining a plurality of components required to generate a verification platform according to the functional description information of the target chip, wherein the plurality of components are components required for simulating the target chip; packaging the plurality of components using the methodological architecture corresponding to the verification platform, and connecting the plurality of packaged components to obtain a verification platform including the design module to be tested and the plurality of packaged and connected components.

[0115] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for performing the following steps: triggering the top-level configuration module in the verification platform to start, so as to use the top-level configuration module to configure the registers of the design module to be tested according to the functional description information of the target chip, and using the top-level configuration module to set the simulation environment of the verification platform; triggering the scenario stimulator in the verification platform to start, so as to generate stimulus data, and input the stimulus data into the design module to be tested, so as to use the stimulus data to drive the design module to be tested, simulate the target chip, and obtain simulation output data.

[0116] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for performing the following steps: in the process of inputting stimulus data into the design module to be tested so as to simulate the target chip in the design module to be tested using the stimulus data, triggering the logic monitor of the verification platform to start up to collect stimulus data and simulation output data, and inputting the stimulus data and simulation output data into the image processing model; after determining that the image processing model has received the simulation output data, using the data processing module in the image processing model to convert the format of the simulation output data to obtain a simulation data code stream.

[0117] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for performing the following steps: obtaining configuration information of the register model in the verification platform and setting information of the simulation environment in the verification platform; sending the configuration information and setting information to the configuration module of the image processing model, so as to use the configuration module to pre-process the configuration information and setting information, so that the configuration module is paired and integrated with the top-level configuration module of the verification platform.

[0118] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for executing the following steps: using the image processing algorithm and the configuration information of the register model in the verification platform to analyze and process the excitation data code stream in predetermined dimensions to obtain an image algorithm output data code stream, wherein the predetermined dimensions include at least one of the following: pixel depth, color temperature, contrast, color vividness, and transition smoothness.

[0119] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for performing the following steps: comparing the simulation data code stream and the image algorithm output data code stream in the image processing model to obtain a comparison result; when the comparison result indicates that the simulation data code stream and the image algorithm output data are consistent or the number of inconsistencies between the simulation data code stream and the image algorithm output data is less than a predetermined threshold, determining that the actual function of the target chip is consistent with the function description information; when the comparison result indicates that the number of inconsistencies between the simulation data code stream and the image algorithm output data is not less than a predetermined threshold, determining that the actual function of the target chip is inconsistent with the function description information.

[0120] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for executing the following steps: storing the verification result in a log.

[0121] According to another aspect of an embodiment of the present application, a processor is further provided, which is used to run a program, wherein when the program is running, any one of the above-mentioned chip hybrid simulation methods based on the general verification methodology and image processing algorithm is executed.

[0122] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0123] In the above embodiments of the present application, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0124] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only exemplary. For example, the division of the units can be a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0125] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0126] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0127] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0128] The above is only a preferred embodiment of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A chip hybrid simulation method based on the Universal Verification Methodology (UVM) and image processing algorithms, comprising: After receiving a chip simulation task, generating a start instruction based on the chip simulation task to trigger the startup of a Universal Verification Methodology (UVM) verification platform, wherein the verification platform is integrated with an image processing model; After the simulation running environment of the verification platform is up and running, inputting stimulus data into the design under test (DUT) module to perform simulation processing on the target chip corresponding to the chip simulation task in the DUT module, obtaining simulation output data; Obtaining the stimulus data and the simulation output data, and sending the stimulus data and the simulation output data to the image processing model to perform analysis and processing on the output data using the image processing model, obtaining a simulation result for the target chip; Performing format conversion on the simulation output data and the stimulus data in the image processing model to obtain a simulation data bitstream and a stimulus data bitstream recognizable by the image processing algorithm in the image processing model; Processing the stimulus data bitstream using the image processing algorithm to obtain an image algorithm output data bitstream; Comparing the simulation data bitstream and the image algorithm output data bitstream in the image processing model to obtain a verification result for the target chip according to the comparison result, wherein the verification result is used to indicate whether the actual function of the target chip is consistent with the function description information.

2. The chip hybrid simulation method based on the general verification methodology and the image processing algorithm according to claim 1, wherein, Before generating a start instruction based on the chip simulation task to trigger the startup of a Universal Verification Methodology (UVM) verification platform, further comprising: Invoking the logic code design of the DUT module to obtain the DUT module, wherein the logic code is pre-written code according to chip simulation requirements; Determining a plurality of components required to generate the verification platform according to the function description information of the target chip, wherein the plurality of components are components required for simulating the target chip; Encapsulating the plurality of components using the methodology framework corresponding to the verification platform, and connecting the encapsulated plurality of components to obtain the verification platform including the DUT module and the encapsulated and connected plurality of components.

3. The chip hybrid simulation method based on the general verification methodology and the image processing algorithm according to claim 1, wherein, After the simulation running environment of the verification platform is up and running, inputting stimulus data into the DUT module to perform simulation processing on the target chip corresponding to the chip simulation task in the DUT module, obtaining simulation output data, including: Triggering the startup of the top-level configuration module in the verification platform to configure the registers of the DUT module using the top-level configuration module according to the function description information of the target chip, and setting the simulation environment of the verification platform using the top-level configuration module; Triggering the startup of the scenario stimulator in the verification platform to generate the stimulus data, and inputting the stimulus data into the DUT module to drive the DUT module using the stimulus data to perform simulation processing on the target chip, obtaining the simulation output data.

4. The chip hybrid simulation method based on the general verification methodology and the image processing algorithm according to claim 1, wherein, Format conversion is performed on the simulation output data and the excitation data in the image processing model to obtain a simulation data bitstream recognizable by the image processing algorithm in the image processing model, including: During the process of inputting the excitation data into the device under test module to simulate the target chip in the device under test module using the excitation data, the logic monitor of the verification platform is triggered to start, so as to collect the excitation data and the simulation output data, and input the excitation data and the simulation output data into the image processing model; After determining that the image processing model has received the simulation output data, the data processing module in the image processing model is used to perform format conversion on the simulation output data to obtain the simulation data bitstream.

5. The chip hybrid simulation method based on the general verification methodology and the image processing algorithm according to claim 1, wherein, Before using the image processing algorithm to process the excitation data bitstream to obtain an image algorithm output data bitstream, it further includes: Obtaining the configuration information of the register model in the verification platform and the setting information of the simulation environment in the verification platform; Sending the configuration information and the setting information to the configuration module of the image processing model, so as to use the configuration module to perform preprocessing on the configuration information and the setting information, so that the configuration module is paired and integrated with the top-level configuration module of the verification platform.

6. The chip hybrid simulation method based on the general verification methodology and the image processing algorithm according to claim 1, wherein, Using the image processing algorithm to process the excitation data bitstream to obtain an image algorithm output data bitstream, including: Performing analysis processing on the excitation data bitstream in a predetermined dimension using the image processing algorithm and the configuration information of the register model in the verification platform to obtain the image algorithm output data bitstream, where the predetermined dimension includes at least one of the following: pixel depth, color temperature, contrast, color vividness, and transition smoothness.

7. The chip hybrid simulation method based on the general verification methodology and the image processing algorithm according to any one of claims 1 to 6, wherein, Comparing the simulation data bitstream and the image algorithm output data bitstream in the image processing model to obtain the verification result of the target chip according to the comparison result, including: Comparing the simulation data bitstream and the image algorithm output data bitstream in the image processing model to obtain a comparison result; When the comparison result indicates that the simulation data bitstream is consistent with the image algorithm output data or the number of inconsistencies between the simulation data bitstream and the image algorithm output data is less than a predetermined threshold, it is determined that the actual function of the target chip is consistent with the function description information; When the comparison result indicates that the number of inconsistencies between the simulation data bitstream and the image algorithm output data is not less than a predetermined threshold, it is determined that the actual function of the target chip is inconsistent with the function description information.

8. The chip hybrid simulation method based on the general verification methodology and the image processing algorithm according to claim 7, wherein, After comparing the simulation data bitstream and the image algorithm output data bitstream in the image processing model to obtain the verification result of the target chip according to the comparison result, it further includes: Storing the verification result in a log.

9. A chip hybrid simulation device based on a general verification methodology and an image processing algorithm, including: A trigger unit, configured to generate a start instruction based on the chip simulation task after receiving the chip simulation task, so as to trigger the start of a general verification methodology verification platform, wherein the verification platform is integrated with an image processing model; A first acquisition unit, configured to input excitation data into a device under test module after the simulation running environment of the verification platform runs, so as to perform simulation processing on a target chip corresponding to the chip simulation task in the device under test module by using the excitation data, and obtain simulation output data; A second acquisition unit, configured to acquire the excitation data and the simulation output data, and send the excitation data and the simulation output data to the image processing model, so as to perform analysis and processing on the output data by using the image processing model, and obtain a simulation result of the target chip; A third acquisition unit, configured to perform format conversion on the simulation output data and the excitation data in the image processing model, so as to obtain a simulation data code stream and an excitation data code stream recognizable by an image processing algorithm in the image processing model; A fourth acquisition unit, configured to process the excitation data code stream by using the image processing algorithm, so as to obtain an image algorithm output data code stream; A fifth acquisition unit, configured to compare the simulation data code stream and the image algorithm output data code stream in the image processing model, so as to obtain a verification result of the target chip according to the comparison result, wherein the verification result is used to indicate whether the actual function of the target chip is consistent with the function description information.

10. A processor for running a program, wherein, When the program runs, it executes the chip hybrid simulation method based on the general verification methodology and the image processing algorithm according to any one of claims 1 to 8.

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