Semiconductor integrated circuit and receiving device

Abstract

To generate a suitable digital signal on the basis of an analog signal.SOLUTION: A semiconductor integrated circuit of an embodiment includes a comparator which performs comparison processing of differential analog signals, and a control circuit configured to determine values of a plurality of bits on the basis of the comparison processing results of the comparator, and generate a digital signal including the determined values of the plurality of bits. The control circuit sets an initial value to a first bit to be determined among the plurality of bits, and if the determination of the first bit is not completed in a first period, sets a first tentative value having a first value to the first bit.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor integrated circuit and a receiving device.

Background Art

[0002] A transmitting device is connected to a receiving circuit via a transmission line. The transmitting device transmits an analog signal with data superimposed thereon to the transmission line. The receiving device receives the analog signal that has passed through the transmission line. The receiving device includes a semiconductor integrated circuit that processes the analog signal. The receiving device generates a digital signal based on the analog signal. The receiving device reproduces data based on the generated digital signal.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The semiconductor integrated circuit and the receiving device according to the present embodiment can generate a more suitable digital signal based on the analog signal.

Means for Solving the Problems

[0005] The semiconductor integrated circuit according to the embodiment includes a comparator that executes a comparison process of differential analog signals, and a control circuit configured to determine values of a plurality of bits based on a result of the comparison process of the comparator and generate a digital signal including the determined values of the plurality of bits. The control circuit sets an initial value for a first bit to be determined among the plurality of bits, and sets a first temporary value having a first value for the first bit when the determination of the first bit is not completed within a first period.

Brief Description of the Drawings

[0006]

Figure 1

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Embodiments for Carrying Out the Invention

[0007] With reference to FIGS. 1 to 20, the semiconductor integrated circuit and the receiving apparatus according to the embodiment will be described. In the following description, elements having the same function and configuration are denoted by the same reference numerals. Also, in each of the following embodiments, when components (for example, circuits, wirings, various voltages and signals, etc.) with reference numerals accompanied by numbers / letters for differentiation at the end do not need to be distinguished from each other, descriptions (reference numerals) with the numbers / letters at the end omitted are used.

[0008] <Embodiment> (1) First Embodiment With reference to FIGS. 1 to 17, the semiconductor integrated circuit and the receiving apparatus according to the first embodiment will be described.

[0009] (a) Configuration Example (a-1) Communication System With reference to FIG. 1, the configuration of the communication system 1 including the semiconductor integrated circuit 22 according to the embodiment will be described. FIG. 1 is a block diagram showing an example of the configuration of the communication system 1 including the semiconductor integrated circuit 22 according to the embodiment.

[0010] The communication system 1 is configured to transmit data from one device to another device by high-speed serial communication. The communication system 1 includes a transmitting device 2, a transmission line 3, and a receiving device 4. The communication system 1 may be composed of a plurality of devices or a plurality of circuits provided on one printed wiring board, or may be composed of a plurality of devices or a plurality of circuits provided on different printed wiring boards.

[0011] The transmitting device 2 is configured to transmit a signal TR and a signal / TR to the receiving device 4 via the transmission line 3. The signals TR and / TR are differential signals. The signals TR and / TR are signals including a plurality of pulses, for example. Data including a bit string is superimposed on each pulse of the signals TR and / TR. The voltage level of each pulse of the signals TR and / TR corresponds to the value of the bit of the data. The data superimposed on the pulse signal is transmitted from the transmitting device 2 to the receiving device 4 via the transmission line 3.

[0012] The transmission line 3 is a physical or spatial transmission medium for transmitting the signals TR and / TR to the receiving device 4. The transmission line 3 is, for example, a wiring connecting the transmitting device 2 and the receiving device 4. Note that the transmission line 3 may be a space capable of wireless communication. The transmission line 3 can have various transmission characteristics depending on the physical structure and material of the transmission medium. The transmission characteristics of the transmission line 3 have, for example, frequency characteristics with gain loss in a specific frequency band.

[0013] The signals TR and / TR transmitted by the transmitting device 2 suffer losses according to the transmission characteristics of the transmission line 3 when the signals TR, / TR pass through the transmission line 3. As a result, inter-symbol interference (ISI) occurs in the signals TR and / TR that have passed through the transmission line 3. For this reason, the signals TR and / TR that have passed through the transmission line 3 are processed as analog signals. Hereinafter, the signals TR and / TR that have passed through the transmission line 3 are referred to as signals RV and / RV. The signals RV and / RV are analog signals.

[0014] The receiving device 4 is configured to receive the signal RV and the signal / RV from the transmission line 3. The receiving device 4 decodes the data superimposed on the signal TR and the signal / TR by the transmitting device 2 based on the signal RV and the signal / RV. The receiving device 4 has a receiving circuit for decoding the data superimposed on the signal TR and the signal / TR. The receiving circuit is a set of a plurality of semiconductor integrated circuits including the semiconductor integrated circuit 22 of the embodiment.

[0015] (a-2) Receiving circuit With reference to FIG. 2, a configuration example of the receiving device 4 of the present embodiment will be described. FIG. 2 is a block diagram showing an example of the configuration of the receiving device 4 of the embodiment.

[0016] The receiving device 4 includes, as a receiving circuit, for example, two pads P1, P2, an analog front-end circuit 10, a time-interleaved analog-to-digital converter circuit 20, a voltage generation circuit 30, a digital signal processing circuit 40, and a clock data recovery circuit 50.

[0017] Each of the pads P1 and P2 is a terminal connected to the transmission line 3. In the example of FIG. 2, a case where each of the pad P1 and the pad P2 receives the signal RV and the signal / RV from the transmitting device 2 via the transmission line 3 is shown.

[0018] The analog front-end (AFE) circuit 10 includes, for example, a continuous-time linear equalizer (CTLE) and a variable gain amplifier (VGA). The CTLE is an amplifier circuit having a frequency characteristic that compensates for the frequency characteristic of the transmission line 3. The VGA is an amplifier circuit capable of changing the gain. The AFE circuit 10 receives the signal RV and the signal / RV from each of the pads P1 and P2. The AFE circuit 10 performs analog processing on the signal RV and the signal / RV using the CTLE and the VGA. The AFE circuit 10 generates a signal Sin and a signal / Sin based on the signal RV and the signal / RV. The signal Sin and the signal / Sin are analog signals similar to the signal RV and the signal / RV. The AFE circuit 10 supplies the signal Sin and / Sin to the time-interleaved analog-to-digital converter circuit 20.

[0019] The time-interleaved analog-to-digital converter (TI-ADC) circuit 20 performs a process of converting an analog signal into a digital signal by a time-interleaving method. The TI-ADC circuit 20 receives the signals Sin and / Sin from the AFE circuit 10. The TI-ADC circuit 20 receives the reference voltages VRp and VRn from the voltage generating circuit 30. The TI-ADC circuit 20 receives the signals CK1 and CK2 from the clock data recovery circuit 50. The TI-ADC circuit 20 converts the signals Sin and / Sin into a signal X0 based on the reference voltages VRp and VRn and the signals CK1 and CK2. The signal X0 is a digital signal. The TI-ADC circuit 20 sends the signal X0 to the digital signal processing circuit 40. The configuration of the TI-ADC circuit 20 will be described later.

[0020] The reference voltages VRp and VRn are voltages used in the process of converting an analog signal into a digital signal in the TI-ADC circuit 20. The TI-ADC circuit 20 generates a signal X0 based on the magnitude relationship between the potential difference between the signals Sin and / Sin and the potential difference (VRp-VRn) between the reference voltages VRp and VRn. Hereinafter, the potential difference (VRp-VRn) between the reference voltages VRp and VRn is also referred to as a reference voltage VREF.

[0021] The signal CK1 is a set of periodic signals including edges having periodicity. For example, the signal CK1 has n r1 Contains n clock signals. r1 is an integer equal to or greater than 1 (for example, 8). r1 The clock signals are, for example, at least 360° / n r1 In the following, the phase of n in the signal CK1 is different. r1 The clock signals are signals CK1_0, ..., and signals CK1_(n r1 The frequency of the signal CK1 is lower than the frequency of the clock signal embedded in the signal TR and / or the signal TR by the transmitting device 2.

[0022] The signal CK2 is a set of periodic signals including edges with periodicity. For example, the signal CK2 includes n r2 clock signals. n r2 is an integer greater than n r1 (e.g., 32). The n r2 clock signals of the signal CK2 are, for example, at least 360° / n r2 each with a different phase. Hereinafter, the n r2 clock signals in the signal CK2 may be distinguished and shown as the signal CK2_0, …, and the signal CK2_(n r2 -1). The frequency of the signal CK2 may be equal to the frequency of the clock signals embedded in the signals TR and / TR by the transmitting device 2. The frequency of the signal CK2 may be different from the frequency of the clock signals embedded in the signals TR and / TR by the transmitting device 2.

[0023] The signal X0 output from the TI-ADC circuit 20 includes a plurality of digital values. Each digital value includes a plurality of bits. One digital value included in the signal X0 is sampled from one symbol of the signals Sin and / Sin based on one signal CK2_j (0 ≦ j ≦ n r2 -1) of the signal CK2. One digital value is, for example, m-bit data. m is a natural number of 1 or more. For example, one digital value is 8-bit data. The value of each bit of the n r2 digital values included in the signal X0 is sampled from n r2 consecutive symbols of the signals Sin and / Sin based on the n r2 signals CK2_0, …, CK2_(n r2 -1) of the signal CK2.

[0024] The consecutive n r2 digital values included in the signal X0 may be distinguished and shown as the digital value X0_0, …, and the digital value X0_(n r2 -1). The m-bit data included in the digital value X0_j is the bit string X0_j <m-1:0>may be shown as follows. j is 0 or more and n r2 -1 or less. Note that the bit string X0_j <m-1:0>is the most significant bit (MSB) X0_j <m-1>It means a column in which m bits from the least significant bit (LSB) X0_j<0> are arranged in order within the data. Hereinafter, the signal X0_j is also called data or a bit string.

[0025] The voltage generation circuit (VREFGEN) 30 is configured to generate a reference voltage VRp and a reference voltage VRn. The voltage generation circuit 30 supplies the generated reference voltages VRp, VRn to the TI-ADC circuit 20.

[0026] The digital signal processing (DSP) circuit 40 includes, for example, a feed-forward equalizer (FFE), a decision feedback equalizer (DFE), and a data processing circuit. The signal X0 is supplied to the DSP circuit 40. The DSP circuit 40 performs digital processing on the signal X0 using the FFE, DFE, and data processing circuit. Specifically, the DSP circuit 40 generates a signal X1 and data DA based on the signal X0. The DSP circuit 40 outputs the signal X1 and the data DA to the clock data recovery circuit 50. The DSP circuit 40 outputs the signal X1 and the data DA to a subsequent circuit (not shown). By the subsequent circuit, the signal X1 and the data DA are processed. The signal X1 and the data DA output to the clock data recovery circuit 50 may be the same signals as, or different signals from, the signal X1 and the data DA output to the subsequent circuit, respectively.

[0027] The signal X1 is a digital signal, similar to the signal X0. One cycle of the signal X1 is a set of n r2 digital values. The data DA is data decoded based on the signal X1.

[0028] The clock data recovery (CDR) circuit 50 receives the signal X1 and the data DA every cycle. The CDR circuit 50 receives, for example, the reference clock signal CKREF from the transmission device 2. The reference clock signal CKREF may be generated within the CDR circuit 50 or within the receiving device 4 independently of the transmission device 2. The CDR circuit 50 calculates the phase correction amounts of the signals CK1 and CK2 based on the reference clock signal CKREF, the signal X1, and the data DA. The CDR circuit 50 regenerates the signals CK1 and CK2 based on the calculated phase correction amounts. The CDR circuit 50 supplies the regenerated signals CK1, CK2 to the TI-ADC circuit 20 every cycle. In this way, the CDR circuit 50 regenerates the signals CK1, CK2 serving as the sampling timing reference for the subsequent one-cycle signal X0 based on the signal X1 and the data DA generated from the one-cycle signal X0. Such cycle-by-cycle circulation processing by the TI-ADC circuit 20, the DSP circuit 40, and the CDR circuit 50 is also called a CDR loop.

[0029] (a-3) Analog-to-digital converter Referring to FIG. 3, the internal configuration of the TI-ADC circuit 20 of the receiving device 4 in this embodiment will be described. FIG. 3 is a block diagram showing an example of the configuration of the TI-ADC circuit 20 of the receiving device 4 of the embodiment. Here, the specific combination of (n r1 , n r2 ) will be described for the case where (8, 32) is applied.

[0030] The TI-ADC circuit 20 includes two sampling front ends (SFE) 21p, 21n and a plurality of successive approximation register analog-to-digital converters (SAR-ADC) 22.

[0031] A plurality of SAR-ADC22s include 32 SAR-ADC22_0, …, 22_31. In the example of FIG. 3, four SAR-ADC22_0, 22_8, 22_16, 22_24 are denoted as "SAR-ADC22_0 + 8k". k is 0 or more and 3 or less. Similarly, four SAR-ADC22_1, 22_9, 22_17, 22_25 are denoted as "SAR-ADC22_1 + 8k". Four SAR-ADC22_2, 22_10, 22_18, 22_26 are denoted as "SAR-ADC22_2 + 8k". Four SAR-ADC22_3, 22_11, 22_19, 22_27 are denoted as "SAR-ADC22_3 + 8k". Four SAR-ADC22_4, 22_12, 22_20, 22_28 are denoted as "SAR-ADC22_4 + 8k". Four SAR-ADC22_5, 22_13, 22_21, 22_29 are denoted as "SAR-ADC22_5 + 8k". Four SAR-ADC22_6, 22_14, 22_22, 22_30 are denoted as "SAR-ADC22_6 + 8k". Four SAR-ADC22_7, 22_15, 22_23, 22_31 are denoted as "SAR-ADC22_7 + 8k".

[0032] SFE21p receives the signal Sin from the AFE circuit 10. SFE21p generates a plurality of voltages Vinp based on the signal Sin. SFE21p outputs the generated plurality of voltages Vinp to a corresponding plurality of SAR-ADC22s. The plurality of voltages Vinp include eight voltages Vinp_0, Vinp_1, Vinp_2, Vinp_3, Vinp_4, Vinp_5, Vinp_6, Vinp_7. The eight voltages Vinp_0, …, Vinp_7 are preferably equal, but may be different from each other.

[0033] SFE21n receives the signal / Sin from the AFE circuit 10. SFE21n generates a plurality of voltages Vinn based on the signal / Sin. SFE21n outputs the generated plurality of voltages Vinn to a corresponding plurality of SAR-ADCs 22. The plurality of voltages Vinn includes eight voltages Vinn_0, Vinn_1, Vinn_2, Vinn_3, Vinn_4, Vinn_5, Vinn_6, Vinn_7. The eight voltages Vinn_0, …, Vinn_7 are preferably equal, but may be different from each other.

[0034] Each of SFE21p and SFE21n has substantially the same configuration. In the following, the configuration of SFE21p will be mainly described.

[0035] SFE21p includes a plurality of buffers 211, a plurality of switching elements 212, a plurality of capacitors 213, and a plurality of buffers 214. The plurality of buffers 211 includes four buffers 211a, 211b, 211c, 211d. The plurality of switching elements 212 includes eight switching elements 212_0, 212_1, 212_2, 212_3, 212_4, 212_5, 212_6, 212_7. The plurality of capacitors 213 includes eight capacitors 213_0, 213_1, 213_2, 213_3, 213_4, 213_5, 213_6, 213_7. The plurality of buffers 214 includes eight buffers 214_0, 214_1, 214_2, 214_3, 214_4, 214_5, 214_6, 214_7. Each of the plurality of switching elements 212 is configured to include, for example, a transistor. The signal CK1 is used as a control signal for controlling the on and off of each switching element 212.

[0036] In SFE21p, the signal Sin is supplied to the input nodes of each of the buffers 211a, 211b, 211c, 211d.

[0037] In SFE21n, the signal / Sin is input to the input nodes of each of the buffers 211a, 211b, 211c, 211d.

[0038] The output node of buffer 211a is connected to the first node of each of switching elements 212_0 and 212_4. The output node of buffer 211b is connected to the first node of each of switching elements 212_2 and 212_6. The output node of buffer 211c is connected to the first node of each of switching elements 212_1 and 212_5. The output node of buffer 211d is connected to the first node of each of switching elements 212_3 and 212_7.

[0039] The second node of switching element 212_0 is connected to the first node of capacitor 213_0 and the input node of buffer 214_0. The second node of capacitor 213_0 is grounded. To ground a node means that the node is connected to the wiring of the reference potential during the operation of SFE21p. When signal CK1_0 is at the "H" level, switching element 212_0 is in the on state. When signal CK1_0 is at the "L" level, switching element 212_0 is in the off state.

[0040] The second node of switching element 212_1 is connected to the first node of capacitor 213_1 and the input node of buffer 214_1. The second node of capacitor 213_1 is grounded. When signal CK1_1 is at the "H" level, switching element 212_1 is in the on state. When signal CK1_1 is at the "L" level, switching element 212_1 is in the off state.

[0041] The second node of switching element 212_2 is connected to the first node of capacitor 213_2 and the input node of buffer 214_2. The second node of capacitor 213_2 is grounded. When signal CK1_2 is at the "H" level, switching element 212_2 is in the on state. When signal CK1_2 is at the "L" level, switching element 212_2 is in the off state.

[0042] The second node of the switching element 212_3 is connected to the first node of the capacitor 213_3 and the input node of the buffer 214_3. The second node of the capacitor 213_3 is grounded. When the signal CK1_3 is at the "H" level, the switching element 212_3 is in the on state. When the signal CK1_3 is at the "L" level, the switching element 212_3 is in the off state.

[0043] The second node of the switching element 212_4 is connected to the first node of the capacitor 213_4 and the input node of the buffer 214_4. The second node of the capacitor 213_4 is grounded. When the signal CK1_4 is at the "H" level, the switching element 212_4 is in the on state. When the signal CK1_4 is at the "L" level, the switching element 212_4 is in the off state.

[0044] The second node of the switching element 212_5 is connected to the first node of the capacitor 213_5 and the input node of the buffer 214_5. The second node of the capacitor 213_5 is grounded. When the signal CK1_5 is at the "H" level, the switching element 212_5 is in the on state. When the signal CK1_5 is at the "L" level, the switching element 212_5 is in the off state.

[0045] The second node of the switching element 212_6 is connected to the first node of the capacitor 213_6 and the input node of the buffer 214_6. The second node of the capacitor 213_6 is grounded. When the signal CK1_6 is at the "H" level, the switching element 212_6 is in the on state. When the signal CK1_6 is at the "L" level, the switching element 212_6 is in the off state.

[0046] The second node of the switching element 212_7 is connected to the first node of the capacitor 213_7 and the input node of the buffer 214_7. The second node of the capacitor 213_7 is grounded. When the signal CK1_7 is at the "H" level, the switching element 212_7 is in the on state. When the signal CK1_7 is at the "L" level, the switching element 212_7 is in the off state.

[0047] As described above, in SFE21p, each of the voltages Vinp_0, …, Vinp_7 corresponding to the signal Sin at the timing when the signals CK1_0, …, CK1_7 are at the "H" level is sequentially held in each of the buffers 214_0, …, 214_7. Similarly, in SFE21n, each of the voltages Vinn_0, …, Vinn_7 corresponding to the signal / Sin at the timing when the signals CK1_0, …, CK1_7 are at the "H" level is sequentially held in each of the buffers 214_0, …, 214_7.

[0048] The output nodes of each of the buffers 214_0 of SFE21p and SFE21n are connected to SAR-ADC22_0, 22_8, 22_16, 22_24. The output nodes of each of the buffers 214_1 of SFE21p and SFE21n are connected to SAR-ADC22_1, 22_9, 22_17, 22_25. The output nodes of each of the buffers 214_2 of SFE21p and SFE21n are connected to SAR-ADC22_2, 22_10, 22_18, 22_26. The output nodes of each of the buffers 214_3 of SFE21p and SFE21n are connected to SAR-ADC22_3, 22_11, 22_19, 22_27. The output nodes of each of the buffers 214_4 of SFE21p and SFE21n are connected to SAR-ADC22_4, 22_12, 22_20, 22_28. The output nodes of each of the buffers 214_5 of SFE21p and SFE21n are connected to SAR-ADC22_5, 22_13, 22_21, 22_29. The output nodes of each of the buffers 214_6 of SFE21p and 21n are connected to SAR-ADC22_6, 22_14, 22_22, 22_30. The output nodes of each of the buffers 214_7 of SFE21p and SFE21n are connected to SAR-ADC22_7, 22_15, 22_23, 22_31.

[0049] SAR-ADC22_0, …, SAR-ADC22_31 receive signals CK2_0, …, CK2_31 respectively. Reference voltage VRp and reference voltage VRn are supplied to each of SAR-ADC22_0, …, SAR-ADC22_31 via different wirings. SAR-ADC22_0, …, SAR-ADC22_31 output signals X0_0, …, X0_31 respectively based on the corresponding signals CK2_0, …, CK2_31 and reference voltages VRp, VRn. Each of SAR-ADC22_0, …, SAR-ADC22_31 has substantially the same configuration. Signal CK2 is used as a control signal for controlling the operation of SAR-ADC22.

[0050] Note that the voltage levels of the reference voltages VRp and VRn may transiently vary according to the operating conditions of the destination SAR-ADCs 22_0, …, 22_31.

[0051] For example, components that operate in response to signal CK1 belong to the Rank-1 hierarchy in the TI-ADC circuit 20. For example, components that operate in response to signal CK2 belong to the Rank-2 hierarchy in the TI-ADC circuit 20.

[0052] (a-4) Successive approximation analog-to-digital converter Referring to FIG. 4, the internal configuration of the SAR-ADC 22 in the TI-ADC circuit 20 in the present embodiment will be described. FIG. 4 is a block diagram showing an example of the internal configuration of the SAR-ADC 22 in the TI-ADC circuit 20 of the embodiment.

[0053] In the example of FIG. 4, an example of the configuration of any one of the 32 SAR-ADCs 22_0, …, 22_31, SAR-ADC 22_j, is shown. j is 0 or more and n r2 -1 (=31) or less.

[0054] The SAR-ADC 22_j executes a determination operation on a supplied bit string. The SAR-ADC 22_j is, for example, a SAR-ADC configured to be able to make a determination up to 8 bits. The determination operation of a certain bit string by the SAR-ADC 22_j is called a SAR operation.

[0055] Hereinafter, as an example of the SAR-ADC 22_j, an asynchronous operation type SAR-ADC will be described.

[0056] The SAR-ADC 22_j includes switching elements 221p_j, 221n_j, a capacitive digital-to-analog converter 222_j, a comparator 223_j, and a control logic circuit 225_j.

[0057] Each of the switching elements 221p_j and 221n_j includes a first node and a second node. The first node of the switching element 221p_j receives the voltage Vinp. The second node of the switching element 221p_j is connected to the first input node of the CDAC 222_j. The first node of the switching element 221n_j receives the voltage Vinn. The second node of the switching element 221n_j is connected to the second input node of the CDAC 222_j.

[0058] The switching elements 221p_j and 221n_j operate in response to the signal CK2_j. When the signal CK2_j is at the "H" level, the switching elements 221p_j and 221n_j are in the on state. When the signal CK2_j is at the "L" level, the switching elements 221p_j and 221n_j are in the off state.

[0059] The capacitive digital-to-analog converter (CDAC) 222_j is composed of a plurality of capacitors and a plurality of switching elements. The plurality of capacitors and the plurality of switching elements constitute a switching capacitor array.

[0060] The CDAC 222_j includes a first input node, a second input node, a first output node, and a second output node. The first input node of the CDAC 222_j is connected to the second input node of the switching element 221p_j. The second input node of the CDAC 222_j is connected to the second input node of the switching element 221n_j.

[0061] The first output node of the CDAC 222_j is connected to the first input node of the comparator 223_j. The second output node of the CDAC 222_j is connected to the second input node of the comparator 223_j.

[0062] CDAC222_j holds the voltages Vinp and Vinn from the switching elements 221p_j and 221n_j in a plurality of capacitors. The charge corresponding to the voltage Vinp at the timing when the signal CK2_j becomes the "H" level is charged to the plurality of capacitors in CDAC222_j. As a result, the voltage Vinp is held in CDAC222_j as the initial value of the voltage Vcmpp. The charge corresponding to the voltage Vinn at the timing when the signal CK2_j becomes the "H" level is charged to the plurality of capacitors in CDAC222_j. As a result, the voltage Vinn is held in CDAC222_j as the initial value of the voltage Vcmpn.

[0063] CDAC222_j outputs the voltage Vcmpp in response to the digital-to-analog conversion of the voltage Vinp from the switching element 221p_j. CDAC222_j outputs the voltage Vcmpn in response to the digital-to-analog conversion of the voltage Vinn from the switching element 221n_j. For example, CDAC222_j performs digital-to-analog conversion using the reference voltages VRp and VRn from the voltage generation circuit 30. The voltages Vcmpp and Vcmpn are analog signals.

[0064] Comparator 223_j includes a first input node and a second input node. The first input node of comparator 223_j receives the voltage Vcmpp from CDAC222_j. The second input node of comparator 223_j receives the voltage Vcmpn from CDAC222_j.

[0065] Comparator 223_j includes a first output node and a second output node. The first output node of comparator 223_j is connected to the first input node of NOR gate 224_j and the control logic circuit 225_j. The second output node of comparator 223_j is connected to the second input node of NOR gate 224_j and the control logic circuit 225_j.

[0066] Comparator 223_j receives the signal CCK from the control logic circuit 225_j. Based on the signal CCK at the "L" level, comparator 223_j resets the first output node and the second output node of comparator 223_j. Comparator 223_j outputs signals Qp and Qn at the "L" level from the reset first and second output nodes.

[0067] Comparator 223_j executes a comparison process to compare the magnitude relationship between the voltage Vcmpp and the voltage Vcmpn based on the signal CCK at the "H" level. Through the comparison process of comparator 223_j, a determination of a plurality of bits included in the bit string X0_j is made. In the comparison process of comparator 223_j, when the difference between the voltage Vcmpp and the voltage Vcmpn (hereinafter referred to as the potential difference (Vcmpp - Vcmpn)) is positive, comparator 223_j outputs a signal Qp at the "H" level from the first output node and a signal Qn at the "L" level from the second output node. In the comparison process of comparator 223_j, when the potential difference (Vcmpp - Vcmpn) is negative, comparator 223_j outputs a signal Qp at the "L" level from the first output node and a signal Qn at the "H" level from the second output node. When the potential difference (Vcmpp - Vcmpn) is regarded as 0, comparator 223_j outputs a signal Qp at the "L" level from the first output node and a signal Qn at the "L" level from the second output node.

[0068] The NOR gate 224_j notifies the control logic circuit 225_j of the completion of the comparison process by the comparator 223_j. For example, when both the signal Qp and the signal Qn have an "L" level, the NOR gate 224_j supplies a signal RY of "H" level to the control logic circuit 225_j. When the signal Qp or the signal Qn has an "H" level, the NOR gate 224_j outputs a signal RY of "L" level to the control logic circuit 225_j. When the signal level of the signal RY output from the NOR gate 224_j transitions from the "L" level to the "H" level, the control logic circuit 225_j is notified that the comparison process has ended or that the comparison process is in a metastable state. The metastable state indicates a state where the value evaluated and determined by the comparison process of the comparator 223_j is not determined.

[0069] The control logic circuit 225_j outputs a signal CCK of "L" level based on a signal CK2_j of "H" level. The control logic circuit 225_j outputs a signal CCK of "H" level based on a signal CK2_j of "L" level. Based on the signal CCK of "H" level, the comparator 223_j is performing a comparison process. The control logic circuit 225_j executes a determination process of sequentially determining from the most significant bit to the least significant bit in a certain bit string (data) X0_j according to the signal from the comparator 223_j based on the signal CK2_j of "L" level. The control logic circuit 225_j outputs the bit string X0_j to a subsequent circuit such as the DSP circuit 40 based on the result of the determination process.

[0070] An example of the determination process for each bit in the bit string X0_j is performed as follows. When the signal Qp has a signal level of "H" level and the signal Qn has a signal level of "L" level (when the potential difference Vcmpp - Vcmpn is positive), the control logic circuit 225_j determines that the corresponding bit is "1". When the signal Qp has a signal level of "L" level and the signal Qn has a signal level of "H" level (when the potential difference Vcmpp - Vcmpn is negative), the control logic circuit 225_j determines that the corresponding bit is "0".

[0071] For example, within a period when the signal level of signal CCK is at the "H" level, if the signal level of the signal output from NOR gate 224_j changes from the "L" level to the "H" level, control logic circuit 225_j detects that the ongoing determination process (comparison process) is in a metastable state.

[0072] Control logic circuit 225_j generates signal CNT. Control logic circuit 225_j supplies the generated signal CNT to CDAC222_j. CDAC222_j controls various operations related to digital - to - analog conversion from voltages Vinp, Vinn to voltages Vcmpp, Vcmpn based on signal CNT.

[0073] In this embodiment, control logic circuit 225_j includes determination processing circuit 900. Determination processing circuit 900 performs a determination process on the value of each bit included in the bit string based on the result of the comparison process of comparator 223_j. In the determination process of each bit included in the bit string, if the signal levels of signal Qp and signal Qn (voltage values of voltages Vcmpp, Vcmpn) are not determined and the determination of a certain bit does not end even after a certain period has elapsed, determination processing circuit 900 sets a temporary value for the value of the bit being determined. After the determination of the bit for which the temporary value has been set ends, determination processing circuit 900 sets the value corresponding to the determination result for the bit for which the temporary value has been set. For example, when the comparison process by comparator 223_j enters a metastable state, control logic circuit 225_j sets a temporary value for the value of the bit to be determined in response to the occurrence of the metastable state.

[0074] (a - 5) Determination Processing Circuit FIG. 5 is a block diagram for explaining the internal configuration of determination processing circuit 900 in semiconductor integrated circuit 22 of this embodiment.

[0075] Determination processing circuit 900 includes clock generation circuit 910, finite state machine 920, a plurality of determination result storage circuits 930, a plurality of state confirmation circuits 940, and output control circuit 950.

[0076] The clock generation circuit 910 generates a periodic signal including edges having periodicity. The clock generation circuit 910 is composed of OR gates. Hereinafter, the clock generation circuit 910 is denoted as the OR gate 910. The OR gate 910 includes a plurality of input nodes and one output node. The OR gate 910 receives a plurality of signals CK2_x + 8k. The OR gate 910 performs a logical sum operation (OR operation) on the plurality of signals CK2_x + 8k.

[0077] Each input node of the OR gate 910 receives a corresponding one of the plurality of signals CK2 among the plurality of signals CK2_x + 8k supplied to the OR gate 910. x is an integer from 0 to 7. In the plurality of signals CK2_x + 8k belonging to one set, for a certain fixed value of x, the value of k is changed in the range from 0 to 3. The plurality of signals CK2_x + 8k supplied to the OR gate 910 are Rank-2 plurality of signals CK2 associated with one of the Rank-1 plurality of signals CK1. A set of Rank-2 plurality of signals CK2 is supplied to each of a plurality of SAR-ADC22 forming a certain set. Any one of the plurality of signals CK2_x + 8k is equal to the signal CK2_j. As a specific example, when x is 0 and k is from 0 to 3, the OR gate 910 receives the signal CK2_0, the signal CK2_8, the signal CK2_16, and the signal CK2_24. The OR gate 910 performs an OR operation on the signal CK2_0, the signal CK2_8, the signal CK2_16, and the signal CK2_24. Hereinafter, this example will be described.

[0078] The output node of the OR gate 910 outputs the signal CK2_SUM_y. The signal CK2_SUM_y is a signal indicating the result of the OR operation of the signals CK2_0, CK2_8, CK2_16, and CK2_24. The signal CK2_SUM_y is a clock signal (synthesized clock signal) generated by the synthesis of the signals CK2_0, CK2_8, CK2_16, and CK2_24. The signal CK2_SUM_y is supplied to the state confirmation circuit 940. y is equal to j. y is, for example, an integer greater than or equal to 0 and less than or equal to 31. The signal CK2_SUM_y is a periodic signal including an edge with periodicity.

[0079] Note that the signal CK2_SUM_y having a certain clock cycle may be generated by a clock oscillation circuit (not shown) without being formed by the synthesis of a plurality of signals CK2_x + 8k.

[0080] The finite state machine (FSM) 920 controls the operations of the plurality of determination result storage circuits 930, the plurality of state confirmation circuits 940, and the output control circuit 950. The FSM 920 receives the signal CKa. The FSM 920 manages which bit among the plurality of bits included in the bit string X0_j is being determined based on the signal CKa. The signal CKa is an asynchronous signal. For example, the signal CKa is a signal corresponding to the signal RY output from the NOR gate 224_j. The FSM 920 is the signal S1 and the signal ACK2 (ACK2 <m-1>,ACK2 <m-2>,…,ACK2<0>) are sent to the output control circuit 950.

[0081] Each of the plurality (for example, m) of determination result storage circuits 930 stores the value of one corresponding bit among the plurality of bits included in the bit string X0_j (hereinafter also referred to as a bit value). Each determination result storage circuit 930 receives a signal DR corresponding to the value determined based on the comparison process of the comparator 223_j. The determination result storage circuit 930 corresponding to the bit being determined among the plurality of determination result storage circuits 930 stores the signal DR based on the result of the comparison process of the comparator 223_j as the bit value for which the determination has ended under the control of the FSM 920. For example, each of the determination result storage circuits 930 stores a value of "0" as an initial value at the start of the SAR operation. The FSM 920 sends a signal indicating the operation state of the bit determination to each of the state confirmation circuits 940.

[0082] Each of the plurality (for example, m) of state confirmation circuits 940 confirms the operation state of the determination of the corresponding bit among the plurality of bits in the bit string X0_j based on the signal from the FSM 920. Thereby, each state confirmation circuit 940 can recognize whether the corresponding bit is being evaluated. Each state confirmation circuit 940, based on the result of the confirmation of the operation state of the bit determination, outputs a metastable table notification signal ACK1 (ACK1 <m-1>,ACK1 <m-2>, …, ACK1<0>) is output. The metastable table notification signal ACK1 is a signal indicating that when the bit determination has not ended within a certain period, the operating state of the bit determination is presumed to be in the metastable state.

[0083] For example, the state confirmation circuit 940 checks whether the ongoing bit determination is in the metastable state based on the number of rising edges of a plurality of clocks of the signal CK2_SUM_y. The state confirmation circuit 940 notifies the corresponding processing unit PU in the output control circuit 950 of the result of checking whether the ongoing bit determination is in the metastable state.

[0084] FIG. 6 is a block diagram showing an example of the internal configuration of a certain state confirmation circuit 940 in the present embodiment. FIG. 6 shows the state confirmation circuit 940 <m-1>shows an example of the internal configuration, but other status confirmation circuits 940 <m-2>,…, the status confirmation circuit 940<0> also has a similar internal configuration.

[0085] status confirmation circuit 940 <m-1>It includes a NAND gate 941a, a delay element 942a, a plurality of flip-flops 943a, 944a, 945a, an AND gate 946a, and an OR gate 947a.

[0086] The NAND gate 941a includes a positive-logic input node, a negative-logic input node, and an output node. The delay element 942a includes an input node and an output node.

[0087] The positive-logic input node of the NAND gate 941a is connected to the output node of the delay element 942a. The input node of the delay element 942a receives the signal CK2_j. The NAND gate 941a receives the signal CK2_j via the delay element 942a at the positive-logic input node. The NAND gate 941a receives the signal CK2_j at the negative-logic input node. The output node of the NAND gate 941a is connected to the reset nodes of each of the flip-flops 943a, 944a, 945a. The NAND gate 941a performs a negative logical product (NAND operation) of the negative-logic signal of the signal CK2_j and the delayed signal of the signal CK2_j.

[0088] Each of the flip-flops 943a, 944a, 945a includes a reset node and a clock node. The reset nodes of each of the flip-flops 943a, 944a, 945a receive a signal from the NAND gate 941a. The reset nodes of each of the flip-flops 943a, 944a, 945a are negative-logic nodes. Each of the flip-flops 943a, 944a, 945a is set to a reset state by the "L" level signal output from the NAND gate 941a. The clock nodes of each of the flip-flops 943a, 944a, 945a receive the signal CK2_SUM_y from the output node of the OR gate 910. Each of the flip-flops 943a, 944a, 945a latches the signal supplied to the input node of each of the flip-flops 943a, 944a, 945a at a timing synchronized with the signal CK2_SUM_y.

[0089] Each flip-flop 943a, 944a, 945a includes an input node and an output node. AND gate 946a includes a first input node, a second input node, and an output node. OR gate 947a includes a first input node, a second input node, and an output node.

[0090] The input node of flip-flop 943a is connected to FSM920. The output node of flip-flop 943a is connected to the input node of flip-flop 944a and the first input node of AND gate 946a. The output node of flip-flop 944a is connected to the second input node of AND gate 946a. The output node of AND gate 946a is connected to the first input node of OR gate 947a. OR gate 947a receives the signal from AND gate 946a at the first input node. The input node of flip-flop 945a is connected to the output node of OR gate 947a. The output node of flip-flop 945a is connected to the second input node of OR gate 947a.

[0091] Flip-flop 943a receives the signal from FSM920 at the input node. Flip-flop 944a receives the signal from flip-flop 943a at the input node. Flip-flop 945a receives the signal from OR gate 947a at the input node. The signal supplied from FSM920 to flip-flop 943a is a signal indicating the operating state of the determination of the corresponding bit. For example, the signal supplied from FSM920 to flip-flop 943a is a signal based on signal RY (and signal CKa).

[0092] AND gate 946a receives the signal from flip-flop 943a at the first input node and the signal from flip-flop 944a at the second input node. AND gate 946a performs a logical product operation (AND operation) on the signal from flip-flop 943a and the signal from flip-flop 944a.

[0093] The OR gate 947a receives the signal from the AND gate 946a at the first input node and receives the signal from the flip-flop 945a at the second input node. The OR gate 947a performs an OR operation on the signal from the AND gate 946a and the signal from the flip-flop 945a.

[0094] The signal output from the OR gate 947a is the metastable notification signal ACK1 <m-1>is supplied to the output control circuit 950.

[0095] status confirmation circuit 940 <m-1>It operates as follows.

[0096] During a certain SAR operation period, each of the plurality of flip - flops 943a, 944a, 945a operates at a timing synchronized with the signal CK2_SUM_y.

[0097] In the current cycle of the signal CK2_SUM_y, the flip - flop 943a stores the signal from the FSM920. The flip - flop 944a stores the signal from the flip - flop 943a. The signal stored in the flip - flop 944a is the same as the signal from the FSM920 in the cycle one before the current cycle of the signal CK2_SUM_y.

[0098] The AND gate 946a performs an AND operation on the signal from the flip - flop 943a and the signal from the flip - flop 944a. The AND gate 946a supplies a signal indicating the result of the AND operation to the OR gate 947a.

[0099] The flip - flop 945a stores the signal output from the OR gate 947a in the cycle one before the current cycle in the signal CK2_SUM_y. The flip - flop 945a supplies the signal from the OR gate 947a in the previous cycle to the OR gate 947a in the current cycle.

[0100] The OR gate 947a performs an OR operation on the signal from the AND gate 946a and the signal from the flip - flop 945a. The OR gate 947a supplies a signal indicating the result of the OR operation to the metastable state notification signal ACK1 <m-1>Output as such. When both the signal from AND gate 946a and the signal from flip-flop 945a have a signal level of "L", OR gate 947a outputs a metastable notification signal ACK1 of "L" level. When at least one of the signal from AND gate 946a and the signal from flip-flop 945a has a signal level of "H", OR gate 947a outputs a metastable notification signal ACK1 of "H" level <m-1>Output it.

[0101] NAND gate 941a receives signal CK2_j at the input node of negative logic. NAND gate 941a receives the delayed signal of signal CK2_j via delay element 942a at the input node of positive logic. NAND gate 941a performs a NAND operation on the negative logic signal of signal CK2_j and the delayed signal of signal CK2_j. NAND gate 941a supplies a signal indicating the result of the NAND operation to the reset nodes of each flip-flop 943a, 944a, 945a.

[0102] When the signal level of the signal from NAND gate 941a is at the "L" level, each flip-flop 943a, 944a, 945a is set to the reset state. The "L" level signal from NAND gate 941a is a signal indicating the end of the SAR operation.

[0103] During the SAR operation, when each of flip-flops 943a, 944a, 945a stores a signal at the "H" level, OR gate 947a outputs a metastable notification signal ACK1 at the "H" level.

[0104] For example, during the period when two rising edges in a plurality of clocks of signal CK2_SUM_y are supplied to flip-flops 943a, 944a, 945a, if FSM920 sets the signal level of a signal related to the determination state of a bit to be determined to the "H" level, both of the two flip-flops 943a, 944a latch the supplied "H" level signal at the timing synchronized with the rising edge of the clock of signal CK2_SUM_y respectively. Thereby, OR gate 947a outputs a metastable notification signal ACK1 at the "H" level <m-1>Output it.

[0105] Through the above operations, the status confirmation circuit 940 <m-1>is the metastable table notification signal ACK1 in the current cycle based on the signal CK2_SUM_y <m-1>Output it. The output meta-table notification signal ACK1 <m-1>has a value indicating whether or not the operation state of the bit determination is in a metastable state in the cycle based on the signal CK2_SUM_y.

[0106] The bit to be determined is recognized by the FSM920. If two rising edges of the signal CK2_SUM_y are detected during the determination period of the bit value to be determined, the corresponding bit value is sent to the processing unit PU being processed. <m-1>Meta-table notification signal ACK1 for <m-1>The state confirmation circuit 940 is configured such that the signal level of <m-1>The signal holding state is controlled.

[0107] In this way, when the determination of the bit to be determined has not been completed within a certain period, the state confirmation circuit 940 can confirm whether the operation state of the determination of the corresponding bit has stalled (for example, metastable state) according to the internal signal state.

[0108] Returning to the description of FIG. 5. The output control circuit 950 outputs the data of the bit string obtained by the SAR operation based on the signals S1, ACK2 from the FSM 920, the signal from the determination result storage circuit 930, and the metastable state notification signal ACK1 from the state confirmation circuit 940.

[0109] In this embodiment, when the output control circuit 950 detects that the determination of the bit value to be determined has not been completed within a certain period based on the metastable state notification signal ACK1 and the signals S1, ACK2 from the FSM 920, it sets a temporary value for the bit value to be determined. As a result, when the determination of a certain bit in the bit string stalls, the output control circuit 950 can output a bit string including the temporary value.

[0110] The output control circuit 950 includes m processing units PU (PU <m-1>,PU <m-2>, …, PU<0>). The output control circuit 950 executes a process of setting bit values in the m-bit bit string X0_j during the period of the SAR operation by the processing of a plurality of processing units PU. When the determination process in the SAR operation is executed for an 8-bit bit string, the output control circuit 950 includes eight processing units PU. Each of the processing units PU is associated with one of a plurality of bits within the bit string. Each processing unit PU sets a provisional value or a value of a determination result to the corresponding bit.

[0111] FIG. 7 is a block diagram showing an example of the internal configuration of the output control circuit 950. In FIG. 7, external components related to the internal configuration of the output control circuit 950 are also shown.

[0112] As shown in FIG. 7, the output control circuit 950 includes eight processing units PU (PU<7>, PU<6>, …, PU<1>, PU<0>). The processing unit PU<7> corresponding to the most significant bit includes a selector 951<7>, an AND gate 953<7>, and a selector 954<7>. Each of the processing units PU<6>, …, PU<1> corresponding to the seventh to second bits includes a selector 951 (951<6>, …, 951<1>), an AND gate 953 (953<6>, …, 953<1>), a selector 954 (954<6>, …, 954<1>), and a NOR gate 959 (959<6>, …, 959<1>). The processing unit PU<0> corresponding to the least significant bit includes a selector 951<0> and a NOR gate 959<0>.

[0113] Each selector 951 includes a first input node, a second input node, an output node, and a control node. The first input node of the selector 951 is connected to the determination result storage circuit 930 of a corresponding one of the plurality of bits included in the bit string X0_j. In the processing unit PU<7> corresponding to the most significant bit of the bit string X0_j, the second input node of the selector 951<7> is connected to, for example, the FSM920. In each of the processing units PU<6>, …, PU<0> corresponding to bits other than the most significant bit, the second input nodes of the selectors 951<6>, …, 951<0> are connected to the output nodes of the corresponding NOR gates 959. The output node of the selector 951 is connected to the input node of a corresponding one of the plurality of flip-flops 991<7>, …, 991<0>. The control node of the selector 951 is connected to the FSM920. The control node of each selector 951 receives a corresponding signal ACK2 (ACK2<7>, …, ACK2<0>) from the FSM920. The signal ACK2 is a signal indicating that the determination of the bit corresponding to the processing unit PU has been completed. Hereinafter, the signal ACK2 is referred to as the determination completion notification signal ACK2.

[0114] The input node of the flip-flop 991 receives a signal from the selector 951. The output node of the flip-flop 991 outputs the stored value. The reset node of the flip-flop 991 receives the signal CK2_j. The reset node of the flip-flop 991 is a node with negative logic. The flip-flop 991 latches the signal from the selector 951 at a timing corresponding to the signal transition of the signal CK2_j. Thereby, each flip-flop 991 stores the signal from the corresponding processing unit PU.

[0115] Each AND gate 953 includes a first input node, a second input node, and an output node. The first input node of the AND gate 953 is connected to the FSM 920. The first input node of the AND gate 953 receives the corresponding determination end notification signal ACK2. The second input node of the AND gate 953 is connected to the corresponding determination result storage circuit 930. The second input node of the AND gate 953 receives the signal (value) stored in the determination result storage circuit 930. The output node of the AND gate 953 is connected to the first input node of the selector 954. The AND gate 953 performs an AND operation on the determination end notification signal ACK2 and the signal from the determination result storage circuit 930. The AND gate 953 sends a signal indicating the result of the AND operation to the selector 954.

[0116] The selector 954 includes a first input node, a second input node, an output node, and a control node. The first input node of the selector 954 is a positive logic input node. The first input node of the selector 954 is connected to the output node of the AND gate 953. The second input node of the selector 954 is a negative logic input node. In the processing unit PU<7> corresponding to the most significant bit, the second input node of the selector 954<7> is connected to the FSM 920. In each of the processing units PU<6>, …, PU<1> corresponding to bits other than the most significant bit, the second input node of the selector 954<6> is connected to the output node of the NOR gate 959 within the same processing unit PU <m-1>The output node of the selector 954 is the subsequent processing unit PU <m-2>is connected to the first input node of the NOR gate 959. The control node of the selector 954 is connected to the status confirmation circuit 940. The control node of the selector 954 receives the metastable table notification signal ACK1.

[0117] The NOR gate 959 includes a first input node, a second input node, and an output node. The first input node of the NOR gate 959 is connected to the output node of the selector 954 of the previous processing unit PU. The first input node of the NOR gate 959 receives a signal from the selector 954 of the previous processing unit PU. The second input node of the NOR gate 959 is connected to the status confirmation circuit 940. The second input node of the NOR gate 959 receives the metastable table notification signal ACK1. The output node of the NOR gate 959 is connected to the second input node of the selector 951 and the second input node of the selector 954 within the same processing unit PU. A certain processing unit PU <m-1>The NOR gate 959 receives the supplied metastable notification signal ACK1 and the previous processing unit PU <m>Execute the result of the NOR operation with the signal from selector 954. NOR gate 959 sends a signal indicating the result of the NOR operation to selector 951 and selector 954.

[0118] A certain processing unit PU <m-1>The selector 954 inside, based on the metastable table notification signal ACK1, selects one of the signal that is the result of the AND operation from the AND gate 953 and the inverted signal of the signal supplied to the second input node, and outputs it to the subsequent processing unit PU <m-2>Output to the NOR gate 959. When the operation state of the determination of the corresponding bit is the metastable state, the selector 954 selects the signal from the AND gate 953. When the state of the determination of the bit is not the metastable state, the selector 954 selects the inverted signal of the signal supplied to the second input node.

[0119] Based on the determination end notification signal ACK2, the selector 951 outputs one of the signal from the determination result storage circuit 930 and the signal supplied to the second input node of the selector 951 to the flip-flop 991. When the determination of the corresponding bit has not ended, the selector 951 selects the signal supplied to the second input node. When the determination of the corresponding bit has ended, the selector 951 selects the signal from the determination result storage circuit 930. The value of the signal supplied to the second input node of the selector 951 corresponds to the provisional value to be set to the bit to be determined.

[0120] Thus, when the operation state of the determination of the corresponding bit is the metastable state, the determination processing circuit 900 can assign a provisional value to the bit whose bit determination is in the metastable state.

[0121] (b) Operation example (b-1) Clock timing With reference to FIG. 8, the clock timing in the receiving device and the semiconductor integrated circuit of the present embodiment will be described. FIG. 8 is a timing chart showing an example of a clock signal in the receiving device of the embodiment.

[0122] The signal CK1 is an 8-phase clock signal with phases shifted at equal intervals. The period of each "H" level of the signal CK1 is T1. In the signal CK1, each of the periods of the "H" level is substantially equal. The period of each "L" level of the signal CK1 is H1. In the signal CK1, each of the periods of the "L" level is substantially equal.

[0123] The signal CK2 is a 32-phase clock signal with equally spaced phase shifts. The period of each "H" level of the signal CK2 is T2. In the signal CK2, each period of the "H" level is substantially equal. The period of each "L" level of the signal CK2 is H2. In the signal CK2, each period of the "L" level is substantially equal.

[0124] The n of the signal CK1 r2 / n r1 The cycle is, for example, equal to one cycle of the signal CK2. n r1 = 8, n r2 = 32, 4(T1 + H1) = T2 + H2. The period H1 is, for example, longer than the period T2.

[0125] Hereinafter, the relationship between the signal CK1_0 and the signal CK2 will be described.

[0126] During the period when the signal level of the first cycle of the signal CK1_0 is at the "H" level (the period T1_0 in FIG. 8), the switching elements 212_0 of each of the SFE21p and SFE21n in FIG. 3 are in the on state. As a result, the charges corresponding to the signals Sin and / Sin are respectively charged to the capacitors 213_0 of the SFE21p and SFE21n. During the period when the signal level of the first cycle of the signal CK1_0 is at the "L" level (the period H1_0 in FIG. 8), the switching elements 212_0 of each of the SFE21p and SFE21n are in the off state. During this period H1_0, the buffer 214_0 holds the charge charged to the capacitor 213_0.

[0127] During the period H1_0, the period when the signal CK2_0 becomes the "H" level (the period T2_0 in FIG. 8) is included. During the period T2_0, the switching elements 221p_0, 221n_0 of the SAR-ADC22_0 are in the on state. As a result, the charges held in the buffers 214_0 of each of the SFE21p and SFE21n are respectively charged to a plurality of capacitors in the CDAC222_0.

[0128] Thereafter, during the period when the signal CK2_0 is at the "L" level (period H2_0 in FIG. 8), the switching elements 221p_0 and 221n_0 of the SAR-ADC22_0 are in the off state. During this period H2_0, the CDAC222_0 holds the charges stored in a plurality of capacitors within the CDAC222_0. The stored charges are preserved over the period H2_0. Using the stored charges, the bit sequence X0_0<7:0> included in the data X0_0 is sequentially determined from the most significant bit to the least significant bit.

[0129] In FIG. 8, the period during which the most significant bit (the first bit) is determined, the period during which the second bit is determined, …, and the period during which the least significant bit is determined are period D MSB , D 2ND , …, D LSB and are respectively indicated as such. In the example of FIG. 8, the period D of the signal CK2_0 MSB is included in the period during which the signal CK2_4 is at the "H" level (period T2_4 in FIG. 8). The period D of the signal CK2_0 2ND is included in the period during which the signal CK2_8 is at the "H" level (period T2_8 in FIG. 8). The period D of the signal CK2_4 MSB is included in the period during which the signal CK2_8 is at the "H" level (period T2_8 in FIG. 8). Note that each of the periods D MSB , D 2ND , …, D LSB may span the periods during which a plurality of clock signals among the signals CK2 are at the "H" level.

[0130] For example, the rising edge of the signal CK2_8 is shifted from the falling edge of the signal CK2_0 by a period D MSB only.

[0131] In signal CK1_0, the operations in the second cycle, third cycle, and fourth cycle are substantially the same as those in the first cycle. That is, during the periods when the second cycle, third cycle, and fourth cycle of signal CK1_0 are at the "H" level (periods T1_8, T1_16, T1_24 in FIG. 8), each switching element 212_0 of SFE21p and SFE21n is in the on state. As a result, the charges corresponding to signal Sin and signal / Sin are respectively charged to the capacitors 213_0 of SFE21p and SFE21n. During the periods when the second cycle, third cycle, and fourth cycle of signal CK1_0 are at the "L" level (periods H1_8, H1_16, H1_24 in FIG. 8), each switching element 212_0 of SFE21p and SFE21n is in the off state. During the period when the switching element 212_0 is in the off state, buffer 214_0 holds the voltage value charged to capacitor 213_0.

[0132] During periods H1_8, H1_16, H1_24, the periods when signals CK2_8, CK2_16, CK2_24 are at the "H" level (periods T2_8, T2_16, T2_24 in FIG. 8) are respectively included. In periods T2_8, T2_16, T2_24, the switching elements 221p_8, 221n_8 of SAR-ADC22_8, the switching elements 221p_16, 221n_16 of SAR-ADC22_16, and the switching elements 221p_24, 221n_24 of SAR-ADC22_24 are respectively in the on state. As a result, the charges held by each buffer 214_0 of SFE21p and SFE21n are respectively charged to the plurality of capacitors of CDAC222_8 in period T2_8, to the plurality of capacitors of CDAC222_16 in period T2_16, and to the plurality of capacitors of CDAC222_24 in period T2_24.

[0133] Thereafter, during the periods when each of the signals CK2_8, CK2_16, and CK2_24 is at the "L" level (periods H2_8, H2_16, and H2_24 in FIG. 8), the switching elements 221p_8, 221n_8 of SAR-ADC22_8, the switching elements 221p_16, 221n_16 of SAR-ADC22_16, and the switching elements 221p_24, 221n_24 of SAR-ADC22_24 are in the off state. In each of the periods H2_8, H2_16, and H2_24, CDAC222_8, 222_16, and 222_24 hold the charges charged to the plurality of capacitors in CDAC222. The held charges are respectively stored over the periods H2_8, H2_16, and H2_24. Then, in each of the periods H2_8, H2_16, and H2_24, using the held charges, the bit strings X0_8<7:0>, X0_16<7:0>, and X0_24<7:0> are sequentially determined from the most significant bit to the least significant bit.

[0134] (b-2) Determination process With reference to FIGS. 9 to 17, the determination process of the determination processing circuit 900 in the operation example of the semiconductor integrated circuit 22 of the present embodiment will be described. Here, the determination process for an 8-bit bit string (data) X0_j will be described. In this case, the value of "m" in FIG. 5 is 8.

[0135] (b-2-1) Example 1 FIG. 9 is a timing chart showing Example 1 of the determination process of the determination processing circuit 900 in the operation example of the semiconductor integrated circuit 22 of the present embodiment. The horizontal axis in FIG. 9 corresponds to time. The vertical axis in FIG. 9 corresponds to the signal level of each signal.

[0136] <Time t0> At time t0 in FIG. 9, the TI-ADC circuit 20 starts the SAR operation by SAR-ADC22_j. Here, as an example, "j" is set to 0. Note that the "H" level corresponds to the value "1", and the "L" level corresponds to the value "0".

[0137] When x = 0, the OR gate 910 in FIG. 5 generates the signal CK2_SUM_y by performing an OR operation on a plurality of signals CK2_0, CK2_8, CK2_16, CK2_24. The formed signal CK2_SUM_y is supplied to the state confirmation circuit 940. Thereby, each state confirmation circuit 940 can confirm whether the operation state of the determination of the target bit is in a metastable state based on the cycle of the signal CK2_SUM_y.

[0138] FIG. 10 is a schematic diagram for explaining the state of the determination processing circuit 900 during the determination processing of a bit string in the semiconductor integrated circuit 22 of the present embodiment. As shown in FIG. 10, each of the plurality of processing units PU of the output control circuit 950 receives a metastable state notification signal ACK1 regarding the corresponding bit and a determination end notification signal ACK2 regarding the corresponding bit.

[0139] At the start of the determination processing of the bit string X0_0 in the SAR operation, since each of the FSM 920 and the state confirmation circuit 940 does not detect the possibility of a metastable state in the determination of each bit, the metastable state notification signals ACK1<7>, …, ACK1<0> regarding each bit respectively have a signal level of "L". At the start of the determination processing of the bit string X0_0 in the SAR operation, the determination end notification signals ACK2<7>, …, ACK2<0> regarding each bit respectively have a signal level of "L".

[0140] At the start of the determination processing of the bit string X0_0 in the SAR operation, each of the plurality of determination result storage circuits 930 stores a value of "0" as an initial value.

[0141] The signal S1 is supplied to the processing unit PU<7> corresponding to the most significant bit which is the first stage of the determination processing as a reference signal for internal control of the output control circuit 950. When the SAR operation is executed, the signal S1 has a signal level of "L". According to the signal level of the signal S1, the value (signal level) of the provisional value set for each bit can be controlled.

[0142] In the processing unit PU<7>, the selector 951<7> selects one of the signal S1 and the signal from the determination result storage circuit 930<7> based on the determination end notification signal ACK2<7>. Based on the "L" level determination end notification signal ACK2<7>, the selector 951<7> selects the signal S1. The selector 951<7> outputs the "L" level signal. As a result, for the 8th bit, the value "0" of the initial setting value is set.

[0143] The AND gate 953<7> performs an AND operation on the determination end notification signal ACK2<7> and the signal from the determination result storage circuit 930<7>. The AND gate 953<7> outputs the result of the AND operation to the selector 954<7>. The AND gate 953<7> outputs an "L" level signal through the AND operation of the "L" level determination end notification signal ACK2<7> and the "L" level signal (initial value) from the determination result storage circuit 930<7>. When the signal level of the determination end notification signal ACK2 is the "L" level, the signal level of the signal output from the AND gate 953 becomes the "L" level regardless of the signal level of the signal of the determination result storage circuit 930.

[0144] The selector 954<7> receives the signal output from the AND gate 953 at the positive logic input node. The selector 954<7> receives the "L" level signal S1 at the negative logic input node. The signal level of the signal supplied to the negative logic input node is inverted. The selector 954<7> selects either the signal from the AND gate 953 or the signal S1 based on the metastable state notification signal ACK1.

[0145] The "L" level metastable state notification signal ACK1<7> is supplied to the selector 954<7>. The selector 954<7> selects the inverted signal of the signal S1 based on the "L" level metastable state notification signal ACK1<7>. The selector 954<7> outputs the inverted signal of the signal S1. An "H" level signal is output from the selector 954<7>.

[0146] In the output control circuit 950, the next-stage 7-bit processing unit PU<6> receives a signal at the "H" level from the selector 954<7> of the previous-stage processing unit PU<7>.

[0147] The signal at the "H" level is supplied to the first input node of the NOR gate 959<6> of the processing unit PU<6>. The metastable state notification signal ACK1<6> at the "L" level is supplied to the second input node of the NOR gate 959<6>.

[0148] The NOR gate 959<6> outputs a signal at the "L" level based on the NOR operation result of the signal at the "H" level and the metastable state notification signal ACK1<6> at the "L" level.

[0149] The signal at the "L" level is supplied from the NOR gate 959<6> to the second input node of the selector 951<6>. The signal from the determination result storage circuit 930<6> is supplied to the first input node of the selector 951<6>.

[0150] The selector 951<6> selects one of the signal from the NOR gate 959<6> and the signal from the determination result storage circuit 930<6> based on the determination end notification signal ACK2<6>. The determination end notification signal ACK2<6> is at the "L" level. Based on the determination end notification signal ACK2<6> at the "L" level, the selector 951<6> selects the signal from the NOR gate 959<6>. The signal at the "L" level is output from the selector 951<6>. Thus, for the 7th bit, the value of "0" of the initial setting value is set.

[0151] The AND gate 953<6> performs an AND operation on the determination end notification signal ACK2<6> and the signal from the determination result storage circuit 930<6>. The signal level of the determination end notification signal ACK2<6> is at the "L" level. Therefore, the result of the AND operation is at the "L" level. The AND gate 953<6> sends a signal at the "L" level to the selector 954<6>.

[0152] Selector 954<6> receives the "L" level signal from AND gate 953<6> at the positive logic input node. Selector 954<6> receives the "L" level signal from NOR gate 959<6> at the negative logic input node. Selector 954<6> selects the signal from NOR gate 959<6> based on the "L" level metastable notification signal ACK1<6>. The signal from NOR gate 959<6> is inverted by the input to the negative logic input node of selector 954<6>. Selector 954<6> sends a "H" level signal to the subsequent processing unit PU<5>.

[0153] Each of the processing units PU<5>, …, PU<0> for the 6th to 1st bits performs substantially the same operation as the operation of the processing unit PU<6> for the 7th bit. As a result, for each of the 6th to 1st bits, an initial setting value of "0" is set.

[0154] As a result, as shown in FIG. 9, at time t0, the output control circuit 950 outputs a digital value ADCOUT of "00000000", which is the initial setting value (hereinafter also referred to as the initial digital value).

[0155] <Time t1> FIG. 11 is a schematic diagram for explaining the operation state of the determination processing circuit 900 during the bit string determination processing in the semiconductor integrated circuit 22 of the present embodiment.

[0156] At time t1 in FIG. 9, the bit value of the 8th bit to be determined is determined based on the evaluation and determination by the comparison processing of the comparator 223_0. For example, the bit value of the 8th bit is "1".

[0157] As shown in FIG. 11, a signal DR<7> indicating the determination result of the 8th bit is supplied to the corresponding determination result storage circuit 930<7>. The determination result storage circuit 930<7> stores a bit value (determination value) of "1".

[0158] Based on the signals Qp, Qn from the comparator 223_0 and the signal RY (signal CKa) from the NOR gate 224_0, the FSM920 changes the signal level of the determination end notification signal ACK2<7> from the "L" level to the "H" level. The determination end notification signal ACK2<7> at the "H" level is supplied to the control node of the selector 951<7>. The signal levels of the determination end notification signals ACK2<6>, …, ACK2<0> regarding other bits are maintained at the "L" level.

[0159] Based on the determination end notification signal ACK2 at the "H" level, the selector 951<7> selects the signal from the determination result storage circuit 930<7>. As a result, the selector 951<7> outputs the "H" level signal corresponding to the "1" bit value in the determination result storage circuit 930.

[0160] The AND gate 953<7> performs an AND operation on the "H" level signal from the determination result storage circuit 930<7> and the determination end notification signal ACK2<7> at the "H" level. Based on the result of the AND operation, the AND gate 953<7> supplies the "H" level signal to the selector 954<7>. When the signal level of the determination end notification signal ACK2 is at the "H" level, the signal level of the signal output from the AND gate 953 has a value corresponding to the signal level of the signal from the determination result storage circuit 930.

[0161] When the determination of the bit value is completed without generating a metastable state like the 8th bit determination, the metastable state notification signal ACK1<7> maintains the signal level at the "L" level.

[0162] Based on the metastable state notification signal ACK1<7> at the "L" level, the selector 954<7> selects the signal S1. As a result, the selector 954<7> outputs the "H" level signal which is the inverted signal of the signal S1.

[0163] The signal output from the selector 954<7> is supplied to the NOR gate 959<6> of the subsequent processing unit PU<6>.

[0164] The bit to be determined changes from the 8th bit to the 7th bit of the bit string X0_0. The FSM920 recognizes that the bit to be determined is the 7th bit.

[0165] In the processing unit PU<6> for the 7th bit, the NOR gate 959<6> performs a NOR operation on the signal at the "H" level and the metastable state notification signal ACK1<6> at the "L" level. The NOR gate 959<6> outputs a signal at the "L" level.

[0166] The selector 951<6> selects the signal from the NOR gate 959<6> based on the determination end notification signal ACK2<6> at the "L" level. The selector 954<6> outputs a signal at the "L" level.

[0167] In this way, the output control circuit 950 outputs a bit value of "0" of the initial setting value for the 7th bit of the bit string.

[0168] Each of the processing units PU<5>, …, PU<0> from the 6th bit to the 1st bit operates substantially in the same manner as the operation of the processing unit PU<6> for the 7th bit.

[0169] As a result, the output control circuit 950 outputs a digital value ADCOUT of "10000000".

[0170] <Time t2a and time t2b> FIG. 12 is a schematic diagram for explaining the operating state of the determination processing circuit 900 during the determination processing of the bit string in the semiconductor integrated circuit 22 of the present embodiment.

[0171] During the SAR operation, the FSM920 supplies a signal indicating the state of the determination processing of the bit to be determined by the comparator 223_0 to the corresponding state confirmation circuit 940 based on the signals RY, Qn, and Qp.

[0172] The status confirmation circuit 940 latches the signal from the FSM920 at a timing synchronized with the rising edge of the signal CK2_SUM_y.

[0173] At each of the times t2a and t2b during the determination process of the 7th bit in FIG. 9, the rising edge of the clock of the signal CK2_SUM_y occurs. The period Tz from the rising edge of the first clock of the signal CK2_SUM_y at time t2a to the rising edge of the second clock of the signal CK2_SUM_y at time t2b corresponds to one cycle of the clock signal CK2_SUM_y.

[0174] At each of the times t2a and t2b, a signal indicating that the determination process of the 7th bit is in progress (a signal indicating that the determination process has not ended) is supplied from the FSM920 to the status confirmation circuit 940<6>.

[0175] If each signal respectively acquired in the status confirmation circuit 940 at a timing synchronized with two rising edges of the signal CK_SUM_y indicates that it is during the determination process in the period from the start time of the determination to a certain time during the determination process of the 7th bit, the value in the status confirmation circuit 940 changes to a value indicating a metastable state. Thereby, the status confirmation circuit 940 can confirm that the determination process regarding the 7th bit is in a metastable state.

[0176] For example, in the status confirmation circuit 940<m-1(=6)> of FIG. 6, the flip-flop 943a latches the "H" level signal from the FSM 920 at the timing of the first rising edge of the signal CK2_SUM_y at time t2a. At the timing of the second rising edge of the signal CK2_SUM_y at time t2b, the flip-flop 943a latches the "H" level signal from the FSM 920 and sends the internal "H" level signal to the flip-flop 944a. At the timing of the second rising edge of time t2b, the flip-flop 944a latches the "H" level signal from the flip-flop 943a. The AND gate 946a outputs an "H" level signal to the OR gate 947a based on the result of the AND operation on the "H" level signals from each of the flip-flops 943a and 944a. The OR gate 947a outputs an "H" level signal ACK1<m-1(=6)> based on the result of the OR operation using the "H" level signal from the AND gate 946a.

[0177] As a result, the signal level of the metastable state notification signal ACK1<6> changes from the "L" level to the "H" level. The status confirmation circuit 940 outputs a metastable state notification signal ACK1<6> having an "H" level signal level.

[0178] At time t2b, as shown in FIG. 12, the NOR gate 959<6> receives the "H" level metastable state notification signal ACK1<6>. The NOR gate 959<6> receives an "H" level signal from the selector 954<7> of the previous processing unit PU<7>. Therefore, the NOR gate 959<6> outputs an "L" level signal based on the result of the NOR operation using the two "H" level signals.

[0179] The "L" level determination end notification signal ACK2<6> is supplied to the control node of the selector 951<6>.

[0180] Selector 951<6> selects the signal from NOR gate 959<6> based on the "L"-level determination end notification signal ACK2<6>. As a result, selector 951<6> outputs the "L"-level signal from NOR gate 959<6>. The "L"-level signal output from selector 951<6> includes the temporary value V1 set at the 7th bit. Thus, the signal output from selector 951<6> is changed from the signal including the initial setting value to the signal including the temporary value V1.

[0181] AND gate 953<6> performs an AND operation on the "L"-level signal of the determination result storage circuit 930<6> and the "L"-level determination end notification signal ACK2<6>. Based on the result of the AND operation, AND gate 953<6> supplies the "L"-level signal to the positive-logic input node of selector 954<6>.

[0182] NOR gate 959<6> supplies the "L"-level signal to the negative-logic input node of selector 954<6>.

[0183] Selector 954<6> selects the signal from AND gate 953<6> based on the "H"-level metastable table notification signal ACK1<6>. As a result, selector 954<6> outputs the "L"-level signal from AND gate 953<6>.

[0184] The "L"-level signal from selector 954<6> is supplied to NOR gate 959<5> of the subsequent processing unit PU<5>.

[0185] In the 6th-bit processing unit PU<5>, NOR gate 959<5> receives the "L"-level signal from the 7th-bit processing unit PU<6> and the "L"-level metastable table notification signal ACK1<5>. NOR gate 959<5> outputs a "H"-level signal through NOR operation.

[0186] Selector 951<5> selects the signal from NOR gate 959<5> based on the "L" level determination end notification signal ACK2<5>. Selector 951<5> outputs a signal at the "H" level. The signal at the "H" level output from selector 951<5> includes the temporary value V2a set at the 6th bit.

[0187] Selector 954<5> selects the signal from NOR gate 959<5> based on the "L" level metastable state notification signal ACK1<5>. As a result, selector 954<6> outputs a signal at the "L" level, which is the inverted signal of the signal from NOR gate 959<5>.

[0188] Each of the processing units PU<4>, …, PU<0> from the 5th bit to the 1st bit operates substantially the same as the operation of the 6th bit processing unit PU<5>. Each of the processing units PU<4>, …, PU<0> from the 5th bit to the 1st bit outputs a signal at the "H" level. The signals output from each of the processing units PU<4>, …, PU<0> include the temporary value V2a.

[0189] As a result, the output control circuit 950 outputs a digital value ADCOUT of "10111111". The value of "0111111" other than the most significant bit in the output digital value ADCOUT is the temporary value V.

[0190] In this way, if the determination of the value of the bit to be determined is not completed even after a period of one cycle (period Tz) or more of the signal CK2_SUM_y has elapsed during the determination period of a certain bit, the temporary value V1 is set as the value of the bit to be determined. In conjunction with the setting of the temporary value for the bit to be determined, the temporary value V2a is set for the bits lower than the bit to be determined. When the temporary value is a digital value including a plurality of bits, the values V2a of one or more lower bits within the temporary value are different from the value V2 of the most significant bit of the temporary value. For example, in a temporary value including a plurality of bits, the most significant bit of the temporary value is set to the value of "0". One or more bits after the second bit of this temporary value are set to the value of "1".

[0191] <Time t3a> FIG. 13 is a schematic diagram for explaining the operation state of the determination processing circuit 900 during the determination processing of the bit string in the semiconductor integrated circuit 22 of the present embodiment.

[0192] At time t3a in FIG. 9, the bit value of the 7th bit to be determined is determined. For example, the bit value of the 7th bit is "1". The FSM 920 detects the end of the determination of the 7th bit based on the signals Qp and Qn from the comparator 223_0 and the signal RY (signal CKa) from the NOR gate 224_0.

[0193] As shown in FIG. 13, the determination result DR<6> of "1" is supplied to the corresponding determination result storage circuit 930<6>. The determination result storage circuit 930<6> stores the bit value of "1".

[0194] The signal level of the determination end notification signal ACK2<6> changes from the "L" level to the "H" level. The "H" level determination end notification signal ACK2<6> is supplied to the control node of the selector 951<6>.

[0195] The selector 951<6> selects the signal from the determination result storage circuit 930<6> based on the "H" level determination end notification signal ACK2<6>. As a result, the selector 951<6> outputs an "H" level signal corresponding to the "1" bit value from the determination result storage circuit 930<6>.

[0196] In this way, in the processing unit PU<6> of the 7th bit, the signal output from the selector 951<6> changes from an "L" level signal to an "H" level signal.

[0197] The AND gate 953<6> performs an AND operation on the "H" level signal from the determination result storage circuit 930<6> and the "H" level determination end notification signal ACK2<6>. The AND gate 953<6> supplies an "H" level signal to the selector 954<6> based on the result of the AND operation.

[0198] Selector 954<6> receives the "H" level signal from AND gate 953<6> at the positive logic input node. Selector 954<6> receives the "L" level signal from NOR gate 959<6> at the negative logic input node.

[0199] Even when the determination of the 7th bit value is completed, the signal level of the metastable state notification signal ACK1<6> regarding the 7th bit processing unit PU<6> is maintained at the "H" level.

[0200] For example, in the state confirmation circuit 940 of FIG. 6, even if the signal level of the signal supplied from the FSM 920 is set to the "L" level by the completion of the determination of the corresponding bit when it is confirmed that the determination state of the corresponding bit is in the metastable state, the flip-flop 945a continues to store the "H" level signal. Therefore, even when the determination of the corresponding bit is completed, the "H" level metastable state notification signal ACK1 <m-1>is output from the OR gate 947a.

[0201] That is, as shown in FIG. 13, the selector 954<6> selects the inverted signal of the signal from the AND gate 953<6> based on the "H" level metastable table notification signal ACK1<6>. As a result, the selector 954<6> outputs an "H" level signal.

[0202] The "H" level signal from the selector 954<6> is supplied to the NOR gate 959<5> of the subsequent processing unit PU<5>.

[0203] The bit to be determined in the bit string X0_0 changes from the 7th bit to the 6th bit. The FSM 920 recognizes that the bit to be determined is the 6th bit.

[0204] In the processing unit PU<5> regarding the 6th bit, the NOR gate 959<5> performs a NOR operation on the "H" level signal and the "L" level metastable table notification signal ACK1<5>. The NOR gate 959<5> outputs an "L" level signal.

[0205] The selector 951<5> selects the signal from the NOR gate 959<5> based on the "L" level determination end notification signal ACK2<5>. The selector 951<5> outputs an "L" level signal. In this way, in response to the change from "0" to "1" in the 7th bit value where the determination has ended, the temporary value V2b set in the 6th bit changes from "1" to "0".

[0206] Regarding the 6th bit of the bit string, the determination result storage circuit 930<5> stores a value of "0" as the initial value before the determination of the 6th bit ends. The determination result storage circuit 930<5> outputs an "L" level signal.

[0207] The AND gate 953<5> outputs an "L" level signal based on the result of the AND operation between the "L" level signal from the determination result storage circuit 930<5> and the "L" level determination end notification signal ACK2<5>.

[0208] The selector 954<5> selects the signal from the NOR gate 959<5> based on the "L" level metastable state notification signal ACK1<5>. The selector 954<5> sends the "H" level signal to the subsequent processing unit PU<4>.

[0209] Each of the processing units PU<4>, …, PU<0> from the 5th bit to the 1st bit outputs an "L" level signal corresponding to the bit value of "0" from the selector 951 based on the "H" level signal from the NOR gate 959 of the previous processing unit PU, the "L" level metastable state notification signal ACK1, and the "L" level determination end notification signal ACK2.

[0210] As a result, the output control circuit 950 outputs a digital value ADCOUT of "11000000" including temporary values from the 6th bit to the 1st bit. The bit value of the 7th bit changes from the temporary value V1 of "0" to the value of "1" according to the determination result DR<6>. The temporary values V2b of each bit from the 6th bit to the 1st bit change from "1" to "0".

[0211] In this way, according to the bit value determined by the end of the determination of a certain bit in the metastable state, the value of the temporary value set for the bits lower than a certain bit in the metastable state is changed.

[0212] <Time t4a> FIG. 14 is a schematic diagram for explaining the operation state of the determination processing circuit 900 during the determination processing of the bit string in the semiconductor integrated circuit 22 of the present embodiment.

[0213] At time t4a in FIG. 9, the determination of the bit value of the sixth bit ends without the occurrence of a metastable state. The FSM 920 detects the end of the determination of the sixth bit according to the signals Qp, Qn, and the signal RY (signal CKa).

[0214] As shown in FIG. 14, for example, when the determined bit value of the sixth bit is "0", the determination result DR<5> of "0" is stored in the determination result storage circuit 930<5> related to the sixth bit.

[0215] The signal level of the determination end notification signal ACK2<5> related to the sixth bit changes from the "L" level to the "H" level.

[0216] Based on the "H" level determination end notification signal ACK2<5>, the selector 951<5> outputs a signal having a signal level corresponding to the value in the determination result storage circuit 930<5>. A signal of the "L" level is output from the selector 951<5>.

[0217] In response to the end of the bit determination of the sixth bit, a signal of the "L" level corresponding to the determination result is supplied from the determination result storage circuit 930<5> to the AND gate 953<5>.

[0218] The AND gate 953<5> supplies a signal of the "L" level to the selector 954<5> based on the result of the AND operation between the signal of the "L" level from the determination result storage circuit 930<5> and the "H" level determination end notification signal ACK2.

[0219] The NOR gate 959<5> outputs a signal of the "L" level by performing a NOR operation on the "H" level signal and the "L" level metastable state notification signal ACK1<5>.

[0220] The selector 954<5> selects the inverted signal of the signal from the NOR gate 959<5> based on the "L" level metastable state notification signal ACK1<5>. The selector 954<5> sends a signal of the "H" level to the processing unit PU<4> of the fifth bit.

[0221] In the fifth-bit processing unit PU<4>, the NOR gate 959<4> receives a signal at the "H" level from the sixth-bit processing unit PU<5>. The NOR gate 959<4> outputs a signal at the "L" level through a NOR operation on the "H" level signal and the "L" level metastable state notification signal ACK1<4>.

[0222] The selector 951<4> selects a signal from the NOR gate 959<4> based on the "L" level determination end notification signal ACK2<4>. Thereby, the selector 951<4> outputs a signal at the "L" level from the NOR gate 959<4>.

[0223] The AND gate 953<4> and the selector 954<4> receive and output the same signals as the AND gate 953<5> and the selector 954<5> of the sixth-bit processing unit PU<5>. That is, the selector 954<4> outputs a signal at the "H" level. Thereby, a signal at the "H" level is supplied to the NOR gate 959<3> of the subsequent fourth-bit processing unit PU<3>.

[0224] Each of the fourth-bit to first-bit processing units PU<3>, …, PU<0> operates based on the "H" level signal from the previous-stage processing unit PU, the "L" level metastable state notification signal ACK1, and the "L" level determination end notification signal ACK2. Thereby, the output control circuit 950 outputs a digital value ADCOUT of "11000000" including a temporary value from the fifth-bit to the first-bit.

[0225] After that, in each of the processing units PU<3>, …, PU<0>, when the bit determination state does not become a metastable state, the processing unit PU corresponding to the bit to be determined outputs a signal corresponding to the value in the determination result storage circuit 930, substantially in the same manner as the operation of the sixth-bit processing unit PU<5> in FIGS. 13 and 14.

[0226] In each of the processing units PU<3>, …, PU<0>, when the state during the determination of the bit value becomes the metastable state, the processing unit PU corresponding to the bit to be determined temporarily sets a provisional value to the corresponding bit in the same manner as the operation of the seventh-bit processing unit PU<6> in FIG. 12.

[0227] <At times t5 and t6> As shown in FIG. 9, at time t5, the signal level of signal CK2_0 changes from the "L" level to the "H" level. Synchronized with the rising edge of signal CK2_0, the SAR operation of SAR-ADC22_0 ends. As a result, the digital value of the bit string output from the output control circuit 950 is fixed. The output control circuit 950 outputs the bit string including the fixed digital value to a plurality of subsequent flip-flops 991<7>, …, 991<0>.

[0228] For example, flip-flops 943a, 944a, and 945a in the state confirmation circuit 940 are set to the reset state at the timing corresponding to the rising edge of signal CK2_0.

[0229] At time t6, the signal level of signal CK2_0 changes from the "H" level to the "L" level.

[0230] Each of flip-flops 991<7>, …, <0> receives the falling edge of signal CK2_0 at the negative logic clock node. Each of flip-flops 991<7>, …, 991<0> latches the signal output from the corresponding processing units PU<7>, …, PU<0> of the output control circuit 950 based on the timing corresponding to the transition of the signal level of signal CK2_0 from the "H" level to the "L" level.

[0231] As a result, the digital value of the bit string obtained by the SAR operation is stored in flip-flop 991.

[0232] The digital value stored in the flip-flop 991 is supplied to the subsequent DSP circuit 40 as the bit string (data) X0_0 obtained by the SAR operation.

[0233] If the determination of one or more bit values on the least significant bit side among the plurality of bits included in the bit string has not been completed within the period of the SAR operation based on the cycle of the signal CK2_0, the output control circuit 950 outputs an 8-bit bit string including a provisional value to the bit for which the bit determination has not been completed to the flip-flop 991. As a result, the bit value for which the determination has not been completed is stored in the flip-flop 991 in a state where it is set to the provisional value.

[0234] For example, during the above-described SAR operation, if the bit determination has been completed only for the 8th bit to the 2nd bit in the bit string X0_0, the value of the least significant 1st bit is a provisional value set according to the determination process of the upper bits.

[0235] Thus, in the present embodiment, when all the evaluations and determinations of the plurality of bits included in the bit string by the SAR operation have not been completed, the determination processing circuit 900 outputs a digital value including a provisional value as the value of the bit string to be determined.

[0236] (b-2-2) Example 2 Referring to FIGS. 15 to 17, another example of the operation example of the semiconductor integrated circuit 22 of the present embodiment will be described.

[0237] FIG. 15 is a timing chart for explaining Example 2 of the operation example of the semiconductor integrated circuit of the present embodiment.

[0238] <At times t0, t1> As shown in FIG. 15, at time t0, similar to the example of FIG. 9, the SAR-ADC22_j starts the SAR operation in response to the falling edge of the signal CK2_j.

[0239] At time t1, in the 8th bit processing unit PU<7>, similar to the operation of FIG. 10 described above, the 8th bit value in the bit string is determined.

[0240] After that, in the 7th bit processing unit PU<6>, the process related to setting the 7th bit value is executed.

[0241] <At times t2a, t2b> At each of times t2a and t2b during the determination period of the 7th bit value, a rising edge of the signal CK2_SUM_y occurs. As a result, the corresponding state confirmation circuit 940<6> confirms that the state of the 7th bit determination is in the metastable state.

[0242] In this case, in the 7th bit processing unit PU<6>, similar to the operation of the processing unit PU<6> in FIG. 11 described above, a value of "0" is set as a temporary value to the 7th bit value. In each of the 6th bit to 1st bit processing units PU<5>,..., PU<0>, a value of "1" is set as a temporary value to each of the 6th bit to 1st bit values.

[0243] As a result, the output control circuit 950 outputs a bit string including the digital value ADCOUT of "10111111".

[0244] <At time t3b> FIG. 16 is a schematic diagram for explaining the operation state of the determination processing circuit 900 during the determination processing of the bit string in the semiconductor integrated circuit 22 of the present embodiment.

[0245] After setting the temporary value for the digital value, based on the bit determination by the comparison process of the comparator 223_j, it is determined that the 7th bit value is "0". The determination result DR<6> of "0" is supplied to the determination result storage circuit 930<6>. As a result, the determination result storage circuit 930<6> stores the value of "0".

[0246] According to the signals Qp, Qn from the comparator 223_j and the signal RY (signal CKa) from the NOR gate 224_j, the FSM920 changes the signal level of the determination completion notification signal ACK2<6> regarding the 7th bit from the "L" level to the "H" level.

[0247] Based on the "H" level determination completion notification signal ACK2<6>, the selector 951<6> selects the signal from the determination result storage circuit 930<6>. The selector 951<6> outputs a "L" level signal from the determination result storage circuit 930<6>.

[0248] As a result, when the determination result of the 7th bit value is "0", the 7th bit value is set to the same "0" as the provisional value.

[0249] Based on the result of the AND operation between the "H" level determination completion notification signal ACK2<6> and the "L" level signal, the AND gate 953<6> outputs a "L" level signal.

[0250] Based on the "H" level metastable state notification signal ACK1<6>, the selector 954<6> supplies the "L" level signal from the AND gate 953<6> to the NOR gate 959<5> of the subsequent processing unit PU<5>.

[0251] In the processing unit PU<5>, based on the result of the NOR operation by the "L" level signal and the "L" level metastable state notification signal ACK1<5>, the NOR gate 959<5> outputs a "H" level signal.

[0252] Based on the "L" level determination completion notification signal ACK2<5>, the selector 951<5> selects the signal from the NOR gate 959<5>. The selector 951<5> outputs a "H" level signal from the NOR gate 959<5>.

[0253] As a result, the provisional value of "1" is set to the value of the 6th bit of the bit string.

[0254] Selector 954<5> selects the signal from NOR gate 959<5> based on the "L" level metastable table notification signal ACK1<5>. Selector 954<5> outputs an "L" level signal, which is the inverted signal of the signal from NOR gate 959<5>, to the subsequent NOR gate 959<4>.

[0255] In the processing units PU<4>, …, PU<0> corresponding to each of the 5th bit to the 1st bit, a dummy value of "1" is set to the corresponding bit value by substantially the same operation as that of the processing unit PU<5>.

[0256] <Time t4b> After the bit value of the 7th bit is determined, the determination process of the bit value of the 6th bit is executed. For example, at time t4b, the bit value of the 6th bit is determined to be "0" without the occurrence of the metastable state.

[0257] FIG. 17 is a schematic diagram for explaining the operation state of the determination processing circuit 900 during the determination process of the bit string in the semiconductor integrated circuit 22 of the present embodiment. As shown in FIG. 17, the determination result storage circuit 930<5> stores a determination result DR<5> of "0".

[0258] Based on the signals Qp, Qn, and the signal RY (signal CKa), FSM 920 changes the signal level of the determination end notification signal ACK2<6> regarding the 6th bit from the "L" level to the "H" level.

[0259] Selector 951<5> selects the signal from the determination result storage circuit 930<5> based on the "H" level determination end notification signal ACK2<6>. Selector 951<6> outputs an "L" level signal.

[0260] AND gate 953<5> outputs an "L" level signal by performing an AND operation with the "H" level determination end notification signal ACK2<6> and the "L" level signal from the determination result storage circuit 930<5>.

[0261] The NOR gate 959<5> outputs a "H" level signal through a NOR operation with the "L" level signal from the previous processing unit PU<6> and the "L" level metastable state notification signal ACK1<5>.

[0262] The selector 954<5> selects the signal from the NOR gate 959<5> based on the "L" level metastable state notification signal ACK1<5>. The selector 954<5> outputs a "L" level signal, which is the inverted signal of the signal from the NOR gate 959<4>, to the NOR gate 959 of the subsequent processing unit PU.

[0263] In each of the subsequent processing units PU<4>, …, PU<0>, the selector 951 outputs the signal from the NOR gate 959 in the same manner as the above example.

[0264] As a result, at time t4b, the output control circuit 950 outputs a digital value ADCOUT of "10011111". The value "11111" from the 5th bit to the 1st bit among the 8-bit digital value is a temporary value.

[0265] After that, each processing unit PU<4>, …, PU<0> outputs a temporary value or a value of the determination result according to whether a metastable state occurs during the determination of the corresponding bit, substantially in the same manner as the above operation. As a result, during the period of the SAR operation, the values of each bit are sequentially set.

[0266] In this way, even if the determination result of the bit in which the metastable state has occurred is the same value as the set temporary value (here, "0"), the value corresponding to the operation of the processing unit PU is set for each corresponding bit according to the presence or absence of the occurrence of the metastable state.

[0267] If the bit value of the eighth bit is determined to be "0" without the occurrence of a metastable state, in the eighth-bit processing unit PU<7>, the selector 954<7> outputs a signal of "H" level, which is the inverted signal of signal S1, based on the "L" level metastable state notification signal ACK1<7> regardless of the value of the eighth-bit determination result DR<7>.

[0268] After that, in the seventh-bit processing unit PU<6>, if the state of the seventh-bit determination is determined to be a metastable state, the NOR gate 959<6> receives the "H" level metastable state notification signal ACK1<6>. The NOR gate 959<6> outputs a signal of "L" level through a NOR operation with the "H" level signal and the "H" level metastable state notification signal ACK1<6>.

[0269] The selector 951<6> outputs the "L" level signal from the NOR gate 959<6> based on the "L" level determination end notification signal ACK2<6>. The temporary value set for the seventh-bit bit in the metastable state is "0".

[0270] In this way, the temporary value set for the bit in the metastable state has a value of "0" regardless of the determination result of the upper bits.

[0271] When the eighth-bit bit determination becomes a metastable state, each processing unit PU operates as follows.

[0272] In the eighth-bit processing unit PU<7> in the metastable state, the selector 951<7> outputs the "L" level signal S1 as the temporary value of the eighth-bit bit value based on the "L" level determination end notification signal ACK2<7>. The AND gate 953<7> outputs a "L" level signal based on the result of an AND operation between the initial value ("0") of the determination result storage circuit 930<7> and the "L" level determination end notification signal ACK2<7>.

[0273] Selector 954<7> selects the "L"-level signal from AND gate 953<7> based on the "H"-level metastable table notification signal ACK1<7>. The "L"-level signal is supplied from selector 954<7> to NOR gate 959<6> of the subsequent processing unit PU<6>.

[0274] In the 7-bit processing unit PU<6>, NOR gate 959<6> outputs an "H"-level signal based on the NOR operation of the "L"-level signal from selector 954<7> and the "L"-level metastable table notification signal ACK1<6>.

[0275] Selector 951<6> outputs the "H"-level signal from NOR gate 959<6> based on the "L"-level determination end notification signal ACK2<6>.

[0276] Selector 954<6> outputs an "L"-level signal, which is the inverted signal of the signal from NOR gate 959<6>, based on the "L"-level metastable table notification signal ACK1<6>.

[0277] Each of the processing units PU<5>, …, PU<0> from the 6-bit to the 1-bit outputs the "H"-level signal from NOR gate 959 through selector 951 by substantially the same operation as that of the 7-bit processing unit PU<6>.

[0278] As a result, during the period until the determination of the 8-bit bit value is completed, output control circuit 950 outputs a digital value of "01111111", which is a provisional value. After that, during the period of the SAR operation, the value of each bit is sequentially set.

[0279] As described above, the determination processing circuit 900 of the semiconductor integrated circuit 22 of the present embodiment executes the determination processing of the bit string in the SAR operation.

[0280] (c) Summary A general SAR-ADC performs bit determination by comparing two differential input signals using a comparator. When the differential input signal to the comparator is small, the time for bit determination by the comparator's comparison process increases exponentially.

[0281] When the SAR-ADC is an asynchronous operation type SAR-ADC, if the determination of a certain bit in the bit sequence is not completed, the determination of the next bit is not shifted. Therefore, if the determination of all bits in the bit sequence is not completed, the value of the lower bits is maintained at the initial value.

[0282] When a long period occurs for the determination of a certain bit during the determination process of the bit sequence in the semiconductor integrated circuit 22 of the present embodiment, a temporary value is set for that bit and the bits lower than that bit.

[0283] For example, during the determination period of a certain bit in the bit sequence, if two rising edges occur in the clock signal CK2_SUM_y that serves as a reference for measuring the bit determination period (when one cycle period Tz of the clock signal CK2_SUM_y has elapsed), the semiconductor integrated circuit 22 of the present embodiment regards the ongoing bit determination as being in a metastable state. In this way, the semiconductor integrated circuit 22 of the present embodiment detects which bit determination has taken a long time.

[0284] The semiconductor integrated circuit 22 of the present embodiment sets a temporary value having a first value for the bit corresponding to the bit determination regarded as the metastable state. Further, the semiconductor integrated circuit of the present embodiment sets a temporary value of a second value different from the first value for one or more bits lower than the bit of the temporary value of the first value.

[0285] The semiconductor integrated circuit 22 of the present embodiment continues the determination process for the bit regarded as the metastable state with the temporary value set in the bit sequence. The semiconductor integrated circuit 22 of the present embodiment re-sets a value corresponding to the bit determination result for the bit of the set temporary value.

[0286] As described above, even if a long determination time occurs for a specific bit in the semiconductor integrated circuit 22 of this embodiment, a provisional value more suitable than that bit can be set for the bits lower than that bit according to the value of that bit.

[0287] As described above, the semiconductor integrated circuit 22 of this embodiment designates an assumed provisional value starting from a bit for which a long time is required for bit determination.

[0288] As a result, even if not all bit determinations are completed within a predetermined period of the SAR operation, the semiconductor integrated circuit 22 of this embodiment can obtain a bit string including a digital value close to the original analog value supplied to the SAR-ADC.

[0289] As a result, the semiconductor integrated circuit and the receiving device of this embodiment can generate a more suitable digital signal based on the analog signal.

[0290] (2) Second Embodiment With reference to FIGS. 18 and 19, the semiconductor integrated circuit of the second embodiment will be described.

[0291] Depending on the time of the rising edge of the clock, even if one or more cycles of the signal CK2_SUM_y have elapsed during the determination of a certain bit, it is possible to confirm that the state of the bit determination is not in a metastable state.

[0292] In the semiconductor integrated circuit 22 of this embodiment, the determination processing circuit 900 of the control logic circuit 225_j uses the falling edge of the clock of the signal CK2_SUM_y in addition to the rising edge of the clock of the signal CK2_SUM_y to confirm whether the state of the bit determination is in a metastable state.

[0293] FIG. 18 is a block diagram showing the internal configuration of the state confirmation circuit 940Z of the determination processing circuit 900 in the semiconductor integrated circuit 22 of this embodiment.

[0294] As shown in FIG. 18, the state confirmation circuit 940Z <m-1>includes two circuit blocks BK1 and BK2, an OR gate 948, and a delay element 949.

[0295] The circuit block BK1 is the state confirmation circuit 940 of FIG. 6 <m-1>It has substantially the same configuration as the internal configuration. Circuit block BK1 includes a NAND gate 941a, a delay element 942a, a plurality of flip-flops 943a, 944a, 945a, an AND gate 946a, and an OR gate 947a.

[0296] The input node of flip-flop 943a receives a signal indicating the operation state of the bit determination from FSM920. The output node of flip-flop 943a is connected to the input node of flip-flop 944a and the first input node of AND gate 946a. The output node of flip-flop 944a is connected to the second input node of AND gate 946a. The output node of AND gate 946a is connected to the first input node of OR gate 947a. The second input node of OR gate 947a is connected to the output node of flip-flop 945a. The input node of flip-flop 945a is connected to the output node of OR gate 947a.

[0297] Circuit block BK2 includes a plurality of flip-flops 943b, 944b, 945b, an AND gate 946b, and an OR gate 947b.

[0298] The input node of flip-flop 943b receives a signal indicating the operation state of the bit determination of FSM920. The output node of flip-flop 943b is connected to the input node of flip-flop 944b and the first input node of AND gate 946b. The output node of flip-flop 944b is connected to the second input node of AND gate 946b. The output node of AND gate 946b is connected to the first input node of OR gate 947b. The second input node of OR gate 947b is connected to the output node of flip-flop 945b. The input node of flip-flop 945b is connected to the output node of OR gate 947b.

[0299] The first input node of the OR gate 948 is connected to the output node of the OR gate 947a. The second input node of the OR gate 948 is connected to the output node of the OR gate 947b. The output node of the OR gate 948 outputs the result of the OR operation between the signal from the circuit block BK1 and the signal from the circuit block BK2. The signal output from the OR gate 948 is the metastable notification signal ACK1 <m-1>It is.

[0300] The output node of the delay element 949 is connected to the clock nodes of each of the flip - flops 943b, 944b, 945b within the circuit block BK2. The input node of the delay element 949 receives the signal CK2_SUM_y. The delay element 949 delays the cycle of the signal CK2_SUM_y by half a cycle.

[0301] Each of the plurality of flip - flops 943a, 944a, 945a within the circuit block BK1 receives the signal CK2_SUM_y at the clock node. Each of the flip - flops 943a, 944a, 945a operates in synchronization with the rising edge of the signal CK2_SUM_y.

[0302] Each of the plurality of flip - flops 943b, 944b, 945b within the circuit block BK2 receives the signal CK2_SUM_y at the clock node via the delay element 949. Each of the flip - flops 943b, 944b, 945b operates in synchronization with the rising edge of the delayed signal of CK2_SUM_y. For example, each of the flip - flops 943b, 944b, 945b latches the supplied signal at a timing that is half a cycle later than that of the flip - flops 943a, 944a, 945a. That is, each of the flip - flops 943b, 944b, 945b operates at a timing corresponding to the falling edge of the signal CK2_SUM_y.

[0303] The reset nodes of each of the plurality of flip - flops 943b, 944b, 945b are connected to the output node of the NAND gate 941a. The plurality of flip - flops 943b, 944b, 945b are set to the reset state at the same timing as the reset of the plurality of flip - flops 943a, 944a, 945a in response to the signal from the NAND gate 941a.

[0304] The state confirmation circuit 940Z in FIG. 18 <m-1>In this case, as in the above-described embodiment, when two rising edges of the signal CK2_SUM_y are detected during the period of determining a certain bit, the state confirmation circuit 940Z <m-1>Outputs a metastable notification signal ACK1 at the "H" level by the operation of circuit block BK1.

[0305] FIG. 19 is a timing chart for explaining an operation example of the determination processing circuit 900 in the semiconductor integrated circuit 22 of the present embodiment.

[0306] As shown in FIG. 19, at time t2z during the period of the 7-bit determination processing, the signal CK2_SUM_y generates one rising edge. During the 7-bit determination period, at times t2c and t2d respectively, the signal CK2_SUM_y generates two falling edges. The period Tz from time t2c to time t2d corresponds to one cycle period of the signal CK2_SUM_y.

[0307] State confirmation circuit 940Z <m-1>In this case, circuit block BK2 latches the signal from FSM920 at the timing of each falling edge of signal CK2_SUM_y twice.

[0308] If two falling edges are detected during the period of determining a certain bit, state confirmation circuit 940Z <m-1>Outputs a metastable notification signal ACK1 at the "H" level by the operation of circuit block BK2.

[0309] Therefore, during a certain bit determination period, when two rising edges of signal CK2_SUM_y are detected or two falling edges of signal CK2_SUM_y are detected, the status confirmation circuit 940Z <m-1>It supplies the output control circuit 950 with the "H"-level metastable table notification signal ACK1.

[0310] In this way, when the bit determination does not end even after the period Tz of one cycle of the signal CK2_SUM_y has elapsed, the determination processing circuit 900 can confirm the possibility of the metastable state in the bit determination by both the rising edge and the falling edge of the clock.

[0311] In the semiconductor integrated circuit 22 of the present embodiment, the determination processing circuit 900 can detect that the bit determination is in the metastable state in a relatively short period.

[0312] Therefore, the semiconductor integrated circuit and the receiving device of the present embodiment can obtain a more suitable digital signal from the analog signal.

[0313] (3) Application examples With reference to FIG. 20, application examples of the semiconductor integrated circuit of the embodiment will be described.

[0314] As shown in FIG. 20, the semiconductor integrated circuit 22 and the receiving devices 4 (4a, 4b) of the embodiment are applied to the information communication system 1000.

[0315] As shown in FIG. 20, the information communication system 1000 includes a host device 1100 and a memory system 1200. The memory system 1200 writes, reads, and erases data in the memory system 1200 based on requests from the host device 1100. The internal configuration of the memory system 1200 will be described later.

[0316] The host device 1100 includes a processor 1101, a RAM 1102, and an interface circuit 1103.

[0317] The processor (hereinafter also referred to as the host processor) 1101 controls various processes and operations of the host device 1100. The host processor 1101 can issue commands (hereinafter referred to as host commands) for requesting (instructions, directives) various processes and operations for the memory system 1200. The host processor 1101 can generate data corresponding to the host commands. The generated data is information used for the processes and operations of the memory system 1200. The generated data is, for example, an address, a parameter, and data to be written to the memory system 1200.

[0318] The RAM 1102 functions as a work area for various data processes by the host processor 1101. The RAM 1102 temporarily stores programs and data used for various processes by the host processor 1101.

[0319] The interface circuit (also referred to as the host interface (host I / F) circuit) 1103 communicates with the memory system 1200 based on a certain interface standard and / or communication protocol. The interface circuit 1103 has a transmission device 2a for data transmission and a reception device 4a for data reception within the physical layer (PHY layer). The reception device 4a includes the semiconductor integrated circuit 22 of the present embodiment.

[0320] Note that the host commands for the memory system 1200 are based on the interface standard of the interface circuit 1103. For example, the interface standard (or communication protocol) used for the interface circuit 1103 is the SAS standard, the SATA standard, the PCI Express TM standard (hereinafter referred to as the PCIe standard), the NVM Express TM It is selected from among standards such as the NVMe standard (hereinafter referred to as the NVMe standard) and the M-PHY standard applied to UFS (Universal Flash Storage) devices. Note that an interface standard compliant with any of these standards or another interface standard may be used for the interface circuit 1203.

[0321] In addition to the above configuration, the host device 1100 may further include a storage device (not shown) such as an HDD (Hard Disc Drive).

[0322] For example, the host device 1100 or the information communication system 1000 is a personal computer, a smartphone, a feature phone, a portable terminal (e.g., a tablet terminal), a game device, an in-vehicle terminal, a router, a base station, or the like.

[0323] The memory system 1200 includes a memory controller 1210 and a NAND flash memory (hereinafter referred to as a flash memory) 1220.

[0324] Based on requests from the host device 1100, the memory controller 1210 instructs (commands) the flash memory 1220 to perform various processes and operations such as data writing, data reading, and data erasure.

[0325] The memory controller 1210 includes a processor 1211, a RAM 1212, a buffer circuit 1213, and interface circuits 1214, 1215.

[0326] The processor 1211 can instruct various processes or operations on the flash memory 1220. For example, the processor 1211 can generate a command (hereinafter also referred to as a controller command) indicating an instruction to the flash memory 1220.

[0327] RAM 1212 functions as a working area for various processes and operations of the processor 1211 within the memory controller 1210. RAM 1212 temporarily stores programs and data (results of calculation processes, data and parameters during calculation processes, etc.) used for various processes by the processor 1211. Note that RAM 1212 may be a memory area provided within the processor 1211.

[0328] The buffer circuit 1213 temporarily stores data transferred between the memory controller 1210 and the host device 1100, and data transferred between the memory controller 1210 and the flash memory 1220.

[0329] The interface circuit (also called the host interface (host I / F) circuit) 1214 performs data transfer between the host device 1100 and the memory controller 1210 based on a certain interface standard. The interface standard and communication protocol of the interface circuit 1214 are the same standard (or a compliant standard) as the interface standard of the interface circuit 1103 of the host device 1100. For example, the interface circuit 1214 performs serial transmission communication with the interface circuit 1103.

[0330] The interface circuit (also called the memory interface (memory I / F) circuit) 1215 performs communication (e.g., data transfer) between the memory controller 1210 and the flash memory 1220 based on the NAND interface standard. The interface circuit 1215 performs, for example, parallel transmission communication with the flash memory 1220. The interface circuit 1215 includes a transmission device and a reception device within the physical layer (PHY layer).

[0331] When the memory controller 1210 instructs the flash memory 1220 to perform an operation, the memory controller 1210 sends a data group including a command and an address (hereinafter also referred to as a memory command set) to the flash memory 1220. When the memory controller 1210 instructs the flash memory 1220 to write data, the memory command set further includes the write data.

[0332] In addition to the above configuration, the memory controller 1210 may include other configurations such as an ECC circuit (not shown) for detecting and correcting errors in the data.

[0333] The flash memory 1220 is a non-volatile semiconductor memory device. The flash memory 1220 can store data substantially non-volatily. The flash memory 1220 writes the data sent from the memory controller 1210 into a memory cell array (not shown). The flash memory 1220 reads out the data requested by the memory controller 1210 from the memory cell array.

[0334] The flash memory 1220 communicates with the memory controller 1210. The communication between the flash memory 1220 and the memory controller 1210 is supported by the NAND interface standard.

[0335] For example, the memory system 1200 is an SSD (Solid State Drive), a UFS (Universal Flash Storage) device, a memory card, or a USB (Universal Serial Bus) memory, etc. Instead of the flash memory 1220, other non-volatile or volatile memory devices may be used in the memory system 1200.

[0336] For example, in the memory system 1200, the interface circuit 1214 of the memory controller 1210 includes a transmission device 2b and a reception device 4b within the physical layer (PHY layer). The reception device 4b includes the semiconductor integrated circuit 22 of the embodiment.

[0337] Regarding the communication (signal transmission) between the host device 1100 and the memory system 1200, the transmission device 2b of the interface circuit 1214 sends various signals (e.g., data) to the reception device 4a of the interface circuit 1103. Regarding the communication between the host device 1100 and the memory system 1200, the reception device 4b of the interface circuit 1214 receives various signals from the transmission device 2a of the interface circuit 1103. For example, within the memory system 1200, the memory controller 1210 can perform various processes on the data from the reception device 4b.

[0338] For example, the transmission device 2b and the reception device 4b are used for relatively high-speed data transfer of 10 Gbps or more (e.g., data transfer of the 100 Gbps class).

[0339] Note that the semiconductor integrated circuit 22 of the embodiment and the reception device 4 of the embodiment may be used for the interface circuit 1215.

[0340] As described above, the semiconductor integrated circuit 22 of the embodiment and the reception device 4 of the embodiment are applied to the host device 1100 and the memory system 1200.

[0341] (4) Others Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope.

[0342] The semiconductor integrated circuit of the embodiment further includes the aspects of Supplementary Note 1 to Supplementary Note 6 below.

[0343] (Supplementary Note 1) The semiconductor integrated circuit includes a comparator that executes comparison processing of differential analog signals, and a control circuit configured to determine values of a plurality of bits based on a result of the comparison processing of the comparator and generate a digital signal including the determined values of the plurality of bits. The control circuit sets an initial value for a first bit to be determined among the plurality of bits, and if the determination of the first bit is not completed within a first period, sets a first temporary value having a first value for the first bit.

[0344] (Supplementary Note 2) In the semiconductor integrated circuit of Supplementary Note 1, the control circuit includes a second circuit configured to generate a periodic signal including an edge having periodicity, and a third circuit configured to confirm an operation state of the determination of the first bit based on the periodic signal.

[0345] (Supplementary Note 3) In the semiconductor integrated circuit of Supplementary Note 2, the first period is a period from a first rising edge of the periodic signal to a second rising edge.

[0346] (Supplementary Note 4) In the semiconductor integrated circuit of Supplementary Note 1, the control circuit includes a first processing circuit that outputs a value of the first bit. The first processing circuit receives a first state notification signal indicating whether the determination of the first bit is in a stalled state and a first end notification signal indicating whether the determination of the first bit has ended. When the first end notification signal indicates that the determination of the first bit has not ended, the first processing circuit outputs the first temporary value as the value of the first bit. When the first end notification signal indicates that the determination of the first bit has ended, the first processing circuit outputs the first determination value of the first bit as the value of the first bit.

[0347] (Supplementary Note 5) In the semiconductor integrated circuit of Supplementary Note 1, the control circuit includes a second processing circuit that outputs the value of a second bit lower than the first bit. When the first state notification signal indicates that the determination of the first bit is not in a stalled state, the first processing circuit outputs a first signal corresponding to the first provisional value to the second processing circuit. When the first state notification signal indicates that the determination of the first bit is in a stalled state, the first processing circuit outputs a second signal to the second processing circuit.

[0348] (Supplementary Note 6) In the semiconductor integrated circuit of Supplementary Note 5, the second signal includes a first value based on a first logical operation between the value of the first end notification signal and the value of the first bit.

Explanation of Signs

[0349] 1: Communication system, 4: Receiver, 20: Time-interleaved analog-to-digital converter circuit, 22_j: Successive approximation analog-to-digital converter, 225_j: Control logic circuit, 900: Determination processing circuit, 910: Clock generation circuit, 920: FSM, 930: Determination result storage circuit, 940: State confirmation circuit, 950: Output control circuit, PU: Processing unit. < / m>

Claims

1. A comparator that executes comparison processing of differential analog signals, a control circuit configured to determine values of a plurality of bits based on a result of the comparison processing of the comparator and generate a digital signal including the determined values of the plurality of bits, comprising: the control circuit: sets an initial value for a first bit to be determined among the plurality of bits, if the determination of the first bit is not completed within a first period, sets a first temporary value having a first value for the first bit, a semiconductor integrated circuit.

2. The control circuit sets a second temporary value having a second value different from the first value for a second bit lower than the first bit among the plurality of bits in response to the setting of the first temporary value. The semiconductor integrated circuit according to Claim 1.

3. The control circuit includes a first circuit configured to store a first determination value of the first bit determined based on the result of the comparison processing, when the determination of the first bit is completed, sets the first determination value for the first bit, The semiconductor integrated circuit according to Claim 1.

4. The control circuit includes a second circuit configured to generate a periodic signal including an edge having periodicity, and a third circuit configured to check an operation state of the determination of the first bit based on the periodic signal. The semiconductor integrated circuit according to Claim 1.

5. The first period is a period from a first rising edge of the periodic signal to a second rising edge, or a period from a first falling edge of the periodic signal to a second falling edge. The semiconductor integrated circuit according to Claim 4.

6. The control circuit includes a first processing circuit that outputs a value of the first bit, the first processing circuit: receives a first state notification signal indicating whether the determination of the first bit is in a stalled state and a first end notification signal indicating whether the determination of the first bit is completed, if the first end notification signal indicates that the determination of the first bit is not completed, outputs the first temporary value as the value of the first bit, if the first end notification signal indicates that the determination of the first bit is completed, outputs the first determination value of the first bit as the value of the first bit. The semiconductor integrated circuit according to Claim 1.

7. The control circuit includes a second processing circuit that outputs a value of a second bit lower than the first bit, the second processing circuit: Receiving a second status notification signal indicating whether the determination of the second bit is in a stalled state and a second end notification signal indicating whether the determination of the second bit has ended, When the first status notification signal indicates that the determination of the first bit is in a stalled state and the second end notification signal indicates that the determination of the second bit has not ended, receiving a second signal from the first processing circuit and outputting, as the value of the second bit, a second provisional value based on a result of a second logical operation between the value of the second signal and the value of the second status notification signal, When the second end notification signal indicates that the determination of the second bit has ended, outputting the second determination value of the second bit as the value of the second bit, The semiconductor integrated circuit according to claim 6.

8. A semiconductor integrated circuit according to any one of claims 1 to 7, An analog circuit that receives a differential signal and outputs an analog signal of the differential based on the received differential signal, A digital circuit that processes the digital signal generated by the semiconductor integrated circuit, A receiving apparatus comprising the same.

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