Semiconductor device and manufacturing method for the same

Abstract

To reduce the occurrence of poor segmenting by laser focusing modified dicing in a step of manufacturing a MEMS device having a bonding structure.SOLUTION: A piezoelectric element 40 has: a first semiconductor substrate 11 having a first bottom surface and a first top surface; a second semiconductor substrate 31 which has a second bottom surface 31a and a second top surface 31b, where the second bottom surface 31a is laminated to face the first top surface, and has first cleaved side surfaces 40a formed by cleaving a first modified region 31d by irradiation with a laser beam 102 in a range extending from the second bottom surface 31a to the second top surface 31b beyond a predetermine height in a height direction toward the second top surface; and first retreating side surfaces 40b which have adhesion layers 45 interposed between the first top surface and the second bottom surface 31a to bond the first semiconductor substrate 11 to the second semiconductor substrate 31, and are formed in a range extending in the height direction from the first bottom surface to the first cleaved side surfaces 40a so to retreat in a width direction more than the first cleaved side surfaces 40a.SELECTED DRAWING: Figure 1B

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] Conventionally, a technology of a micro electro mechanical system (MEMS) for fabricating a mechanical structure on a semiconductor substrate such as silicon using semiconductor manufacturing technology has been provided. In a MEMS device to which MEMS technology is applied, for example, there is a piezoelectric element in which a transducer that drives a diaphragm with a piezoelectric body and a subframe that forms a frame surrounding the diaphragm are each formed on a silicon substrate, and these are bonded so as to be laminated (see Patent Document 1). The piezoelectric element of the MEMS device may be fabricated using a silicon on insulator (SOI) wafer in which a buried layer composed of a buried oxide (BOX) layer and an active layer is formed on the surface of the silicon substrate (see Patent Document 2).

[0003] In the process of manufacturing a MEMS device, when a wafer is diced and separated into individual pieces using blade dicing commonly used in semiconductor manufacturing, the movable parts or functional parts of the MEMS device may be contaminated or damaged by cooling water and cleaning water. For this reason, for dicing in the manufacturing process of a MEMS device, dicing by laser beam focusing and modification, also referred to as stealth dicing, in which a laser beam is focused on a wafer to form a modified region and then an external force such as tape expansion is applied to cut, may be used (see Patent Document 3).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

[0005] [Summary] When dicing a wafer by laser beam focusing and modification during the manufacturing process of a MEMS device having a bonded structure like the piezoelectric element described above, if dicing by laser beam focusing and modification is applied, the laser beam may be attenuated by the adhesive or BOX layer used for bonding, resulting in defective dicing.

[0006] In view of the above circumstances, the present disclosure proposes a semiconductor device having a bonded structure and using MEMS technology, and a manufacturing method thereof, and aims to provide a semiconductor device and a manufacturing method thereof that reduce defective dicing due to an adhesive or a BOX layer in dicing by laser beam focusing and modification.

[0007] In order to solve the above problems, a semiconductor device according to the present disclosure includes a first substrate having a first bottom surface and a first top surface, and a second substrate having a second bottom surface and a second top surface, the second bottom surface being laminated so as to face the first top surface, and including a first cleavage side surface formed by cleaving a modified region formed by irradiating a laser beam in a range from the second bottom surface to the second top surface until reaching the second top surface beyond a predetermined height in the height direction from the second bottom surface to the second top surface. In a range from the first bottom surface in the height direction to the first cleavage side surface of the second substrate, a first retreat side surface formed so as to retreat in the width direction from the first cleavage side surface is included.

[0008] A manufacturing method of a semiconductor device according to the present disclosure includes a step of forming a first groove on a first top surface of a first substrate having a first bottom surface and a first top surface, a step of forming a second groove on a second bottom surface of a second substrate having a second bottom surface and a second top surface, a step of bonding and laminating the first substrate and the second substrate so that the first top surface and the second bottom surface face each other and the first groove and the second groove are connected to form a connection groove, a step of making the connection groove communicate with the first bottom surface in the laminate, a step of irradiating a laser beam along a direction in which the connection groove extends toward the second top surface to form a modified region in the laminate, and a step of dividing and dicing the laminate in the modified region.

[0009] Moreover, the method for manufacturing a semiconductor device according to the present disclosure includes a step of forming a first groove on a first top surface of a first substrate having a first bottom surface and a first top surface, a step of forming a second groove on a second bottom surface of a second substrate having a second bottom surface and a second top surface, a step of bonding the first substrate and the second substrate so that the first top surface and the second bottom surface face each other and the first groove and the second groove are connected to form a connection groove to constitute a laminate, a step of irradiating a laser beam along a direction in which the connection groove extends toward the second top surface to form a first modified region in the laminate, a step of irradiating a laser beam along a direction in which the connection groove extends toward the first bottom surface to form a second modified region in the laminate, and a step of dividing the laminate by the first modified region and the second modified region to individualize it.

Brief Description of the Drawings

[0010]

Figure 1A

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[0011] [Detailed Description] Hereinafter, the semiconductor device and its manufacturing method of the present disclosure will be described in detail with reference to the drawings for an example of a piezoelectric element. Needless to say, the semiconductor device and its manufacturing method of the present disclosure are applicable not only to piezoelectric elements but also to other types of semiconductor devices and their manufacturing methods.

[0012] The embodiments described below show comprehensive or specific examples. The numerical values, shapes, materials, components, installation positions, and connection forms of the components shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Among the components in the following embodiments, components not described in the independent claims indicating the highest-level concept are described as optional components. Furthermore, the dimensional ratios in the drawings are exaggerated for convenience of explanation and may differ from the actual ratios. In addition, the following embodiments and their modifications may include similar components, and the same reference numerals are assigned to the similar components, and duplicate explanations are omitted.

[0013] (Piezoelectric element) FIG. 1A is a plan view of the piezoelectric element 40 of the present embodiment. FIG. 1B is a cross-sectional view showing a cross-section of the piezoelectric element 40 shown in FIG. 1A cut along the cutting line IB-IB in the figure. The piezoelectric element 40 of the present embodiment is a MEMS using semiconductor manufacturing technology, and the top surface 10b of the first laminate 10 including the first semiconductor substrate 11 and the bottom surface 31a of the second semiconductor substrate 31 are bonded together by an adhesive layer 45. In the piezoelectric element 40, the first laminate 10 constitutes a transducer, and the second semiconductor substrate 31 constitutes a subframe.

[0014] The first laminate 10 is formed by laminating, in order, a first semiconductor substrate 11, a first insulating layer 12, a semiconductor layer 13, a second insulating layer 14, a first protective layer 15, a first metal layer 17, a piezoelectric layer 18, a second metal layer 19, and a second protective layer 16. On the bottom surface 10a of the first laminate 10, a first cavity 10c reaching the semiconductor layer 13 is formed so that the semiconductor layer 13 forms a vibrating membrane 10d. On the top surface 10b of the first laminate 10, a slit 10e reaching the first cavity 10c is formed around the vibrating membrane 10d leaving a fixed end so that the vibrating membrane 10d forms a rectangular cantilever structure in plan view. Also, electrode pads 25 that open the second protective layer 16 and are connected to the first metal layer 17 and the second metal layer 19 are formed at a pair of corners sandwiching the fixed end of the vibrating membrane 10d in the first laminate 10 having a rectangular shape in plan view.

[0015] The first metal layer 17, the piezoelectric layer 18, and the second metal layer 19 laminated on the semiconductor layer 13 that forms the diaphragm 10d constitute driving means for vibrating the diaphragm 10d in accordance with the applied voltage. Hereinafter, in the first laminate 10, the first metal layer 17, the piezoelectric layer 18, and the second metal layer 19 that constitute the driving means, and the first protective layer 15 and the second protective layer 16 that cover them are referred to as the driving layer 23.

[0016] In the first laminate 10, the first semiconductor substrate 11, the first insulating layer 12, and the semiconductor layer 13 are constituted by an SOI wafer. Specifically, the first semiconductor substrate 11 corresponds to the support layer of the SOI wafer and is made of silicon (Si), the first insulating layer 12 corresponds to the BOX layer and is made of silicon dioxide (SiO2), and the semiconductor layer 13 corresponds to the active layer and is made of Si. Among these, the first insulating layer 12 of the BOX layer and the semiconductor layer 13 of the active layer are collectively referred to as the buried layer 22.

[0017] The second insulating layer 14 may be formed by sequentially laminating aluminum oxide (Al2O3) on SiO2. The first metal layer 17 may be formed by sequentially laminating titanium dioxide (TiO2) and platinum (Pt). TiO2 is interposed between the upper layer Pt and the lower layer second insulating layer 14 for adhesion. The piezoelectric layer 18 may be made of lead zirconate titanate (PZT). The second metal layer 19 may be formed by sequentially laminating iridium oxide (IrO2) and iridium (Ir). The first protective layer 15 and the second protective layer 16 may be formed by sequentially laminating Al2O3 and SiO2. Here, SiO2 serves as an interlayer insulating film, and Al2O3 serves as a hydrogen barrier film.

[0018] The second semiconductor substrate 31 has a frame-like shape surrounding the diaphragm 10d, and forms a second cavity 31c that communicates from the bottom surface 31a to the top surface 31b above the diaphragm 10d. Notches 31f are formed at a pair of opposite corners on the outer periphery of the second semiconductor substrate 31 so that the electrode pads 25 formed on the first laminate 10 are exposed. The bottom surface 31a of the second semiconductor substrate 31 is bonded by an adhesive layer 45 interposed between the top surface 10b of the first laminate 10. The second semiconductor substrate 31 may be made of Si.

[0019] On the side surface of the piezoelectric element 40, the range from the bottom surface 31a of the second semiconductor substrate 31 to the top surface 31b exceeding a predetermined height in the height direction is composed of a first cleavage side surface 40a formed by cleaving a modified region formed by irradiating a laser beam. The range from the bottom surface 10a of the first laminate 10 to the first cleavage side surface 40a of the second semiconductor substrate 31 in the height direction is composed of a first retreat side surface 40b that retreats by a first displacement D1 in the width direction from the first cleavage side surface 40a. Here, the width direction is the direction connecting the first cleavage side surface 40a and the first cleavage side surface 40a facing the opposite side across the piezoelectric element 40, as shown by the width W in the figure.

[0020] In the piezoelectric element 40 of the present embodiment, since the first retreat side surface 40b that has been cut off and retreated in advance by a scribe line is formed in the adhesive layer 45 and the first insulating layer 12 of the BOX layer, there is no need for dicing. Therefore, in the manufacturing method of the piezoelectric element 40 described later, there is no need to dice the adhesive layer 45 and the first insulating layer 12, which are concerned about fragmentation defects due to attenuation of the laser beam in the dicing process by laser beam focusing modification, and fragmentation defects such as non-separation and meandering of the chip sides can be reduced.

[0021] (Modification 1) FIG. 2 is a cross-sectional view of the piezoelectric element 41 of Modification 1. The piezoelectric element 41 of Modification 1 is different from the piezoelectric element 40 of the present embodiment in that, on the side surface of the first laminate 10, the embedded layer 22 is formed from the second retreat side surface 40c in the height direction, and the first semiconductor substrate 11 is formed from the third retreat side surface 40d, and the side surface is composed of the first cleavage side surface 40a and the first retreat side surface 40b. Since other configurations are the same as those of the piezoelectric element 40 of the present embodiment, corresponding components are denoted by common reference numerals to clarify the correspondence relationship.

[0022] Also, on the side surface of the piezoelectric element 41 of Modification 1, the range from the bottom surface 31a of the second semiconductor substrate 31 to the top surface 31b exceeding a predetermined height in the height direction is composed of the first cleavage side surface 40a formed by splitting the modified region formed by irradiating laser light. The range from the bottom surface 31a of the second semiconductor substrate 31 to the first cleavage side surface 40a in the height direction is composed of the first retreat side surface 40b retreated by the first displacement D1 in the width direction from the first cleavage side surface 40a. The adhesive layer 45 directly below the second semiconductor substrate 31 also constitutes the first retreat side surface 40b common to the second semiconductor substrate 31.

[0023] On the side surface of the first laminate 10, the range of the embedded layer 22 in the height direction constitutes the second retreat side surface 40c retreated by the second displacement D2 in the width direction from the first cleavage side surface 40a, and the range of the first semiconductor substrate 11 constitutes the third retreat side surface 40d retreated by the third displacement D3 in the width direction from the first cleavage side surface 40a. The first displacement D1, the second displacement D2, and the third displacement D3 satisfy the relational expression D1 > D2 ≧ D3.

[0024] The piezoelectric element 41 of Modification 1 satisfies the relational expression D1 > D2, and the first displacement D1 of the first retreat side surface 40b including the adhesive layer 45 in the height direction is larger than the second displacement D2 of the second retreat side surface 40c of the embedded layer 22. Therefore, the adhesive flowing from the adhesive layer 45 during manufacturing can be accommodated in the space along the first retreat side surface 40b, so as not to flow into the scribe line. When the first displacement D1 is large enough, for example, 25 μm or more, the inflow of the adhesive into the scribe line can be ignored, and D1 ≤ D2 may be used instead of D1 > D2. In this way, since there is no concern that the laser beam is attenuated by the adhesive flowing into the scribe line and chip separation failure occurs, the handling of the adhesive constituting the adhesive layer 45 becomes easy.

[0025] Also, the piezoelectric element 41 of Modification 1 satisfies the relational expression D2 ≥ D3, so that the second displacement D2 of the second retreat side surface 40c of the embedded layer 22 in the height direction is equal to or greater than the third displacement D3 of the third retreat side surface 40d of the first semiconductor substrate 11. Therefore, the embedded layer 22 is farther from the scribe line than the first semiconductor substrate 11, and the embedded layer 22 does not protrude into the scribe line. Since the embedded layer 22 is as thin as about several tens of μm in thickness, if it protrudes into the scribe line, it is easily broken and can cause particles or the like.

[0026] (Modification 2) FIG. 3 is a cross-sectional view of the piezoelectric element 42 of Modification 2. The piezoelectric element 42 of Modification 2 is different from the piezoelectric element 41 of Modification 1 whose side surface is composed of the first cleavage side surface 40a, the first retreat side surface 40b, the second retreat side surface 40c, and the third retreat side surface 40d in that a second cleavage side surface 40e aligned with the first cleavage side surface 40a in the width direction is formed on the side surface of the first semiconductor substrate 11 of the first laminate 10. Since other configurations are the same as those of the piezoelectric element 40 of Modification 1, corresponding components are given common reference numerals to clarify the correspondence.

[0027] Before dicing and separating the piezoelectric element 42 of Modification 2, each piezoelectric element 42 is connected to an adjacent piezoelectric element by a second cleavage side surface 40e together with the first cleavage side surface 40a. For this reason, mechanical robustness is provided to the wafer before the individual pieces in which the piezoelectric element 42 is formed, facilitating handling.

[0028] (Manufacturing method) Next, the manufacturing method of the piezoelectric element 40 of the present embodiment will be described. First, the process of manufacturing the first laminate 10 that will constitute the transducer will be described with reference to FIGS. 4A to 4G. The first semiconductor substrate 11, the first insulating layer 12, and the semiconductor layer 13 shown in FIG. 4A are constituted by an SOI wafer. Specifically, the first semiconductor substrate 11 corresponds to the support layer of the SOI wafer, the first insulating layer 12 corresponds to the BOX layer, and the semiconductor layer 13 corresponds to the active layer. A third insulating layer 27 is laminated on the bottom surface of the SOI wafer, and a second insulating layer 14, a first metal layer 17, a piezoelectric layer 18, and a second metal layer 19 are laminated in order on the top surface of the SOI wafer to constitute the first laminate 10.

[0029] As shown in FIG. 4B, unnecessary portions are removed by etching so that the first metal layer 17, the piezoelectric layer 18, and the second metal layer 19 laminated in order on the second insulating layer 14 are formed in appropriate shapes. As shown in FIG. 4C, a first protective layer 15 is formed so as to cover the second insulating layer 14 on which the first metal layer 17, the piezoelectric layer 18, and the second metal layer 19 processed into appropriate shapes by etching are laminated. As shown in FIG. 4D, a first opening 15a is formed in the first protective layer 15 so that electrodes can be connected to the first metal layer 17 and the second metal layer 19, respectively. Further, a second opening 15b is formed in the first protective layer 15 at a position where a slit 10e is formed in the first laminate 10, and a third opening 15c is formed along a scribeline that will serve as a cut line when dicing into individual pieces.

[0030] As shown in FIG. 4E, an electrode 21 and a wiring (not shown) connected to the electrode 21 are formed. The electrode 21 and the wiring may be formed by laminating an aluminum (Al) - copper (Cu) alloy and titanium nitride (TiN). TiN is a barrier metal. As shown in FIG. 4F, after covering the first protective layer 15 in which the electrode 21, the second opening 15b, and the third opening 15c are formed with the second protective layer 16, the second protective layer 16 covering the second opening 15b and the third opening 15c is removed by etching. As shown in FIG. 4G, by etching to deepen the second opening 15b and the third opening 15c and forming a first groove 46 and a second groove 47 reaching the top surface of the first semiconductor substrate 11, the first laminate 10 is obtained. A third insulating layer 27 is further laminated on the bottom surface 10a of the first laminate 10.

[0031] FIG. 5 is a plan view of the first laminate 10 formed in the process from FIGS. 4A to 4E. The process diagram of FIG. 4G corresponds to a cross - section cut along the cutting line IVG - IVG in FIG. 5. In the top - most second protective layer 16 of the first laminate 10, a first groove 46 reaching the first semiconductor substrate 11 is formed so as to surround the periphery leaving the fixed end of the diaphragm 10d in a cantilever shape in plan view. In the scribe line, a second groove 47 reaching the first semiconductor substrate 11 is formed. Also, a pair of electrode pads 25 formed by opening the second protective layer 16 are connected to the first metal layer 17 and the second metal layer 19 via the wiring layer 24, respectively.

[0032] A process of processing a second semiconductor substrate 31 that will constitute a sub - frame using FIGS. 6A to 6F will be described. As shown in FIG. 6A, a fourth insulating layer 32 and a fifth insulating layer 33 are laminated on the bottom surface 31a and the top surface 31b of the second semiconductor substrate 31. The second semiconductor substrate 31 may be made of Si, and the fourth insulating layer 32 and the fifth insulating layer 33 may be made of SiO2. In this case, the SiO2 of the fourth insulating layer 32 and the fifth insulating layer 33 may be formed by oxidizing the surface of the second semiconductor substrate 31 made of Si.

[0033] As shown in FIG. 6B, openings 35 are formed in the fourth insulating layer 32 and the fifth insulating layer 33. The openings 35 are respectively formed at positions for forming grooves penetrating the second semiconductor substrate 31 to cut off unnecessary portions of the second semiconductor substrate 31 and at scribe lines.

[0034] As shown in FIG. 6C, a temporary fixing substrate 51 is attached onto the fifth insulating layer 33 laminated on the top surface 31b of the second semiconductor substrate 31 with a temporary adhesive layer 52 such as a tape interposed therebetween. Then, a mask 53 is laminated on the fourth insulating layer 32 laminated on the bottom surface 31a of the second semiconductor substrate 31 so as to expose the openings 35 corresponding to the grooves penetrating the second semiconductor substrate 31, and etching is performed. By the etching, a third groove 36 is formed which penetrates the second semiconductor substrate 31 from the opening of the mask 53 and reaches the temporary adhesive layer 52.

[0035] As shown in FIG. 6D, the mask 53 laminated on the fourth insulating layer 32 is removed, and etching is performed to remove up to a predetermined height from the openings 35 corresponding to the scribe lines where the third groove 36 was not formed and covered by the mask 53 to form a fourth groove 37. As shown in FIG. 6E, after removing the temporary fixing substrate 51 leaving the temporary adhesive layer 52, the portion separated from the second semiconductor substrate 31 by the third groove 36 is removed together with the temporary adhesive layer 52. Further, the fourth insulating layer 32 and the fifth insulating layer 33 are also removed. As shown in FIG. 6F, a second cavity 31c is formed in the second semiconductor substrate 31. In the scribe lines of the second semiconductor substrate 31, a fourth groove 37 is formed from the bottom surface 31a up to a predetermined height.

[0036] FIG. 7 is a plan view of the second semiconductor substrate 31 processed in the steps from FIG. A to FIG. 6F. The process diagram of FIG. 6F corresponds to a cross section cut along the cutting line VIF-VIF in FIG. 7. The second semiconductor substrate 31 has a frame-like shape surrounding the second cavity 31c.

[0037] A process of processing a second laminate 60 including a first laminate 10 and a second semiconductor substrate 31 that constitute a piezoelectric element 40 of the present embodiment will be described with reference to FIGS. 8A to 8C. As shown in FIG. 8A, the first laminate 10 shown in FIG. 4G and the second semiconductor substrate 31 shown in FIG. 6F are bonded together to form the second laminate 60. Specifically, they are bonded with an adhesive layer 45 interposed therebetween such that the top surface 10b of the first laminate 10 shown in FIG. 4G and the bottom surface 31a of the second semiconductor substrate 31 shown in FIG. 6F face each other.

[0038] In the second laminate 60, a first groove 46 formed in the first laminate 10 and a fourth groove 37 formed in the second semiconductor substrate 31 are formed so as to be aligned at the top surface 10b of the first laminate 10 and the bottom surface 31a of the second semiconductor substrate 31. The first groove 46 and the fourth groove 37 are connected at the top surface 10b of the first laminate 10 and the bottom surface 31a of the second semiconductor substrate 31 to form a single connecting groove 49 having a width W1.

[0039] As shown in FIG. 8B, the third insulating layer 27 laminated on the bottom surface 10a of the first laminate 10 and a portion from the bottom surface of the first laminate 10 to a predetermined height are removed by grinding and polishing so that the first laminate 10 has a predetermined thickness. Thereafter, a portion directly below the diaphragm 10d in the first laminate 10 processed to a predetermined thickness is removed by etching to form a first cavity 10c between the bottom surface 10a of the first laminate 10 and the diaphragm 10d. Simultaneously with the formation of the first cavity 10c, a portion of the scribe line of the first laminate 10 is removed by etching. By removing the portion of the scribe line, the connecting groove 49 is extended to the bottom surface 10a of the first laminate 10 and communicates with the bottom surface 10a to open to the bottom surface 10a.

[0040] As shown in FIG. 8C, laser light 102 is condensed and irradiated from a laser light source 101 along the direction in which the connecting groove 49 extends toward the top surface 31b of the second semiconductor substrate 31. By irradiating the laser light 102, a first modified region 31d extending from the top surface 31b of the second semiconductor substrate 31 to the connecting groove 49 in the height direction is formed in the central portion of the scribe line.

[0041] After forming the first modified region 31d, when an external force is applied to the second laminate 60 by means of tape expansion or the like, the second laminate 60 is split at the first modified region 31d and separated into individual piezoelectric elements 40 of the present embodiment as shown in FIGS. 1A and 1B. The split first modified region 31d becomes the first split side surface 40a of the piezoelectric element 40. The wall surface of the connection groove 49 having the first width W1 in the second laminate 60 forms a first retracted side surface 40b that retracts by a first displacement D1 in the width direction from the first split side surface 40a until reaching the first split side surface 40a formed on the second semiconductor substrate 31 in the height direction from the bottom surface 10a of the first laminate 10. Here, there is a relationship of W1 = 2D1 between the first width W1 and the first displacement D1.

[0042] According to the present embodiment, in the second laminate 60 in which the first laminate 10 and the second semiconductor substrate 31 are laminated, a connection groove 49 is formed that extends in the height direction from the bottom surface 10a of the first laminate 10 beyond the top surface 10b of the first laminate 10 and the bottom surface 31a of the second semiconductor substrate 31. Therefore, by condensing and irradiating the laser light 102 toward the top surface 31b of the second semiconductor substrate 31 in the direction in which the connection groove 49 extends, the first modified region 31d is formed in the second semiconductor substrate 31, and the second semiconductor substrate 31 can be separated at the first modified region 31d to be separated into individual piezoelectric elements 40 of the present embodiment.

[0043] In the present embodiment, the connection groove 49 extending across the first laminate 10 and the second semiconductor substrate 31 of the second laminate 60 is formed by penetrating the adhesive layer 45 and the first insulating layer 12 of the BOX layer. Therefore, the laser light 102 irradiated along the direction in which the connection groove 49 extends does not pass through the adhesive layer 45 and the first insulating layer 12, and the laser light 102 is not attenuated by the adhesive constituting the adhesive layer 45 or the BOX layer. As a result, the occurrence of fragmentation defects such as non-separation and meandering of the chip sides due to attenuation of the laser light 102 is reduced.

[0044] According to this embodiment, in the dicing process, it is sufficient to irradiate the second semiconductor substrate 31 with the laser light 102 to form the first modified region 31d on the second semiconductor substrate 31, and it is not necessary to irradiate the first laminate 10 with the laser light 102. Therefore, the laser light source 101 that irradiates the laser light 102 only needs to be installed on the side facing the second semiconductor substrate 31 of the second laminate 60.

[0045] In this embodiment, dicing by laser beam focusing and modification is used. For dicing by laser beam focusing and modification, the cooling water and cleaning water used in blade dicing generally used in semiconductor manufacturing are not required. Therefore, there is no concern that the movable part and functional part of the piezoelectric element 40 will be contaminated or damaged.

[0046] (Modification Example 1 of the Manufacturing Method) As a modification example 1 of the manufacturing method, the manufacturing method of the piezoelectric element 41 of modification example 1 shown in FIG. 2 will be described. The manufacturing method of the piezoelectric element 41 of modification example 1 is different from the second laminate 60 of this embodiment shown in FIG. 8 in that the connection groove 49 has a first width W1, a second width W2, and a third width W3 as shown in the third laminate 61 of FIG. 9, and the connection groove 49 has only a single first width W1.

[0047] FIG. 10 is an enlarged view of a portion of the third laminate 61 including the connection groove 49. The connection groove 49 has a first width W1 in the range of the second semiconductor substrate 31 in the height direction. The adhesive layer 45 immediately below the second semiconductor substrate 31 also constitutes the connection groove 49 having the same first width as the second semiconductor substrate 31. Further, in the range of the buried layer 22 in the height direction in the first semiconductor substrate 11, it has a second width W2, and in the range of the first semiconductor substrate 11, it has a third width W3. The first width W1, the second width W2, and the third width W3 satisfy the relational expression W1 > W2 ≧ W3.

[0048] In order to fabricate such a third laminate 61, instead of forming a second groove 47 having a single width such as the first width W1 in the manufacturing process of the first laminate 10 shown in FIG. 4G, the range of the first insulating layer 12 and the semiconductor layer 13 constituting the embedded layer 22 in the height direction has a second width W2, and the range of the first semiconductor substrate 11 has a third width W3. It may be formed in the second groove 47.

[0049] The third laminate 61 is diced by laser beam focusing and modification in the same manner as FIG. 8C showing the manufacturing method of the piezoelectric element 40 of the present embodiment, and is separated into individual pieces into the piezoelectric element 41 of Modification 1 as shown in FIG. 2. In the piezoelectric element 41 of Modification 1, the first displacement D1, the second displacement D2, and the third displacement D3 in which the first rearward side surface 40b, the second rearward side surface 40c, and the third rearward side surface 40d are each recessed in the width direction from the first cleavage side surface 40a are the first width W1, the second width W2, and the third width W3 of the connection groove 49, and there is a relationship of W1 = 2D1, W2 = 2D2, and W3 = 2D3.

[0050] In Modification 1, the first width W1 of the connection groove 49 formed including the adhesive layer 45 on the second semiconductor substrate 31 is larger than the second width W2 of the connection groove 49 formed in the embedded layer 22 of the first laminate 10, that is, W1>W2. By having such a relationship, it is possible to prevent the adhesive flowing from the adhesive layer 45 during manufacturing from being accommodated in the space along the wall surface of the connection groove 49 having the first width W1 and flowing into the connection groove 49. When the first width W1 is sufficiently large, for example, 50 μm or more, the inflow of the adhesive into the connection groove 49 can be ignored, and not only W1>W2 but also W1≦W2 may be used. Thus, since there is no concern that the laser beam is attenuated by the adhesive flowing into the connection groove 49 and fragmentation failure occurs, the handling of the adhesive constituting the adhesive layer 45 becomes easy.

[0051] Also, in Modification 1, in the first laminate 10, the second width W2 of the connection groove 49 in the range of the embedded layer 22 in the height direction is equal to or greater than the third width W3 of the connection groove 49 in the range of the first semiconductor substrate 11, that is, W2≧W3. By having such a relationship, the embedded layer 22 will be farther from the scribe line than the first semiconductor substrate 11, and the embedded layer 22 will not protrude into the connection groove 49. Since the embedded layer 22 is as thin as about several tens of μm in thickness, if it protrudes into the connection groove 49, it will be easily broken, which may cause particles and the like.

[0052] (Modification 2 of the manufacturing method) As Modification 2 of the manufacturing method, the manufacturing method of the piezoelectric element 42 of Modification 2 shown in FIG. 3 will be described. The manufacturing method of the piezoelectric element 41 of Modification 2 is different from the manufacturing method of the piezoelectric element 41 of Modification 1 in that, as shown in FIG. 11, in the first laminate 10, the connection groove 49 is formed only in the range of the embedded layer 22 in the height direction without reaching the bottom surface 10a of the first laminate 10.

[0053] In order to fabricate such a fourth laminate 62, it is only necessary to leave the range of the first semiconductor substrate 11 of the first laminate 10 without forming the connection groove 49 in the height direction. For this purpose, in the manufacturing process of the first laminate 10 shown in FIG. 4E, the second opening 15b formed in the first protective layer 15 of the first laminate 10 may be reinterpreted as the second groove 47, and the process of digging the second groove 47 in the second opening 15b in the next FIG. 4G may be omitted.

[0054] The fourth laminate 62 is also diced by laser beam focusing modification and separated into individual piezoelectric elements 42 as in the modification example 2 shown in FIG. 3. However, in the fourth laminate 62, the connection groove 49 remains inside without reaching either the bottom surface 10a of the first laminate 10 or the top surface 31b of the second semiconductor substrate 31. For this reason, in laser beam focusing dicing, laser light 102 is focused and irradiated from the laser light source 101 along the direction in which the connection groove 49 extends, toward the top surface 31b of the second semiconductor substrate 31 and the bottom surface 10a of the first laminate 10, respectively. By irradiating the laser light 102, a first modified region 31d extending from the top surface 31b of the second semiconductor substrate 31 to the connection groove 49 in the height direction and a second modified region 11f extending from the bottom surface 10a of the first laminate 10 to the connection groove 49 are formed in the central portion of the scribe line, respectively.

[0055] After forming the first modified region 31d and the second modified region 11f, when an external force is applied to the fourth laminate 62 by means of tape expansion or the like, the fourth laminate 62 is cleaved and separated at the first modified region 31d and the second modified region 11f. In the piezoelectric element 42 of the modification example 2, the first modified region 31d and the second modified region 11f form a first cleavage side surface 40a and a second cleavage side surface 40e, respectively, by cleavage.

[0056] In the modification example 2, the connection groove 49 extending across the first laminate 10 and the second semiconductor substrate 31 that constitute the fourth laminate 62 does not open to the bottom surface 10a of the first laminate 10 or the top surface 31b of the second semiconductor substrate 31, and is formed to remain inside the fourth laminate 62. Since the connection groove 49 does not open on the surface of the fourth laminate 62, it is mechanically robust and easy to handle.

[0057] As described above in detail, it is clear to those skilled in the art that the present disclosure is not limited to the embodiments described in the present disclosure. One or more elements of one embodiment can be combined with one or more elements of another embodiment. The present disclosure can be implemented as modifications and variations without departing from the spirit and scope of the present disclosure as defined by the claims. Therefore, the description of the present disclosure is for illustrative purposes and does not have any limiting meaning for the present disclosure.

[0058] (Appendix 1) The piezoelectric element 40 includes a first semiconductor substrate 11 having a first bottom surface and a first top surface, and a second semiconductor substrate 31 having a second bottom surface 31a and a second top surface 31b, the second bottom surface 31a being laminated so as to face the first top surface, and a first modified region 31d formed by irradiating a laser beam 102 in a range from the second bottom surface 31a facing the first top surface to reaching the second top surface 31b beyond a predetermined height in the height direction is split to form a first split side surface 40a. The piezoelectric element 40 further includes an adhesive layer 45 interposed between the first top surface and the second bottom surface 31a to bond the first semiconductor substrate 11 and the second semiconductor substrate 31 together, and includes a first retracted side surface 40b formed to retract in the width direction from the first split side surface 40a in a range from the first bottom surface to reaching the first split side surface 40a in the height direction. In the manufacturing method of the piezoelectric element 40, it is possible to reduce the fragmentation defect in the dicing process by laser beam focusing and modification.

[0059] (Appendix 2) In the piezoelectric element 40 described in Appendix 1, the first semiconductor substrate 11 includes an embedded layer 22 formed to a predetermined depth from the first top surface. The embedded layer 22 is composed of a first insulating layer 12 of a BOX layer and a semiconductor layer 13 of an active layer, and the semiconductor layer 13 constitutes a vibrating membrane 10d.

[0060] (Appendix 3) The piezoelectric element 40 described in Supplementary Note 2 further includes a second retracted side surface 40c that retracts in the width direction within the range of the embedded layer 22 in the height direction and does not reach the first retracted side surface 40b but retreats further than the first cleavage side surface 40a, and a third retracted side surface 40d that retracts in the width direction within the range from the bottom surface of the first semiconductor substrate 11 to the embedded layer 22 in the height direction, does not reach the second retracted side surface 40c, or aligns with the second retracted side surface 40c. This facilitates the handling of the adhesive that forms the adhesive layer 45 in the manufacturing process.

[0061] (Supplementary Note 4) In the piezoelectric element 41 described in Supplementary Note 3, with the first cleavage side surface 40a as a reference, the first displacement D1, the second displacement D2, and the third displacement D3 in which the first retracted side surface 40b, the second retracted side surface 40c, and the third retracted side surface 40d each retract in the width direction satisfy D1 > D2 ≥ D3. This facilitates the handling of the adhesive that forms the adhesive layer 45 in the manufacturing process.

[0062] (Supplementary Note 5) The piezoelectric element 40 described in any one of Supplementary Notes 1 to 4 is formed by cleaving a second modified region 11f formed by irradiating a laser beam 102 within the range from the bottom surface 10a to a predetermined height in the first semiconductor substrate 11, and further includes a second cleavage side surface 40e that aligns with the first cleavage side surface 40a in the width direction. This provides mechanical robustness and facilitates handling in the manufacturing process.

[0063] (Supplementary Note 6) The piezoelectric element 40 described in any one of Supplementary Notes 1 to 5 is constituted by a microelectromechanical system. The first semiconductor substrate 11 constitutes a transducer that drives the diaphragm 10d, and the second semiconductor substrate 31 constitutes a subframe that surrounds the diaphragm 10d. It can be manufactured using semiconductor manufacturing technology.

[0064] (Supplementary Note 7) The method for manufacturing the piezoelectric element 40 includes a step of forming a first groove 46 on the first top surface of a first semiconductor substrate 11 having a first bottom surface and a first top surface, a step of forming a fourth groove 37 on the second bottom surface 31a of a second semiconductor substrate 31 having a second bottom surface 31a and a second top surface 31b, a step of bonding the first semiconductor substrate 11 and the second semiconductor substrate 31 so that the first top surface and the second bottom surface 31a face each other and the first groove 46 and the fourth groove 37 are connected to form a connecting groove 49, thereby constituting a second laminate 60, a step of making the connecting groove 49 communicate with the first bottom surface in the second laminate 60, a step of irradiating a laser beam 102 along the direction in which the connecting groove 49 extends toward the second top surface 31b to form a first modified region 31d in the second laminate 60, and a step of dividing the second laminate 60 by the first modified region 31d to individualize it. It is possible to reduce the occurrence of defective individualization in the dicing process by laser beam focusing and modification.

[0065] (Appendix 8) In the method for manufacturing the piezoelectric element 40 according to Appendix 7, an embedded layer 22 is formed from the top surface of the first semiconductor substrate 11 to a predetermined depth. The embedded layer 22 is composed of a first insulating layer 12 of a BOX layer and a semiconductor layer 13 of an active layer, and the semiconductor layer 13 constitutes a vibration film 10d.

[0066] (Appendix 9) In the method for manufacturing the piezoelectric element 40 according to Appendix 7 or 8, the connecting groove 49 has a first width W1. The connecting groove 49 having a single first width W1 is easy to manufacture.

[0067] (Appendix 10) In the method for manufacturing the piezoelectric element 40 according to Appendix 8, the connecting groove 49 has a first width W1 in the range of the second semiconductor substrate 31 in the height direction, includes a second width W2 that is narrower than the first width W1 in the range of the embedded layer 22 in the height direction, and includes a third width W3 that is narrower than or equal to the second width W2 in the range from the bottom surface of the first semiconductor substrate 11 to the embedded layer 22 in the height direction. It is possible to prevent the adhesive constituting the adhesive layer 45 from flowing into the connecting groove 49.

[0068] (Appendix 11) In the method for manufacturing the piezoelectric element 40 described in Supplementary Note 10, the first width W1, the second width W2, and the third width satisfy the relational expression W1 > W2 ≧ W3. It is possible to prevent the adhesive constituting the adhesive layer 45 from flowing into the connection groove 49.

[0069] (Supplementary Note 12) In the method for manufacturing the piezoelectric element 40 according to any one of Supplementary Notes 7 to 11, the modification region forms a cleavage side surface by the step of singulating. Since cooling water and cleaning water used generally in semiconductor manufacturing are not required, there is no concern that the movable parts and functional parts of the piezoelectric element 40 are contaminated or damaged.

[0070] (Supplementary Note 13) The method for manufacturing the piezoelectric element 42 of Modification 2 includes a step of forming a first groove 46 on the top surface of a first semiconductor substrate 11 having a first bottom surface and a first top surface, a step of forming a fourth groove 37 on the second bottom surface 31a of a second semiconductor substrate 31 having a second bottom surface and a second top surface, a step of bonding the first semiconductor substrate 11 and the second semiconductor substrate 31 so that the first top surface of the first semiconductor substrate 11 and the second bottom surface 31a of the second semiconductor substrate 31 face each other and the first groove 46 and the fourth groove 37 are connected to form a connection groove 49 to constitute a fourth laminate 62, a step of irradiating a laser beam 102 along the direction in which the connection groove 49 extends toward the second top surface 31b to form a first modification region 31d in the fourth laminate 62, a step of irradiating a laser beam 102 along the direction in which the connection groove 49 extends toward the first bottom surface to form a second modification region 11f in the fourth laminate 62, and a step of dividing the fourth laminate 62 by the first modification region 31d and the second modification region 11f to singulate. It is possible to reduce singulation defects in the step of dicing by laser beam focusing and modification. Further, it provides mechanical robustness to the fourth laminate 62 and facilitates handling.

[0071] (Supplementary Note 14) In the method for manufacturing the piezoelectric element 42 according to the modification example 2 described in Supplementary Note 13, the first modified region 31d and the second modified region 11f respectively form the first cleavage side surface 40a and the second cleavage side surface 40e by the singulation process. Further, since cooling water and cleaning water used in general semiconductor manufacturing by blade dicing are not required, there is no concern that the movable parts and functional parts of the piezoelectric element 40 will be contaminated or damaged.

Explanation of Signs

[0072] 10 First laminate 10c First cavity 10d Diaphragm 10e Slit 11 First semiconductor substrate 12 First insulating layer 13 Semiconductor layer 14 Second insulating layer 15 First protective layer 16 Second protective layer 17 First metal layer 18 Piezoelectric layer 19 Second metal layer 21 Electrode 22 Embedded layer 23 Driving layer 31 Second semiconductor substrate 31c Second cavity 37 Fourth groove 40 Piezoelectric element 40a First cleavage side surface 40b First retreat side surface 40c Second retreat side surface 40d Third retreat side surface 40e Second cleavage side surface 46 First groove 47 Second groove 49 Connecting groove 101 Laser light source 102 Laser light

Claims

1. a first substrate having a first bottom surface and a first top surface; a second substrate having a second bottom surface and a second top surface, laminated such that the second bottom surface faces the first top surface, and including a first cleavage side surface formed by cleaving a first modified region formed by irradiating a laser beam in a range from the second bottom surface facing the first top surface to reaching the second top surface beyond a predetermined height in the height direction; an adhesive layer interposed between the first top surface and the second bottom surface to bond the first substrate and the second substrate; and comprising; a semiconductor device including a first retreat side surface formed in a range from the first bottom surface in the height direction to reach the first cleavage side surface and retreating in the width direction from the first cleavage side surface.

2. The semiconductor device according to claim 1, wherein the first substrate includes an embedded layer formed to a predetermined depth from the first top surface.

3. a second retreat side surface that retreats in the width direction from the first cleavage side surface within the range of the embedded layer in the height direction but does not reach the first retreat side surface; and a third retreat side surface that retreats in the width direction from the first cleavage side surface within a range from the first bottom surface to the embedded layer in the height direction, does not reach the second retreat side surface or aligns with the second retreat side surface; The semiconductor device according to claim 2, further comprising.

4. Based on the first cleavage side surface, first displacement D1, second displacement D2, and third displacement D3 in which the first retreat side surface, the second retreat side surface, and the third retreat side surface retreat in the width direction respectively satisfy D1 > D2 ≧ D3. The semiconductor device according to claim 3.

5. In the first substrate, within a range from the first bottom surface to a predetermined height, a second modified region formed by irradiating a laser beam is cleaved, and further including a second cleavage side surface that aligns with the first cleavage side surface in the width direction. The semiconductor device according to claim 1.

6. The semiconductor device according to any one of claims 1 to 5, which is constituted by a microelectromechanical system, wherein the first substrate constitutes a transducer that drives a diaphragm, and the second substrate constitutes a sub-frame that surrounds the diaphragm.

7. a step of forming a first groove on the first top surface of a first substrate having a first bottom surface and a first top surface; a step of forming a second groove on the second bottom surface of a second substrate having a second bottom surface and a second top surface; a step of bonding and laminating the first substrate and the second substrate so that the first top surface and the second bottom surface face each other and the first groove and the second groove are connected to form a connecting groove to form a laminate; A step of making the connection groove communicate with the first bottom surface in the laminate; A step of forming a modified region in the laminate by irradiating a laser beam along the direction in which the connection groove extends toward the second top surface; A step of dividing the laminate in the modified region to individualize it A method of manufacturing a semiconductor device including the above steps.

8. The method of manufacturing a semiconductor device according to claim 7, wherein an embedded layer is formed to a predetermined depth from the first top surface of the first substrate.

9. The method of manufacturing a semiconductor device according to claim 7 or 8, wherein the connection groove has a first width.

10. The connection groove has a first width in the range of the second substrate in the height direction, includes a second width that is narrower than the first width in the range of the embedded layer in the height direction, and includes a third width that is narrower than or equal to the second width in the range from the first bottom surface to the embedded layer in the height direction. The method of manufacturing a semiconductor device according to claim 8.

11. For the first width W1, the second width W2, and the third width, the method of manufacturing a semiconductor device according to claim 10 satisfies the relational expression W2 > W1 ≧ W3.

12. The method of manufacturing a semiconductor device according to claim 7, wherein the modified region forms a cleavage side surface in the step of individualizing.

13. A step of forming a first groove on the first top surface of the first substrate having a first bottom surface and a first top surface; A step of forming a second groove on the second bottom surface of the second substrate having a second bottom surface and a second top surface; A step of bonding the first substrate and the second substrate so that the first top surface and the second bottom surface face each other and the first groove and the second groove are connected to form a connection groove, thereby constituting a laminate; A step of forming a first modified region in the laminate by irradiating a laser beam along the direction in which the connection groove extends toward the second top surface; A step of forming a second modified region in the laminate by irradiating a laser beam along the direction in which the connection groove extends toward the first bottom surface; A step of dividing the laminate in the first modified region and the second modified region to individualize it A method of manufacturing a semiconductor device including the above steps.

14. The method of manufacturing a semiconductor device according to claim 13, wherein the first modified region and the second modified region respectively form a first cleavage side surface and a second cleavage side surface in the step of individualizing.

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