Semiconductor device

Abstract

To provide a silicon carbide semiconductor device with improved reliability, in which the entry of hydrogen ions in a gate electrode and a gate insulating film is prevented.SOLUTION: A silicon carbide semiconductor device includes a silicon carbide substrate 2 formed of silicon carbide of a first conductivity type, a drift layer 3 formed of silicon carbide of the first conductivity type on the first surface 30 of the silicon carbide substrate, a plurality of body layers 4 formed of silicon carbide of a second conductivity type on the drift layer, a plurality of source layers 5 formed of silicon carbide of the first conductivity type on each of them, a gate insulating film 7 formed in contact with the body layer and the source layer, a gate electrode 8, an interlayer insulating film 9 formed so as to cover the gate electrode with the gate insulating film, and a conductive barrier layer 15 for preventing passage of hydrogen ions, which is provided between the side part of the interlayer insulating film and the source electrode.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a silicon carbide semiconductor device. In particular, it relates to a silicon carbide semiconductor device with improved reliability.

Background Art

[0002] A semiconductor device using silicon carbide (SiC) for a substrate and a drift layer (epitaxial layer) can achieve higher breakdown voltage, lower loss, and higher speed than a semiconductor device using silicon (Si) for the substrate, and is thus used, for example, as a power semiconductor device.

[0003] For example, in the SiC-MOSFET as a silicon carbide semiconductor device described in Patent Document 1, a TEOS (Tetra Ethyl Ortho Silicate) oxide film is deposited as an interlayer insulating film for insulating a gate electrode and a source wiring, etc., a BPSG (Boro Phospho Silicate Glass) film is deposited on the TEOS oxide film, and it is disclosed that a three-layer insulating film is formed by further depositing a TEOS oxide film on the BPSG. Non-Patent Document 1 shows that in a trench-type power SiC-MOSFET, when hydrogen ions (H+) enter the device, it has an effect of impairing the reliability of the HTRB (High-Temperature Reverse Bias) test, and as a countermeasure, by adopting a material with a high phosphorus concentration in the interlayer insulating film, hydrogen ions can be adsorbed to prevent hydrogen ions from entering the inside of the semiconductor device and improve the reliability of the semiconductor device.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Non-Patent Documents

[0005]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] Silicon carbide semiconductor devices such as SiC-MOSFETs are often encapsulated with resin. Hydrogen ions precipitated from the resin pass through the source wiring electrode, gate electrode, and gate insulating film and reach the channel area of the body layer, which impairs the reliability in the HTRB (High Temperature Reverse Bias) test and causes fluctuations in the gate threshold voltage (Vth) and an increase in leakage current of the silicon carbide semiconductor device. Therefore, it is required to prevent hydrogen ions from passing through the interlayer insulating film. In view of these problems, an object of the present invention is to provide a silicon carbide semiconductor device that prevents hydrogen ions from reaching the gate electrode and the gate insulating film from the source wiring electrode and improves reliability.

Means for Solving the Problems

[0007] One aspect of the silicon carbide semiconductor device of the present invention is a silicon carbide substrate formed of silicon carbide of a first conductivity type, a drift layer formed of silicon carbide of the first conductivity type on the first surface of the silicon carbide substrate, a plurality of body layers formed of silicon carbide of a second conductivity type on the drift layer, A plurality of source layers, each formed of silicon carbide of a first conductivity type (one of n-type and p-type) having a higher impurity concentration than the drift layer, on each of the plurality of body layers; A gate insulating film formed to be in contact with the body layer and the source layer; A gate electrode formed on the gate insulating film; An interlayer insulating film formed to cover the gate electrode together with the gate insulating film; A conductive barrier layer provided between a side portion of the interlayer insulating film and a source electrode to prevent passage of hydrogen ions and comprising the same.

[0008] Thus, since a conductive barrier layer for preventing the passage of hydrogen ions is provided between the side portion of the interlayer insulating film of the silicon carbide semiconductor device and the source electrode, the space between the interlayer insulating film and the source electrode is blocked by the conductive barrier, so that hydrogen ions can be prevented from entering the channel area via the gate insulating film and the gate electrode. Therefore, it is possible to prevent a decrease in reliability, a change in gate threshold voltage (Vth), and an increase in leakage current in the HTRB (High Temperature Reverse Bias) test due to hydrogen ions reaching the channel area, and the reliability of the silicon carbide semiconductor device 1 can be improved.

[0009] As a specific aspect of the above-described aspect, in the silicon carbide semiconductor device of the present invention, the conductive barrier layer is made of tantalum, tantalum nitride, titanium nitride, or amorphous silicon carbide.

[0010] Thus, since the conductive barrier layer is made of tantalum, tantalum nitride, titanium nitride, or amorphous silicon carbide, these materials have conductivity and are difficult to permeate hydrogen, so it is possible to prevent the passage of hydrogen ions as a conductive barrier layer without increasing the electrical resistance value. Thereby, it becomes possible to enhance the reliability of the silicon carbide semiconductor device.

[0011] As a specific aspect of the above-described aspect, in the silicon carbide semiconductor device of the present invention, the conductive barrier layer is provided so as to cover a side portion of the interlayer insulating film and a part of the source electrode, and an upper surface of the interlayer insulating film is formed so as not to be covered by the conductive barrier layer.

[0012] In this way, the conductive barrier layer is formed such that the upper surface of the interlayer insulating film is not covered by the conductive barrier layer. Therefore, since the conductive barrier layer is divided into left and right, even when the temperature rises, it is possible to prevent the conductive barrier layer from being damaged by thermal stress in the left-right direction.

[0013] As a specific aspect of the above-described aspect, in the silicon carbide semiconductor device of the present invention, the conductive barrier layer covers a lower end of a side portion of the interlayer insulating film, a side end portion of the upper portion of the source electrode on the interlayer insulating film side, and between them, and is formed so as not to cover an upper corner portion of the interlayer insulating film.

[0014] In this way, since the conductive barrier layer covers at least the lower end of the side portion of the interlayer insulating film, the side end portion of the upper portion of the source electrode on the interlayer insulating film side, and between them, it is possible to prevent hydrogen ions from entering the gate electrode and the gate insulating film, and improve the reliability of the silicon carbide semiconductor device. Further, since it is formed so as not to cover the upper corner portion of the interlayer insulating film, the conductive barrier layer does not have a structure that presses the interlayer insulating film from above the corner portion, so when the temperature of the silicon carbide semiconductor device rises, it is possible to prevent the conductive barrier layer from being damaged by thermal stress due to expansion of members in the vertical direction.

[0015] As a specific aspect of the above-described aspect, in the silicon carbide semiconductor device of the present invention, in a plan view, an outer end portion of a lower portion of the conductive barrier layer is inside an outer end portion of the source layer, In a plan view, in a range where the source electrode and the source layer overlap, an upper surface of the source electrode includes a region covered by the conductive barrier layer and a region not covered by the conductive barrier layer.

[0016] Thus, since the upper surface of the source electrode includes a region covered by the conductive barrier layer and a region not covered by the conductive barrier layer, it is possible to prevent hydrogen ions from entering the channel area without significantly increasing the electrical resistance value by the conductive barrier layer, and a highly reliable silicon carbide semiconductor device can be realized without changing the characteristics.

Advantages of the Invention

[0017] According to the present invention, since a conductive barrier layer for preventing the passage of hydrogen ions is provided between the side portion of the interlayer insulating film of the silicon carbide semiconductor device and the source electrode, the space between the interlayer insulating film and the source electrode is blocked by the conductive barrier, so that hydrogen ions can be prevented from entering the channel area via the gate insulating film and the gate electrode. For this reason, it is possible to prevent a decrease in reliability in the HTRB (High Temperature Reverse Bias) test due to hydrogen ions reaching the channel area, a change in the gate threshold voltage (Vth), and an increase in leakage current, and the reliability of the silicon carbide semiconductor device 1 can be improved.

Brief Description of the Drawings

[0018]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Embodiments for Carrying Out the Invention

[0019] <Regarding the definitions in the description> In the embodiments described below, it is assumed that the first conductivity type in the silicon carbide semiconductor device is n-type and the second conductivity type is p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0020] Also, regarding the terms indicating directions such as up and down, left and right, side, inside, and outside, for convenience, since they are based on FIG. 1, they may be different from the actual product orientation. Also, the drawings are schematic, and include parts where the relationship between the thickness and the planar dimensions, and the ratio of the thicknesses of the respective layers are different from the actual ones. Also, there are parts where the dimensional relationships and ratios are different between the drawings.

[0021] <Configuration of the embodiment> An embodiment of the silicon carbide semiconductor device according to the present invention will be described. FIG. 1 is a cross-sectional view of a silicon carbide semiconductor device 1 as a unit cell that is the minimum unit structure of a planar SiC-MOSFET. A plurality of silicon carbide semiconductor devices similar to the silicon carbide semiconductor device 1 in FIG. 1 are provided inside a semiconductor chip (not shown).

[0022] The silicon carbide semiconductor device 1 in FIG. 1 includes a silicon carbide substrate 2, a drift layer 3, two body layers 4, two source layers 5, two body contact layers 6, a gate insulating film 7, a gate electrode 8, an interlayer insulating film 9, two source electrodes 10, a source wiring electrode 11, a drain electrode 12, and a conductive barrier layer 15.

[0023] As shown in FIG. 1, a planar MOSFET is formed on an n + -type silicon carbide substrate 2 of the first conductivity type. The silicon carbide substrate 2 has a first surface 30 on the upper main surface side and a second surface 31 on the lower main surface side in the drawing of FIG. 1. The n + -type silicon carbide substrate 2 is configured to have a higher impurity concentration than the n-type drift layer 3 described later.

[0024] Two p-type body layers 4, which are the second conductivity type, are formed at a distance from each other on the upper surface (the side opposite to the silicon carbide substrate 2) of the n-type drift layer 3. The body layer 4 has a thickness of about 1 μm. The p-type body layer 4 is formed by, for example, ion implantation of aluminum.

[0025] On each of the p-type body layers 4, a high-impurity n + A source layer 5 of the n type is provided. + The impurity concentration of the n-type source layer 5 is higher than that of the n-type drift layer 3. + The thickness of the p-type source layer 5 is, for example, about 0.3 to 0.4 μm. + On the outside of the source layer 5 of the mold, p + A body contact layer 6 of the p type is provided. + The p-type body contact layer 6 is configured to have a higher impurity concentration than the p-type body layer 4.

[0026] The body layer 4 is made of n + The gate insulating film 7 is disposed between the source layer 5 and the drift layer 3 of the semiconductor device and is in contact with the gate insulating film 7. The gate insulating film 7 is disposed on the drift layer 3, the body layer 4, and the source layer 5, and a gate electrode 8 is provided on the upper surface of the gate insulating film 7. The gate electrode 8 is made of polysilicon into which n-type impurities [e.g., phosphorus (P)] are ion-implanted to enhance conductivity. The gate electrode 8 has a contact hole (not shown because it is a cross section different from that in FIG. 2) provided in the interlayer insulating film 9, and is electrically connected to a gate pad of a semiconductor chip (not shown) via an external wiring.

[0027] An interlayer insulating film 9 is formed so as to cover a part of the gate electrode 8 and the gate insulating film 7. One of the roles of the interlayer insulating film 9 is to insulate the gate electrode 8 from other energizing members such as the source wiring electrode 11. This interlayer insulating film 9 is composed of one or a plurality of layers of different types. In the present embodiment, specifically, for example, the interlayer insulating film 9 is configured with a two-layer structure of a BPSG film formed to cover the gate electrode 8 and a TEOS oxide film formed to cover this BPSG film. The interlayer insulating film 9 is formed so as to cover the upper part of the gate electrode 8 and the upper part of the gate insulating film 7. Since the interlayer insulating film 9 has a low hydrogen ion transmittance, it prevents hydrogen ions from reaching the channel area from the source wiring electrode 11 via the gate insulating film 7.

[0028] A conductive barrier layer 15 is provided between the side portion of the interlayer insulating film and the source electrode 10. Preferred materials for the conductive barrier layer 15 are tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), and amorphous silicon carbide. However, as long as the material of the conductive barrier layer 15 has conductivity and a hydrogen transmittance lower than that of aluminum (hydrogen transmittance: 1×10 -12 [m -1 ·s -1 ·Pa -0.5 ) which is the material of the source electrode 10, it can exhibit its effect. Therefore, the material of the conductive barrier layer 15 has an electrical resistivity of 1.6 [uΩ·cm] or more and 100 [uΩ·cm] or less, and a hydrogen transmittance of 1×10 -20 [m -1 ·s -1 ·Pa -0.5 or more and less than 1×10 -12 [m -1 ·s -1 ·Pa -0.5 , and other materials than the above materials may be used.

[0029] As shown in FIG. 1, the conductive barrier layer 15 is provided so as to cover the side portion 42 of the interlayer insulating film 9 and a part of the source electrode 10 (on the side of the interlayer insulating film 9). Further, the upper surface 9a of the interlayer insulating film 9 is formed so as not to be covered by the conductive barrier layer 15. Here, the "upper surface 9a of the interlayer insulating film 9" includes at least the uppermost and flattest portions of the upper part of the interlayer insulating film 9. Thereby, the conductive barrier layers 15 are provided separately on the left and right.

[0030] The conductive barrier layer 15 is provided so as to cover the lower end 43 of the side portion 42 of the interlayer insulating film 9, the end portion 10a on the interlayer insulating film side at the upper part of the source electrode 10, and the space therebetween, and not to cover the corner portion 41 at the upper part of the interlayer insulating film 9. That is, the conductive barrier layer 15 has a height up to the upper end 15a and does not cover the corner portion 41 from above.

[0031] Also, in a plan view, the outer end portion 15b at the lower part of the conductive barrier layer 15 is located inside (on the side of the interlayer insulating film 9) than the outer end portion 5a of the source layer 5. Further, in a plan view, in the range where the source electrode 10 and the source layer 5 overlap, the upper surface of the source electrode 10 includes a region covered by the conductive barrier layer 15 and a region not covered by the conductive barrier layer 15. That is, in a plan view, from the outside of the outer end portion 15b at the lower part of the conductive barrier layer 15 to the inside of the outer end portion 5a of the source layer 5, the upper surface of the source electrode 10 is a region not covered by the conductive barrier layer 15. Also, in a plan view, the distance from the outer end portion 15b at the lower part of the conductive barrier layer 15 to the outer end portion 5a of the source layer 5 is, for example, about 100 nm, and the distance from the outer end portion 15b at the lower part of the conductive barrier layer 15 to the end portion 10a on the interlayer insulating film side at the upper part of the source electrode 10 is, for example, about 100 nm.

[0032] The source electrode 10 is formed on the source layer 5 and the body contact layer 6. The source electrode 10 is made of, for example, nickel silicide (NiSi). The source wiring electrode 11 is in contact with and electrically connected to the source electrode 10, and is provided on the source electrode 10 and the interlayer insulating film 9 (9a of the first layer). The source wiring electrode 11 is made of, for example, aluminum, but may also be an alloy of aluminum and copper or an alloy of aluminum and silicon (Al-Si).

[0033] On the source wiring electrode 11, a wiring 13 is provided via a ball bond 13a. As the material of the wiring 13, for example, aluminum or an alloy of aluminum and copper (Al-Cu) is used.

[0034] In the planar SiC-MOSFET as the silicon carbide semiconductor device 1 configured as described above, in the body layer 4 mentioned above, the region near the gate insulating film 7 is the channel area. Using this channel region as a current path, an electron current flows from the source electrode 10 through the source layer 5 and the drift layer 3 to the drain electrode 12. Also, by controlling the applied voltage of the gate electrode 8 and controlling the width of the depletion layer formed in the channel area, the current flowing through the channel area is controlled, so that the current flowing between the source electrode 10 and the drain electrode 12 can be controlled.

[0035] In this way, by providing the conductive barrier layer 15 between the side portion 42 of the interlayer insulating film 9 and the source electrode 10, the space between the interlayer insulating film 9 and the source electrode 10 is blocked by the conductive barrier layer 15, so that hydrogen ions can be prevented from entering the gate insulating film 7 and the gate electrode 8. As a result, the conductive barrier layer 15 prevents hydrogen ions from entering the channel area, so that the reliability of the silicon carbide semiconductor device 1 can be improved.

[0036] When the conductive barrier layer 15 covers the entire surface of the interlayer insulating film 9, if the temperature of the silicon carbide semiconductor device 1 rises during the manufacturing process or operation, due to the difference in the coefficient of thermal expansion of the members, thermal stress may occur and the conductive barrier layer 15 or the interlayer insulating film 9 may be damaged. In view of this problem, in the silicon carbide semiconductor device 1 of the present embodiment, as described above, the conductive barrier layer 15 is formed so that the upper surface 9a of the interlayer insulating film 9 is not covered by the conductive barrier layer 15. For this reason, since the conductive barrier layer 15 is divided into left and right as shown in FIG. 1, even when the temperature rises, it is possible to prevent the conductive barrier layer 15 from being damaged by the thermal stress in the left and right directions.

[0037] When the conductive barrier layer 15 covers the entire surface of the interlayer insulating film 9, there is also a possibility that thermal stress may occur in the vertical direction. In the silicon carbide semiconductor device 1 of the present embodiment, as described above, the conductive barrier layer 15 is provided so as not to cover the upper corner portion 41 of the interlayer insulating film 9. That is, the conductive barrier layer 15 has a height up to the upper end 15a and does not cover the corner portion 41 from above. As a result, since the conductive barrier layer 15 does not have a structure that presses the interlayer insulating film 9 from above the corner portion 41, it is possible to prevent the conductive barrier layer 15 from being damaged by the thermal stress due to the expansion of the members in the vertical direction.

[0038] Further, since the electrical resistivity of the conductive barrier layer 15 is higher than the electrical resistivity of the source wiring electrode 11, if the conductive barrier layer 15 covers the entire upper surface of the source electrode 10, the electrical resistance value will increase. In view of this problem, as described above, in the range where the source electrode 10 and the source layer 5 overlap, the upper surface of the source electrode 10 has a region covered by the conductive barrier layer 15 and a region not covered by the conductive barrier layer 15. Therefore, it is possible to effectively prevent the intrusion of hydrogen ions into the channel area while not increasing the electrical resistance value between the source electrodes of the source electrode wiring so much.

[0039] Note that in this embodiment, an example has been described in which the lower end of the interlayer insulating film 9 abuts only on the upper surface of the gate insulating film 7 and does not cover the source electrode 10. However, the lower end of the interlayer insulating film 9 may be configured to be wide horizontally so as to cover a part of the source electrode 10. Further, although the side portion 42 of the interlayer insulating film 9 has been described as an example provided perpendicular to the silicon carbide substrate 2, it may be inclined. <Manufacturing Process of Embodiment> The manufacturing process of the silicon carbide semiconductor device 1 of this embodiment will be described with reference to FIGS. 2 to 5. As shown in FIG. 2(A), an n-type silicon carbide substrate 2 of the first conductivity type is prepared. Thereafter, an n-type drift layer 3 is epitaxially grown on the first surface 30 (the upper surface in FIG. 1) of the silicon carbide substrate 2. + Next, a mask such as SiO2 is formed on the surface of the n-type drift layer 3, and a mask 20 is formed through a photolithography process so that the upper part of the formation planned region of the p-type body layer 4 of the second conductivity type is exposed. Thereafter, ion implantation of p-type impurity aluminum (Al) is performed from above the mask 20. The thickness of the body layer 4 is, for example, 1 μm. In this embodiment, p-type impurities such as Al are used, but B (boron) or BF2 (boron difluoride) may also be used.

[0040] Next, as shown in FIG. 2(B), a layer of the same material as the mask 20 (for example, SiO2) is laminated on the main surface of the silicon carbide substrate 2, and then a mask 21 formed wider from the mask 20 is formed by a self-alignment method formed by anisotropic etching. The upper part of the formation planned region of the n-type source layer 5 is exposed in the formed mask 21. Then, for example, nitrogen (N) is ion-implanted as an n-type impurity from above the mask 21. In this embodiment, for example, nitrogen (N) is used as the n-type impurity, but phosphorus (P) may also be used.

[0041] Next, as shown in FIG. 2(B), a layer of the same material as the mask 20 (for example, SiO2) is laminated on the main surface of the silicon carbide substrate 2, and then a mask 21 formed wider from the mask 20 is formed by a self-alignment method formed by anisotropic etching. The upper part of the formation planned region of the n-type source layer 5 is exposed in the formed mask 21. Then, for example, nitrogen (N) is ion-implanted as an n-type impurity from above the mask 21. In this embodiment, for example, nitrogen (N) is used as the n-type impurity, but phosphorus (P) may also be used.

[0042] Next, as shown in FIG. 2(C), after removing the mask 21, a mask 23 such as SiO2 is formed, and then, through a photolithography process, the mask 23 is formed so that the upper part of the planned formation region of the body contact layer 6 is exposed. Thereafter, for example, aluminum (Al) is ion-implanted as a p-type impurity into the planned formation region of the body contact layer 6 to form the body contact layer 6.

[0043] Next, after removing the mask 23, annealing is performed at, for example, 1600°C. By this annealing, the body layer 4, the source layer 5, and the body contact layer 6 are activated.

[0044] Next, as shown in FIG. 3(A), a gate insulating film 7 of, for example, SiO2 is formed. Specifically, by heating a region including the upper part of the body layer 4, the n-type source layer 5, and the body contact layer 6 at 900 to 1350°C for thermal oxidation to form SiO2, and patterning the gate insulating film 7 using the resist formed by photolithography and etching as a mask, the gate insulating film 7 is formed. + Next, as shown in FIG. 3(B), a gate electrode 8 is formed on the surface of the gate insulating film 7. Specifically, in order to enhance conductivity, for example, after forming a polysilicon layer doped with an n-type impurity, patterning is performed using the resist formed by photolithography and etching as a mask.

[0045]

[0046] ​Next, as shown in FIG. 3(C), an interlayer insulating film 9 is formed so as to cover the gate electrode 8. The interlayer insulating film 9 may have, for example, a single-layer structure made of BPSG, TEOS, or PSG, or may have a multilayer structure. For example, in the case of a two-layer structure of a BPSG insulating film and a TEOS film, a BPSG insulating film may be formed on the gate electrode 8, and a TEOS insulating film may be formed thereon. In that case, a BPSG film is formed over the entire main surface of the wafer including the gate electrode 8, and the BPSG film is patterned using the resist formed by photolithography and etching as a mask to form a first interlayer insulating film made of BPSG. Thereafter, a TEOS film is formed over the entire main surface of the wafer including the first interlayer insulating film made of BPSG, and the TEOS film is patterned using the resist formed by photolithography and etching as a mask to form a TEOS insulating film as the second interlayer insulating film. The BPSG film is subjected to reflow to perform planarization of the upper portion and to make the corners of the interlayer insulating film 9 rounded as shown in FIG. 3(C) and the like. By making it rounded, concentration of electrolysis due to the corners in the interlayer insulating film 9 can be prevented.

[0047] Next, as shown in FIG. 4(A), a source electrode 10 made of, for example, nickel silicide (NiSi) is formed. Specifically, first, nickel (Ni) is deposited on the main surface side of the silicon carbide substrate 2 including the upper portions of the source layer 5 and the body contact layer 6 by sputtering. Thereafter, an annealing process for alloying is performed. Specifically, the silicon carbide substrate 2 on which nickel (Ni) is deposited is subjected to heat treatment at 900° C. or higher and 1100° C. or lower, for example, by laser. As a result, at least a part of the source electrode 10 (the portion where the Ni film contacts the source layer 5 and the body contact layer 6) is silicided to become nickel silicide. Thereafter, the nickel (Ni) portion that has not been silicided is removed. Thereby, the source electrode 10 that makes an ohmic contact with the source layer 5 and the body contact layer 6 is formed.

[0048] Next, as shown in FIG. 4(B), a conductor film 15d is formed, for example, by sputtering over the entire main surface of the wafer including the interlayer insulating film 9. Since the material of the conductor film 15d is the same as that of the above-described conductive barrier layer 15, for example, it is tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), or amorphous silicon carbide.

[0049] Next, as shown in FIG. 4(C), the conductor film 15d is anisotropically etched, for example, by RIE or the like, and removed by an equal thickness from above to form the conductive barrier layer 15. As shown in FIG. 1 described above, the conductive barrier layer 15 is formed so as to cover between the lower end 43 of the side portion 42 of the interlayer insulating film 9 and the interlayer insulating film side end portion 10a at the upper part of the source electrode 10. In this way, after forming the conductor film 15d over the entire main surface of the wafer including the surface of the interlayer insulating film 9, since anisotropic etching is used, if the conductor film 15d is etched by the same thickness, the conductive barrier layer 15 can be left as shown in FIG. 4(C). Therefore, the conductive barrier layer 15 can be formed without a mask during etching.

[0050] Next, as shown in FIG. 5(A), a source wiring electrode 11 is formed. Specifically, the source wiring electrode 11 is formed, for example, by sputtering so as to cover the source electrode 10, the interlayer insulating film 9, and the conductive barrier layer 15. The material of the source wiring electrode 11 is, for example, aluminum (Al), but it may also be an alloy of aluminum and copper (Al-Cu) or a compound of aluminum and silicon (Al-Si). Also, the thickness of the source wiring electrode 11 is about 5 μm. Next, as shown in FIG. 5(A), a drain electrode 12 made of, for example, NiSi is formed on the second surface 31 of the silicon carbide substrate 2. The drain electrode 12 is formed, for example, by depositing nickel (Ni) by sputtering, and then the deposited nickel is heated, for example, by laser annealing. As a result, at least a part of the nickel is silicided. Thereafter, the nickel that has not been silicided is removed. Thereby, the drain electrode 12 is formed. By these steps, the silicon carbide semiconductor device 1 is manufactured.

[0051] Next, as shown in FIG. 5(B), a wiring (bonding wire) 13 is attached to the source wiring electrode 11 via a ball bond 13a. This wiring 13 is made of, for example, an alloy of aluminum (Al) and copper (Cu).

[0052] Next, as shown in FIG. 6, the silicon carbide semiconductor device 1 and the wiring 13 are encapsulated (molded) with a molding resin 14. Specifically, the molding resin 14 is provided on the main surface so as to cover the source wiring electrode 11 side.

[0053] In the above embodiment, as an example of the silicon carbide semiconductor device of the present invention, an example applied to a planar SiC-MOSFET has been described, but it is also applicable to an IGBT.

[0054] Although the present invention has been described above, when implementing the present invention, various modifications and additions are possible without departing from the gist of the present invention, not limited to the above-described examples.

Explanation of Reference Numerals

[0055] 1 Semiconductor device 2 Silicon carbide substrate 3 Drift layer 4 Body layer 5 Source layer 6 Body contact layer 7 Gate insulating film 8 Gate electrode 9 Interlayer insulating film 10 Source electrode 11 Source wiring electrode 12 Drain electrode 13 Wiring 13a Ball bond 14 Molding resin 15 Conductive barrier layer 30 First surface

Claims

1. A silicon carbide substrate formed of silicon carbide of a first conductivity type, a drift layer formed of silicon carbide of the first conductivity type on a first surface of the silicon carbide substrate, a plurality of body layers formed of silicon carbide of a second conductivity type on the drift layer, a plurality of source layers respectively formed of silicon carbide of the first conductivity type having a higher impurity concentration than the drift layer on each of the plurality of body layers, a gate insulating film formed so as to be in contact with the body layer and the source layer, a gate electrode formed on the gate insulating film, an interlayer insulating film formed so as to cover the gate electrode together with the gate insulating film, a conductive barrier layer provided between a side portion of the interlayer insulating film and a source electrode to prevent passage of hydrogen ions and a silicon carbide semiconductor device including the same.

2. The conductive barrier layer is made of tantalum, tantalum nitride, titanium nitride or amorphous silicon carbide The silicon carbide semiconductor device according to claim 1.

3. The conductive barrier layer is provided so as to cover a side portion of the interlayer insulating film and a part of the source electrode, and an upper surface of the interlayer insulating film is formed so as not to be covered by the conductive barrier layer The silicon carbide semiconductor device according to claim 1.

4. The conductive barrier layer covers a lower end of a side portion of the interlayer insulating film, an end portion of the source electrode on the interlayer insulating film side at an upper portion, and between them, and is formed so as not to cover an upper corner portion of the interlayer insulating film The silicon carbide semiconductor device according to claim 1.

5. In a plan view, an outer end portion at a lower portion of the conductive barrier layer is located inside an outer end portion of the source layer, In a plan view, in a range where the source electrode and the source layer overlap, an upper surface of the source electrode includes a region covered by the conductive barrier layer and a region not covered by the conductive barrier layer The silicon carbide semiconductor device according to claim 1.

Images