Manufacturing method of wiring board

Abstract

To provide a manufacturing method of a wiring board, in which a thickness of a circuit plain conductor layer formed onto a front surface of an insulation layer is larger than that of a signal wiring conductive layer, and a thickness of an electrolyte copper plating film constructing the conductive layer is small.SOLUTION: A method comprises steps of: forming a first plain conductive layer and a signal wiring conductive layer to a first concave part into which a plurality of first plating resits is formed to a front surface of a seed layer of a base part insulation layer; forming a second concave part to the front surface of the seed layer by removing a first plating resist from the seed layer; forming a second plating resist to a second concave part so as to be larger than a thickness of the first plain conductive layer; forming a second plain conductive layer to a third concave part to be formed by a second plaiting resist that is adjacent to the front surface of the first plain conductive layer; exposing a circuit plain conductive layer and a signal wiring conductive layer that are formed by the first plain conductive layer and the second plain conductive layer by removing the second plating resist from the seed layer; and removing the seed layer from the base part insulation layer.SELECTED DRAWING: None

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a wiring board in which the thickness of a circuit plane conductor layer for a ground circuit or a power supply circuit formed on the surface of an insulating layer is larger than the thickness of a signal wiring conductor layer for signals, and the variation in the thickness of the electrolytic copper plating film constituting these conductor layers is small.

Background Art

[0002] By sufficiently supplying power to the mounted semiconductor element, a semiconductor element with a low operating voltage can be stably operated, and a small and high-density wiring board with fine line and space has been proposed. Such a wiring board is formed by disposing a strip-shaped wiring conductor for signals and a plane conductor for grounding or power supply on the same main surface of an insulating layer, and is characterized in that the thickness of the plane conductor is larger than the thickness of the strip-shaped wiring conductor.

[0003] FIG. 3 is a schematic cross-sectional view showing an example of an embodiment of such a wiring board. As shown in FIG. 3, the wiring board includes an insulating layer 1, a conductor layer 2, and a solder resist layer 3. The conductor layer 2 includes a strip-shaped wiring conductor 2a for signals and a plane conductor 2b for grounding or power supply. In order to deposit the plane conductor 2b thicker than the thickness of the strip-shaped wiring conductor 2a, for example, when depositing electrolytic copper plating in the semi-additive method, a direct current power supply is used to perform electrolytic copper plating at a current density greater than 3 (A / dm 2 ) or more (Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the technology disclosed in Patent Document 1, electrolytic copper plating is performed at a high current density in order to deposit the plane conductor 2b thicker than the thickness of the strip-shaped wiring conductor 2a provided on the wiring substrate. For this reason, the variation in the thickness of the electrolytic copper plating film becomes large. As a result, such a wiring substrate cannot supply sufficient power to the semiconductor element mounted on the wiring substrate, so that a semiconductor element with a low operating voltage cannot operate stably.

Means for Solving the Problems

[0006] The method for manufacturing a wiring substrate according to the present invention is a method for manufacturing a wiring substrate having a circuit plane conductor layer and a signal wiring conductor layer in one conductor layer formed on a base insulating layer, comprising: preparing a base insulating layer on which a seed layer is formed; forming a plurality of first plating resists on the surface of the seed layer to form a first recess for forming a first plane conductor layer constituting a part of the circuit plane conductor layer and the signal wiring conductor layer; forming the first plane conductor layer and the signal wiring conductor layer in the first recess; removing the first plating resist from the seed layer to form a second recess for forming a second plating resist on the surface of the seed layer; forming the second plating resist in the second recess to be larger than the thickness of the first plane conductor layer and covering the signal wiring conductor layer; forming a second plane conductor layer constituting a part of the circuit plane conductor layer in a third recess formed by the second plating resist adjacent to the conductor layer surface of the first plane conductor layer; removing the second plating resist from the seed layer to expose the circuit plane conductor layer composed of the first plane conductor layer and the second plane conductor layer and the signal wiring conductor layer; and removing the seed layer from the base insulating layer.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2A

Figure 2B

Figure 2C

Figure 2D

Figure 2E

Figure 2F

Figure 2G

Figure 2H

Figure 3

Embodiments for Carrying Out the Invention

[0008] <Regarding the Wiring Board to be Manufactured by the Present Invention> An embodiment of the wiring board of the present invention will be described with reference to the drawings. In the examples shown in FIGS. 1 to 2, for the dimensions of each member, particularly the dimensions in the height direction, they are described with dimensions different from the actual dimensions in order to better understand the features of the present invention.

[0009] FIG. 1 is a cross-sectional view for explaining an embodiment of a wiring board targeted by the manufacturing method of the wiring board according to the present invention. In FIG. 1, the wiring board 10 may be a substrate with a core, in which a conductor layer composed of a circuit plane conductor layer 11 and a signal wiring conductor layer 12 for signals and a base insulating layer 13 are alternately laminated on one or both sides of a core substrate (not shown). That is, in the wiring board 10, the circuit plane conductor layer 11 and the signal wiring conductor layer 12 for signals are mixed in one conductor layer formed on the base insulating layer 13, and even when the thickness of the circuit plane conductor layer 11 is larger than the thickness of the signal wiring conductor layer 12 for signals, it is characterized in that the variation in the thickness of these conductor layers is small.

[0010] Here, the circuit plane conductor layer 11 may be a ground circuit plane conductor layer 11 or a power supply circuit plane conductor layer 11. As will be described later, the circuit plane conductor layer 11 includes at least a first plane conductor layer 11A formed on the surface of the base insulating layer 13, and a second plane conductor layer 11B, which is an additional conductor layer, formed on the surface of the first plane conductor layer 11A. In addition, when forming conductor layers on both sides of the core substrate, the conductor layers facing each other through the core substrate may be connected via through-hole conductors (not shown).

[0011] Further, the wiring board 10 may be a coreless substrate formed by alternately laminating a conductor layer composed of a circuit plane conductor layer 11 and a signal wiring conductor layer 12 for signals and a base insulating layer 13 on a support plate (not shown) and then removing the support plate. As shown in FIG. 1, in any case, the wiring board 10 includes at least the outermost base insulating layer 13 among the base insulating layers, and the circuit plane conductor layer 11 and the signal wiring conductor layer 12 for signals are mixed and formed in one conductor layer on the base insulating layer 13. Note that, although there are many cases where a plurality of other conductor layers composed of the circuit plane conductor layer 11 and the signal wiring conductor layer 12 for signals and the base insulating layer 13 are alternately provided below the base insulating layer 13, they are omitted in the figure.

[0012] One conductor layer formed on the base insulating layer 13 consists of a circuit plane conductor layer 11 and a signal wiring conductor layer 12 for signals. The conductor layer consisting of the circuit plane conductor layer 11 and the signal wiring conductor layer 12 formed on the base insulating layer 13 may be composed of, for example, an electrolytic copper plating film formed by a well-known semi-additive method or the like. The circuit plane conductor layer 11 is used for potential supply or power supply and functions as a plurality of conductors for grounding or power supply. The circuit plane conductor layer 11 has a certain thickness T1 and may have a wide rectangular shape with a width L1 when viewed from the upper surface of the wiring substrate 10. Also, the circuit plane conductor layer 11 has a certain thickness T1. The thickness T1 of the circuit plane conductor layer 11 is uniform and has extremely little variation. The thickness T1 of the circuit plane conductor layer 11 may be 20 to 50 μm, preferably 30 to 40 μm. The width L1 of the circuit plane conductor layer 11 can be appropriately set according to the use of the circuit plane conductor layer 11. The width L1 of the circuit plane conductor layer 11 may be, for example, 1 to 50 μm.

[0013] The signal wiring conductor layer 12 functions as a plurality of conductors for transmitting electrical signals. The signal wiring conductor layer 12 may be a strip-shaped signal wiring when viewed from the upper surface of the wiring substrate 10. The signal wiring conductor layer 12 has a certain thickness. The thickness T2 of the signal wiring conductor layer 12 is uniform and has extremely little variation. The thickness T2 of the signal wiring conductor layer 12 may be 5 to 30 μm. The width of the signal wiring conductor layer is represented by L2 and can be appropriately set. The width L2 of the signal wiring conductor layer 12 may be, for example, 1 to 10 μm.

[0014] The base insulating layer 13 can be formed of, for example, a resin composition containing an inorganic filler such as silica or alumina and an epoxy resin. Thus, in the wiring board 10, the circuit plane conductor layer 11 and the signal wiring conductor layer 12 for signals are mixed in one conductor layer formed on the base insulating layer 13, the thickness variation of these conductor layers is small, and the thickness T1 of the circuit plane conductor layer 11 is 1.5 to 3.0 times the thickness T2 of the signal wiring conductor layer 12 for signals.

[0015] Therefore, in the wiring board 10 according to the present invention, no noise is generated even when the operating voltage of the semiconductor element is lowered, and sufficient power supply can be executed. Since the thickness T1 of the circuit plane conductor layer 11 of the wiring board 10 is larger than the thickness T2 of the signal wiring conductor layer 12 for signals, wiring with a fine line and space can be formed, and miniaturization thereof can also be achieved.

[0016] Note that a solder resist layer (not shown) can also be provided on the surface of the base insulating layer 13, which is the outermost one among at least one layer of base insulating layers 13 provided in the wiring board 10, and on the surface of the conductor layer in which the circuit plane conductor layer 11 and the signal wiring conductor layer 12 formed on the base insulating layer 13 are mixed.

[0017] <An embodiment of a method for manufacturing a wiring board according to the present invention> Figs. 2A to 2H are cross-sectional views for explaining an embodiment of a method for manufacturing a wiring board according to the present invention. Hereinafter, an embodiment of a method for manufacturing a wiring board according to the present invention will be described with reference to Figs. 2A to 2H.

[0018] First, as shown in FIG. 2A, prepare a base insulating layer 13 on which a seed layer 14 is formed. That is, the seed layer 14 is formed on the upper surface which is the surface of the base insulating layer 13. The seed layer 14 may be formed not only on the upper surface of the base insulating layer 13 but also on the upper and lower surfaces which are its surfaces. The base insulating layer 13 is a resin composition containing an inorganic filler such as silica or alumina and an epoxy resin, and specifically, it may be an electrical insulating material obtained by impregnating a glass cloth with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. The seed layer 14 may be formed from an electroless copper plating film after roughening the surface of the base insulating layer 13 with a permanganic acid solution.

[0019] Next, as shown in FIG. 2B, form a plurality of first plating resists 15 on the surface of the seed layer 14 of the base insulating layer 13. The first plating resist 15 may be composed of, for example, a first plating resist 15A, a first plating resist 15B, and a first plating resist 15C. The seed layer surface 14A, the first plating resist 15A, and the first plating resist 15B form a first recess 16A for forming a first plane conductor layer 11A which is a part of the circuit plane conductor layer 11. On the other hand, the seed layer surface 14B, the first plating resist 15B, and the first plating resist 15C form a first recess 16B for forming the signal wiring conductor layer 12.

[0020] The first recess 16A for forming the first plane conductor layer 11A is formed from the first plating resist 15A, the first plating resist 15B, and the seed layer surface 14A. That is, the first recess 16A has the seed layer surface 14A of the seed layer 14 as its bottom surface, and is formed from the right side wall surface of the adjacent first plating resist 15A and the left side wall surface of the first plating resist 15B facing the right side wall surface of the first plating resist 15A. On the other hand, the first recess 16B for forming the signal wiring conductor layer 12 is formed from the first plating resist 15B, the first plating resist 15C, and the seed layer surface 14B. That is, the first concave portion 16B is formed with the seed layer surface 14B of the seed layer 14 as the bottom surface, the right side wall surface of the adjacent first plating resist 15B, and the left side wall surface of the first plating resist 15C facing the right side wall surface of the first plating resist 15B.

[0021] The interval formed between the right side wall surface of the first plating resist 15A and the left side wall surface of the first plating resist 15B facing the right side wall surface of the first plating resist 15A corresponds to the length in the width direction of the circuit plane conductor layer 11, which is the ground circuit plane conductor layer width or the power supply circuit plane conductor layer width. The interval formed between the right side wall surface of the first plating resist 15A and the left side wall surface of the first plating resist 15B can be appropriately set according to the form of the first plane conductor layer 11A that constitutes a part of the circuit plane conductor layer 11. The interval formed between the wall surface of the first plating resist 15A and the wall surface of the first plating resist 15B can be set to 1 to 50 μm according to the ground circuit plane conductor layer width or the power supply circuit plane conductor layer width L1, which is the form of the first plane conductor layer 11A.

[0022] The interval formed between the right side wall surface of the first plating resist 15B and the left side wall surface of the first plating resist 15C facing the right side wall surface of the first plating resist 15B corresponds to the length in the width direction of the signal wiring conductor layer 12, which is the signal wiring conductor layer width. The interval formed between the wall surface of the first plating resist 15B and the wall surface of the first plating resist 15C can be appropriately set according to the form of the signal wiring conductor layer 12, which is the signal wiring conductor layer width. The interval formed between the wall surface of the first plating resist 15B and the wall surface of the first plating resist 15C can be set to 1 to 10 μm according to the signal wiring conductor layer width L2 of the signal wiring conductor layer 12.

[0023] Next, as shown in FIG. 2C, a first plane conductor layer 11A is formed in the first recess 16A, and a signal wiring conductor layer 12 is formed in the first recess 16B. That is, with the seed layer surface 14A of the seed layer 14 as the bottom surface, a first plane conductor layer 11A made of an electrolytic copper plating film is formed inside the first recess 16A formed from the right side wall surface of the first plating resist 15A, which is the first plating resist 15 adjacent thereto, and the left side wall surface of the first plating resist 15B, and serves as the base of the circuit plane conductor layer 11. Also, with the seed layer surface 14B of the seed layer 14 as the bottom surface, a signal wiring conductor layer 12 made of an electrolytic copper plating film is formed inside the first recess 16B formed from the right side wall surface of the first plating resist 15B, which is the first plating resist 15 adjacent thereto, and the left side wall surface of the first plating resist 15C.

[0024] The thickness of the first plane conductor layer 11A formed inside the first recess 16A may be 5 to 30 μm, preferably 20 to 25 μm. The thickness of the first plane conductor layer 11A formed inside the first recess 16A corresponds to a part of the thickness of the circuit plane conductor layer 11. Also, the thickness T2 of the signal wiring conductor layer 12 formed inside the first recess 16B may be 5 to 30 μm, preferably 7 to 10 μm. The thickness of the first plane conductor layer 11A, which serves as the base of the circuit plane conductor layer 11, may be the same as or different from the thickness T2 of the signal wiring conductor layer 12, but it is preferably the same.

[0025] Here, a direct current is used to deposit the electrolytic copper plating film constituting the first plane conductor layer 11A and the signal wiring conductor layer 12. The first current density of the direct current applied to form the electrolytic copper plating film constituting the first plane conductor layer 11A and the signal wiring conductor layer 12 is preferably 0.8 to 1.5 A / dm 2 That is preferred. That is, in the method for manufacturing a wiring board according to the present invention, the first current density of the direct current used to deposit the electrolytic copper plating film constituting the first plane conductor layer 11A and the signal wiring conductor layer 12 is set extremely lower than the current density of the direct current employed to form the electrolytic copper plating film as the prior art.

[0026] Therefore, in the method for manufacturing a wiring board according to the present invention, the variation in the thickness of the electrolytic copper plating film forming the first plane conductor layer 11A that constitutes a part of the circuit plane conductor layer 11 included in the wiring board 10 becomes small. Similarly, the variation in the thickness of the electrolytic plating film forming the signal wiring conductor layer 12 included in the wiring board 10 also becomes small. Note that the time for applying the direct current used to deposit the electrolytic copper plating films constituting the first plane conductor layer 11A and the signal wiring conductor layer 12 only needs to be able to form a predetermined thickness of the first plane conductor layer 11A and a predetermined thickness of the signal wiring conductor layer 12, and can be appropriately set according to the forms of the circuit plane conductor layer 11 and the signal wiring conductor layer 12.

[0027] Next, as shown in FIG. 2D, by removing the first plating resists 15A to 15C formed on the surface of the seed layer 14 of the base insulating layer 13 from the seed layer 14, second recesses 16C to 16E for forming second plating resists 17A and 17B on the surface of the seed layer 14 are formed. That is, by removing the first plating resist 15A, the first plating resist 15B, and the first plating resist 15C from the surface of the seed layer 14, a seed layer surface 14C, a seed layer surface 14D, and a seed layer surface 14E of the seed layer 14 are exposed on the surface of the seed layer 14. Furthermore, by removing the first plating resist 15A, the first plating resist 15B, and the first plating resist 15C from the surface of the seed layer 14 of the base insulating layer 13, a second recess 16C is formed with the seed layer surface 14C of the seed layer 14 as the bottom surface and including the left side wall surface of the first plane conductor layer 11A. A second recess 16D is formed with the seed layer surface 14D of the seed layer 14 as the bottom surface and including the right side wall surface of the first plane conductor layer 11A and the left side wall surface of the signal wiring conductor layer 12, and a second recess 16E is formed with the seed layer surface 14E of the seed layer 14 as the bottom surface and including the right side wall surface of the signal wiring conductor layer 12. Then, the first plane conductor layer 11A and the signal wiring conductor layer 12 are exposed on the surface of the seed layer 14.

[0028] Next, as shown in FIG. 2E, second plating resists 17A and 17B are formed in the second recesses 16C to 16E to be larger than the thickness of the first plane conductor layer 11A so as to cover the signal wiring conductor layer 12. That is, with the seed layer surface 14C of the seed layer 14 as the bottom surface, the second plating resist 17A is formed in the second recess 16C formed including the left side wall surface of the first plane conductor layer 11A. Here, the thickness of the second plating resist 17A is formed to be larger than the thickness of the first plane conductor layer 11A.

[0029] Furthermore, with the seed layer surface 14D of the seed layer 14 as the bottom surface, the second recess 16D is formed including the right side wall surface of the first plane conductor layer 11A and the left side wall surface of the signal wiring conductor layer 12. Also, with the seed layer surface 14E of the seed layer 14 as the bottom surface, the second recess 16E is formed including the right side wall surface of the signal wiring conductor layer 12. Then, the second plating resist 17B is formed so as to cover and surround all of the left side wall surface, upper surface, and right side wall surface of the signal wiring conductor layer 12 in the second recess 16D and the second recess 16E. As a result, the second plating resist 17B has reverse recesses with respect to the seed layer surfaces 14D and 14E which are the surfaces of the seed layer 14 of the base insulating layer 13. The reverse recesses that the second plating resist 17B has correspond to the cross-sectional shape of the signal wiring conductor layer 12. The thickness of the second plating resist 17A and the thickness of the second plating resist 17B are formed to be larger than the thickness of the first plane conductor layer 11A. Note that the thickness of the second plating resist 17A may be the same as the thickness of the second plating resist 17B.

[0030] Next, as shown in FIG. 2F, with the conductor layer surface S of the first plane conductor layer 11A as the bottom surface, a second plane conductor layer 11B made of an electrolytic copper plating film is formed as an additional conductor layer in the third recess 18 formed including the right side wall surface of the second plating resist 17A and the left side wall surface of the second plating resist 17B. The second plane conductor layer 11B formed in the third recess 18 constitutes a part of the circuit plane conductor layer 11 by being added to the first plane conductor layer 11A. That is, the second plane conductor layer 11B serves as an additional conductor layer that constitutes the circuit plane conductor layer 11. The thickness of the second plane conductor layer 11B may be 10 to 30 μm, preferably 20 to 25 μm. The second plane conductor layer 11B is integrated with the first plane conductor layer 11A to constitute the circuit plane conductor layer 11.

[0031] In this way, the electrolytic copper plating film constituting the second plane conductor layer 11B is added to the electrolytic copper plating film constituting the first plane conductor layer 11A. Here, a direct current is used to form the electrolytic copper plating film constituting the second plane conductor layer 11B. The second current density of the direct current used to form the electrolytic copper plating film constituting the second plane conductor layer 11B may be slightly higher than the first current density, and is preferably 1.0 to 1.5 A / dm 2 is preferred. That is, in the method for manufacturing a wiring board according to the present invention, the second current density adopted to form the electrolytic copper plating film constituting the second plane conductor layer 11B, which is added as an additional conductive layer to the first plane conductor layer 11A constituting a part of the circuit plane conductor layer 11, is set lower than the current density adopted to form the electrolytic copper plating film as a conventional technique. Therefore, in the method for manufacturing a wiring board according to the present invention, the variation in the thickness of the electrolytic copper plating film forming the second plane conductor layer 11B, which constitutes a part of the circuit plane conductor layer 11 included in the wiring board 10, is reduced. In this way, in the method for manufacturing a wiring board according to the present invention, the first plane conductor layer 11A, the signal wiring conductor layer 12, and the second plane conductor layer 11B are formed from an electrolytic copper plating film, and the electrolytic plating film is deposited by a direct current of a current density of 0.8 to 1.5 A / dm 2 As a result, the variation in the thickness of all the electrolytic copper plating films forming the first plane conductor layer 11A, the signal wiring conductor layer 12, and the second plane conductor layer 11B constituting the circuit plane conductor layer 11 is reduced.

[0032] The application time of the direct current used for depositing the electrolytic copper plating film constituting the second plane conductor layer 11B can be appropriately set according to the form of the plane conductor layer 11 for the circuit. The application time of the direct current used for forming the electrolytic copper plating film constituting the second plane conductor layer 11B can be set, for example, to 5 to 30 minutes. The application time of the direct current used for depositing the electrolytic copper plating film constituting the second plane conductor layer 11B may be the same as or different from the application time of the direct current used for depositing the electrolytic copper plating film constituting the first plane conductor layer 11A. Also, when making the thickness of the electrolytic copper plating film of the second plane conductor layer 11B larger than the thickness of the electrolytic copper plating film of the first plane conductor layer 11A, the application time of the direct current used for depositing the electrolytic copper plating film constituting the second plane conductor layer 11B may be set longer than the application time of the direct current used for depositing the electrolytic copper plating film of the first plane conductor layer 11A.

[0033] When the second plane conductor layer 11B is deposited on the conductor layer surface S of the first plane conductor layer 11A, the interface between the first plane conductor layer 11A and the second plane conductor layer 11B becomes the bonding interface of these conductor layers. As a result, a circuit plane conductor layer 11 in which the first plane conductor layer 11A and the second plane conductor layer 11B are integrated is formed. The thickness of the first plane conductor layer 11A and the thickness of the second plane conductor layer 11B may be the same or different and can be appropriately set.

[0034] Next, as shown in FIG. 2G, by removing the second plating resists 17A and 17B from the seed layer 14, the circuit plane conductor layer 11 composed of the first plane conductor layer 11A and the second plane conductor layer 11B and the signal wiring conductor layer 12 are exposed. That is, the second plating resist 17A and the second plating resist 17B are removed from the surface of the seed layer 14 of the base insulating layer 13. As a result, on the surface of the seed layer 14, the circuit plane conductor layer 11 formed by integrating the first plane conductor layer 11A and the second plane conductor layer 11B and the signal wiring conductor layer 12 are exposed. Also, by removing the second plating resist 17A and the second plating resist 17B from the surface of the seed layer 14, the seed layer surfaces 14C, 14D, and 14E formed in the lower layers of the second plating resist 17A and the second plating resist 17B are exposed again.

[0035] Finally, as shown in FIG. 2H, the seed layer 14 formed in the base insulating layer 13 is removed. The seed layer 14 is removed by etching. As a result, the base insulating layer 13 is exposed. On the surface of the base insulating layer 13, a circuit plane conductor layer 11 formed from the first plane conductor layer 11A and the second plane conductor layer 11B and a signal wiring conductor layer 12 for signals are formed. The ratio of the thickness of the circuit plane conductor layer 11 composed of the first plane conductor layer 11A and the second plane conductor layer 11B which is an additional conductor layer to the thickness of the signal wiring conductor layer 12 can be set to 1.5 to 3.0. That is, in the manufacturing method of the wiring board according to the present invention, without increasing the electrolytic density of the direct current used to deposit the electrolytic copper plating film constituting the circuit plane conductor layer 11 in order to increase the thickness of the circuit plane conductor layer 11, by adding the second plane conductor layer 11B having a role as an additional layer body layer to the first plane conductor layer 11A, the thickness of the circuit plane conductor layer 11 can be ensured to be large.

[0036] In this way, according to the manufacturing method of the wiring board according to the present invention, in one conductor layer formed on the base insulating layer 13, a circuit plane conductor layer 11 composed of a first plane conductor layer 11A serving as a base conductor layer and a second plane conductor layer 11B serving as an additional conductor layer and a signal wiring conductor layer 12 are mixed, and there is almost no variation in the thickness of these conductor layers, and moreover, a wiring board 10 can be manufactured in which the thickness of the circuit plane conductor layer 11 is large with respect to the thickness of the signal wiring conductor layer 12 for signals.

[0037] In the manufacturing method of the wiring board according to the present invention described above, after forming a first plane conductor layer and a signal wiring conductor layer made of an electrolytic copper plating film under electrolytic conditions with a low current density on the surface of the base insulating layer, a second plane conductor layer is further added to the first plane conductor layer to form a circuit plane conductor layer composed of the first plane conductor layer and the second plane conductor layer in one conductor layer. Therefore, in the manufacturing method of the wiring board according to the present invention, the thickness of the circuit plane conductor layer can be made larger than the thickness of the signal wiring conductor layer. Moreover, since the deposition of the electrolytic copper plating film constituting the circuit plane conductor layer and the signal wiring conductor layer can be performed under conditions of low current density in such a manufacturing method of the wiring board, a wiring board with a small variation in the thickness of the electrolytic copper plating film constituting the conductor layer can be manufactured.

Explanation of Reference Numerals

[0038] 10 Wiring board 11 Circuit plane conductor layer (for ground circuit or power supply circuit) 11A First plane conductor layer 11B Second plane conductor layer 12 Signal wiring conductor layer 13 Base insulating layer L1 Width of circuit plane conductor layer L2 Width of signal wiring conductor layer T1 Thickness of circuit plane conductor layer T2 Thickness of signal wiring conductor layer 14 Seed layer 14A~E Seed layer surface 15 First plating resist 15A First plating resist (left side) 15B First plating resist (center) 15C First plating resist (right side) 16 First recess 16A First recess (for first plane conductor layer) 16B First recess (for signal wiring conductor layer) 16C Second recess (for second plating resist) 16D Second recess (for second plating resist) 16E Second recess (for second plating resist) 17A Second plating resist (left side) 17B Second plating resist (right side) S Surface of the first plane conductor layer 18 Third recess (for second plane conductor layer)

Claims

1. A method for manufacturing a wiring board having a circuit plane conductor layer and a signal wiring conductor layer in one conductor layer formed on a base insulating layer, comprising: preparing a base insulating layer on which a seed layer is formed; forming a plurality of first plating resists on the surface of the seed layer to form a first recess for forming a first plane conductor layer that constitutes a part of the circuit plane conductor layer and the signal wiring conductor layer; forming the first plane conductor layer and the signal wiring conductor layer in the first recess; removing the first plating resist from the seed layer to form a second recess for forming a second plating resist on the surface of the seed layer; forming the second plating resist in the second recess to be larger than the thickness of the first plane conductor layer and covering the signal wiring conductor layer; forming a second plane conductor layer that constitutes a part of the circuit plane conductor layer in a third recess formed by the second plating resist adjacent to the conductor layer surface of the first plane conductor layer; removing the second plating resist from the seed layer to expose the circuit plane conductor layer composed of the first plane conductor layer and the second plane conductor layer and the signal wiring conductor layer; removing the seed layer from the base insulating layer. A method for manufacturing a wiring board.

2. The method for manufacturing a wiring board according to claim 1, The first plane conductor layer, the signal wiring conductor layer, and the second plane conductor layer are formed from an electrolytic copper plating film, and the electrolytic plating film is deposited by a direct current of 0.8 to 1.5 A / dm ２ of a wiring board manufacturing method deposited by a direct current of

3. The method for manufacturing a wiring board according to claim 1, wherein a ratio of a thickness of the circuit plane conductor layer composed of the first plane conductor layer and the second plane conductor layer to a thickness of the signal wiring conductor layer is 1.5 to 3.

0. A method for manufacturing a wiring board.

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