Cell multiplex inverter

Abstract

To provide s cell multiplex inverter that comprises a plurality of cells connected in multiplexed form to each phase of an AC system through star connection, and even when an imbalance has occurred in AC voltages or when an imbalanced AC voltage is to be intentionally outputted, that can eliminate a need of providing a cell to a corresponding phase or increasing a cell DC voltage only in the corresponding phase, and furthermore, that can suppress a common mode current.SOLUTION: Phase voltage detection signals vU, vV, vW or a voltage command values vU*, vV*, vW* are converted into values on rotating coordinates synchronous with a system frequency and values on rotating coordinates in a reverse direction to the system frequency so as to extract DC components. On the basis of a normal-phase d-axis component V1d, a normal-phase q-axis component V1q, a reverse-phase d-axis component V2q, and a reverse-phase q-axis component V2q, all of which are DC components, a zero-phase-voltage d-axis component V0d and a zero-phase-voltage q-axis component V0q are calculated. The zero-phase-voltage d-axis component V0d and the zero-phase-voltage q-axis component V0q are multiplied by a cosine wave and by a sine wave, and then the results are added together, and the resulting value is added to the voltage command values vU*, vV*, vW*, to thereby obtain corrected voltage command values vU*', vV*', vW*'.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a cell multi-inverter in which a plurality of cells are connected in multiple in a star connection to each phase of an AC system.

Background Art

[0002] As an example of a cell multi-inverter, a modular multi-level cascade converter (MMCC) of a single-star bridge cell (SSBC) connected to a three-phase AC system is known. Also known is a configuration in which a separate power source, a DC / DC converter, etc. are connected to the DC side of the full-bridge cell of the MMCC-SSBC.

[0003] As a main example of this configuration, there is a solid state transformer (SST) as in Patent Document 1, for example. Fig. 1 shows an SST composed of three cells per phase, which combines an MMCC-SSBC and a dual active bridge (DAB) type bidirectional isolated DC / DC converter.

[0004] High-voltage AC power can be converted into DC power by cells connected in series, the DC power can be converted into high-frequency AC power, and then converted into DC power by insulation and rectification with a transformer. Reverse power flow is also possible. Since the SST uses a high-frequency transformer, it can be made smaller than a conventional commercial frequency transformer.

[0005] Also, as another application, the high-voltage multi-inverter of Patent Document 2 is applicable.

[0006] When connecting to an unbalanced three-phase AC system with an SST, or when intentionally outputting an unbalanced three-phase AC voltage with a high-voltage multi-inverter, the phase voltage amplitude of a certain phase increases, and the AC voltage that the cell connected to the corresponding phase should output also increases.

[0007] To cope with this, it is necessary to increase the DC voltage of the cell, but this also leads to an increase in the withstand voltage required for the components, resulting in an increase in cost and size. Using a switching device with a high withstand voltage for the cell also causes an increase in losses.

[0008] In addition, depending on the device, there may be cases where operation is required to continue even if some cells fail.

[0009] Patent Document 1 discloses the main circuit configuration of an SST, and Patent Document 2 discloses the configuration of a high-voltage multi-inverter.

[0010] Patent Documents 3 and 4 disclose methods for continuing operation when a cell fails. In both documents, a short circuit of the first failed cell is performed. However, this alone causes a decrease in the amplitude of the AC voltage that can be output in the phase with the failed cell. Therefore, in Patent Document 3, a spare cell prepared in advance for the corresponding phase is inserted. In Patent Document 4, the DC voltage of the non-failed cells in the corresponding phase is increased.

[0011] Patent Documents 5 and 6 disclose techniques for coping with voltage imbalance by using a zero-phase voltage in an MMCC-SSBC. The purpose of this technique is to balance the capacitor voltages of each cell.

[0012] Patent Document 7 is a technique for reducing the peak of the voltage command value by superimposing a zero-phase voltage on the voltage command value of a single-machine three-phase inverter that does not perform cell multiplexing. It can also cope with the case of outputting an unbalanced three-phase AC voltage and equalize the voltage command value peaks of each phase. The technique of Patent Document 7 can be applied to an MMCC-SSBC and a high-voltage multi-inverter.

Prior Art Documents

Patent Documents

[0013]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0014] However, Patent Documents 1 and 2 do not particularly mention the connection to an unbalanced system, the output of unbalanced voltage, or the countermeasures when a cell fails.

[0015] In Patent Document 3, it is necessary to incorporate a spare cell into the device, and a switch for turning on the spare cell is also required, which increases the cost and size. If no failure occurs, the spare cell may not be used and may be wasted.

[0016] In Patent Document 4, in order to increase the DC voltage of other cells in the corresponding phase, a cell design based on this is required, which causes problems such as increased cost, size, and losses. Also, neither Patent Document 3 nor 4 describes a method for dealing with voltage imbalance.

[0017] In Patent Documents 5 and 6, only capacitors are connected to the DC side of each cell, and applications that do not handle active power such as reactive power compensation devices are assumed. However, in high-voltage multi-level inverters and SSTs, there is a separate path for active power to pass through. Therefore, power sharing between cells can be performed using this path to balance the capacitor voltage. As a result, the importance of the technologies in Patent Documents 5 and 6 is reduced. Also, neither Patent Document 5 nor 6 describes a method for dealing with cell failure.

[0018] In Patent Document 7, harmonics that are odd multiples of 3 are superimposed as zero-phase voltage. However, the higher the frequency of the superimposed zero-phase voltage, the larger the common-mode current flows through the stray capacitance of the circuit. This may cause many problems such as increased heat generation of components, reduced efficiency, malfunction of the ground fault detector, breakdown of the insulation of the high-frequency transformer, and electromagnetic interference to other devices. Therefore, it is necessary to lower the frequency of the superimposed zero-phase voltage. Also, Patent Document 7 does not describe a method for dealing with cell failures.

[0019] From the above, in a cell multi-inverter in which a plurality of cells are connected in multiple in a star connection to each phase of an AC system, even when an imbalance occurs in the AC voltage or when an intentionally unbalanced AC voltage is output, it is necessary to eliminate the need to turn on the cell in the corresponding phase and to raise the DC voltage of the cell only in the corresponding phase, and further suppress the common-mode current.

Means for Solving the Problems

[0020] The present invention has been devised in view of the above-described conventional problems. One aspect thereof is a cell multi-inverter including a plurality of cells connected in multiple in a star connection to each phase of an AC system and having a full-bridge circuit on the AC system side, a correction voltage command value generation unit that generates a correction voltage command value by superimposing a zero-phase voltage having the same frequency as the fundamental wave on a voltage command value, and a gate signal generation unit that generates a gate signal of the full-bridge circuit based on the correction voltage command value. The correction voltage command value generation unit is characterized in that the zero-phase voltage having the same frequency as the fundamental wave is superimposed on the voltage command value so that the amplitude difference of the correction voltage command values of each phase becomes small.

[0021] In another aspect, a cell multilevel inverter includes a plurality of cells that are star-connected in multiple phases to each phase of an AC system and have a full-bridge circuit on the AC system side, a correction voltage command value generation unit that generates a correction voltage command value by superimposing a zero-phase voltage having the same frequency as the fundamental wave on a voltage command value, and a gate signal generation unit that generates a gate signal for the full-bridge circuit based on the correction voltage command value. The correction voltage command value generation unit superimposes the zero-phase voltage having the same frequency as the fundamental wave such that the value obtained by multiplying the amplitude of the correction voltage command value of each phase by the number of cells in each phase and dividing by the number of cells operating without failure in each phase has a small difference among the three phases.

[0022] In one aspect, the correction voltage command value generation unit includes a phase output unit that outputs a phase ωt synchronized with the AC voltage of the system, a first dq converter that converts a value obtained by multiplying the phase voltage detection signal or the voltage command value, or the phase voltage detection signal or the voltage command value by a coefficient obtained by dividing the number of cells in each phase by the number of cells operating without failure in each phase into a value on a rotating coordinate synchronized with the system frequency, a second dq converter that converts a value obtained by multiplying the phase voltage detection signal or the voltage command value, or the phase voltage detection signal or the voltage command value by a coefficient obtained by dividing the number of cells in each phase by the number of cells operating without failure in each phase into a value on a rotating coordinate rotating in the opposite direction to the system frequency, an arithmetic unit that calculates a zero-phase voltage d-axis component and a zero-phase voltage q-axis component for equalizing the AC-side output voltages of the cells based on a positive-phase d-axis component and a positive-phase q-axis component obtained by extracting a DC component from the output of the first dq converter and a negative-phase d-axis component and a negative-phase q-axis component obtained by extracting a DC component from the output of the second dq converter, a first multiplier that multiplies the zero-phase voltage d-axis component by cosωt or sinωt, a second multiplier that multiplies the zero-phase voltage q-axis component by sinωt when the first multiplier multiplies by cosωt and multiplies the zero-phase voltage q-axis component by cosωt when the first multiplier multiplies by sinωt, a first adder that adds the output of the first multiplier and the output of the second multiplier, and a second adder that adds the output of the first adder to the voltage command value and outputs the result as the correction voltage command value.

[0023] Also, as one aspect thereof, the arithmetic unit is characterized by calculating the zero-phase voltage d-axis component and the zero-phase voltage q-axis component based on equation (3).

[0024]

Number

[0025] V 0d : Zero-phase voltage d-axis component V 0q : Zero-phase voltage q-axis component V 1d : Positive-phase voltage d-axis component V 1q : Positive-phase voltage q-axis component V 2d : Negative-phase voltage d-axis component V 2q : Negative-phase voltage q-axis component.

[0026] Also, as another aspect, the arithmetic unit is characterized by calculating the zero-phase voltage d-axis component and the zero-phase voltage q-axis component based on equation (4).

[0027]

Number

[0028] V 0d : Zero-phase voltage d-axis component V 0q : Zero-phase voltage q-axis component V 1d : Positive-phase voltage d-axis component V 1q : Positive-phase voltage q-axis component V 2d : Negative-phase voltage d-axis component V 2q : Negative-phase voltage q-axis component.

[0029] Also, as another aspect, the arithmetic unit is characterized by calculating the zero-phase voltage d-axis component and the zero-phase voltage q-axis component based on equation (5).

[0030]

Number

[0031] V 0d : Zero-phase voltage d-axis component V 0q : Zero-phase voltage q-axis component V 2d : Reverse-phase voltage d-axis component V 2q : Reverse-phase voltage q-axis component V1: Positive-phase voltage component.

[0032] Also, as one aspect thereof, the corrected voltage command value generation unit, when the reverse-phase d-axis component V 2d = V 1d , and the reverse-phase q-axis component is V 2q = 0, sets the zero-phase voltage d-axis component V 0d = -V 1d / 2, the zero-phase voltage q-axis component V 0q = 0, and when the reverse-phase d-axis component V 2d = -V 1d / 2, and the reverse-phase q-axis component is V 2q = -√3V 1d , sets the zero-phase voltage d-axis component V 0d = V 1d / 4, the zero-phase voltage q-axis component V 0q = √3V 1d / 4, and when the reverse-phase d-axis component V 2d = -V 1d / 2, and the reverse-phase q-axis component is V 2q = √3V 1d , sets the zero-phase voltage d-axis component V 0d = V 1d / 4, the zero-phase voltage q-axis component V 0q = -√3V 1d / 4, which is characterized in that.

Advantages of the Invention

[0033] According to the present invention, in a cell multi-inverter in which a plurality of cells are connected in series to each phase of an AC system, even when an imbalance occurs in the AC voltage or when an intentionally unbalanced AC voltage is output, there is no need to turn on the cells in the corresponding phase or to raise the DC voltage of the cells only in the corresponding phase, and it is possible to suppress the common mode current.

Brief Description of the Drawings

[0034]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Modes for Carrying Out the Invention

[0035] Hereinafter, Embodiments 1 to 3 of the cell multi-inverter in the present invention will be described in detail with reference to FIGS. 1 to 6.

[0036] [Embodiment 1] First, as an example of a cell multi-inverter, the main circuit configuration of the MMCC-SSBC shown in FIG. 1 will be described.

[0037] As shown in FIG. 1(a), in the U-phase of the AC system AC, cells cellu1, cellu2, and cellu3 are connected in series via the reactor Lu. Similarly, in the V-phase of the AC system AC, cells cellv1, cellv2, and cellv3 are connected in series via the reactor Lv, and in the W-phase of the AC system AC, cells cellw1, cellw2, and cellw3 are connected in series via the reactor Lw. Here, the AC phase voltage (phase voltage detection signal) is v U ,vV , v W shall be set as such.

[0038] The DC terminals of cells cellu1, cellu2, cellu3, cellv1, cellv2, cellv3, cellw1, cellw2, and cellw3 are connected in parallel. Let the DC voltage of cells cellu1 to cellw3 be V DC shall be set as such.

[0039] Fig. 1(b) shows the configuration per cell. One end of switching devices S1 and S3 is connected to one AC terminal of the cell. Also, one end of switching devices S2 and S4 is connected to the other AC terminal of the cell. The other ends of switching devices S1 and S2 are connected to one end of the first capacitor C1. The other ends of switching devices S3 and S4 are connected to the other end of the first capacitor C1. With the above switching devices S1, S2, S3, and S4, a full-bridge circuit provided on the AC system AC side is formed.

[0040] Switching devices S5 and S6 are connected in series between one end and the other end of the first capacitor C1. Also, switching devices S7 and S8 are connected in series between one end and the other end of the first capacitor C1.

[0041] One end of reactor L1 is connected to the connection point of switching devices S5 and S6. One end of reactor L2 is connected to the connection point of switching devices S7 and S8. The primary winding of transformer Tr is connected between the other end of reactor L1 and the other end of reactor L2.

[0042] A second capacitor C2 is connected between one DC terminal and the other DC terminal of the cell. Switching devices S9 and S11 are connected in series between one end and the other end of the second capacitor C2. Also, switching devices S10 and S12 are connected in series between one end and the other end of the second capacitor C2.

[0043] One end of reactor L3 is connected to the connection points of switching devices S9 and S11. One end of reactor L4 is connected to the connection points of switching devices S10 and S12. A secondary winding of transformer Tr is connected between the other ends of reactor L3 and reactor L4. Note that reactors L1 to L4 in Fig. 1(b) may be omitted.

[0044] The cells in Fig. 1(b) adjust the active power to be transferred by adjusting the phase difference of the inverter output voltages on both sides of transformer Tr. Gate signals of switching devices S5 to S12 are generated so that the phase difference of the inverter output voltages on both sides of transformer Tr becomes a desired phase difference (that is, so that the desired active power to be transferred is obtained). Since the gate signals of the switching devices S5 to S12 of the inverters on both sides of transformer Tr are not directly related to the present invention, detailed description thereof is omitted here, and a conventionally known method is used.

[0045] The gate signals “gate” of the switching devices S1 to S4 of the full-bridge circuit provided on the AC side of the AC system AC are input with the gate signals generated according to Embodiment 1 described later.

[0046] Fig. 2 shows another example of the circuit diagram per cell. In this example, an LLC resonant converter is applied as the bidirectional isolation type DC / DC converter.

[0047] As shown in Fig. 2, a third capacitor C3 is connected between the connection points of switching devices S5 and S6 and reactor L1. Also, a fourth capacitor C4 is connected between the connection points of switching devices S7 and S8 and reactor L2. Also, a fifth capacitor C5 is connected between the connection points of switching devices S9 and S11 and reactor L3. Also, a sixth capacitor C6 is connected between the connection points of switching devices S10 and S12 and reactor L4.

[0048] The NOT circuit 26 inverts a signal with a duty ratio of 50%. The dead time section 27 inserts dead time into the signal with a duty ratio of 50% and the signal obtained by inverting the signal with a duty ratio of 50%, and outputs it to the switching devices S5 to S12 of the inverters on both sides of the transformer Tr as a gate signal. Other circuit configurations are the same as those in Fig. 1(b).

[0049] In Fig. 2, the third to sixth capacitors C3 to C6 are connected in series to the transformer (high-frequency transformer) Tr. As a result, resonance occurs between the leakage inductance of the transformer Tr and the reactors L1 to L4 connected in series separately. The inverters on both sides of the transformer Tr output an AC voltage at this resonance frequency. The duty ratio of the gate signals for driving the inverters on both sides of the transformer Tr is fixed at 50%. As a result, the active power corresponding to the difference in the DC voltages on both sides of the transformer Tr is transferred through the transformer Tr. Since the gate signals of the switching devices S5 to S12 of the inverters on both sides of the transformer Tr are not directly related to the present invention, detailed description thereof is omitted here.

[0050] The gate signals “gate” of the switching devices S1 to S4 of the full-bridge circuit provided on the AC side of the AC power system are input with the gate signals generated according to Embodiment 1 described later.

[0051] Fig. 3 shows a block diagram of the corrected voltage command value generation unit of Embodiment 1. In Embodiment 1, the voltage duties of each cell are equalized in applications where it is not necessary to equalize the power duties of each cell.

[0052] The phase output unit (for example, PLL: Phase-Locked Loop) 1 outputs a phase ωt synchronized with the AC voltage of the power system from the phase voltage detection signals v U , v V , v W of the AC power system.

[0053] The phase voltage detection signals v U , v V , v WIt may detect the line voltage and convert it to the phase voltage by calculation. Also, instead of the phase voltage detection signals v U , v V , v W , the voltage command values v U *, v V *, v W * may be input to the phase output unit 1. Furthermore, the system AC voltage input to the phase output unit 1 may be only one representative phase.

[0054] In the motor drive application of the high-voltage multi-inverter, the phase ωt may be detected from a rotary encoder, resolver, etc., or the phase ωt estimated by an observer, etc. may be used. Hereinafter, the phase output unit 1 is denoted as PLL1.

[0055] The first low-pass filter 2 removes switching noise, etc. from the phase voltage detection signals v U , v V , v W (voltage command values v U *, v V *, v W *).

[0056] The first dq converter 3 converts the phase voltage detection signals v U , v V , v W to which the first low-pass filter 2 is applied into values on a rotating coordinate synchronized with the system frequency based on the phase ωt.

[0057] The second low-pass filters 4 and 5 extract only the DC components from the output of the first dq converter 3. Among the outputs of the second low-pass filters 4 and 5, the d-axis component is the positive-phase d-axis component V U , v V , v W of the phase voltage detection signals v 1d , and the q-axis component is the positive-phase q-axis component V 1q . If PLL1 is operating normally, the positive-phase q-axis component V 1q of the output of the second low-pass filter 5 is zero, so it is not used.

[0058] The second dq converter 6 is for the phase voltage detection signals v to which the first low-pass filter 2 is applied.U , v V , v W is converted into a value on a rotating coordinate that rotates in the direction opposite to the frequency of the system based on the phase - ωt.

[0059] The third low - pass filters 7 and 8 extract only the DC components from the output of the second dq converter 6. The outputs of the third low - pass filters 7 and 8 are the reverse - phase d - axis component V U , v V , v W of the phase voltage detection signals v 2d , and the reverse - phase q - axis component V 2q , respectively.

[0060] The calculator 9 obtains the zero - phase voltage d - axis component V 1d , the zero - phase voltage q - axis component V 1q , the reverse - phase d - axis component V 2d , and the reverse - phase q - axis component V 2q from the obtained positive - phase d - axis component V 0d , positive - phase q - axis component V 0q using the following equation (3). The zero - phase voltage d - axis component V 0d and the zero - phase voltage q - axis component V 0q may also be obtained using equation (4) or (5) instead of equation (3). In this calculator 9, when the amplitudes of the positive - phase component and the reverse - phase component of the AC voltage are approximately equal, V 0d = V 0q = 0 is output.

[0061] The oscillator 10 outputs a sine wave sinωt and a cosine wave cosωt from the phase ωt.

[0062] The first multiplier 11 obtains the product of the zero - phase voltage d - axis component V 0d and the cosine wave cosωt. The second multiplier 12 obtains the product of the zero - phase voltage q - axis component V 0q and the sine wave sinωt.

[0063] The first adder 13 obtains the sum of V 0d cosωt output by the first multiplier 11 and V 0q sinωt output by the second multiplier 12.

[0064] The second adders 14, 15, and 16 add V U *, v V *, v W *, respectively, to the V 0d cosωt + V 0q sinωt obtained by the first adder 13. When the voltage command values v U *, v V *, v W * are given as fixed sine waves, they may be obtained by feedback control of voltage or current. The outputs v U *’, v V *’, v W *’ of the second adders 14, 15, and 16 are the corrected voltage command values.

[0065] The corrected voltage command values v U *’, v V *’, v W *’ generate gate signals (on / off command signals) by carrier triangular wave comparison or the like in the subsequent stage (gate signal generation unit), and are input to the switching devices S1 to S4 of the full-bridge circuits provided on the AC side of the AC system of each cell in FIGS. 1(b) and 2. The above gate signal generation method is disclosed in Patent Document 6.

[0066] In the first embodiment, zero-phase voltage having the same frequency as the fundamental wave is superimposed on the three-phase voltage command values v U *’, v V *’, v W *’ so that the amplitudes of the corrected voltage command values v U *, v V *, v W * of each phase are equal (the difference is small). The zero-phase voltage required for this is obtained by calculation. Assuming that the voltage command values v U *, v V *, v W * are approximately equal to the AC phase voltages (phase voltage detection signals) v U , v V , v W , the AC phase voltages (phase voltage detection signals) v U , v V , v W are defined as in the following equation (1).

[0067]

Number

[0068] Here, V 1d is the positive-phase d-axis component of the AC voltage, V 2d is the negative-phase d-axis component, V 2q is the negative-phase q-axis component. V 1q is the positive-phase q-axis component, which is zero if PLL1 is operating normally.

[0069] V 0d , V 0q are the zero-phase voltage d-axis component and zero-phase voltage q-axis component superimposed according to Embodiment 1. Since the purpose is to equalize the defined amplitudes of the AC voltages, the zero-phase voltage d-axis component V 0d , zero-phase voltage q-axis component V 0q are obtained.

[0070]

Number

[0071] Solving this equation gives Equation (3).

[0072]

Number

[0073] If the positive-phase q-axis component V 1q is close to zero, Equation (3) can be approximated by Equation (4).

[0074]

Number

[0075] If the positive-phase q-axis component V 1q is equal to zero, Equation (3) can be simplified to Equation (5). In Equation (5), V1 represents the positive-phase component of the AC voltage.

[0076]

Number

[0077] Embodiment 1 calculates the necessary zero-phase voltage d-axis component V 0d , zero-phase voltage q-axis component V 0q and superimposes them on the voltage command values v U *, v V *, v W *. First, the AC phase voltage detection signals v U , v V , v W are detected, or the voltage command values v U *, v V *, v W * are directly input, and they are converted into values on a rotating coordinate synchronized with the system frequency to extract the DC components, thereby obtaining the positive-phase d-axis component V 1d , positive-phase q-axis component V 1q . Also, the negative-phase d-axis component V 2d , negative-phase q-axis component V 2q can be obtained by extracting the DC components from the values on a rotating coordinate rotating in the opposite direction to the system frequency.

[0078] After that, the zero-phase voltage d-axis component V 0d , zero-phase voltage q-axis component V 0q are calculated using equation (3), and the zero-phase voltage to be superimposed is obtained from the products of each with the cosine wave cosωt and sine wave sinωt, and added to the voltage command values v U *, v V *, v W *. In grid-connected applications, if the PLL is operating normally, the positive-phase q-axis component V 1q is zero, so the zero-phase voltage d-axis component V 0d , zero-phase voltage q-axis component V 0q can also be calculated using equations (4) and (5).

[0079] In equations (3), (4), and (5), when the denominator is zero, that is, when the amplitudes of the positive-phase voltage and negative-phase voltage are equal, there is no solution, and the voltage command values v U *, v V *, v WThe amplitudes of * cannot be made equal. Therefore, when the amplitudes of the positive-phase voltage and the negative-phase voltage are approximately equal, the zero-phase voltage d-axis component V 0d , and the zero-phase voltage q-axis component V 0q are set to zero.

[0080] According to the first embodiment, in a star-connected cell multilevel inverter such as MMCC-SSBC, even when an imbalance occurs in the AC voltage or when an intentionally unbalanced AC voltage is output, the AC output voltages of the cells can be made equal. As a result, when the voltage amplitude of a certain phase increases, there is no need to turn on the cells in the corresponding phase or only increase the DC voltage of the cells in the corresponding phase. Also, since the superimposed zero-phase voltage is only the fundamental wave component, the common-mode current can be suppressed.

[0081] In the first embodiment, it is necessary to increase or raise the DC voltages of all cells in advance, but compared with the prior art, the increase in the DC voltage can be significantly suppressed, minimizing the increase in the breakdown voltage of the cells and reducing the cost and size.

[0082] Also, in the first embodiment, since the superimposed zero-phase voltage is obtained by feedforward, it can quickly follow even when there are fluctuations in the AC voltage, and the stability of the device is high in principle.

[0083] [Embodiment 2] Fig. 4 shows a block diagram of the correction voltage command value generation unit of the second embodiment. The second embodiment is different from the first embodiment in the following points.

[0084] In the coefficient multiplier 17, the phase voltage detection signals v U , v V , v W (or the voltage command values v U *, v V *, v W *) are multiplied by the coefficients N / n U , N / n V , N / n W . The numerator N of the coefficient is the number of cells in each phase. In the example of Fig. 1, N = 3. The denominator n of the coefficient U , n V,n W is the number of cells operating without failure in each phase. And the phase voltage detection signals v U , v V , v W (or the voltage command values v U *, v V *, v W *) use the values obtained by multiplying these coefficients.

[0085] In the second embodiment, a function of reducing the voltage duty of the phase with a failed cell is added to the first embodiment. The necessary zero-phase voltage would originally need to be obtained by solving equation (6).

[0086]

Equation

[0087] However, in equation (6), the number of variables increases, making it difficult to derive the solution. Moreover, the derived equation becomes very complex, making it difficult to implement in the control program.

[0088] Therefore, coefficients are multiplied by the phase voltage detection signals v U , v V , v W to make the AC voltage of the phase including the failed cell appear larger according to the number of failed cells, and the direct-axis component V 1d , quadrature-axis component V 1q , inverse direct-axis component V 2d , inverse quadrature-axis component V 2q are obtained and substituted into equation (3) to approximately obtain the necessary zero-phase voltage direct-axis component V 0d , zero-phase voltage quadrature-axis component V 0q .

[0089] By superimposing this zero-phase voltage direct-axis component V 0d , zero-phase voltage quadrature-axis component V 0q on the voltage command values v U *, v V *, v W *, the amplitude of the voltage command value of the phase with the failed cell can be reduced. Here, as an example of the coefficients, N / n U, N / n V , N / n W is used.

[0090] The effect of Embodiment 2 will be described with reference to FIG. 5. FIG. 5(a) shows the phasor diagram of the voltage command value when the number of cells in each phase is N = 3 and the AC voltage is three-phase balanced and there is no reverse-phase voltage (V 2d = V 2q = 0).

[0091] Here, consider the case where one cell in the U phase fails and n U = 2. FIG. 5(b) shows the case of maintaining the line voltage by applying Patent Document 4. The remaining two cells in the U phase need to output an AC voltage 1.5 times as large. To cope with this, the DC voltage of the U-phase cells also needs to be increased to 1.5 times.

[0092] FIG. 5(c) shows the case where the technology of Embodiment 2 is applied. By superimposing the zero-phase voltage d-axis component V U *, v V *, v W * and the zero-phase voltage q-axis component V 0d to the voltage command values v 0q , the output voltage of the U-phase cells can be decreased. Although the output voltages of the V-phase and W-phase cells increase, the same line voltage can be maintained by increasing the AC voltage of all cells including the U phase to about 1.15 times.

[0093] That is, the zero-phase voltage having the same frequency as the fundamental wave is superimposed so that the values obtained by multiplying the amplitudes of the corrected voltage command values v U *’, v V *’, v W *’ of each phase by the number of cells N in each phase and dividing by the number of cells n U , n V , n W operating without failure in each phase have small differences among the three phases.

[0094] Note that generating the gate signal based on FIG. 4 is for healthy cells without faults. For faulty cells, the AC system side turns on the switching devices S1 and S3, or turns on the switching devices S2 and S4 to output zero voltage, or performs a short-circuit treatment with an external switch. The switching devices S5 to S12 are turned off.

[0095] According to the second embodiment, in addition to the effects of the first embodiment, even when a part of the cells fails and a short-circuit treatment is performed, the AC output voltage of the cells can be made uniform. Even when more cells fail than in the prior art, the operation can be continued.

[0096] [Embodiment 3] FIG. 6 shows a block diagram of the correction voltage command value generation unit of the third embodiment. The configuration before the arithmetic unit 9 is the same as that of the first embodiment or the second embodiment. The third embodiment is different from the first and second embodiments in the following points.

[0097] In the third embodiment, in the arithmetic unit 9 for obtaining the zero-phase voltage d-axis component V 0d , zero-phase voltage q-axis component V 0q , equation (5) is used.

[0098] The comparator 18 determines whether the reverse-phase d-axis component V 2d is equal to the positive-phase d-axis component V 1d . The comparator 19 determines whether the reverse-phase d-axis component V 2d is equal to -V 1d / 2. The comparator 20 determines whether the reverse-phase q-axis component V 2q is equal to 0. The comparator 21 determines whether the reverse-phase q-axis component V 2q is equal to -√3V 1d / 2. The comparator 22 determines whether the reverse-phase q-axis component V 2q is equal to √3V 1d / 2.

[0099] Note that the comparator 18 sets a threshold value in advance and compares the reverse-phase d-axis component V 2d with the positive-phase d-axis component V 1dIf the difference is less than the threshold value, it may be regarded as equal. Hysteresis characteristics may be given to the threshold value. The same applies to comparators 19 to 22.

[0100] AND element 23 outputs 1 when the reverse-phase d-axis component V 2d is equal to -V 1d / 2 and the reverse-phase q-axis component V 2q is equal to √3V 1d / 2, and outputs 0 in other cases. Switch SW1 outputs V 0d / 4 as the zero-phase voltage d-axis component V 1d when the output of AND element 23 is 1, and outputs the result of equation (5) when it is 0. Switch SW2 outputs -√3V 0q / 4 as the zero-phase voltage q-axis component V 1d when the output of AND element 23 is 1, and outputs the result of equation (5) when it is 0.

[0101] AND element 24 outputs 1 when the reverse-phase d-axis component V 2d is equal to -V 1d / 2 and the reverse-phase q-axis component V 2q is equal to -√3V 1d / 2, and outputs 0 in other cases. Switch SW3 outputs V 0d / 4 as the zero-phase voltage d-axis component V 1d when the output of AND element 24 is 1, and outputs the result of switch SW1 when it is 0. Switch SW4 outputs √3V 0q / 4 as the zero-phase voltage q-axis component V 1d when the output of AND element 24 is 1, and outputs the result of switch SW2 when it is 0.

[0102] AND element 25 outputs 1 when the reverse-phase d-axis component V 2d is equal to the positive-phase d-axis component V 1d and the reverse-phase q-axis component V 2q is equal to 0, and outputs 0 in other cases. Switch SW5 outputs -V 0d as the zero-phase voltage d-axis component V 1dIf it is 0, the result of switch SW3 is output. If the output of AND element 25 is 1, switch SW6 outputs 0 as the zero-phase voltage q-axis component V 0q and outputs 0 as the result of switch SW4 if it is 0.

[0103] Table 1 shows the zero-phase voltage d-axis component V finally output by switch SW5 0d and the zero-phase voltage q-axis component V output by switch SW6 0q .

[0104]

Table 1

[0105] In Embodiments 1 and 2, when the amplitudes of the positive-phase voltage and the negative-phase voltage are equal, the denominator of equations (3), (4), and (5) becomes zero and they have no solutions. However, if the numerator is also zero, there is a possibility of having solutions. Therefore, assuming a system connection application for simplification and obtaining the condition for both the numerator and denominator to become zero in equation (5), equation (7) is obtained as one of them.

[0106]

Equation

[0107] Substituting equation (7) into equation (1) and finding the zero-phase voltage that satisfies equation (2) again under the condition of V 1q =0, equation (8) is obtained.

[0108]

Equation

[0109] At this time, the zero-phase voltage q-axis component V 0q can be any value, indicating that there are infinitely many solutions. Among these infinite solutions, the one with the minimum amplitude of the zero-phase voltage is given by equation (9).

[0110]

Equation

[0111] There are two other conditions under which both the numerator and the denominator become zero, in addition to equation (7). The combinations of conditions and solutions are shown in equations (10) and (11).

[0112]

Mathematics

[0113]

Mathematics

[0114] Examples of the conditions of equations (7), (10), and (11) are line-to-line short circuits and phase-to-ground faults. Embodiment 3 detects the voltage conditions of equations (7), (10), and (11) and superimposes a zero-phase voltage to equalize the amplitudes of the voltage command values of each phase. In power system interconnections, there are applications where continuous operation during faults (FRT) is required even during short circuit and ground fault accidents, and Embodiment 3 can also handle such applications.

[0115] According to Embodiment 3, even when a line-to-line short circuit or a phase-to-ground fault occurs in an AC power system, the effects of Embodiment 1 and Embodiment 2 can be obtained.

[0116] As described above, in the present invention, although detailed descriptions have been made only for the specific examples described, it is obvious to those skilled in the art that various modifications and variations are possible within the scope of the technical idea of the present invention, and it is natural that such modifications and variations belong to the scope of the claims.

Explanation of Reference Signs

[0117] AC... AC power system 1... PLL (Phase-Locked Loop) 2, 4, 5, 7, 8... First to third low-pass filters 3... First dq converter 6... Second dq converter 9…Calculator 10…Oscillator 11, 12…First, second multipliers 13 - 16…First - second adders 17…Coefficient calculator 18 - 22…Comparators 23 - 25…AND elements SW1 - SW6…Switches

Claims

1. A cell multi-inverter having a plurality of cells connected in multiple in a star configuration to each phase of an AC system and having a full-bridge circuit on the AC system side, a correction voltage command value generation unit that generates a correction voltage command value by superimposing a zero-phase voltage having the same frequency as the fundamental wave on a voltage command value, and a gate signal generation unit that generates a gate signal for the full-bridge circuit based on the correction voltage command value, wherein the correction voltage command value generation unit superimposes the zero-phase voltage having the same frequency as the fundamental wave on the voltage command value so that the amplitude difference of the correction voltage command values of each phase becomes small. A cell multi-inverter characterized by this.

2. A cell multi-inverter having a plurality of cells connected in multiple in a star configuration to each phase of an AC system and having a full-bridge circuit on the AC system side, a correction voltage command value generation unit that generates a correction voltage command value by superimposing a zero-phase voltage having the same frequency as the fundamental wave on a voltage command value, and a gate signal generation unit that generates a gate signal for the full-bridge circuit based on the correction voltage command value, wherein the correction voltage command value generation unit superimposes the zero-phase voltage having the same frequency as the fundamental wave so that the value obtained by multiplying the amplitude of the correction voltage command value of each phase by the number of cells in each phase and dividing by the number of cells operating without failure in each phase has a small difference among the three phases. A cell multi-inverter characterized by this.

3. the correction voltage command value generation unit a phase output unit that outputs a phase ωt synchronized with the AC voltage of the system, a first dq converter that converts a phase voltage detection signal or the voltage command value, or a value obtained by multiplying the phase voltage detection signal or the voltage command value by a coefficient obtained by dividing the number of cells in each phase by the number of cells operating without failure in each phase into a value on a rotating coordinate synchronized with the system frequency, a second dq converter that converts a phase voltage detection signal or the voltage command value, or a value obtained by multiplying the phase voltage detection signal or the voltage command value by a coefficient obtained by dividing the number of cells in each phase by the number of cells operating without failure in each phase into a value on a rotating coordinate rotating in the opposite direction to the system frequency, an arithmetic unit that calculates a zero-phase voltage d-axis component and a zero-phase voltage q-axis component that equalize the AC-side output voltages of the cells based on the positive-phase d-axis component and positive-phase q-axis component obtained by extracting the DC component from the output of the first dq converter and the reverse-phase d-axis component and reverse-phase q-axis component obtained by extracting the DC component from the output of the second dq converter, a first multiplier that multiplies the zero-phase voltage d-axis component by cosωt or sinωt, When multiplying by cosωt with the first multiplier, multiply the zero-phase voltage q-axis component by sinωt, and when multiplying by sinωt with the first multiplier, multiply the zero-phase voltage q-axis component by cosωt; a second multiplier; a first adder that adds the output of the first multiplier and the output of the second multiplier; a second adder that adds the output of the first adder to the voltage command value and outputs the result as the corrected voltage command value; The cell multi-inverter according to claim 1 or 2, characterized by comprising the above components.

4. The cell multi-inverter according to claim 3, characterized in that the calculator calculates the zero-phase voltage d-axis component and the zero-phase voltage q-axis component based on equation (3). [Number 3] V ０ｄ : Zero-phase voltage d-axis component V ０ｑ : Zero-phase voltage q-axis component V １ｄ : Positive-phase voltage d-axis component V １ｑ : Positive-phase voltage q-axis component V ２ｄ : Reverse-phase voltage d-axis component V ２ｑ : Inverse-phase voltage q-axis component

5. The cell multi-inverter according to claim 3, characterized in that the calculator calculates the zero-phase voltage d-axis component and the zero-phase voltage q-axis component based on equation (4). 【Number 4】 V ０ｄ : Zero-phase voltage d-axis component V ０ｑ : Zero-phase voltage q-axis component V １ｄ : Positive-phase voltage d-axis component V １ｑ : Positive-phase voltage q-axis component V ２ｄ : Inverse-phase voltage d-axis component V ２ｑ : Negative-phase voltage q-axis component

6. The cell multi-inverter according to claim 3, characterized in that the calculator calculates the zero-phase voltage d-axis component and the zero-phase voltage q-axis component based on equation (5). 【Number 5】 V ０ｄ : Zero-phase voltage d-axis component V ０ｑ : Zero-phase voltage q-axis component V ２ｄ : Reverse-phase voltage d-axis component V ２ｑ : Inverse-phase voltage q-axis component V １ : Voltage positive-phase component

7. The corrected voltage command value generation unit The reverse-phase d-axis component V ２ｄ = V １ｄ and when the reverse-phase q-axis component is V ２ｑ = 0, the zero-phase voltage d-axis component V ０ｄ = -V １ｄ / 2, the zero-phase voltage q-axis component V ０ｑ = 0, The reverse-phase d-axis component V ２ｄ = -V １ｄ / 2, and when the reverse-phase q-axis component is V ２ｑ = -√3V １ｄ / 2, the zero-phase voltage d-axis component V ０ｄ = V １ｄ / 4, the zero-phase voltage q-axis component V ０ｑ = √3V １ｄ / 4, and The reverse-phase d-axis component V ２ｄ = -V １ｄ / 2, and when the reverse-phase q-axis component is V ２ｑ = √3V １ｄ / 2, the zero-phase voltage d-axis component V ０ｄ = V １ｄ / 4, the zero-phase voltage q-axis component V ０ｑ = -√3V １ｄ / 4, and the cell multi-inverter according to claim 6, characterized in that.

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