Cell multiple inverter

Abstract

To equalize an AC output voltage of a cell even when an unbalanced AC voltage occurs or when an unbalanced AC voltage is intentionally output in a cell multiple inverter with multiple cells multilaterally connected in star connection to each phase of an AC system.SOLUTION: A correction voltage command value generation unit is configured to superimpose a sine wave in the opposite phase to a certain phase onto a voltage command value as a zero-phase voltage if the amplitude of the voltage command value of the phase is greater than the amplitude of the voltage command value of the other phase and superimpose a sine wave in the same phase as the phase as a zero-phase voltage on the voltage command value if the amplitude of the voltage command value of the phase is smaller than the amplitude of the voltage command value of the other phase.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a cell multi-inverter in which a plurality of cells are connected in multiple in a star connection to each phase of an AC system.

Background Art

[0002] As an example of a cell multi-inverter, a modular multi-level cascade converter (MMCC) of a single star bridge cell (SSBC) connected to a three-phase AC system is known. Also known is a configuration in which a separate power supply, a DC / DC converter, etc. are connected to the DC side of the full bridge cell of MMCC-SSBC.

[0003] As a main example of this configuration, there is a solid state transformer (SST) as in Patent Document 1, for example. Fig. 1 shows an SST consisting of three cells per phase in which MMCC-SSBC and a dual active bridge (DAB) type bidirectional isolated DC / DC converter are combined.

[0004] High-voltage AC power can be converted into DC power by cells connected in series, the DC power can be converted into high-frequency AC power, and then converted back into DC power by insulation and rectification with a transformer. Reverse power flow is also possible. Since the SST uses a high-frequency transformer, it can be made smaller than a conventional commercial frequency transformer.

[0005] Another application is the high-voltage multi-inverter of Patent Document 2.

[0006] When connecting to an unbalanced three-phase AC system with an SST, or when intentionally outputting an unbalanced three-phase AC voltage with a high-voltage multi-inverter, the phase voltage amplitude of a certain phase increases, and the AC voltage that the cells connected to the corresponding phase should output also increases.

[0007] To address this, it is necessary to increase the DC voltage of the cells. However, this also leads to an increase in the breakdown voltage required for the components, resulting in increased costs and size. Using switching devices with a high breakdown voltage in the cells also causes an increase in losses.

[0008] In addition, depending on the device, operation may need to continue even if some cells fail.

[0009] Patent Document 1 discloses the main circuit configuration of an SST, and Patent Document 2 discloses the configuration of a high-voltage multi-inverter.

[0010] Patent Documents 3 and 4 disclose methods for continuing operation when a cell fails. In both documents, the first failed cell is short-circuited. However, this alone causes a decrease in the amplitude of the AC voltage that can be output in the phase with the failed cell. Therefore, in Patent Document 3, a spare cell prepared in advance for the corresponding phase is inserted. In Patent Document 4, the DC voltage of the non-failed cells in the corresponding phase is increased.

[0011] Patent Documents 5 and 6 disclose techniques for dealing with voltage imbalance by using zero-phase voltage in an MMCC-SSBC. The purpose of this technique is to balance the capacitor voltages of each cell.

[0012] Patent Document 7 is a technique for reducing the peak of the voltage command value by superimposing zero-phase voltage on the voltage command value of a single-unit three-phase inverter that does not perform cell multiplexing. It can also handle the case of outputting an unbalanced three-phase AC voltage and equalize the voltage command value peaks of each phase. The technique of Patent Document 7 can be applied to an MMCC-SSBC or a high-voltage multi-inverter.

Prior Art Documents

Patent Documents

[0013]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0014] However, Patent Documents 1 and 2 do not particularly mention the connection to an unbalanced system, the output of unbalanced voltage, or the countermeasures when a cell fails.

[0015] In Patent Document 3, it is necessary to incorporate a spare cell into the device, and a switch for inserting the spare cell is also required, resulting in an increase in cost and size. If no failure occurs, the spare cell may not be used and may be wasted.

[0016] In Patent Document 4, in order to increase the DC voltage of other cells in the corresponding phase, cell design based on this is required, leading to problems such as an increase in cost, size, and losses. Also, neither Patent Document 3 nor 4 describes a method for dealing with voltage imbalance.

[0017] In Patent Documents 5 and 6, only capacitors are connected to the DC side of each cell, and applications that do not handle active power such as reactive power compensation devices are assumed. However, in high - voltage multi - level inverters and SSTs, there is a separate path for active power to pass. Therefore, power sharing between cells can be performed using this path to balance the capacitor voltage. As a result, the importance of the technologies in Patent Documents 5 and 6 is reduced. Also, neither Patent Documents 5 nor 6 describe a method for dealing with cell failure.

[0018] In Patent Document 7, harmonics that are odd multiples of 3 are superimposed as zero-phase voltage. However, the higher the frequency of the superimposed zero-phase voltage, the greater the common-mode current flowing through the stray capacitance of the circuit. This may cause many problems such as increased heat generation of components, reduced efficiency, malfunction of the ground fault detector, breakdown of the insulation of the high-frequency transformer, and electromagnetic interference to other devices. Therefore, it is necessary to lower the frequency of the superimposed zero-phase voltage. Also, Patent Document 7 does not describe a method for dealing with cell failures.

[0019] From the above, in a cell multi-inverter in which a plurality of cells are connected in multiple in a star connection to each phase of an AC system, even when an imbalance occurs in the AC voltage or when an intentionally unbalanced AC voltage is output, it is an issue to equalize the AC output voltages of the cells.

Means for Solving the Problem

[0020] The present invention has been devised in view of the above-mentioned conventional problems. One aspect thereof is a cell multi-inverter including: a plurality of cells connected in multiple in a star connection to each phase of an AC system and having a full-bridge circuit on the AC system side; a correction voltage command value generation unit that superimposes a zero-phase voltage having the same frequency as the fundamental wave on a voltage command value to generate a correction voltage command value; and a gate signal generation unit that generates a gate signal of the full-bridge circuit based on the correction voltage command value. The correction voltage command value generation unit superimposes a sine wave having a phase opposite to that of a certain phase as the zero-phase voltage on the voltage command value if the amplitude of the voltage command value of a certain phase is greater than the amplitude of the voltage command value of other phases, and superimposes a sine wave having the same phase as that of a certain phase as the zero-phase voltage on the voltage command value if the amplitude of the voltage command value of a certain phase is smaller than the amplitude of the voltage command value of other phases.

[0021] Also, in one aspect, the corrected voltage command value generation unit includes: a first adder that adds the zero-phase voltage to the voltage command value and outputs the corrected voltage command value; an amplitude detector that outputs the amplitude of the corrected voltage command value for each phase; a first subtractor that calculates the deviation between the three-phase average value of the amplitude of the corrected voltage command value and the amplitude of the corrected voltage command value; an amplifier that amplifies the deviation between the three-phase average value and the amplitude; a third multiplier that multiplies the output of the amplifier by a sine wave in the same phase as the voltage command value; and a fourth adder that adds the outputs of the three-phase third multipliers and outputs the result as the zero-phase voltage.

[0022] Also, in one aspect, the amplitude used by the first subtractor is a value obtained by multiplying the amplitude of the voltage command value by a coefficient based on the number of failed cell stacks, and the three-phase average value is the three-phase average value of the amplitude after the coefficient multiplication.

[0023] Also, in one aspect, the amplitude of the voltage command value is the effective value of the voltage command value.

[0024] Also, in another aspect, the amplitude of the voltage command value is a value obtained by extracting the amplitude of the fundamental wave component of the voltage command value.

[0025] Also, in another aspect, the amplitude of the voltage command value is the peak value per cycle of the voltage command value.

[0026] Also, in one aspect, for the sine wave in the same phase as the voltage command value, the phase of one of the three phases is the phase obtained by a PLL or a rotary encoder or a resolver, or the phase estimated by an observer, and the phases of the other phases are the phases obtained by adding a fixed value to the phase of one of the three phases.

[0027] In another aspect, the correction voltage command value generation unit includes a phase output unit that outputs a phase ωt synchronized with the AC voltage of the system, a fourth multiplier that multiplies the correction voltage command value by cosωt, a fifth multiplier that doubles the output of the fourth multiplier, a second low-pass filter that extracts a DC component from the output of the fifth multiplier and outputs a in-phase component synchronized with cosωt among the correction voltage command values, a sixth multiplier that multiplies the correction voltage command value by sinωt, a seventh multiplier that doubles the output of the sixth multiplier, a third low-pass filter that extracts a DC component from the output of the seventh multiplier and outputs a quadrature component synchronized with sinωt among the correction voltage command values, an eighth multiplier that multiplies the in-phase component by cosωt, a ninth multiplier that multiplies the quadrature component by sinωt, and a fifth adder that adds the output of the eighth multiplier and the output of the ninth multiplier. It is characterized in that the output of the fifth adder is a sine wave having the same phase as the voltage command value.

[0028] In one aspect, the correction voltage command value generation unit includes a phase output unit that outputs a phase ωt synchronized with the AC voltage of the system, a first dq converter that converts a phase voltage detection signal or the voltage command value into values on a rotating coordinate synchronized with the system frequency, a second dq converter that converts the phase voltage detection signal or the voltage command value into values on a rotating coordinate rotating in the opposite direction to the system frequency, an arithmetic unit that calculates a zero-phase voltage d-axis component and a zero-phase voltage q-axis component for equalizing the AC-side output voltages of the respective cells based on a positive-phase d-axis component and a positive-phase q-axis component obtained by extracting a DC component from the output of the first dq converter and a negative-phase d-axis component and a negative-phase q-axis component obtained by extracting a DC component from the output of the second dq converter, a tenth multiplier that multiplies the zero-phase voltage d-axis component by cosωt, an eleventh multiplier that multiplies the zero-phase voltage q-axis component by sinωt, a seventh adder that adds the output of the tenth multiplier and the output of the eleventh multiplier, and an eighth adder that adds the output of the seventh adder to the voltage command value. The first adder uses the voltage command value obtained by adding the output of the seventh adder to the voltage command value by the eighth adder.

[0029] Also, in one aspect, the arithmetic unit is characterized by calculating the zero-phase voltage d-axis component and the zero-phase voltage q-axis component based on equation (1).

[0030]

Number

[0031] V 0d : Zero-phase voltage d-axis component V 0q : Zero-phase voltage q-axis component V 1d : Positive-phase voltage d-axis component V 1q : Positive-phase voltage q-axis component V 2d : Negative-phase voltage d-axis component V 2q : Negative-phase voltage q-axis component.

[0032] Also, in another aspect, the arithmetic unit is characterized by calculating the zero-phase voltage d-axis component and the zero-phase voltage q-axis component based on equation (2).

[0033]

Number

[0034] V 0d : Zero-phase voltage d-axis component V 0q : Zero-phase voltage q-axis component V 1d : Positive-phase voltage d-axis component V 1q : Positive-phase voltage q-axis component V 2d : Negative-phase voltage d-axis component V 2q : Negative-phase voltage q-axis component.

[0035] Also, in another aspect, the arithmetic unit is characterized by calculating the zero-phase voltage d-axis component and the zero-phase voltage q-axis component based on equation (3).

[0036]

Number

[0037] V 0d : Zero-phase voltage d-axis component V 0q : Zero-phase voltage q-axis component V 2d : Reverse-phase voltage d-axis component V 2q : Reverse-phase voltage q-axis component V1: Positive-phase voltage component.

[0038] Further, as one aspect thereof, the phase voltage detection signal or the voltage command value used in the first dq converter and the second dq converter is a value obtained by multiplying the phase voltage detection signal or the voltage command value by a coefficient obtained by dividing the number of cell units per phase by the number of cell units operating without failure in each phase.

Effect of the Invention

[0039] According to the present invention, in a cell multi-inverter in which a plurality of cells are connected in multiple in a star connection to each phase of an AC system, even when an imbalance occurs in the AC voltage or when an intentionally unbalanced AC voltage is output, it is possible to equalize the AC output voltage of the cells.

Brief Description of the Drawings

[0040]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Modes for Carrying Out the Invention

[0041] Hereinafter, Embodiments 1 to 4 of the cell multi-inverter in the present invention will be described in detail with reference to FIGS. 1 to 6.

[0042] [Embodiment 1] First, as an example of the cell multi-inverter, the main circuit configuration of the MMCC-SSBC shown in FIG. 1 will be described.

[0043] As shown in FIG. 1(a), in the U-phase of the AC power system AC, cells cellu1, cellu2, and cellu3 are connected in series via a reactor Lu. Similarly, in the V-phase of the AC power system AC, cells cellv1, cellv2, and cellv3 are connected in series via a reactor Lv, and in the W-phase of the AC power system AC, cells cellw1, cellw2, and cellw3 are connected in series via a reactor Lw. Here, let the AC phase voltage (phase voltage detection signal) be v U , v V , v W .

[0044] The DC terminals of cells cellu1, cellu2, cellu3, cellv1, cellv2, cellv3, cellw1, cellw2, and cellw3 are connected in parallel. Let the DC voltage of cells cellu1 to cellw3 be V DC .

[0045] FIG. 1(b) shows the configuration per cell. One end of switching devices S1 and S3 is connected to one AC terminal of the cell. Also, one end of switching devices S2 and S4 is connected to the other AC terminal of the cell. The other ends of switching devices S1 and S2 are connected to one end of the first capacitor C1. The other ends of switching devices S3 and S4 are connected to the other end of the first capacitor C1. With the above switching devices S1, S2, S3, and S4, a full-bridge circuit provided on the AC power system AC side is formed.

[0046] Switching devices S5 and S6 are connected in series between one end and the other end of the first capacitor C1. Also, switching devices S7 and S8 are connected in series between one end and the other end of the first capacitor C1.

[0047] One end of the reactor L1 is connected to the connection point of the switching devices S5 and S6. One end of the reactor L2 is connected to the connection point of the switching devices S7 and S8. The primary winding of the transformer Tr is connected between the other end of the reactor L1 and the other end of the reactor L2.

[0048] A second capacitor C2 is connected between one DC terminal and the other DC terminal of the cell. Switching devices S9 and S11 are connected in series between one end and the other end of the second capacitor C2. Also, switching devices S10 and S12 are connected in series between one end and the other end of the second capacitor C2.

[0049] One end of the reactor L3 is connected to the connection point of the switching devices S9 and S11. One end of the reactor L4 is connected to the connection point of the switching devices S10 and S12. The secondary winding of the transformer Tr is connected between the other end of the reactor L3 and the other end of the reactor L4. Note that the reactors L1 to L4 in Fig. 1(b) may be omitted.

[0050] The cell in Fig. 1(b) adjusts the active power to be transferred by adjusting the phase difference of the inverter output voltages on both sides of the transformer Tr. Gate signals of the switching devices S5 to S12 are generated so that the phase difference of the output voltages of the inverters on both sides of the transformer Tr becomes a desired phase difference (that is, so that the desired active power to be transferred is obtained). Since the gate signals of the switching devices S5 to S12 of the inverters on both sides of the transformer Tr are not directly related to the present invention, detailed description here is omitted, and a conventionally known method is used.

[0051] The gate signals "gate" of the switching devices S1 to S4 of the full-bridge circuit provided on the AC side of the AC system are input with the gate signals generated according to Embodiment 1 described later.

[0052] Fig. 2 shows another example of the circuit diagram per cell. In this example, an LLC resonant converter is applied as the bidirectional isolation type DC / DC converter.

[0053] As shown in Fig. 2, a third capacitor C3 is connected between the connection point of the switching devices S5 and S6 and the reactor L1. Also, a fourth capacitor C4 is connected between the connection point of the switching devices S7 and S8 and the reactor L2. Also, a fifth capacitor C5 is connected between the connection point of the switching devices S9 and S11 and the reactor L3. Also, a sixth capacitor C6 is connected between the connection point of the switching devices S10 and S12 and the reactor L4.

[0054] The NOT circuit 37 inverts the signal with a duty ratio of 50%. The dead time section 38 inserts a dead time into the signal with a duty ratio of 50% and the signal obtained by inverting the signal with a duty ratio of 50%, and outputs it as a gate signal to the switching devices S5 to S12 of the inverters on both sides of the transformer Tr. The other circuit configuration is the same as that in Fig. 1(b).

[0055] In Fig. 2, third to sixth capacitors C3 to C6 are connected in series to the transformer (high-frequency transformer) Tr. As a result, resonance occurs between the leakage inductance of the transformer Tr and the reactors L1 to L4 connected in series separately. The inverters on both sides of the transformer Tr output an AC voltage at this resonance frequency. The duty ratio of the gate signals for driving the inverters on both sides of the transformer Tr is fixed at 50%. As a result, the active power corresponding to the difference in the DC voltages on both sides of the transformer Tr is transferred through the transformer Tr. Since the gate signals of the switching devices S5 to S12 of the inverters on both sides of the transformer Tr are not directly related to the invention of the present application, detailed description thereof is omitted here.

[0056] The gate signals "gate" of the switching devices S1 to S4 of the full-bridge circuit provided on the AC side of the AC system are input with the gate signals generated according to Embodiment 1 described later.

[0057] Fig. 3 shows a block diagram of the corrected voltage command value generation unit according to Embodiment 1. In Embodiment 1, the voltage duties of the respective cells are equalized in applications where it is not necessary to equalize the power duties of the respective cells.

[0058] The first adders 1u, 1v, 1w superimpose the zero-phase voltage obtained in the previous operation cycle on the voltage command values v U *, v V *, v W *, and output the corrected voltage command values v U *’, v V *’, v W *’. The voltage command values v U *, v V *, v W * may be given as a sine wave with a determined amplitude and frequency, or may be obtained by feedback control of voltage or current.

[0059] The corrected voltage command values v U *’, v V *’, v W *’ generate gate signals (on / off command signals) by carrier triangular wave comparison or the like in the subsequent stage (gate signal generation unit), and are input to the switching devices S1 to S4 of the full-bridge circuit provided on the AC side of the AC system of each cell in Figs. 1(b) and 2. Note that the above gate signal generation method is disclosed in Patent Document 6.

[0060] The amplitude detectors 2u, 2v, 2w detect the amplitudes of the corrected voltage command values v U *’, v V *’, v W *’. In Embodiment 1, the amplitude detectors 2u, 2v, 2w are configured as follows as an example of obtaining the effective values of the corrected voltage command values v U *’, v V *’, v W *’. Alternatively, as shown in Embodiment 3 described later, the corrected voltage command values v U *’, vV *’, v W *’ may calculate the amplitude of the fundamental wave, or the correction voltage command value v U *’, v V *’, v W *’ may memorize and output the peak value per cycle.

[0061] The first multipliers 3u, 3v, 3w calculate the square of the correction voltage command value v U *’, v V *’, v W *’. The first low-pass filters 4u, 4v, 4w extract the DC component per cycle from the outputs of the first multipliers 3u, 3v, 3w. The square root calculators 5u, 5v, 5w calculate the square root of the outputs of the first low-pass filters 4u, 4v, 4w. The outputs of the square root calculators 5u, 5v, 5w become the amplitude of the correction voltage command value v U *’, v V *’, v W *’.

[0062] The square root calculators 5u, 5v, 5w may be omitted because of the high calculation load. In this case, it is necessary to note that the object to be amplified by the amplifiers 9u, 9v, 9w described later becomes the square of the effective value, so the gain is likely to become excessive.

[0063] The second adder 6 calculates the sum of the amplitudes of the correction voltage command value v U *’, v V *’, v W *’. The second multiplier 7 multiplies the sum of the amplitudes of the correction voltage command value v U *’, v V *’, v W *’ (the output of the second adder 6) by 1 / 3 to calculate the three-phase average value. The first subtractors 8u, 8v, 8w calculate the deviation between the three-phase average value and the amplitude of the correction voltage command value v U *’, v V *’, v W *’.

[0064] The amplifiers 9u, 9v, 9w amplify the outputs of the first subtractors 8u, 8v, 8w (the deviation between the three-phase average value and the amplitude). Here, a proportional-integral controller is used as an example.

[0065] The phase output unit (for example, PLL: Phase-Locked Loop) 10 outputs a phase ωt synchronized with the AC voltage of the AC power system from the phase voltage detection signals v U , v V , v W from the AC power system.

[0066] The phase voltage detection signals v U , v V , v W may detect the line voltage and convert it to the phase voltage by calculation. Also, instead of the phase voltage detection signals v U , v V , v W , voltage command values v U *, v V *, v W * may be input. The AC power system voltage input to the phase output unit 10 may be only one representative phase. In motor drive applications, the phase ωt may be detected from a rotary encoder, resolver, etc., or the phase estimated by an observer, etc. may be used. Hereinafter, the phase output unit 10 is denoted as PLL 10.

[0067] The oscillator 11u outputs a sine wave with the same phase and amplitude 1 as the voltage command value v U * from the phase ωt. The second subtractor 12v subtracts 2π / 3 from the phase ωt. The oscillator 11v outputs a sine wave with the same phase and amplitude 1 as the voltage command value v V * from the phase ωt - 2π / 3. The third adder 12w adds 2π / 3 to the phase ωt. The oscillator 11w outputs a sine wave with the same phase and amplitude 1 as the voltage command value v W * from the phase ωt + 2π / 3.

[0068] The third multipliers 13u, 13v, 13w multiply the outputs of the amplifiers 9u, 9v, 9w of each phase by the sine waves (outputs of the oscillators 11u, 11v, 11w) synchronized with the voltage command values v U *, v V *, v W * of each phase.

[0069] The fourth adder 14 adds the sums of the three third multipliers 13u, 13v, 13w to the voltage command values v of each phaseU *, v V *, v W Output as the zero-phase voltage to be superimposed on *. The output of the fourth adder 14 is temporarily stored in the buffer 15, and the voltage command value v U *, v V *, v W is added to * to obtain the corrected voltage command value v U *’, v V *’, v W *’.

[0070] In the first embodiment, the three-phase voltage command values v U *, v V *, v W The purpose is to equalize the amplitudes of the voltage command values of each phase by superimposing the zero-phase voltage on *.

[0071] In the first embodiment, the amplitudes of the corrected voltage command values v U *’, v V *’, v W *’ are detected, and the deviation from the three-phase average value is obtained. If the amplitude of the corrected voltage command value v U *’ is smaller than the three-phase average value, a sine wave with the same phase as the corrected voltage command value v U *’ is added as the zero-phase voltage to increase the amplitude of the corrected voltage command value v U *’. If the amplitude of the corrected voltage command value v U *’ is larger than the three-phase average value, a sine wave with the opposite phase to the corrected voltage command value v U *’ is added as the zero-phase voltage to decrease the amplitude of the corrected voltage command value v U *’.

[0072] This is performed for three phases, and the zero-phase voltage to be superimposed is the sum of the three phases. In the next calculation cycle, the corrected voltage command value v U *’, v V *’, v W *’ with the zero-phase voltage superimposed in the previous calculation is detected. If there is an integration element in the amplifier, the deviation becomes zero and the corrected voltage command value v U *’, v V *’, v W *’ is repeated until the amplitudes are equal. If there is no integration element, the deviation is reduced until it reaches a value corresponding to the gain.

[0073] By the above operation, when there is an imbalance in the AC voltage or when an intentionally imbalanced AC voltage is output, the amplitudes of the correction voltage command values v U *’, v V *’, v W *’ can be made equal.

[0074] In the first embodiment, a sine wave in the same phase as the voltage command value has a phase obtained by a PLL or a rotary encoder or a resolver for one of the three phases, or a phase estimated by an observer, and the other phases have phases obtained by adding a fixed value to the phase of one of the three phases. That is, assuming that the correction voltage command values v U *’, v V *’, v W *’ are synchronized with cosωt, cos(ωt - 2π / 3), and cos(ωt + 2π / 3), respectively.

[0075] This holds as long as the PLL10 is operating normally. When the phase of the AC voltage changes suddenly due to a fault or a sudden change in the load, the synchronization may be temporarily lost.

[0076] The greater the phase difference, the more time it takes for the amplitudes of the correction voltage command values v U *’, v V *’, v W *’ to become equal. In particular, when the phase difference exceeds π / 2, a zero-phase voltage that increases the amplitude of the correction voltage command values v U *’, v V *’, v W *’ will be superimposed.

[0077] However, for example, in the case of the Fault Ride-Through (FRT) requirement, it is required to continue operation for a phase jump within 41°. Under this condition, the first embodiment can be applied without becoming unstable.

[0078] As described above, according to the first embodiment, in a star-connected cell multilevel inverter such as MMCC-SSBC, even when an imbalance occurs in the AC voltage or when an intentionally unbalanced AC voltage is output, the AC output voltages of the cells can be made equal. As a result, when the voltage amplitude of a certain phase increases, there is no need to connect cells to the corresponding phase or only increase the DC voltage of the cells in the corresponding phase.

[0079] Also, since the superimposed zero-phase voltage is only a fundamental wave component, the common-mode current can be suppressed.

[0080] In the first embodiment, it is necessary to increase or raise the DC voltages of all cells in advance. However, compared with the prior art, the increase in the DC voltage can be significantly suppressed, minimizing the increase in the breakdown voltage of the cells and reducing the cost and size.

[0081] Also, since the superimposed zero-phase voltage is obtained by feedback, the first embodiment can equalize the AC output voltages of the cells even when there are disturbances such as when there is a detection error in the AC voltage.

[0082] [Embodiment 2] Fig. 4 shows a block diagram of the correction voltage command value generation unit of the second embodiment. The second embodiment is different from the first embodiment in the following points.

[0083] The coefficient multipliers 16u, 16v, 16w multiply the amplitudes of the correction voltage command values v U *’, v V *’, v W *’ (outputs of the amplitude detectors 2u, 2v, 2w) by the coefficients N / n U , N / n V , N / n W The numerator N of the coefficient is the number of cells in each phase. The denominator n U , n V , n W of the coefficient is the number of cells that are operating without failure in each phase.

[0084] The amplitudes used in the first subtractors 8u, 8v, and 8w are values obtained by multiplying the amplitudes by a coefficient, and the three-phase average value is the three-phase average value of the amplitudes after the coefficient multiplication.

[0085] In the second embodiment, a function for reducing the voltage duty of the phase with a failed cell is added to the first embodiment. The detected corrected voltage command value v U *’, v V *’, v W *’ is multiplied by a coefficient, and the AC voltage of the phase including the failed cell is made to appear larger according to the number of failed cells, and the average value and deviation are obtained.

[0086] By superimposing the zero-phase voltage obtained by amplifying this deviation, the amplitude of the voltage command value of the phase with the failed cell can be decreased.

[0087] Note that the gate signals are generated based on FIG. 4 for healthy cells without failures. For failed cells, the switching devices S1, S3 on the AC system side are turned on, or the switching devices S2, S4 are turned on to output zero voltage, or a short-circuit treatment is performed with an external switch. The switching devices S5 to S12 are turned off.

[0088] As described above, according to the second embodiment, in addition to the effects of the first embodiment, even when a part of the cells fails and a short-circuit treatment is performed, the AC output voltages of the cells can be made uniform. Even when more cells fail than in the prior art, the operation can be continued.

[0089] [Embodiment 3] FIG. 5 shows a block diagram of the corrected voltage command value generation unit of the third embodiment. The third embodiment is different from the second embodiment in the following points.

[0090] The oscillator 17 inputs the phase ωt output from the PLL 10 and outputs a sine wave sin ωt. The oscillator 18 inputs the phase ωt output from the PLL 10 and outputs a cosine wave cos ωt.

[0091] In the first embodiment, the voltage command value v U* is synchronized with cosωt, voltage command value v V * is synchronized with cos(ωt - 2π / 3), v W Although it was assumed that * is synchronized with cos(ωt + 2π / 3), in the third embodiment, sine waves (in the same phase) synchronized with the voltage command value of each phase are prepared by the following blocks.

[0092] The fourth multiplier 19u obtains the product of the corrected voltage command value v U *’ and the cosine wave cosωt. The fifth multiplier 20u doubles the output of the fourth multiplier 19u. The second low-pass filter 4u extracts the DC component from 2v U *’cosωt. The output of the second low-pass filter 4u is the component (v U *’ among those synchronized with the cosine wave cosωt (v U * in-phase component).

[0093] The sixth multiplier 21u obtains the product of the corrected voltage command value v U *’ and the sine wave sinωt. The seventh multiplier 22u doubles the output of the sixth multiplier 21u. The third low-pass filter 4u extracts the DC component from 2v U *’sinωt. The output of the third low-pass filter 4u is the component (v U *’ among those synchronized with the sine wave sinωt (v U * quadrature component).

[0094] The eighth multiplier 23u obtains the product of the v U * in-phase component and the cosine wave cosωt. The ninth multiplier 24u obtains the product of the v U * quadrature component and the sine wave sinωt. The fifth adder 25u adds the outputs of the two eighth and ninth multipliers 23u and 24u. The output of the fifth adder 25u is a sine wave having the same phase and amplitude as the fundamental wave component of the voltage command value v U *. The third multiplier 13u multiplies this sine wave by the output of the U-phase amplifier 9u instead of cosωt. The same applies to the V-phase and W-phase.

[0095] Accordingly, the corrected voltage command values v U *’, v V *’, v WThe amplitude detectors 2u, 2v, and 2w of '*' are changed to the following configuration for obtaining the amplitude of the fundamental wave using the values of the above blocks. Similar to Embodiment 2, the effective value may be used, or the peak value per cycle may be stored and output.

[0096] The 10th multiplier 26u multiplies v U * the in-phase component and v U * the square of each of the quadrature components. The 6th adder 27u adds the outputs of the two 10th multipliers 26. The square root calculator 28u calculates the square root of the output of the 6th adder 27u. The square root calculator 28u may be omitted because of its high computational load. The precautions in this case are the same as those in Embodiment 1. The same applies to the V-phase and W-phase.

[0097] In this Embodiment 3, the correction voltage command values v U *’, v V *’, v W *’ are different from those in Embodiment 1 in that a sine wave synchronized with them is accurately obtained. As a result, when phase jumps in the power grid occur frequently, or when continuous operation is required at phase jumps exceeding the FRT requirements, the time until the amplitudes of the correction voltage command values v U *’, v V *’, v W *’ become equal can be shortened, and the destabilization of the feedback control can be prevented.

[0098] Also, in the drive application of a synchronous motor, a rotary encoder or the like is used to detect the phase ωt, but the phase of the rotary encoder does not always match the voltage phase. In Embodiments 1 and 2, correction is required when the difference is large, but in this Embodiment 3, it can be applied without correction even when the difference is large.

[0099] According to this Embodiment 3, when the power grid is unstable and phase jumps occur frequently, or when continuous operation is required for large phase jumps, the convergence time can be shortened and destabilization can be prevented compared to Embodiment 1 and Embodiment 2. Also, it can be easily applied to motor drive applications. However, the computational load is smaller in Embodiment 1 and Embodiment 2.

[0100] [Embodiment 4] FIG. 6 shows a block diagram of the correction voltage command value generation unit according to Embodiment 4. Embodiment 4 combines feedforward control with Embodiment 3.

[0101] The input of the feedforward control is the voltage command value v U *, v V *, v W *, but it is necessary to use the value before adding the zero-phase voltage. The phase voltage detection signals v U , v V , v W may also be input. The input of the feedback control needs to be the sum of the zero-phase voltage by the feedback control in the previous calculation cycle and the zero-phase voltage by the feedforward.

[0102] In the second coefficient multipliers 29u, 29v, and 29w, the voltage command value v U *, v V *, v W *(or the phase voltage detection signals v U , v V , v W ) is multiplied by the coefficients N / n U , N / n V , N / n W . The numerator N of the coefficient is the number of cell stacks in each phase. In the example of FIG. 1, N = 3. The denominator n U , n V , n W is the number of cell stacks that are operating without failure in each phase. And the voltage command values v U *, v V *, v W *(or the phase voltage detection signals v U , v V , v W ) used by the first dq converter 30 and the second dq converter 31 described later are the values obtained by multiplying this coefficient.

[0103] The first dq converter 30 multiplies the voltage command value v U , N / n V , N / n W by the coefficients N / n U *, v V*, v W * is converted to a value on a rotating coordinate synchronized with the system frequency based on the phase ωt.

[0104] If only the DC component is extracted from the output of the first dq converter 30, the d-axis component is the voltage command value v U *, v V *, v W The positive-phase d-axis component V of * 1d , and the q-axis component is the positive-phase q-axis component V 1q If the PLL10 is operating normally, since the positive-phase q-axis component V 1q is zero, it is not used.

[0105] The second dq converter 31 multiplies the voltage command value v by the coefficient N / n U , N / n V , N / n W and converts * to a value on a rotating coordinate that rotates in the direction opposite to the system frequency based on the phase -ωt. U *, v V *, v W * is converted to a value on a rotating coordinate that rotates in the direction opposite to the system frequency based on the phase -ωt.

[0106] If only the DC component is extracted from the output of the second dq converter 31, they are respectively the voltage command value v U *, v V *, v W The negative-phase d-axis component V of * 2d , and the negative-phase q-axis component V 2q result.

[0107] The arithmetic unit 32 obtains the zero-phase voltage d-axis component V from the obtained positive-phase d-axis component V 1d , positive-phase q-axis component V 1q , negative-phase d-axis component V 2d , and negative-phase q-axis component V 2q using the following equation (1). The zero-phase voltage d-axis component V 0d , and zero-phase voltage q-axis component V 0q can also be obtained using equation (2) or (3) instead of equation (1). In this arithmetic unit 32, when the amplitudes of the positive-phase and negative-phase components of the AC voltage are approximately equal, V 0d = V 0q = 0 is output. 0d = V 0q = 0 is output.

[0108] The 11th multiplier 33 calculates the product of the zero-phase voltage d-axis component V 0d and the cosine wave cosωt. The 12th multiplier 34 calculates the product of the zero-phase voltage q-axis component V 0q and the sine wave sinωt.

[0109] The 7th adder 35 calculates the sum of V 0d cosωt output by the 11th multiplier 33 and V 0q sinωt output by the 12th multiplier 34.

[0110] The 8th adders 36u, 36v, 36w add V U *, v V *, v W *, respectively, with V 0d cosωt + V 0q sinωt obtained by the 7th adder 35. In Embodiment 4, the outputs of the 8th adders 36u, 36v, 36w are output to the 1st adders 1u, 1v, 1w. The 1st adders 1u, 1v, 1w superimpose the zero-phase voltage obtained in the previous calculation cycle on the outputs of the 8th adders 36u, 36v, 36w, and output the corrected voltage command values v U *’, v V *’, v W *’.

[0111] The following shows equations (1) to (3).

[0112]

Equation

[0113] If the positive-phase q-axis component V 1q is close to zero, equation (1) can be approximated by equation (2).

[0114]

Equation

[0115] If the positive-phase q-axis component V 1qIf it is equal to zero, equation (1) can be simplified to equation (3). In equation (3), V1 represents the positive-phase component of the AC voltage.

[0116]

Number

[0117] In the fourth embodiment, with respect to the third embodiment, the amplitudes of the feedforward correction voltage command values v U *’, v V *’, v W *’ are made equal, and the deviation due to detection error or the like is corrected by feedback. Therefore, even if the feedback gain is reduced, the time until the amplitudes of the correction voltage command values v U *’, v V *’, v W *’ become equal can be shortened, and the stability is also improved. In addition to the effect of feedback that can reduce the deviation (it can be made zero by using an integrating amplifier), the effect of feedforward can also be obtained.

[0118] As described above, according to the fourth embodiment, the zero-phase voltage that is superimposed is determined by using feedforward and feedback in combination. Even if the gain of the feedback is reduced, the response to voltage fluctuations is fast, and the AC output voltage of the cell can be made uniform even in the presence of disturbances while improving the stability.

[0119] As described above, in the present invention, although the detailed description has been made only for the specific examples described, it is obvious to those skilled in the art that various modifications and corrections are possible within the scope of the technical idea of the present invention, and it is natural that such modifications and corrections belong to the scope of the claims.

Explanation of Signs

[0120] AC... AC system 1u, 1v, 1w... First adder 2u, 2v, 2w... Amplitude detector 3u, 3v, 3w... First multiplier 4u, 4v, 4w... First low-pass filter 5u, 5v, 5w... Square root calculator 6... Second adder 7... Second multiplier 8u, 8v, 8w... First subtractor 9u, 9v, 9w... Amplifier 10... Phase output section (PLL) 11u, 11v, 11w... Oscillator 12v... Second subtractor 12w... Third adder 13u, 13v, 13w... Second multiplier 14... Fourth adder 15... Buffer

Claims

1. A plurality of cells that are star-connected in multiple phases to each phase of an AC system and have a full-bridge circuit on the AC system side; a correction voltage command value generation unit that generates a correction voltage command value by superimposing a zero-phase voltage having the same frequency as the fundamental wave on a voltage command value; and a gate signal generation unit that generates a gate signal for the full-bridge circuit based on the correction voltage command value. The cell multi-inverter is characterized in that the correction voltage command value generation unit if the amplitude of the voltage command value of a certain phase is larger than the amplitude of the voltage command value of other phases, a sine wave having a phase opposite to that of the certain phase is superimposed on the voltage command value as the zero-phase voltage; and if the amplitude of the voltage command value of a certain phase is smaller than the amplitude of the voltage command value of other phases, a sine wave having the same phase as the certain phase is superimposed on the voltage command value as the zero-phase voltage. A cell multi-inverter characterized by this.

2. the correction voltage command value generation unit a first adder that adds the zero-phase voltage to the voltage command value and outputs the correction voltage command value; an amplitude detector that outputs the amplitude of the correction voltage command value of each phase; a first subtractor that calculates the deviation between the three-phase average value of the amplitude of the correction voltage command value and the amplitude of the correction voltage command value; an amplifier that amplifies the deviation between the three-phase average value and the amplitude; a third multiplier that multiplies the output of the amplifier by a sine wave having the same phase as the voltage command value; a fourth adder that adds the outputs of the three-phase third multipliers and outputs them as the zero-phase voltage, The cell multi-inverter according to claim 1, characterized by comprising the above.

3. The amplitude used in the first subtractor is a value obtained by multiplying the amplitude of the voltage command value by a coefficient based on the number of failed cell units, and the three-phase average value is the three-phase average value of the amplitude after the coefficient multiplication. The cell multi-inverter according to claim 2, characterized by this.

4. The amplitude of the voltage command value is the effective value of the voltage command value. The cell multi-inverter according to claim 1, characterized by this.

5. The amplitude of the voltage command value is a value obtained by extracting the amplitude of the fundamental wave component of the voltage command value. The cell multi-inverter according to claim 1, characterized by this.

6. The amplitude of the voltage command value is the peak value per cycle of the voltage command value. The cell multi-inverter according to claim 1, characterized by this.

7. The sine wave in the same phase as the voltage command value has a phase obtained by a PLL, a rotary encoder, or a resolver for one of the three phases, or a phase estimated by an observer, and the other phases have a phase obtained by adding a fixed value to the phase of one of the three phases. The cell multilevel inverter according to claim 2, characterized in that.

8. The correction voltage command value generation unit A phase output unit that outputs a phase ωt synchronized with the AC voltage of the system, A fourth multiplier that multiplies the correction voltage command value by cos ωt, A fifth multiplier that doubles the output of the fourth multiplier, A second low-pass filter that extracts a DC component from the output of the fifth multiplier and outputs a in-phase component synchronized with cos ωt among the correction voltage command values, A sixth multiplier that multiplies the correction voltage command value by sin ωt, A seventh multiplier that doubles the output of the sixth multiplier, A third low-pass filter that extracts a DC component from the output of the seventh multiplier and outputs a quadrature component synchronized with sin ωt among the correction voltage command values, An eighth multiplier that multiplies the in-phase component by cos ωt, A ninth multiplier that multiplies the quadrature component by sin ωt, A fifth adder that adds the output of the eighth multiplier and the output of the ninth multiplier, The cell multilevel inverter according to claim 2, further comprising: and outputting the output of the fifth adder as a sine wave in the same phase as the voltage command value.

9. The correction voltage command value generation unit A phase output unit that outputs a phase ωt synchronized with the AC voltage of the system, A first dq converter that converts a phase voltage detection signal or the voltage command value into a value on a rotating coordinate synchronized with the system frequency, A second dq converter that converts a phase voltage detection signal or the voltage command value into a value on a rotating coordinate rotating in the opposite direction to the system frequency, Based on the positive-phase d-axis component and positive-phase q-axis component obtained by extracting the DC component from the output of the first dq converter, and the negative-phase d-axis component and negative-phase q-axis component obtained by extracting the DC component from the output of the second dq converter, an arithmetic unit that calculates a zero-phase voltage d-axis component and a zero-phase voltage q-axis component that equalize the AC-side output voltage of each cell, A tenth multiplier that multiplies the zero-phase voltage d-axis component by cos ωt, An eleventh multiplier that multiplies the zero-phase voltage q-axis component by sin ωt, A seventh adder that adds the output of the tenth multiplier and the output of the eleventh multiplier, An eighth adder that adds the output of the seventh adder to the voltage command value, Comprising The cell multi-inverter according to claim 2, wherein the first adder uses the voltage command value obtained by adding the output of the seventh adder by the eighth adder.

10. The cell multi-inverter according to claim 9, wherein the arithmetic unit calculates the zero-phase voltage d-axis component and the zero-phase voltage q-axis component based on equation (1). 【Number 1】 V ０ｄ : Zero-phase voltage d-axis component V ０ｑ : Zero-phase voltage q-axis component V １ｄ : Positive-phase voltage d-axis component V １ｑ : Positive-phase voltage q-axis component V ２ｄ : Reverse-phase voltage d-axis component V ２ｑ : Negative-phase voltage q-axis component

11. The cell multi-inverter according to claim 9, wherein the arithmetic unit calculates the zero-phase voltage d-axis component and the zero-phase voltage q-axis component based on equation (2). 【Number 2】 V ０ｄ : Zero-phase voltage d-axis component V ０ｑ : Zero-phase voltage q-axis component V １ｄ : Positive-phase voltage d-axis component V １ｑ : Positive-phase voltage q-axis component V ２ｄ : Inverse-phase voltage d-axis component V ２ｑ : Negative-phase voltage q-axis component

12. The cell multi-inverter according to claim 9, wherein the arithmetic unit calculates the zero-phase voltage d-axis component and the zero-phase voltage q-axis component based on equation (3). [Number 3] V ０ｄ : Zero-phase voltage d-axis component V ０ｑ : Zero-phase voltage q-axis component V ２ｄ : Inverse voltage d-axis component V ２ｑ : Negative-phase voltage q-axis component V １ : Voltage positive-phase component

13. The phase voltage detection signal or the voltage command value used in the first dq converter and the second dq converter is a value obtained by multiplying the phase voltage detection signal or the voltage command value by a coefficient obtained by dividing the number of cell units in each phase by the number of cell units operating without failure in each phase, for the cell multi-inverter according to claim 9.

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