Inverter device

Abstract

To provide an inverter device that can maintain a voltage between a first phase and a third phase to be a predetermined voltage, in an autonomous operation mode in which the inverter device is cut off from a system and supplies power to a load.SOLUTION: The inverter device comprises: a first terminal that outputs a first phase of a single-phase current; a second terminal that is connected to a neutral line; a third terminal that outputs a second phase of the single-phase current; and a control unit that adjusts at least one of the phase of a first voltage between the first terminal and the second terminal and the phase of a second voltage between the third terminal and the second terminal so as to adjust the phase difference between the first voltage and the second voltage to a predetermined phase difference.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to an inverter device.

Background Art

[0002] A single-phase three-wire inverter device that converts direct current into single-phase alternating current is used. The single-phase three-wire inverter device includes, for example, a first phase and a third phase from which single-phase alternating current is output, and a second phase that serves as a neutral point. In the single-phase three-wire inverter device, loads are connected between the first phase and the second phase, between the third phase and the second phase, and between the first phase and the third phase, respectively.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In an inverter device, for example, the first-phase-second-phase voltage between the first phase and the second phase and the third-phase-second-phase voltage between the third phase and the second phase are each controlled to 100 V. rms And the phase difference between the first-phase-second-phase voltage and the third-phase-second-phase voltage is controlled to be 180 degrees based on the frequency of 50 Hz or 60 Hz of the alternating current power supplied from the power system. By controlling the first-phase-second-phase voltage and the third-phase-second-phase voltage in this way, the first-phase-third-phase voltage between the first phase and the third phase becomes 200 V. rms That is.

[0005] When the supply of AC power from the system is interrupted due to a power outage or the like, the inverter device transitions to an independent operation mode in which power is supplied from the inverter device to the load. In the independent operation mode, the AC voltage, frequency, and phase supplied to the load will be generated by the inverter device. Depending on the load configuration connected to the inverter device, the phase difference between the voltage between the first phase and the second phase and the voltage between the third phase and the second phase may vary from 180 degrees. When the phase difference between the voltage between the first phase and the second phase and the voltage between the third phase and the second phase varies from 180 degrees, the voltage between the first phase and the third phase will not be maintained at 200V rms and will not be maintained.

[0006] One aspect of the disclosed technology aims to provide an inverter device that can maintain the voltage between the first phase and the third phase at a predetermined voltage even in the case of an independent operation mode in which power is supplied from the inverter device to the load while being disconnected from the system.

Means for Solving the Problem

[0007] One aspect of the disclosed technology is exemplified by the following inverter device. This inverter device includes a first terminal that outputs a first phase of single-phase AC, a second terminal connected to the neutral line, a third terminal that outputs a second phase of the single-phase AC, and a control unit that adjusts at least one of the phase of the first voltage between the first terminal and the second terminal and the phase of the second voltage between the third terminal and the second terminal so that the phase difference between the first voltage and the second voltage becomes a desired phase difference.

[0008] According to this inverter device, in the independent operation mode in which power is supplied from the inverter device to the load while being disconnected from the system, at least one of the phase of the first voltage and the phase of the second voltage is adjusted so that the phase difference between the first voltage and the second voltage becomes the predetermined phase difference. Therefore, the phase difference between the first voltage and the second voltage is maintained at the predetermined phase difference. As a result, this inverter device has the voltage between the first terminal and the third terminal The pressure can be controlled to a desired voltage. That is, according to this inverter device, a decrease in the control accuracy of the voltage between the first terminal and the third terminal is suppressed.

[0009] This inverter device may further have the following features. The control unit determines a first vector obtained by changing the phase of the vector indicating the first voltage between the first terminal and the second terminal by a predetermined amount, and a second vector indicating the second voltage between the second terminal and the third terminal, and adjusts at least one of the phase of the first voltage and the phase of the second voltage so that the voltage indicated by the composite vector of the first vector and the second vector becomes the maximum value of the AC voltage output between the first terminal and the second terminal.

[0010] When the phase difference between the first voltage and the second voltage deviates from the predetermined phase difference, the voltage indicated by the composite vector becomes a value different from the maximum value of the AC voltage output between the first terminal and the second terminal. According to such an inverter device, at least one of the phase of the first voltage and the phase of the second voltage is adjusted so that the voltage indicated by the composite vector becomes the maximum value of the AC voltage output between the first terminal and the second terminal. As a result, the phase of the first voltage and the phase difference between the first voltage and the second voltage are adjusted to the predetermined phase difference.

[0011] This inverter device may further have the following features. The control unit determines the sign of a correction value used for adjusting at least one of the phase of the first voltage and the second phase based on the magnitudes of the current output from the first terminal and the current output from the third terminal.

[0012] According to such an inverter device having such features, the sign of the correction value used for adjusting at least one of the phase of the first voltage and the second phase can be easily determined.

[0013] This inverter device may further have the following features. The control unit performs dq conversion on each of the first voltage and the second voltage, and adjusts the phase of the first voltage and the phase of the second voltage so that both the q-axis voltage related to the first voltage and the q-axis voltage related to the second voltage become "0".

[0014] When a phase difference occurs between the output voltage and the voltage command value, a q-axis voltage is generated in the dq conversion. This inverter device having such a feature adjusts the phase of the first voltage and the phase of the second voltage so that both the q-axis voltage related to the first voltage and the q-axis voltage related to the second voltage become "0", thereby adjusting the phase of the first voltage and the phase difference between the first voltage and the second voltage to the predetermined phase difference. Note that the inverter device may adjust the phase of the first voltage and the phase of the second voltage so that the sum of the q-axis voltage related to the first voltage and the q-axis voltage related to the second voltage becomes "0".

[0015] This inverter device may further have the following features. It further includes a storage unit that stores the correspondence between current and phase delay amount. The control unit acquires a first phase delay amount corresponding to the first current output from the first terminal from the correspondence, acquires a third phase delay amount corresponding to the third current output from the third terminal from the correspondence, and determines a correction value for adjusting at least one of the phase of the first voltage and the phase of the second voltage based on the first phase delay amount and the third phase delay amount.

[0016] The correspondence between current and phase delay amount is determined, for example, at the time of designing this inverter device. According to this inverter device having such a feature, by referring to the correspondence, the phase of the first voltage and the phase difference between the first voltage and the second voltage can be adjusted to the predetermined phase difference.

[0017] This inverter device may further have the following features. This control unit... of the first voltage Calculate a first phase delay amount based on the difference between the zero-crossing point and the zero-crossing point of the first voltage command value for outputting the first voltage, calculate a second phase delay amount based on the difference between the zero-crossing point of the second voltage and the zero-crossing point of the second voltage command value for outputting the second voltage, and determine a correction value used for adjusting at least one of the phase of the first voltage and the phase of the second voltage based on the first phase delay amount and the second phase delay amount.

[0018] According to the inverter device having such a feature, the first phase delay amount and the third phase delay amount can be calculated based on the zero-crossing point, and at least one of the phase of the first voltage and the phase of the second voltage can be adjusted so that the phase difference between the first voltage and the second voltage becomes the predetermined phase difference using these phase delay amounts.

Effect of the Invention

[0019] According to the disclosed technology, even in the case of the self-operating mode in which power is supplied from the inverter device to the load in a state of being disconnected from the system, the voltage between the first phase and the third phase can be maintained at a predetermined voltage.

Brief Description of the Drawings

[0020]

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DETAILED DESCRIPTION OF THE INVENTION

[0021] <APPLICATION EXAMPLE> An application example of the present invention will be described. An application example of the present invention is, for example, an inverter device 1 illustrated in FIG. 1. The inverter device 1 DC / DC-converts the DC power input from the storage battery 82 by the converter circuit 14. Then, in the inverter device 1, the DC power DC / DC-converted by the converter circuit 14 is output as single-phase three-wire AC power by the inverter circuit 10. A U-phase power line 21 is connected to the U-phase terminal 11 of the inverter device 1. An O-phase power line 22 is connected to the O-phase terminal 12 of the inverter device 1. A W-phase power line 23 is connected to the W-phase terminal 13 of the inverter device 1. |

[0022] In the case of the interconnection operation between the inverter device 1 and the power system, the voltage of each phase is controlled by the power system, and the inverter device 1 performs current control. On the other hand, in the self-operating mode in which power is supplied from the inverter device 1 to the load in a state of being disconnected from the power system, the inverter device 1 performs voltage control. The inverter device 1 performs voltage control so that, for example, the voltage between U and O and the voltage between W and O become 100 V rms Since the phase difference between the voltage between U and O and the voltage between W and O is 180 degrees, the voltage between U and W supplied by the inverter device 1 is 200 V, which is twice the voltage between U and O (or the voltage between W and O). rms becomes.

[0023] However, if there is a bias in the loads connected to the U-phase power line 21 and the O-phase power line 22, and the loads connected to the W-phase power line 23 and the O-phase power line 22, the phase difference between the U-O voltage and the W-O voltage may deviate from 180 degrees. In such a case, the voltage between U and W becomes lower than twice the voltage between U and O. That is, when the phase difference between the U-O voltage and the W-O voltage deviates from 180 degrees, the control accuracy of the voltage between U and W decreases, and a desired voltage cannot be obtained.

[0024] Therefore, when the inverter device 1 according to this application example transitions to the self-supporting mode in which it is disconnected from the power grid and the inverter device 1 supplies power to the load, at least one of the phase of the voltage between U and O and the phase of the voltage between W and O is adjusted so that the phase difference between the voltage between U and O and the voltage between W and O becomes 180 degrees.

[0025] According to this application example, since at least one of the phase of the voltage between U and O and the phase of the voltage between W and O is adjusted so that the phase difference between the voltage between U and O and the voltage between W and O becomes 180 degrees, the voltage between U and W can be maintained at twice the voltage between U and O. That is, according to this application example, a decrease in the control accuracy of the voltage between U and W can be suppressed.

[0026] <Embodiment> Hereinafter, embodiments will be described with reference to the drawings. FIG. 1 is a diagram showing an example of the inverter device 1 according to the embodiment. The inverter device 1 performs DC / DC conversion on the DC power input from the storage battery 82 by the converter circuit 14, and the inverter circuit 10 converts the converted DC power into single-phase three-wire AC power and outputs it.

[0027] The inverter device 1 includes a converter circuit 14 and an inverter circuit 10. The converter circuit 14 performs DC / DC conversion on the DC power input from the storage battery 82 and outputs the converted DC power to the inverter circuit 10.

[0028] The inverter circuit 10 has, for example, a processor, a memory, and a predetermined electric circuit, and outputs the DC power input from the converter circuit 14 as single-phase three-wire AC power of the U-phase, O-phase, and W-phase. The inverter circuit 10 outputs the power of the U-phase to the U-phase terminal 11 and the power of the W-phase to the W-phase terminal 13. For example, a ground side wire is connected to the O-phase terminal 12. The O-phase terminal 12 is used, for example, as a reference potential. Note that a ground side wire may be connected to the O-phase terminal 12 There may be cases where it is not. The inverter circuit 10 performs voltage control so that the U-O voltage between the U-phase and the O-phase and the W-O voltage between the W-phase and the O-phase become a predetermined effective voltage. In the present embodiment, the predetermined effective voltage is, for example, 100V rms It is.

[0029] A U-phase power line 21 is connected to the U-phase terminal 11. An O-phase power line 22 is connected to the O-phase terminal 12. A W-phase power line 23 is connected to the W-phase terminal 13. Loads can be connected between the U-phase power line 21 and the O-phase power line 22, between the W-phase power line 23 and the O-phase power line 22, and between the U-phase power line 21 and the W-phase power line 23, respectively. In the example of FIG. 1, a 100V load 2 is connected between the U-phase power line 21 and the O-phase power line 22, a 100V load 3 is connected between the W-phase power line 23 and the O-phase power line 22, and a 200V load 4 is connected between the U-phase power line 21 and the W-phase power line 23.

[0030] FIG. 2 is a diagram showing an example of voltage control by the inverter circuit 10. The vertical axis in FIG. 2 illustrates voltage, and the horizontal axis illustrates time. The graph G1 illustrates the time-series change of the U-O voltage. The graph G2 illustrates the time-series change of the W-O voltage. The inverter circuit 10 controls so that the effective voltage between U and O and the effective voltage between W and O of the voltage each become 100V rms And the phase difference between the U-O voltage and the W-O voltage is controlled to 180 degrees. As a result, as illustrated by the arrow G4, the effective voltage between U and W between the U-phase and the W-phase is 200V rmsIt becomes. That is, the voltage between U and W in the inverter device 1 is generated as a result of controlling the voltage between U and O and the voltage between W and O. The time-series change of the voltage between U and W generated in this way is illustrated by the graph G3.

[0031] FIG. 3 is a vector diagram showing an example of voltage control by the inverter circuit 10 according to the embodiment. In FIG. 3, as illustrated in FIG. 1, a vector diagram is illustrated when 100V loads 2 and 3 are connected between the U-phase power line 21 and the O-phase power line 22, and between the W-phase power line 23 and the O-phase power line 22, respectively. Further, in FIG. 3, a vector diagram is illustrated when there is no bias in the loads connected to the U-phase power line 21 and the O-phase power line 22 of the inverter device 1 and the loads connected to the W-phase power line 23 and the O-phase power line 22.

[0032] In FIG. 3, the inclination of each vector G11, G12, G13, G14 with respect to the X axis illustrates the phase delay or advance, and the length of each vector G11, G12, G13, G14 illustrates the effective voltage. Vector G11 illustrates the voltage command value of the voltage between U and O. Vector G12 illustrates the voltage command value of the voltage between W and O. Vector G13 illustrates the voltage between U and O generated by the voltage command value illustrated by vector G11. Vector G14 illustrates the voltage between W and O generated by the voltage command value illustrated by vector G12. The voltage between U and W is the voltage indicated by the composite vector generated by vector G13 indicating the voltage between U and O and vector G14 indicating the voltage between U and W.

[0033] The delay of vectors G13 and G14 with respect to vectors G11 and G12 occurs due to the loads connected to the U-phase power line 21, the O-phase power line 22, and the W-phase power line 23 acting as disturbances. In the example of FIG. 3, as in FIG. 1, since there is no bias in the loads connected to the U-phase power line 21, the O-phase power line 22, and the W-phase power line 23, the delay with respect to the voltage command values of the voltage between U and O and the voltage between W and O is both the delay α1.

[0034] Since the delays occurring with respect to the voltage command value are equal for the voltage between U and O and the voltage between W and O, the effective voltage between U and W is 100 V, which is the effective voltage between U and O rms and 100 V, which is the effective voltage between W and O rms added together to give 200 V rms as a result.

[0035] Here, if there is a bias in the load connected to the U-phase power line 21 and the O-phase power line 22 of the inverter device 1 operating in the self-sustained operation mode, and the load connected to the W-phase power line 23 and the O-phase power line 22 has a bias, the phase difference between the voltage between U and O and the voltage between W and O may deviate from 180 degrees. When the phase difference deviates from 180 degrees, the effective voltage between U and W deviates from 200 V rms accordingly.

[0036] FIG. 4 is a diagram illustrating a case where there is a bias in the load connected to the inverter device 1 in the embodiment. In the example of FIG. 4, a 100 V load 3 is connected between the W-phase power line 23 and the O-phase power line 22, while no load is connected between the U-phase power line 21 and the O-phase power line 22.

[0037] FIG. 5 is a vector diagram showing an example of voltage control by the inverter circuit 10 according to the embodiment. FIG. 5 illustrates a vector diagram in the case where, as illustrated in FIG. 4, a 100 V load 3 is connected between the W-phase power line 23 and the O-phase power line 22, while no load is connected between the U-phase power line 21 and the O-phase power line 22.

[0038] In FIG. 5, the slopes of the vectors G21, G22, G23, and G24 with respect to the X-axis illustrate phase delays or advances, and the lengths of the vectors G21, G22, G23, and G24 illustrate the effective values of the voltages. Vector G21 illustrates the voltage command value of the voltage between U and O. Vector G22 illustrates the voltage command value of the voltage between W and O. Vector G23 illustrates the voltage between U and O generated by the voltage command value illustrated by vector G21. Vector G24 illustrates the voltage between W and O generated by the voltage command value illustrated by vector G22. The voltage between U and W is the voltage indicated by the resultant vector generated by vector G23 indicating the voltage between U and O and vector G24 indicating the voltage between W and O.

[0039] Here, in the example of FIG. 4, the inverter device 1 is operating in the self-sustained operation mode. Therefore, due to the influence of the bias of the connected load, the delay α2 of the voltage between U and O illustrated by vector G23 with respect to the voltage command value illustrated by vector G21 and the delay α3 of the voltage between W and O illustrated by vector G14 with respect to the voltage command value illustrated by vector G12 are different values.

[0040] Since the delays that occur with respect to the voltage command value in the voltage between U and O and the voltage between W and O are different, the effective voltage between U and W is lower than the sum of 100 V, which is the effective voltage between U and O, rms and 100 V, rms which is the effective voltage between W and O, rms and is 200 V. That is, in the inverter device 1, if there is a bias between the load connected between the U-phase power line 21 and the O-phase power line 22 and the load connected between the U-phase power line 21 and the O-phase power line 22, the control accuracy of the effective voltage between U and W may decrease.

[0041] That is, in the inverter device 1, when there is a bias in the load connected in the self-operating mode, the control accuracy of the effective voltage between U and W decreases. Further, when there is a bias between the load connected between the W-phase power line 23 and the O-phase power line 22 and the load connected between the U-phase power line 21 and the O-phase power line 22, the control accuracy of the effective voltage between U and W further decreases. In the present embodiment, in order to avoid such a decrease in the control accuracy of the effective voltage between U and W, the following configuration is adopted.

[0042] FIG. 6 is a diagram showing an example of a processing block realized by the inverter circuit 10 of the inverter device 1 according to the embodiment. The inverter circuit 10 includes an adjustment unit 101, a voltage control unit 102, and a storage unit 103. The inverter circuit 10 executes a computer program developed to be executable in a memory, thereby executing the processing of each part such as the adjustment unit 101 and the voltage control unit 102 of the inverter circuit 10. Note that at least a part of the adjustment unit 101 and the voltage control unit 102 may be realized by a hardware circuit.

[0043] The adjustment unit 101 adjusts at least one of the voltage command values of the voltage between U and O and the voltage between W and O so that the phase difference between the voltage between U and O and the voltage between W and O is maintained at 180 degrees. The voltage control unit 102 controls the voltage between U and O and the voltage between W and O according to the voltage command value adjusted by the adjustment unit 101.

[0044] The storage unit 103 is a non-volatile auxiliary storage unit. The storage unit 103 is, for example, an Erasable Programmable ROM (EPROM), a Solid State Drive (SSD), a Hard Disk Drive (HDD), or the like.

[0045] FIG. 7 is a vector diagram illustrating a state in which the phase of the voltage command value is adjusted by the inverter circuit 10 in the embodiment. In FIG. 7, a state in which the inverter circuit 10 adjusts the voltage command value of the voltage between W and O in the state of FIG. 5 is illustrated.

[0046] In FIG. 7, the slopes of the vectors G31, G32, G33, G34 with respect to the X-axis illustrate phase delays or advances, and the lengths of the vectors G31, G32, G33, G34 illustrate the effective values of the voltages. Vector G31 illustrates the voltage command value of the voltage between U and O. Vector G32 illustrates the voltage command value of the voltage between W and O. Vector G33 illustrates the voltage between U and O generated by the voltage command value illustrated by vector G31. Vector G34 illustrates the voltage between W and O generated by the voltage command value illustrated by vector G32. The voltage between U and W is the voltage indicated by the composite vector generated by vector G33 indicating the voltage between U and O and vector G34 indicating the voltage between U and W.

[0047] The delay of the voltage between W and O (vector G34) with respect to the voltage command value of the voltage between W and O (vector G32) by the adjustment unit 101 of the inverter circuit 10 becomes α5 adjusted so that the phase difference from the voltage between U and O is 180 degrees. As a result of the adjustment by the adjustment unit 101, since the phase difference between the voltage between U and O and the voltage between W and O is 180 degrees, the effective voltage between U and W is 100 V, which is the effective voltage between U and O rms and 100 V, which is the effective voltage between W and O rms added to obtain 200 V rms Therefore, according to the present embodiment, even in the case of the self-sustained operation mode in which power is supplied from the inverter device 1 to the load separated from the power system, the voltage between U and W can be maintained at 200 V rms

[0048] (Implementation example of the adjustment unit 101) The above adjustment unit 101 can be realized by various implementation methods. Hereinafter, with reference to the drawings, an implementation example of the adjustment unit 101 described above will be described.

[0049] (First implementation example) ​In the first implementation example, at least one of the voltage command value of the voltage between U and O and the voltage command value of the voltage between W and O is adjusted so that the voltage indicated by the composite vector of the vector obtained by changing the phase of the vector indicating the voltage between U and O by a predetermined amount and the vector indicating the voltage between W and O becomes the desired effective voltage value.

[0050] FIG. 8 is a block diagram showing an example of the first implementation example of the adjustment unit 101. In the first implementation example, the adjustment unit 101 includes an all-pass filter 111, an effective value calculation unit 112, an integrator 113, and an oscillation unit 114.

[0051] The voltage between U and O is input to the all-pass filter 111. By inputting the voltage between U and O to the all-pass filter 111, the phase of the voltage between U and O is advanced by 90 degrees. A value obtained by subtracting the voltage between W and O from the voltage between U and O whose phase has been advanced by 90 degrees is input to the effective value calculation unit 112. The effective value calculation unit 112 calculates the effective value of the voltage based on the input value.

[0052] A voltage deviation obtained by subtracting the calculation result by the effective value calculation unit 112 from 100√2V is input to the integrator 113. The integrator 113 converts the input voltage deviation into a phase by multiplying it by "K / TS". Here, "T" is the integration time constant, and "K" is the unit conversion gain. The unit conversion gain is a coefficient determined based on the relationship between the phase and the voltage deviation. The unit conversion gain will be described later with reference to FIG. 9.

[0053] The oscillation unit 114 outputs a self-oscillation reference θ indicating a reference frequency. The self-oscillation reference θ output by the oscillation unit 114 is, for example, a signal indicating the same frequency as the frequency of the power supplied by the system. The frequency indicated by the self-oscillation reference θ output by the oscillation unit 114 is, for example, 50 Hz. The adjustment unit 101 determines a correction value for the voltage command value of the voltage between W and O by subtracting the calculation result of the integrator 113 from the self-oscillation reference θ output by the oscillation unit 114.

[0054] FIG. 9 is a diagram for explaining the unit conversion gain in the embodiment. The vertical axis in FIG. 9 illustrates the phase, and the horizontal axis illustrates the voltage deviation. The voltage deviation is, for example, a value obtained by subtracting the operation result by the effective value calculation unit 112 from 100√2V. The relationship between the phase and the voltage deviation is approximated by a straight line illustrated by the graph L41 in FIG. 9. The graph L41 is represented by a linear equation "y = Kx + b". Here, "y" is the phase, "x" is the voltage deviation, "K" is the unit conversion gain, and "b" is a constant. That is, the unit conversion gain "K" is determined as the slope of the graph L41 showing the relationship between the phase and the voltage deviation.

[0055] FIG. 10 is a vector diagram illustrating a case where the voltage command value between W and O is not adjusted by the adjustment unit 101 in the first implementation example. In FIG. 10, as a result of the phase delay of the voltage between W and O, the effective voltage between U and W becomes 200V rms The case where it is less than will be described.

[0056] In FIG. 10, the slopes of the vectors G41, G42, G43, G44, G46, and G47 with respect to the X-axis illustrate the phase delay or advance, and the lengths of the vectors G41, G42, G43, G44, G46, and G47 illustrate the effective values of the voltages. The vector G41 illustrates the voltage command value of the voltage between U and O. The vector G42 illustrates the voltage command value of the voltage between W and O. The vector G43 illustrates the voltage between U and O generated by the voltage command value illustrated by the vector G41. The vector G44 illustrates the voltage between W and O generated by the voltage command value illustrated by the vector G42. The voltage between U and W is the voltage indicated by the composite vector generated by the vector G43 indicating the voltage between U and O and the vector G44 indicating the voltage between W and O. The vector G46 illustrates a state where the phase of the voltage between U and O is advanced by 90 degrees by the all-pass filter 111. The vector G47 illustrates a composite vector calculated from the voltage between W and O illustrated by the vector G44 and the voltage between U and O with the phase advanced by 90 degrees illustrated by the vector G46.

[0057] Here, it is assumed that the phase difference between the voltage command value of the U-O voltage exemplified by the vector G41 and the U-O voltage exemplified by the vector G43 is α4. Also, it is assumed that the phase difference between the voltage command value of the W-O voltage exemplified by the vector G42 and the W-O voltage exemplified by the vector G44 is α5. In the case of the example in FIG. 10, if the adjustment by the adjustment unit 101 is not performed, the effective voltage calculated by the effective value calculation unit 112 is less than 100√2 V.

[0058] FIG. 11 is a vector diagram illustrating a case where the voltage command value of the W-O voltage is adjusted by the adjustment unit 101 in the first implementation example. Since the vectors G41, G43, G46 and the phase differences α4, α5 are the same as those in FIG. 10, the description thereof is omitted. The vector G52 exemplifies the voltage command value of the W-O voltage corrected by the adjustment unit 101. The vector G54 exemplifies the W-O voltage generated by the voltage command value exemplified by the vector G52. The U-W voltage is the voltage indicated by the composite vector generated by the vector G43 indicating the U-O voltage and the vector G5 4.

[0059] The voltage command value of the W-O voltage by the adjustment unit 101 is adjusted from the vector G42 (see FIG. 10) to the vector G52. As a result, the phase difference with respect to the X-axis of the vector G42, which was "0", becomes α6 with respect to the X-axis in the vector G52. As a result, the phase difference with respect to the X-axis of the W-O voltage exemplified by the vector G54 becomes "α5 + α6", and the vector G52 is delayed in phase from the vector G42. The phase difference α6 is determined so that the phase difference between the vector G54 and the vector G43 becomes 180 degrees. As a result, the effective voltage calculated by the effective value calculation unit 112 based on the W-O voltage exemplified by the vector G54 exemplified by the vector G57 and the U-O voltage with a 90-degree advanced phase exemplified by the vector G46 becomes 100√2 V.

[0060] In FIGS. 10 and 11, due to the delay in the phase of the W-O voltage, the effective voltage between U and W is 200 V rmsAlthough the adjustment when it becomes smaller has been described, the effective voltage between U and W becomes 200V due to the phase of the effective voltage between W and O advancing. rms The adjustment when it becomes smaller is the same. That is, the effective voltage between U and W becomes 200V due to the phase of the voltage between W and O advancing. rms When it becomes smaller than 200V, the phase of the voltage command value of the voltage between W and O may be advanced so that the phase difference between the vector indicating the voltage between U and O and the vector indicating the voltage between W and O becomes 180 degrees.

[0061] In the first implementation example described above, the phase of the voltage command value between W and O is adjusted, but the phase of the voltage command value between U and O may also be adjusted. Also, in the first implementation example, the all-pass filter 111 is adopted, but an element other than the all-pass filter 111 may be adopted as long as it can change the phase of the voltage between U and O. Further, in the first implementation example, the phase of the voltage between U and O is changed by 90 degrees by the all-pass filter 111, but it may be changed to a phase other than 90 degrees by an element other than the all-pass filter 111. Also, the all-pass filter 111 may be applied to the voltage between W and O.

[0062] When the phase difference between the voltage between U and O and the voltage between W and O deviates from 180 degrees, the voltage indicated by the composite vector exemplified by the vector G47 becomes a value different from 100√2V. In the first implementation example, at least one of the voltage command value of the voltage between U and O and the voltage command value of the voltage between W and O is adjusted so that the voltage indicated by the composite vector exemplified by the vector G47 becomes 100√2V, whereby the effective voltage between U and W can be controlled to 200V. rms can be controlled.

[0063] (Second implementation example) FIG. 12 is a block diagram showing an example of a second implementation example of the adjustment unit 101. In the second implementation example, the adjustment unit 101 includes an integrator 113, an oscillator 114, a switch 115, and a determination unit 116. In the second implementation example, the switch 115 switches the direction of phase adjustment. Note that the same reference numerals are given to the components common to the first implementation example, and the description thereof is omitted.

[0064] Switch 115 is a switch that switches according to a selection signal input from the determination unit 116 to the terminals P1 and P2. To terminal P1 of switch 115, 200V rms and the difference from the effective voltage between U and W are input. Also, to terminal P2 of switch 115, 200V rms and the value obtained by multiplying the difference from the effective voltage between U and W by "-1" are input.

[0065] The determination unit 116 determines whether to switch switch 115 to terminal P1 or terminal P2 using the effective current value of the U-phase and the effective current value of the W-phase. When the effective current value of the U-phase flowing through the U-phase power line 21 is smaller than the effective current value of the W-phase flowing through the W-phase power line 23, the determination unit 116 outputs a selection signal for selecting terminal P1 to switch 115. Also, determination unit 1 116 outputs a selection signal for selecting terminal P2 to switch 115 when the effective current value of the U-phase flowing through the U-phase power line 21 is larger than the effective current value of the W-phase flowing through the W-phase power line 23.

[0066] The integrator 113 receives an input from either one of the terminals P1 and P2 of switch 115. The adjustment unit 101 subtracts the value output from the integrator 113 from the self-oscillation reference θ output by the oscillation unit 114 to determine a correction value for the phase of the voltage command value of the voltage between W and O.

[0067] FIG. 13 is a first vector diagram illustrating a state in which the effective voltage between U and W is not adjusted to 200V rms in the second implementation example. The example of FIG. 13 illustrates a vector diagram in a case where, for example, a 100V load 3 is connected between the W-phase power line 23 and the O-phase power line 22, while no load is connected between the U-phase power line 21 and the O-phase power line 22 (see FIG. 4).

[0068] In FIG. 13, the slopes of the vectors G61, G62, G63, G64, and G65 with respect to the X-axis illustrate phase delays or advances, and the lengths of the vectors G61, G62, G63, G64, and G65 illustrate the effective values of the voltages. The vector G61 illustrates the voltage command value of the voltage between U and O. The vector G62 illustrates the voltage command value of the voltage between W and O. The vector G63 illustrates the voltage between U and O generated by the voltage command value illustrated by the vector G61. The vector G64 illustrates the voltage between W and O generated by the voltage command value illustrated by the vector G62. The vector G65 illustrates the voltage between U and W generated by the voltage between U and O and the voltage between U and W.

[0069] In the example of FIG. 13, since a 100V load 3 is connected between the W-phase power line 23 and the O-phase power line 22 while no load is connected between the U-phase power line 21 and the O-phase power line 22, the effective value of the current in the U-phase becomes smaller than the effective value of the current in the W-phase. Therefore, at the switch 115, the terminal P1 is selected. That is, in the example of FIG. 13, the phase output by the integrator 113 is subtracted from the self-oscillation reference θ output by the oscillation unit 114 to determine the correction value for the voltage command value. By selecting the terminal P1, as illustrated in FIG. 13, the phase of the voltage command value of the voltage between U and O illustrated by the vector G61 is adjusted in the negative direction.

[0070] Also, for example, when no load is connected between the W-phase power line 23 and the O-phase power line 22 while a 100V load 2 is connected between the U-phase power line 21 and the O-phase power line 22, the effective value of the current in the U-phase becomes larger than the effective value of the current in the W-phase. Therefore, at the switch 115, the terminal P2 is selected. That is, the value obtained by multiplying the phase output by the integrator 113 by "-1" is subtracted from the self-oscillation reference θ output by the oscillation unit 114 to determine the correction value for the voltage command value. By selecting the terminal P2, the voltage command value of the voltage between U and O illustrated by the vector G61 is adjusted in the positive direction.

[0071] (Third implementation example) In the third embodiment, the voltage between U and O and the voltage between W and O are divided into the d-axis direction and the q-axis direction. Here, the component in the q-axis direction appears when the effective value of the voltage deviates from the voltage command value. Therefore, in the third embodiment, by controlling the q-axis voltage to be "0", the phase difference between the voltage between U and O and the voltage between W and O is set to 180 degrees.

[0072] FIG. 14 is a block diagram showing an example of a third implementation example of the adjustment unit 101. In the third implementation example, the adjustment unit 101 includes an all-pass filter 111, an integrator 113, an oscillation unit 114, and a converter 117.

[0073] In the example of FIG. 14, a configuration for adjusting the phase of the voltage command value of the voltage between U and O will be described. FIG. 15 is a vector diagram illustrating the state before adjustment according to the third embodiment. The upper part of FIG. 15 is a diagram illustrating the voltage command value of the voltage between U and O, the voltage between U and O, the voltage command value of the voltage between W and O, the voltage between W and O, and the voltage between U and W. The lower part of FIG. 15 is a diagram illustrating the state where the voltage between U and O is converted into the d-axis voltage and the q-axis voltage.

[0074] In FIG. 15, the inclination of each vector G71, G72, G73, G74 with respect to the X axis illustrates the phase delay or advance, and the length of each vector G71, G72, G73, G74 illustrates the voltage. Vector G71 illustrates the voltage command value of the voltage between U and O. Vector G72 illustrates the voltage command value of the voltage between W and O. Vector G73 illustrates the voltage between U and O generated by the voltage command value illustrated by vector G71. Vector G74 illustrates the voltage between W and O generated by the voltage command value illustrated by vector G72. The voltage between U and W is the voltage indicated by the composite vector generated by vector G73 indicating the voltage between U and O and vector G74 indicating the voltage between W and O. Also, vector G76 illustrates the d-axis voltage related to the effective voltage between U and O. Vector G77 illustrates the q-axis voltage related to the voltage between U and O.

[0075] The converter 117 receives the voltage between U and O and the voltage between U and O whose phase has been advanced by 90 degrees by the all-pass filter 111. The converter 117 further receives the self-oscillation reference θ output from the oscillation unit 114.

[0076] Based on the input voltage between U and O, the voltage between U and O whose phase has been advanced by 90 degrees by the all-pass filter 111, and the self-oscillation reference θ, the converter 117 converts the voltage between U and O into the d-axis voltage (not shown) of the U phase exemplified by the vector G76 and the q-axis voltage (V q_uo ) of the U phase exemplified by the vector G77. Then, the converter 117 outputs the converted q-axis voltage (V q_uo ) of the U phase. For the conversion of the voltage between U and O into the d-axis voltage and the q-axis voltage, for example, the technique described in Japanese Patent Application Laid-Open No. 2012-050215 can be adopted. Similarly, for the voltage between W and O, it is converted into the d-axis voltage (not shown) of the W phase and the q-axis voltage (V q_wo ) of the W phase exemplified by the vector G78.

[0077] The integrator 113 receives the value obtained by subtracting the q-axis voltage (V q_uo ) of the U phase from the converter 117 from 0. The integrator 113 converts the input value into a phase. The adjustment unit 101 determines the result of subtracting the phase converted by the integrator 113 from the self-oscillation θ as the phase correction value for the voltage command value of the voltage between U and O. Similarly, for the q-axis voltage (V q_wo ) of the W phase, the phase correction value for the voltage command value of the voltage between W and O is determined. By such processing, the phase correction value for the voltage command value of the voltage between U and O that makes the q-axis voltage (V q_uo ) of the U phase "0", and the phase correction value for the voltage command value of the voltage between W and O that makes the q-axis voltage (V q_wo ) of the W phase "0" are determined.

[0078] FIG. 16 is a vector diagram illustrating the adjustment result according to the third implementation example. In the example of FIG. 16, the q-axis voltage (V q_uo ) of the U phase and the q-axis voltage (V q_wo) As a result of determining the phase correction value for the voltage command value of the voltage between W and O so that all of them become "0", the phase difference between the voltage between U and O and the voltage between W and O becomes 180 degrees. Therefore, the voltage between U and O can be controlled to 200V rms can be controlled to

[0079] In the third implementation example, although both the q-axis voltage (V q_uo ) of the U-phase and the q-axis voltage (V q_wo ) of the W-phase are controlled to be "0", according to the following (Equation 1) to (Equation 3), it is also possible to perform control equivalent to making both the q-axis voltage (V q_uo ) and the q-axis voltage (V q_wo ) "0". [Number]

[0080] (Fourth implementation example) In the third implementation example described above, although both the q-axis voltage (V q_uo ) of the U-phase and the q-axis voltage (V q_wo ) of the W-phase are controlled to be "0", it may also be controlled so that the sum of the q-axis voltage (V q_uo ) and the q-axis voltage (V q_wo ) of the W-phase becomes "0". FIG. 17 is a block diagram showing an example of a fourth implementation example of the adjustment unit 101. In the fourth implementation example, the adjustment unit 101 includes all-pass filters 111A and 111B, an integrator 113, an oscillation unit 114, and converters 117A and 117B.

[0081] Similar to the converter 117, the converter 117A converts the input voltage between U and O, the voltage between U and O whose phase has been advanced by 90 degrees by the all-pass filter 111A, and the self-oscillation reference θ into the d-axis voltage and the q-axis voltage (V q_uo ) of the U-phase, and outputs the q-axis voltage (V q_uo ). The converter 117B performs the same processing as the converter 117A for the voltage between W and O. That is, the converter 117B converts the input voltage between W and O, the voltage between W and O whose phase has been advanced by 90 degrees by the all-pass filter 111A, and the self-oscillation reference θ into the d-axis voltage and the q-axis voltage (Vq_wo ) is converted, and the q-axis voltage (V q_wo ) is output.

[0082] The integrator 113 receives as input the value obtained by subtracting from 0 the sum of the q-axis voltage (V q_uo ) of the U-phase from the converter 117A and the q-axis voltage (V q_wo ) of the converter 117B. The integrator 113 converts the input value into a phase. The adjustment unit 101 determines the phase correction value for the voltage command value of the U-O voltage and the phase correction value for the voltage command value of the W-O voltage based on the result of subtracting the phase converted by the integrator 113 from the self-oscillation θ. By such processing, the phase correction value of the voltage command value of the U-O voltage and the phase correction value of the voltage command value of the W-O voltage that make the sum of the q-axis voltage (V q_uo ) of the U-phase and the q-axis voltage (V q_wo ) of the W-phase equal to "0" are determined.

[0083] FIG. 18 is a vector diagram illustrating the adjustment result according to the fourth implementation example. The state before adjustment is illustrated in the upper part of FIG. 15. By the fourth implementation example, the sum of the q-axis voltage (V q_uo ) of the U-phase and the q-axis voltage (V q_wo ) of the W-phase becomes "0", so that the phase difference between the U-O voltage and the W-O voltage becomes 180 degrees. Therefore, the U-O voltage can be controlled to 200V rms .

[0084] Note that in the fourth implementation example, the sum of the q-axis voltage (V q_uo ) of the U-phase and the q-axis voltage (V q_wo ) of the W-phase is controlled to be "0", but control equivalent to making the sum of the q-axis voltage (V q_uo ) and the q-axis voltage (V q_wo ) equal to "0" is also possible by the following (Equation 4) to (Equation 5). [Number]

[0085] (Fifth implementation example) In the fifth implementation example, the correspondence relationship between the effective current and the phase delay amount is stored in the storage unit 103 in advance, and at least one of the phase of the voltage command value of the voltage between U and O and the phase of the voltage command value of the voltage between W and O is adjusted using the correspondence relationship.

[0086] FIG. 19 is a block diagram showing an example of the fifth implementation example of the adjustment unit 101. In the fifth implementation example, the adjustment unit 101 includes determination units 118A and 118B, an integrator 113A, and an oscillation unit 114.

[0087] The determination unit 118A determines the phase delay amount corresponding to the input effective current value of the U phase based on the correspondence relationship between the effective current value of the U phase and the phase delay amount stored in the storage unit 103 in advance. The determination unit 118B determines the phase delay amount corresponding to the input effective current value of the W phase based on the correspondence relationship between the effective current value of the W phase and the phase delay amount stored in the storage unit 103 in advance.

[0088] FIG. 20 is a diagram illustrating the correspondence relationship between the phase delay amount and the current. In FIG. 20, the vertical axis illustrates the phase delay amount, and the horizontal axis illustrates the current. The current is the effective current value of the U phase or the effective current value of the W phase. Referring to FIG. 20, it can be understood that the phase delay amount increases as the current increases. The correspondence relationship illustrated in FIG. 20 is determined, for example, by a test during the manufacture of the inverter device 1. The correspondence relationship illustrated in FIG. 20 is stored in the storage unit 103, for example.

[0089] The integrator 113A receives as input the phase obtained by subtracting the phase delay amount of the W phase determined by the determination unit 118B from the phase delay amount of the U phase determined by the determination unit 118A. The integrator 113 outputs a value obtained by multiplying the input phase by "1 / TS".

[0090] The adjustment unit 101 determines a correction value for the phase of the voltage command value of the voltage between U and O or the phase of the voltage command value of the voltage between W and O by subtracting the phase output by the integrator 113A from the self-oscillation reference θ.

[0091] Although the correspondence between the phase delay amount and the current was briefly introduced with reference to FIG. 20, the phase delay amount may be associated with the active power and the reactive power. FIG. 21 is a diagram illustrating another example of the correspondence between the phase delay amount and the current. In the region R1 of FIG. 21, the value of the active power is stored. In the region R2, the value of the reactive power is stored. In the region R3, the phase delay amount associated with the active power and the reactive power is stored. The determination units 118A and 118B may determine the phase delay amount based on the correspondence illustrated in FIG. 21 when the active power and the reactive power are input instead of the effective current value. Note that the correspondence illustrated in FIG. 21 is stored in the storage unit 103, for example.

[0092] According to the fifth implementation example as well, since the phases of the U-O voltage and the W-O voltage can be adjusted, the U-W voltage can be controlled to 200V rms to be controlled.

[0093] (Sixth implementation example) In the sixth implementation example, a configuration will be described in which the phase delay at the zero cross is detected and at least one of the phase of the voltage command value of the U-O voltage and the phase of the voltage command value of the W-O voltage is adjusted.

[0094] FIG. 22 is a block diagram showing an example of the sixth implementation example of the adjustment unit 101. In the sixth implementation example, the adjustment unit 101 includes calculation units 119A and 119B, an integrator 113A, and an oscillation unit 114.

[0095] The voltage command value of the U-O voltage and the voltage value of the U-O phase are input to the calculation unit 119A. The calculation unit 119A calculates the phase delay amount from when the voltage command value of the U-O voltage crosses “0” until the voltage value of the U-O phase crosses “0”. The calculation unit 119A outputs the calculated phase delay amount.

[0096] The voltage command value of the W-O voltage and the voltage value of the W-O phase are input to the calculation unit 119B. The calculation unit 119B calculates the phase delay amount from when the voltage command value of the W-O voltage crosses “0” until the voltage value of the W-O phase crosses “0”. The calculation unit 119B outputs the calculated phase delay amount.

[0097] FIG. 23 is a diagram schematically showing the amount of phase delay at the time of zero crossing. The vertical axis in FIG. 23 illustrates voltage, and the horizontal axis illustrates time. Graph G81 illustrates the voltage command value. Graph G82 illustrates the voltage value. In the example of FIG. 23, for example, the voltage command value crosses zero at time T1, and the voltage value crosses zero at time T2. The calculation units 119A and 119B calculate the amount of phase delay based on the time difference from time T1 to time T2.

[0098] The integrator 113A receives a phase obtained by subtracting the amount of phase delay calculated by the calculation unit 119B from the amount of phase delay calculated by the calculation unit 119A. The integrator 113 outputs a value obtained by multiplying the input phase by "1 / TS".

[0099] The adjustment unit 101 determines a correction value for the phase of the voltage command value between U and O or the phase of the voltage command value between W and O by subtracting the phase output by the integrator 113A from the self-oscillation reference θ.

[0100] According to the sixth implementation example, since the phases of the voltage between U and O and the voltage between W and O can be adjusted, the voltage between U and W can be controlled to 200V rms can be controlled.

[0101] <Modification Example> In the embodiment described above, the inverter device 1 includes the inverter circuit 10 and the converter circuit 14, but the converter circuit 14 may be a device separate from the inverter device 1.

[0102] The embodiments and modification examples disclosed above can be combined with each other.

[0103] <Appendix 1> A first terminal (11) that outputs a first phase of single-phase alternating current, A second terminal (12) connected to the neutral line, A third terminal (13) that outputs a second phase of the single-phase alternating current, A control unit (10) that adjusts at least one of the phase of the first voltage and the phase of the second voltage so that the phase difference between the first voltage between the first terminal (11) and the second terminal (12) and the second voltage between the third terminal (13) and the second terminal (12) becomes a predetermined phase difference. Inverter device (1). <Appendix 2> The control unit (10) is Determine a first vector in which the phase of the vector indicating the first voltage between the first terminal (11) and the second terminal (12) is changed by a predetermined amount, and a second vector indicating the second voltage between the second terminal (11) and the third terminal (13), Adjust at least one of the phase of the first voltage and the phase of the second voltage so that the voltage indicated by the combined vector of the first vector and the second vector becomes a desired AC voltage to be output between the first terminal and the second terminal. The inverter device (1) according to Appendix 1. <Appendix 3> The control unit (10) is based on the magnitudes of the current output from the first terminal (11) and the current output from the third terminal (13) to determine the sign of the correction value used to adjust at least one of the phase of the first voltage and the phase of the second voltage. The inverter device (1) according to Appendix 1. <Appendix 4> The control unit (10) performs dq conversion on each of the first voltage and the second voltage, and adjusts the phase of the first voltage and the phase of the second voltage so that both the q-axis voltage related to the first voltage and the q-axis voltage related to the second voltage become "0". The inverter device (1) according to Appendix 1. <Appendix 5> The control unit (10) performs dq conversion on each of the first voltage and the second voltage, and adjusts the phase of the first voltage and the phase of the second voltage so that the sum of the q-axis voltage related to the first voltage and the q-axis voltage related to the second voltage becomes "0". The inverter device (1) according to Appendix 1. <Appendix 6> further comprising a storage unit (103) for storing the correspondence relationship between the current and the phase delay amount, the control unit, obtains a first phase delay amount corresponding to a first current output from the first terminal (11) from the correspondence relationship, obtains a third phase delay amount corresponding to a third current output from the third terminal (13) from the correspondence relationship, determines a correction value for adjusting at least one of the phase of the first voltage and the phase of the second voltage based on the first phase delay amount and the third phase delay amount, the inverter device (1) according to Appendix 1. <Appendix 7> the control unit, calculates a first phase delay amount based on the difference between the zero-crossing point of the first voltage and the zero-crossing point of the first voltage command value for outputting the first voltage, calculates a second phase delay amount based on the difference between the zero-crossing point of the second voltage and the zero-crossing point of the second voltage command value for outputting the second voltage, determines a correction value for use in adjusting at least one of the phase of the first voltage and the phase of the second voltage based on the first phase delay amount and the second phase delay amount, the inverter device (1) according to Appendix 1.

Explanation of Reference Signs

[0104] 1 ·· Inverter device 2 ·· 100V load 3 ·· 100V load 4 ·· 200V load 10 ·· Inverter circuit 11 ·· U-phase terminal 12 ·· O-phase terminal 13 ·· W-phase terminal 14 ·· Converter circuit 21 ·· U-phase power line 22 ·· O-phase power line 23 ·· W-phase power line 82 ·· Storage battery 101 ·· Adjustment unit 102··Voltage control unit 111··All-pass filter 112··RMS value calculation unit 113··Integrator 113A··Integrator 114··Oscillator 115··Switch 116··Judgment unit 117··Converter 118A··Calculation unit 118B··Calculation unit 119A··Calculation unit 119B··Calculation unit P1··Terminal P2··Terminal

Claims

1. A first terminal that outputs a first phase of single-phase alternating current, A second terminal connected to the neutral line, A third terminal that outputs a second phase of the single-phase alternating current, A control unit that adjusts at least one of the phase of the first voltage and the phase of the second voltage so that a phase difference between a first voltage between the first terminal and the second terminal and a second voltage between the third terminal and the second terminal becomes a predetermined phase difference. An inverter device comprising: An inverter device.

2. The control unit, Determines a first vector in which the phase of a vector indicating the first voltage between the first terminal and the second terminal is changed by a predetermined amount, and a second vector indicating the second voltage between the second terminal and the third terminal, Adjusts at least one of the phase of the first voltage and the phase of the second voltage so that the voltage indicated by the combined vector of the first vector and the second vector becomes a desired alternating current voltage to be output between the first terminal and the second terminal. The inverter device according to claim 1. The inverter device according to claim 1.

3. The control unit determines the sign of a correction value used for adjusting at least one of the phase of the first voltage and the phase of the second voltage based on the magnitudes of the current output from the first terminal and the current output from the third terminal. The inverter device according to claim 1. The inverter device according to claim 1.

4. The control unit performs dq conversion on each of the first voltage and the second voltage, and adjusts the phase of the first voltage and the phase of the second voltage so that both the q-axis voltage related to the first voltage and the q-axis voltage related to the second voltage become "0". The inverter device according to claim 1. The inverter device according to claim 1.

5. The control unit performs dq conversion on each of the first voltage and the second voltage, and adjusts the phase of the first voltage and the phase of the second voltage so that the sum of the q-axis voltage related to the first voltage and the q-axis voltage related to the second voltage becomes "0". The inverter device according to claim 1. The inverter device according to claim 1.

6. Further comprising a storage unit that stores a correspondence relationship between current and phase delay amount, The control unit, Obtains a first phase delay amount corresponding to a first current output from the first terminal from the correspondence relationship, Obtains a third phase delay amount corresponding to a third current output from the third terminal from the correspondence relationship, Determines a correction value for adjusting at least one of the phase of the first voltage and the phase of the second voltage based on the first phase delay amount and the third phase delay amount. The inverter device according to claim 1.

7. The control unit calculates a first phase delay amount based on the difference between the zero-crossing point of the first voltage and the zero-crossing point of a first voltage command value for outputting the first voltage, calculates a second phase delay amount based on the difference between the zero-crossing point of the second voltage and the zero-crossing point of a second voltage command value for outputting the second voltage, and determines a correction value used for adjusting at least one of the phase of the first voltage and the phase of the second voltage based on the first phase delay amount and the second phase delay amount. The inverter device according to claim 1.

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